Introduction to
Field Programmable Gate Arrays
FPGAs
John Coughlan
Technology Department
Outline

Q. What does FPGA stand for?

FPGA Architecture



FPGA Design Flow



Hardware Description Languages
Design Tools
FPGAs Applications



Common characteristics
Specialised blocks
Particle Physics
Computing
Trends and Future of FPGAs
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
What does FPGA stand for?




Field Programmable Gate Array
Field : “in the field”
Programmable : “Re-Configurable” Change Logic Functions
Gate Array : reference to ASIC internal architecture
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
What is an FPGA?







Field Programmable Gate Array
(Very) Large Scale Integrated Circuit
Digital Logic
Programmed after manufacture rather than unchangeable
Application Specific Integrated Circuit ASIC
First appeared in 1980’s. Took off in last decade.
Standard IC manufacturing process
Following Moore’s Law
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Why are they of Interest?

Essential Components in modern HEP Electronics (& Industry!)



Data Acquisition (Millions Channels)
Triggers
Computer Interfaces VME
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
What is an FPGA?

Field Programmable Gate Array




Configurable (Programmable) General Logic Blocks
Configurable Interconnects
Plus Special Purpose Blocks (Embedded Processors)
Configured (multiple times) to perform variety of tasks (HEP)
Programmable
interconnect
Programmable
logic blocks
Simple Logic Block ‘Islands’ in a ‘Sea’ of Interconnects
10,000 … 100,000+ (Massively Parallel HEP)
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Little bit of History…


FPGAs appeared in the 1980’s. Took off in last decade.
Bridge gap between simple Programmable Logic and semi
custom ASICs (Application Specific Integration Circuits).
PLDs
SPLDs
CPLDs
ASICs
The
GAP
Gate Arrays
Structured ASICs*
Standard Cell
Full Custom
*Not available circa early 1980s
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Previous Generations Logic Devices





Simple Logic (used to “glue” other ICs together)
Reprogrammable (UV light, electrically eraseable)
Cheap
Easy to Program
Many different variations
Eg. Implement Logic as ‘Sum of Products’ Terms
a
b
c
Predefined link
Programmable link
PLDs
&
&
SPLDs
&
CPLDs
a & b & c
a & c
!b & !c
PLAs
PALs
GALs
etc.
l
PROMs
l
Predefined AND array
l
a !a b !b c !c
w
x
y
Programmable
OR array

w = (a & c) | (!b & !c)
x = (a & b & c) | (!b & !c)
y = (a & b & c)
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Little bit of History…
PLDs
SPLDs
CPLDs
ASICs
The
GAP
Gate Arrays
Structured ASICs*
Standard Cell
Full Custom
*Not available circa early 1980s
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ASICs





Large Complex Functions
Customised for Extremes of Speed, Low Power, Radiation
Hard (HEP)
(Very) Expensive (in small quantities) @ 90 nm ~ $1M mask set
(Very) Hard to Design.
Long Design cycles.
Not Reprogrammable. High Risk
Semi Custom Gate Arrays.
I/O cells/pads
Channels


Basic cells
ASICs
(a) Single-column arrays
Gate
Arrays
Structured
ASICs
Standard
Cell
(b) Dual-column arrays
Full
Custom
Increasing complexity
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGAs best of both worlds…





Large Complex Functions
Programmability, Flexibility.
Massively Parallel Architecture
Fast Turnaround Designs
Mass produced. Cheap
PLDs
SPLDs
CPLDs
ASICs
The
GAP
Gate Arrays
Structured ASICs*
Standard Cell

Prototype ASICs

Power Hungry
Full Custom
*Not available circa early 1980s
Programmable
interconnect
Programmable
logic blocks
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Common FPGA Characteristics

Logic Elements




Programmable
logic blocks
SRAM blocks
Routing Resources


Programmable
interconnect
Memory Resources


Lookup Table
Flip Flops
Multiplexers
Hierarchy Programmable Channels between Logic Elements
Configurable I/O

Interfaces to the real world. Logic Levels. Fast Serial I/O

Massively Parallel Architecture (HEP)
Clocked Logic Design

CMOS based using SRAM cells for configuration

j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Elements




Lookup Table LUTs (Combinatorial Logic)
a
Multiplexers
b
c
Flip-Flops (Clocked Registered Logic)
Options configured by SRAM cells
Required function
Truth table
AND
&
OR
|
y
y = (a & b) | c
a b c
y
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit SR
16x1 RAM
Programmable
interconnect
Programmable
logic blocks
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
SRAM
j.coughlan@rl.ac.uk
set/reset
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Memory




SRAM blocks
Data Buffers (HEP)
FIFOs
Code
j.coughlan@rl.ac.uk
Columns of embedded
RAM blocks
Arrays of
programmable
logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
System on a Chip

Recently Embedded Micro-Processors in Fabric





Hard Cores e.g. RISC PowerPC
Soft Cores
Peripherals Timers, GPIO
Run Operating System e.g. Linux
Combine Micro-Processor
& Massively Parallel Logic
uP
uP
uP
uP
uP

Dual Design Flows


Firmware HDL
Software C
j.coughlan@rl.ac.uk
(a) One embedded core
(b) Four embedded cores
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Input and Output




Several hundred of I/O pins
All flavours of Logic Levels e.g. LVDS, TTL
High Speed Serial Transceivers (up to 10? Gbps) (HEP)
Ethernet MAC Cores
1
0
2
7
Transceiver block
General-purpose I/O
banks 0 through 7
3
4
j.coughlan@rl.ac.uk
Differential pairs
6
5
FPGA
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Ethernet FPGA and PC Networks





Ethernet MAC COREs inside FPGA
Drive Data via Serialiser I/O and Optical Transceiver chip
Direct to Network Card in PC.
2 IP Nodes on Network.
Small DAQ systems
Dev Board
V2 Pro FPGA
Rocket IO MGTs
Prog’ Data
Generator
SFP
Gb Opto Transceiver
Tx1
Tx2
Tx3
Tx4
Quixtream ®
UDP core
Gigabit
Ethernet
RAID 0
PC
Gb NIC
Rx1
Prog’ Data
Generator
Trigger
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programming an FPGA

Field Programmable Gate Array



Configurable (Programmable) General Logic Blocks
Configurable Interconnects
Bit File contains the Configuration Information
Programmable
interconnect
Programmable
logic blocks
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programming (Configuring) an FPGA





SRAM cells holding configuration are Volatile Memory
Lose configuration when board power is turned off.
Keep Bit Pattern describes the Logic Functions in non-Volatile
Memory e.g. ROM or Compact Flash card
Reprogramming takes ~ secs
Uses JTAG Boundary Scan
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Design Flows

High level Description of Logic Design


Schematic
Hardware Description Language

Compile into Netlist. Low (Logic Gates) level description.

Target Netlist to FPGA Fabric





Mapping and Packing
Placing and Routing
Tools Generate the Bit File
Simulation
Timing Analysis
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Packing
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Design Flows



Schematic Capture of Logic Design.
Useful at Top level.
Create Netlist. Text file with signal connections.
SET_A
SET
SET_B
Schematic
capture
G1 = NAND
Gate-level
netlist
CLOCK
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
Q
G2 = NOT
N-Q
G4 = DFF
END CIRCUIT=TEST;
Detect and fix problems
N_DATA
DATA
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
CLEAR_A
Logic
Simulator
Place-andRoute
Functional
verification
Extraction and
timing analysis
CLEAR
CLEAR_B
G3 = OR
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
Detect and fix problems
GATE
GATE
GATE
GATE
G1=NAND
G2=NOT
G3=OR
G4=DFF
(IN1=SET_A, IN2=SET_B, OUT1=SET);
(IN1=DATA, OUT1=N_DATA);
(IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR);
(IN1=SET, IN2=N_DATA, IN3=CLOCK,
IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages

Behavioural / Register Transfer Level Description



Program Statements. Loops. If Statements …etc
Describing Mixture of Combinatorial and Sequential Logic and
Signals between.
Engineers call it Firmware
Behavioral
(Algorithmic)

VHDL (VHSIC Hardware Description Language)




Very High Speed Integrated Circuit
VERILOG (US)
Synthesis (Compilation)
Generate Netlist
j.coughlan@rl.ac.uk
Functional
Loops
Processes
RTL
Boolean
Gate
Structural
Switch
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL Firmware Hardware Description
architecture Behavioral of dpmbufctrl is
signal acount
signal dcount
signal bram_addr_i
: std_logic_vector(31 downto 0);
: std_logic_vector(31 downto 0);
: std_logic_vector(31 downto 0);
begin
bram_en <='1';
bram_rst <= '0';
--bit order reverse address and data buses to match EDK scheme
bram_addr(0 to 31) <= bram_addr_i(31 downto 0);
--N.B. EDK DOCM addresses are byte orientated count in 4s for whole words
g1 : process(clk, rst)
variable state : integer range 0 to 3;
variable buf_zone: integer range 0 to 1;
begin
j.coughlan@rl.ac.uk
if clk'event and clk = '1' then
if rst = '1' then
buf_zone:=0;
acount <= (others => '0');
dcount <= (others => '0');
bram_wen <= (others => '0');
bram_addr_i <= X"00001FFC"; -bram_dout_i <= (others => '0');
state:=0;
elsif state = 0 then
--wait for din(0) at address 1FFC to be set to zero
--what about pipeline of BRAM - need to wait before polling?
bram_wen <= (others => '0');
acount <= (others => '0');
bram_addr_i <= X"00001FFC";
bram_dout_i <= (others => '0');
dcount <= dcount;
if bram_din_i = X"00000000" then
state := 1;
else
The Design Warrior’s Guide to FPGAs
state := 0;
Devices, Tools, and Flows. ISBN 0750676043
end if;
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages




View Logic as collection of Processes operating in Parallel
Language Constructs for Multiplexers, FlipFlops …etc
Restrictive set of RTL for Synthesis
Synthesis Tools recognise certain code constructs and
generate appropriate logic
if
SEL == “00“ then Y
elseif SEL == “01“ then Y
elseif SEL == “10“ then Y
else
Y
end if;
=
=
=
=
A;
B;
C;
D;
4:1 MUX
case SEL of;
“00“: Y
“01“: Y
“10“: Y
otherwise: Y
end case;
2:1 MUX
2:1 MUX
D
2:1 MUX
=
=
=
=
A;
B;
C;
D;
A
B
C
D
00
01
10
Y
11
C
B
Y
A
SEL
SEL == 10
SEL == 01
SEL == 00
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic



Pipelined. Clocked Logic.
Combinational and Sequential Logic.
Register Transfer Level Logic.
Three levels of logic
AND
Combinational
Logic
Combinational
Logic
OR
&
From previous
bank of registers
|
NOR
|
Combinational
Logic
Data In
To next bank
of registers
etc.
Programmable
interconnect
Programmable
logic blocks
Registers
Combinational
Logic
Registers
Combinational
Logic
Registers
16-bit SR
16x1 RAM
Data In
etc.
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
Clock
clock enable
set/reset
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL Firmware is Not a Computer Program
/* C/C++ */
a = 6 /* C/C++ init */
b = 2 /* C/C++ init */
a = b;
b = a;
/* a = 2 and b = 2 ; sequential */
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
VHDL Firmware is Not a Computer Program
/* C/C++ */
a = 6 /* C/C++ init */
b = 2 /* C/C++ init */
a = b;
b = a;
/* a = 2 and b = 2 ; sequential */
But
/* HDL */
a = 6 /* HDL register init */
b = 2 /* HDL register init */
a = b;
b = a;
/* a = 2 but b = 6 ; concurrent */
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages


Synthesis (Compilation)
Generate Netlist
Register
transfer level
Gate-level
netlist
Mapping
Logic
Synthesis
RTL
j.coughlan@rl.ac.uk
Packing
Place-andRoute
Logic
Simulator
Logic
Simulator
RTL functional
verification
Gate-level functional
verification
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Software Languages?

Can Logic be expressed at a higher level of Abstraction?
Familiar to Software Programmer?

System C







C/C++ Representation of Algorithms
Class based
Faster simulation
Auto translation to HDL
Lacks support by Tools
Augmented C++


Behavioral
(Algorithmic)
Loops
Processes
Functional
Special Statements to support
Concurrency, clocks, pins ..etc
RTL
Boolean
Gate
Structural

Digital Signal Processing Functions
j.coughlan@rl.ac.uk
Switch
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Firmware Libraries

Libraries of Firmware aka IP (Intellectual Property), Cores




Libraries




Buy from FPGA Vendor
Buy from Third Parties
Open Source
VHDL code
Black Box NetList
Hardwired in Silicon
Large User Community
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Debugging Designs

Logic Simulation Tools



Create Computer model of Logic
Feed Test Vector signals in and compare output with expected
pattern
Virtual Logic Analysers

Capture signals in real time whilst FPGA is running logic
Columns of embedded
RAM blocks
JTAG (from external virtual logic
analyzer program or another
internal logic analyzer block)
Signals we wish
to monitor
Virtual Logic
Analyzer
Arrays of
programmable
logic blocks
Embedded
RAM Block
Control
Logic
Start/Stop
conditions to
trigger on
j.coughlan@rl.ac.uk
JTAG (to external virtual logic
analyzer program or another
internal logic analyzer block)
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
15 Years Evolution

SRAM based FPGA devices following Moore’s Law



200 x Logic
40 x Faster
Logic Element cost ~ 1$ in 1990 ; $0.002 in 2004
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Trends

State of Art is 65nm on 300 mm wafers
Top of range 100,000+ Logic Elements
1,000 pins (Ball Grid Arrays)

Same cost






1995 : 500 Logic Elements
2000 : 10,000 Logic Elements
2005 : 50,000 Logic Elements
Challenges



Power. Leakage currents.
Signal Integrity
Design complexity
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Manufactures Market Share
$2.1B
$2.6B
$4.1B
$2.6B
$2.3B
$2.6B
$3.1B
31%
33%
34%
32%
31%
32%
32%
20%
18%
17%
28%
24%
49%
50%
51%
2002
2003
2004
100%
Market Share (%)
80%
60%
39%
32%
40%
20%
30%
0%
Calendar year 1998
35%
1999
Xilinx
j.coughlan@rl.ac.uk
38%
2000
44%
2001
Altera
All Others
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Radiation Hardness









FPGAs in Standard CMOS Process
Not Designed for Very Rad Hard environments
Not used in Front End Electronics (inside Detectors)
Single Event Upsets
SRAM Reconfigure
Design Logic Triple Redundancy
Are used in low level Rad environments (outside Detectors)
In satellites
On Mars
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Research Developments

High Performance Computing

CRAY XD1 : OPTERON + FPGA
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Research Developments
Uninitialized
SRAM cells

Reconfigurable Computing

Virtual Hardware
Configuration
data stream
X
XX XX
XX XX XX X
X
X XX XX XX X
XX XX XX XX XX XX
X
X XX XX XX XX XX
X XX XX XX X
Primary
X
X
X
XX XX XX
outputs
X XX
X
Primary
inputs
SRAM cells
loaded with 0s and 1s
1
00 1
01 101 01 0
1
0
01 00 00
00 1
11 101 01 101 001 01
0
0 01 10 01 11 11
1
1 10
10 10 01
1
01 001 10
0 01
1
Primary
outputs
Primary
inputs
(a) Unconfigured
(b) Configured
Configuration data
stored in memory device
Function A
Unused resources
Active tasks
Inactive tasks
Function A
Function B
Function B
Function C
Overwrite function B
with new function C
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary

Q. What does FPGA stand for?
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary

Overview of Field Programmable Gate Arrays




Architecture
Programming
Design Flows
Trends

Why they are of interest (in HEP)

Thanks for your attention

Please come along and visit our electronics lab
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Spare Slides
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Choosing an FPGA

Vendor
Resources Logic
Memory
I/O pins
Packaging
Device Families

Vendor Tools, IP Cores








Special Purpose blocks e.g. CPUs
Speed Grade
Cost
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Packaging




FPGA Package is a little PCB
Ball Grid Arrays
Assembly is a critical Manufacturing Step
Signal Integrity Issues
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Special Purpose Blocks

Digital Signal Processing Functions



FIR Filters
Digital Radio
Advantage over DSP chips Massively Parallel System
RAM blocks
Multipliers
Logic blocks
Multiplier
Adder
Accumulator
A[n:0]
x
B[n:0]
+
Y[(2n - 1):0]
MAC
j.coughlan@rl.ac.uk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)