SDR TX Project
Hardware / Software Update
October 2008
Jerry Boyd, WB8WFK
(Hardware and FPGA VHDL )
Mike Pendley, K5ATM (PIC Software)
This is an ARTS Project
Software defined ARDF radio
transmitter
New approach to solve a reoccurring problem
– A need exists for an easy to build “NO-Tune” reliable ARDF
transmitter that does not require any complex test equipment
other then a DVM , wattmeter and receiver to verify operation
after assembly
– Simple Alignment (tune RF output stage)
– As a result of this development effort Other ham radio related
applications are possible
•A short list of possible applications
–APRS
–PSK
–RF Signal generator for equipment testing
The Problem
Our Current FOX Boxes are
–
–
–
–
LARGE and heavy
Tend to fall out of sync
Limited to 2m FM MCW and 80m CW
Programming switches and radios need to
be adjusted to change frequencies and
configuration.
The Problem
Root cause
– All problems can be traced to systems that are wired together
using mutable connectors, cables and equipment
interconnected to function as an ARDF transmitter
– RF gets into and upsets controller
– Radios are not designed for high duty cycle
– Equipment not designed for this application
– Wires can get caught in equipment during
transport to location and interrupt
operation
– Lots of opportunity for something
to go wrong
The Solution
A Software Defined Radio That can
–
–
–
–
–
–
–
–
–
Dynamically change frequency
Dynamically change modulation modes
Conserve power during “down” time
Use SI station “real time clock” to stay in sync and “auto
recover” if power is interrupted after sync
Phone home with state of health information
A user interface that is easy to configure
Shielded enclosure that protects all electronics
Radio designed for continuous duty cycle (homing beacon
mode)
Every thing contained in one hardware package with power
input, SI input and antenna connections
The Solution
A Software Defined Radio
– First Generation WB8WFK K5ATM SDR (w/o PA amps)
demonstrated at 2005 ARDF championships
– Used as homing transmitter for the 2005 USA ARDF championships
Tools used
• Recent changes in industry ( free tools for
download from the internet) make a
project like this possible
Free development environments
• Xilinx
– WWW.Xilinx.com Webpack ISE development
environment for development of VHDL and FPGA
code
• JAVA IDK
– Sun Microsystems. Used to develop lookup ROMs, I
wrote Java code that automatically writes VHDL code
to define modulation parameters
• Microchip
– PIC ISE development environment for generating PIC
controller code
Purchased Items
• PIC dim II card development kit and PIC
programmer. I took part in a group buy by
the Albuquerque Yahoo PIC group
• BASYS Digiletinc.com Xilinx eval board.
purchased last Christmas
• SI score keeping system Purchased
Summer 2008 by Albuquerque transmitter
hunters
2nd Generation Prototype
Class C RF amp
Voltage
regulator
OP amp for D/A,
AM Modulator & RF
power control
Signal Processor FPGA
($10 Xilinx chip). FPGA,
regulators , clock and
boot ROM are only
features being used on
$59 eval board
Pre driver
Mixer
Open Bench testing of SI interface
SI pinch data
(Time and Stick
number) displayed
on PIC dim LCD
0x23 = station 35
or MO5 for FJWW
score keeping
software
02B8F3 = SI stick
Number 247347
was punched
8 33 6 =
Punch time was
8:33 06 PM
PIC DIM2 card and Xilinx FPGA eval board used for SI interface
concept testing. Next steep is to produce ~ 3 inch X 4 inch PCB board
with all processing and I/O support electronics combined to finish
development
2nd generation Block Diagram of
today's demo hardware
Simple Block Diagram
Signal processor using Xilinx FPGA
Mixer
145.565
130MHz
LO
PIC
Fox
Controller
FM modulator
AM modulator
Synthesizer
HF and VHF
Packet modem (TX only)
Control Logic
VHF
Simple
bandpass
Filter
Driver
RF
15.565
8
HF not used in today's demo
RS-232 to SI station
PA
Class C
Modulator
Power
Control
The hart of the system
• Phase accumulators operating at 200 MHz
– Generates both HF and VHF signals
• VHDL state machines
– Generate modulation formats and handles DSP control
• VHF signals generated at HF then mixed up to VHF
– FPGA generates LO (130 MHz) and formatted transmit IF signal (14 to 18
MHz) that represents modulated up converted144 to 148 MHz carrier
– AM modulation is the one exception and that’s done under FPGA digital
control of the Class C VHF Power amp
– Sample output from Java code for configuring phase accumulators
VHF DDS phase inc is
VHF DDS phase inc is
VHF DDS phase inc is
VHF DDS phase inc is
309022897
334255830
355730666
377205503
counts for 144.3900
counts for 145.5650
counts for 146.5650
counts for 147.5650
Mhz;
Mhz;
Mhz;
Mhz;
DDS set to 14.39000000
DDS set to 15.56500000
DDS set to 16.56500000
DDS set to 17.56500000
Mhz
Mhz
Mhz
Mhz
• HF signals (80 meters) are direct generated
– Sample output from Java code configuring phase accumulators
HF DDS phase inc is
HF DDS phase inc is
HF DDS phase inc is
HF DDS phase inc is
76879915 counts for 3.5800 Mhz
81604379 counts for 3.8000 Mhz
76020921 counts for 3.5400 Mhz
75806173 counts for 3.5300 Mhz
Software
2m (VHF) Transmission modes to be
supported
– FM MCW Cont carrier
– FM MCW keyed carrier
– AM MCW Cont carrier
– CW
– AM MCW keyed carrier
– FM packet (1200 baud)
– APRS tracker?
145.565 VHF
AM Modulation
Software (cont)
2m Transmission modes to be supported
-Sport ID data packet
sent while TX is off
cycle
-VHF TX would be
used during a HF hunt
to support SI data
-Panic button located
at each control station
to request medical
assistance
K0OV photo
First SI data sent Via Packet
•
•
First on air test of SI reporting KPC3 TNC was decoding packets. Each SI
punch event is sent 4 times (binary data) to aid reception at finish line
Note 0X02 = STX and OX03 = ETX
57 42 38 57 46 4B 2D 31 3E 41 50 54 44 44 53 2D
31 2C 57 49 44 45 32 2D 32 3A 20 3C 55 49 3E 3A
0D 0A 02 53 21 23 10 02 B8 F3 10 00 2A C7 10 03
A6 10 0A 03 0D 0A 57 42 38 57 46 4B 2D 31 3E 41
50 54 44 44 53 2D 31 2C 57 49 44 45 32 2D 32 3A
20 3C 55 49 3E 3A 0D 0A 02 53 21 23 10 02 B8 F3
10 00 2A C7 10 03 A6 10 0A 03 0D 0A 57 42 38 57
46 4B 2D 31 3E 41 50 54 44 44 53 2D 31 2C 57 49
44 45 32 2D 32 3A 20 3C 55 49 3E 3A 0D 0A 02 53
21 23 10 02 B8 F3 10 00 2A C7 10 03 A6 10 0A 03
0D 0A 57 42 38 57 46 4B 2D 31 3E 41 50 54 44 44
53 2D 31 2C 57 49 44 45 32 2D 32 3A 20 3C 55 49
3E 3A 0D 0A 02 53 21 23 10 02 B8 F3 10 00 2A C7
10 03 A6 10 0A 03 0D 0A
..¦.....
First packet send via RF on 9/21/2008
Red indicates enbedded SI punch data
WB8WFK-1>APTDDS1,WIDE2-2: <UI>:
...S!#..¸ó..*Ç..
¦.....WB8WFK-1>A
PTDDS-1,WIDE2-2:
<UI>:...S!#..¸ó
..*Ç..¦.....WB8W
FK-1>APTDDS-1,WI
DE2-2: <UI>:...S
!#..¸ó..*Ç..¦...
..WB8WFK-1>APTDD
S-1,WIDE2-2: <UI
>:...S!#..¸ó..*Ç
Our SI system
Software
Other Transmission modes
– Special modes for car hunts are possible
• Random on time
• Variable and random
power output
• Short TX times
• Keyed carrier modes
• Different modulation formats
This is a transmitter used on an
Albuquerque T hunt by Mike Pendley
K5ATM
Software
Other Transmission modes
– HF side
• 80M CW used for 80 meter ARDF
HF CW 3.58 MHz
What next
• BASIC concept is verified using open bench setup! I am
happy with signal processor operation
• Now its time to:
– Develop 2 X 3 inch Circuit board and User interface
– Write SPI based interface VHDL code for signal processor FPGA
to allow full control of signal processor by the PIC processor
(Modulation Mode and frequency selection). Currently done using
dip switches
– Develop panic button interface to allow runners to call for medical
help at any control point
– Field test prototype with all of the above functions
• Design of the PC board with necessary I/O to support the
above is now in process. Schedule will allow testing
design over Christmas holiday break
• There will be another PCB before the final design is done
to develop PA board (HF and VHF) that mounts on top of
the signal processor board ~ January 2009 time frame
3 X 4 inch PCB Board layout has
started
Demo
• Demonstrate Generation 2 prototype
system
Some Other Projects
Questions