16.317: Microprocessor
System Design I
Instructor: Dr. Michael Geiger
Spring 2012
Lecture 22: Virtual memory
Lecture outline
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Announcements/reminders
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Lab 2 due 3/28
HW 3 due 3/26
Lecture outline
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Review
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Virtual memory
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4/13/2015
Local memory accesses
Interrupt descriptor table
Task switching
Benefits
VM and 80386 segmentation
Paging
Microprocessors I: Lecture 22
2
Review
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Local memory access
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Selector indicates access is global (TI == 1)
LDTR points to LDT descriptor in GDT
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Index field in selector chooses descriptor from LDT
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Descriptor provides starting address of segment
Provide starting address, length of interrupt service routines
Limited to 256 descriptors
Stored in IDT; IDTR holds base/limit of IDT
Task switching
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4/13/2015
Descriptor addr = (LDT base) + (selector index * 8)
Interrupt descriptors
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Actual base, limit of LDT stored in LDTR cache
Task register (TR): selector for current task state segment (TSS)
TSS stores all state (register values) for current task
Task switch: jump/call that changes TR; old TSS saved and new one
loaded
Microprocessors I: Lecture 22
3
Problems with memory
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DRAM may be too expensive to buy
enough to cover whole address space
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Most systems run multiple programs
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4/13/2015
We need our programs to work even if they
require more memory than we have
A program that works with 512 MB RAM
should still work with 256 MB RAM
Most processors don’t have hardware
multitasking support (like the 386)
Microprocessors I: Lecture 22
4
Solutions
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Leave the problem up to the programmer
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Overlays
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Compiler identifies mutually exclusive regions
Virtual memory
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Assume programmer knows exact memory
configuration
Use hardware and software to automatically
translate references from virtual address (what
the programmer sees) to physical address
(index to DRAM or disk)
Most virtual addresses not present in physical
memory!
Microprocessors I: Lecture 22
5
Virtual Address and VA Space
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80386 virtual addresses: 48-bit
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Used by Memory Management Unit (MMU)
Consists of
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Segment can be as large as 4GB
Virtual address space can be 246 bytes (64
Terabytes)
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4/13/2015
Selector (16bit): can be one of the segment
selector register
Offset (32bit): can be EIP or other 32-bit registers
2 bits used for privilege level in selector
Microprocessors I: Lecture 22
6
Address translation
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Virtual address  physical address
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Need address translation mechanism
May take multiple steps
On 80386, two (main) levels
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Virtual address (VA)  linear address (LA)
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Linear address  physical address (PA)
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Uses selectors, descriptors discussed so far
If using segmented memory model, PA == LA
If using paged memory model, translate LA to PA
Microprocessors I: Lecture 22
7
Segmented Partition of Virtual
Address Space
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80386 virtual memory space is divided into
global and local memory address space
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Up to 8192 segments may exist in either global
or local address space
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32 Terabytes global address space
32 Terabytes local address space
Because maximum size of GDT is 64KBytes, each
descriptor is 8bytes, 64KB/8B = 8192
Not all descriptors are normally in use
Task has both global and local memory space
Microprocessors I: Lecture 22
8
Physical Memory Space and Virtualto-Physical Address Translation
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4GB physical memory vs 64TB virtual memory
space
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Segments not in use is stored on secondary
storage device
Address translation: 48bit VA -> 32bit PA
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Just a small amount of the information in virtual
memory can reside in physical memory
Segment translation
Page translation
Microprocessors I: Lecture 22
9
Memory Swap
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MMU determines whether or not a segment or
page resides in physical memory
If not present, “swap”
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4/13/2015
memory management software initiates loading of
the segment or page from external storage device to
physical memory
A segment or page in physical memory will be
swapped out and stored in external storage device
Microprocessors I: Lecture 22
10
Segmentation Virtual to Physical
Address Translation
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48-bit virtual address (selector + offset) translated to
32-bit physical address
“Selector” used to find segment descriptor in LDT
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Segment descriptor cache defines the location and size
of code/data segment
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64-bit segment descriptor cache register in 80386 contains:
access rights (12b), base address(32b), limit(20b)
Code/data segments in physical memory
Offset is the address of the data to be accessed in the
segment
Segment base address + offset = 32b linear address
32b linear address is physical address, if paging is
disabled
Microprocessors I: Lecture 22
11
Example
Segment selector = 0100H
offset = 00002000H
segment base address = 00030000H
Q:What is the virtual address? Physical address?
A: VA = 0100:00002000H
linear address = base address + offset
= 00030000H+00002000H
= 00032000H
if paging disabled, PA = linear addr = 00032000H
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4/13/2015
Microprocessors I: Lecture 22
12
Paged partition of Virtual
Address Space
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Physical memory is organized in 4KB pages
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Simplifies the implementation of the memory
management software
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Fixed 4K pages make space allocation and
deallocation easier than segmentation
Space in a page might not be fully utilized
Linear address is not direct physical address
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4GB/4KB = 1,048,496 pages
Undergo a second translation - page translation
Format: 12-b offset, 10-b page, 10-b directory field
Microprocessors I: Lecture 22
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Managing virtual memory
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Effectively treat main memory as a cache
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Blocks are called pages
Misses are called page faults
Virtual address consists of virtual page
number and page offset
Virtual page number
31
4/13/2015
Page offset
11
Microprocessors I: Lecture 22
0
14
Virtual address spaces
Page Table
Physical
Memory Space
frame
A virtual address space
is divided into blocks
of memory called pages
frame
frame
frame
virtual
address
OS
manages
the page
table for
each ASID
4/13/2015
A machine
usually supports
pages of a few
sizes
(MIPS R4000):
A page table is indexed by a
virtual address
A valid page table entry codes physical
memory “frame”
address for the page
Microprocessors I: Lecture 22
15
Details of Page Table
Page Table
Physical
Memory Space
Virtual Address
12
offset
frame
frame
V page no.
frame
Page Table
frame
virtual
address
Page Table
Base Reg
index
into
page
table
V
Access
Rights
PA
table located
in physical P page no.
memory
offset
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Physical Address
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Page table maps virtual page numbers to physical frames
(“PTE” = Page Table Entry)
Virtual memory => treat memory  cache for disk
4/13/2015
Microprocessors I: Lecture 22
16
Paging on 80386
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Two-level page table
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First level: “page directory”
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Second level: “page table”
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Starting address of each “page table” stored in page
directory
Indexed by middle 10 bits of linear address
Provides starting address of physical page frame
Physical address = (page frame base) +
(offset)
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Starting address stored in CR3 (page directory base
register (PDBR))
Indexed by upper 10 bits of linear address
Offset = lowest 12 bits of linear address
Microprocessors I: Lecture 22
17
Virtual memory performance
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Address translation accesses memory to get
PTE  every memory access twice as long
Solution: store recently used translations
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Translation lookaside buffer (TLB): a cache for
page table entries
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“Tag” is the virtual page #
TLB small  often fully associative
TLB entry also contains valid bit (for that translation);
reference & dirty bits (for the page itself!)
Microprocessors I: Lecture 22
18
Next time
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4/13/2015
Virtual memory examples
Microprocessors I: Lecture 22
19