SoC Challenges &
Transaction Level Modeling (TLM)
Dr. Eng. Amr T. Abdel-Hamid
Spring 2008
System-On-a-Chip Design
ELECT 1002
Table Of Contents
SoC Design
 SoC Challenges
 TLM Model Concepts
 TLMs for different design domains
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SoC Challenges
SoC Design
 Explosive Complexity:
 The smaller the better
 Time-to-market
 the amount of time require
d for conceiving an idea in
to a real product for sales
Shorter times-to-market
 Sky-rocketing Cost
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System Design Level
SoC Design
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Solutions
SoC Design



TLM
Reuse of implementations (IP Design Reuse)
System standards
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Classic Design Flow
SoC Design
Algorithmic Design
Architectural Design
System Level Design (Co-design Level)
Behavioral Model
(Spec.)
Partitioning
VHDL/Verilog
Software
S/W Design
Implementation
RTL
Implementation
RTL Model
H/W Design
Gate
Synthesis
Gate Model
Layout
Generation
Layout
Synthesis Tools
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System Integration
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System Description Models
SoC Design
 Transistor level
 HSpice, Schematic
 Gate level
 Netlist, PALASM, TEGAS
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 RT Level
 HDLs
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Modern Design Flow
SoC Design
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Levels of Abstraction
SoC Design
Three levels of abstraction:
1. Functional level
• Executable Specification
• Un-Timed
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2.
Architecture level
• Analyze SoC architecture
• Early SW development
• Estimated timing
3.
Micro-Architecture level
• Pin level
• RTL/Behavioral HW design
• Exact Timing
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Transaction Level Modeling - TLM
SoC Design
 Transaction is the exchange of data or an event between two comp
onent of a modeled and simulated system
 data can be anything from a word to a complex data structure
 event transaction models synchronization aspects that ensure correct operatio
n of the SoC
 The behavior of functional blocks can be separated from communicati
on
 The communication is described in terms of sending transactions
TLM only focus on mapping out data flow details,
i.e. the type of data that flows and where it is stored
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TLM – cont.
SoC Design
RTL:
• The bus is wires
• Each device on the
bus has a pin-accura
te interface
• Each device interfac
e must implement the
bus protocol
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TLM:
• Bus model enforces
the bus protocol
• Each device commu
nicates via transactio
n level API
• Less code, fewer pi
ns, fewer
•events => much fast
er
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Basics of TLM
SoC Design
Transaction : exchange of a data or an event between tw
o components of a modeled and simulated system
Module : structural entity, which contain processes, ports,
channels, and other modules
Channel : implements one or more interfaces, and serves
as a container for communication functionality
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Port : object through which a module can access a chan
nel’s interface.
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Basics of TLM
SoC Design
Primitive & Hierarchical Channel
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 Hierarchical channels contain processes, ports, modules a
nd channels, but primitive channels do not
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TLM Advantages
SoC Design
 SW development delay
SW team can begin SW developi
ng or testing stage much sooner
 HW/SW communication
HW parts can communicate with
SW parts in this common enviro
nment. Makes the SW debug eas
ier.
 Design space exploration
Designers can decide on its part
itioning (module and HW/SW par
titioning) in the early stages of t
he design.
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 Simulation speed
The number of events decreases
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TLM Abstraction Models
SoC Design
 Time granularity for communication/computation objects ca
n be classified into 3 basic categories.
 Models B, C, D and E could be classified as TLMs.
A. "Specification model"
"Untimed functioal models"
Communication
Cycletimed
D
C. "Bus-arbitration model"
"Transaction model"
Approximatetimed
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Untimed
C
E
D. "Bus-functional model"
"Communicatin model"
"Behavior level model"
A
B
Untimed
Approximatetimed
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B. "Component-assembly model"
"Architecture model"
"Timed functonal model"
F
Cycletimed
Computation
E. "Cycle-accurate computation
model"
F. "Implementation model"
"Register transfer model"
TLM Abstraction Models
SoC Design
1.
Specification model
2.
3.
4.
5.
PE*-assembly model or Component Assembly
Bus-arbitration model
Time-accurate communication model
Cycle-accurate computation model
6.
Implementation model
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* Processing elements
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A: “Specification Model”
SoC Design
Objects
- Computation
-Behaviors
- Communication
-Variables
Composition
B1
-
v1 = a*a;
-
Hierarchy
Order
-Sequential
v1
-Parallel
B2B3
-Piped
B3
B2
v3= v1- b*b;
v2 = v1 + b*b;
-States
- Synchronization
v2
v3
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B4
v4 = v2 + v3;
c = sequ(v4);
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-Notify/Wait
B: “Component-Assembly Model”
SoC Design
Composition
PE1
B1
cv11
-
Hierarchy
-
Order
v1 = a*a;
PE3
v2 = v1 + b*b;
-Parallel
v3= v1- b*b;
-Piped
v3
PE2
B2
-Sequential
B3
cv12
Objects
- Computation
- Proc
- IPs
- Memories
- Communication
-Variable channels
cv2
-States
B4
v4 = v2 + v3;
c = sequ(v4);
-
Synchronization
-Notify/Wait
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C: “Bus-Arbitration Model”
SoC Design
Objects
- Computation
- Proc
- IPs (Arbiters) PE1
B1
- Memories
v1 = a*a;
- Communication
- Abstract bus
channels
PE2
Composition
PE4
(Arbiter)
PE3
-
Order
-Sequential
B3
v3= v1- b*b;
cv12
1
cv2
-Parallel
-Piped
2
v3
cv11
-States
B4
1. Master interface
2. Slave interface
3. Arbiter interface
v4 = v2 + v3;
c = sequ(v4);
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Bus arbiter arbitrates bus conflict
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Hierarchy
3
B2
v2 = v1 + b*b;
-
-
Synchronization
-Notify/Wait
D: “Bus-Functional Model”
Composition
PE4
(Arbiter)
PE1
3
B1
B3
v1 = a*a;
v3= v1- b*b;
1
PE2
address[15:0]
address[15:0]
data[31:0]
data[31:0]
ready
ack ready
ack
2
v3
B4
B2
v2 = v1 + b*b;
-
Hierarchy
-
Order
PE3
IProtocolSlav
e
SoC Design
Objects
- Computation
- Proc
- IPs (Arbiters)
- Memories
- Communication
- Protocol bus
channels
1: master interface
2: slave interface
3: arbitor interface
v4 = v2 + v3;
c = sequ(v4);
-Sequential
-Parallel
-Piped
-States
- Synchronization
-Notify/Wait
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•Time/cycle accurate communication (time constraint)
•Approximate timed computation
•Protocol channel provides functions for all abstraction bus transaction
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E: “Cycle-Accurate Computation Model”
SoC Design
Objects
- Computation
- Proc
- IPs (Arbiters)
- Memories
- Wrappers
- Communication
- Abstract bus
channels
Composition
PE4
S0
-
Hierarchy
-
Order
S1
S2
S3
-Sequential
-Parallel
4
PE1
PE3
MOV r1, 10
MUL r1, r1, r1
....
3
4
S0
cv12
cv2
1
cv11
PE2
MLA
...
r1, r2, r2, r1
....
S1
2
4
S2
S3
S4
4
1.
2.
3.
4.
Master interface
Slave interface
Arbiter interface
Wrapper
-Piped
-States
- Synchronization
-Notify/Wait
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• Modeled at register-transfer level
• PE are pin accurate and execute cycle-accurately
• Wrappers convert data transfer from higher level of abstraction to lowe
r level abstraction
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F: “Implementation Model”
SoC Design
Objects
- Computation
- Proc
- IPs (Arbiters)
- Memories
- Communication
-Buses (wires)
PE1
req
Composition
PE2
interrupt
interrupt
MOV r1, 10
MUL r1, r1, r1
....
MLA
req
...
r1, r2, r2, r1
....
MCNTR
MADDR
MDATA
-
Hierarchy
-
Order
-Sequential
-Parallel
PE4
PE3
-Piped
S0
S0
S1
interrupt
-States
S1
S2
S2
S3
- Synchronization
S3
S4
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-Notify/Wait
SOC Design Tasks
1. PE assembly and model generation
SoC Design
Specification
model
2. Communication exploration and busarbitration model generation
1
PE-assembly
model
System
Design
3. Protocol refinement and time-accurate
communication model generation
2
4. RTL/ISS* synthesis
Bus-arbitration
model
7
3
8
5. IP replacement
5
Time-accurate
Communication
model
Cycle-accurate
Computation
model
6. Interconnect network generation
7. Accurate communication feedback
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4
Component
Design
Implementation
model
6
8. Accurate computation feedback
* ISS : Instruction set simulator
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SOC Design Tasks
Communication
SoC Design
Cycletimed
D
4
F
3
Approximatetimed
C
6
5
E
2
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Untimed
1
A
Untimed
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B
Approximatetimed
Cycletimed
Computation
Characteristics of Different Abstraction Models
SoC Design
Models
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Specification
model
Componentassembly model
Bus-arbitration
model
Bus-functional
model
Cycle-accurate
computation
model
Implementation
model
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Communication
time
no
Computation
time
no
Communication
scheme
variable
PE interface
no
approximate
variable channel
abstract
approximate
approximate
abstract
time/cycle
accurate
approximate
approximate
cycle-accurate
abstract bus
channel
protocol bus
channel
abstract bus
channel
cycle-accurate
cycle-accurate
bus (wire)
(no PE)
abstract
pin-accurate
pin-accurate
References
SoC Design
The credit of these slides goes to:
 D. Gajski, L. Cai, “Transaction Level Modeling: An Overview”, Center for Embedded Computer Sy
stems, University of California, Irvine, 2004.
 Z. Navabi, “The Role of SystemC in theEvolution of Hardware Design”, Worcester Polytechnic Ins
titute.
 B. Vanthournout, “SoC design methodology Using SystemC”, Coware, 2003.
 F. Ghenassia, “Transaction Level Modeling with SystemC: TLM Concepts and Applications for E
mbedded Systems, Springer, 2005.
& Others
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