⭐ MODULE–I : INTRODUCTION TO
VERILOG HDL (DETAILED EXAM NOTES)
1. Introduction to Verilog HDL
Verilog HDL is a hardware description language used to model, design, simulate and
synthesize digital circuits at different levels of abstraction.
The book explains that HDLs emerged as digital systems became more complex, and
designers required a standard language to describe behavior and structure of circuits (page
4) .
Need for Verilog
●​ Earlier designs used schematic entry → difficult for large designs
●​ Digital complexity increased → CAD tools evolved
●​ Designers needed a behavioral/structural language to describe system architecture
before fabrication
Features of Verilog
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Describes circuits at RTL, gate-level, and switch-level
Allows functional verification before fabrication
Supports both procedural and concurrent modeling
C-like syntax → easy to learn
Industry-standard language for ASIC/FPGA design
2. Popularity of Verilog HDL
As explained in section 1.5 Popularity of Verilog HDL (page 7) , Verilog became widely
adopted because of:
Reasons for Popularity
1.​ Simple and easy to learn​
Verilog resembles C language → easier for programmers and engineers.
2.​ Fast simulation​
Efficient event-driven simulators enable quick testing.
3.​ Supported by most CAD/EDA tools​
Simulation + synthesis tools widely support Verilog RTL.
4.​ Library support​
All fabrication vendors provide Verilog libraries for gate-level & post-synthesis
simulation.
5.​ Supports design reusability​
Modules can be reused across designs.
6.​ Powerful PLI (Programming Language Interface)​
Allows integration of C programs with Verilog simulators.
7.​ Ideal for large digital systems​
Handles behavioral to gate-level descriptions effectively.
3. Module Concept
Module is the basic building block of Verilog (page 15) .
●​ A module can be can element or a collection of lower level design blocks.
●​ Elements are grouped into modules to provide common functionality that is used at
many places in the design
●​ A module provides the necessary functionality to the higher level block through its
port interface, but internal implementation
●​ This allows the designer to modify module internals without affecting the rest of
design
Definition
●​ A module is declared by the keyword ‘module’, a corresponding keyword endmodule
must appear at the end od the module definition.
●​ module_name -> identifier for module
●​ module_terminal_list -> describes input and output terminals
General Syntax
module module_name(port_list);
// signal declarations
// behavioral/gate/dataflow description
endmodule
Key points
●​ A module provides a template; each instantiation creates unique hardware.
●​ Modules cannot be nested (page 18) .
●​ Supports hierarchical modeling through instantiation.
4. Module Modeling Styles (Levels of
Abstraction)
1) Behavioral or Algorithmic Level
Highest level of abstraction provided by verilogHDL, A module can be implemented in terms
of the desired design algorithm without concern for the hardware implementation details,
Designing at this level is very similar to C programming
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Uses sequential statements
Describes algorithm-like behavior
Implemented using always blocks
Example: FSMs, counters
2) Dataflow Level
At this level the module is designed by specifying the data flow, The designer is aware of
how data flows between hardware registers and how the data is processed in the design.
●​ Describes flow of data through operators
●​ Uses continuous assignments (assign)
●​ Represents combinational logic efficiently
3) Gate-Level Modeling
The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.
●​ Describes logic using primitive gates (and, xor, or, not)
●​ Structural representation close to schematic
4) Switch-Level Modeling
This is the lowest level of abstraction provided by verilogHDL. A module can be implemented
in terms of switches , storage nodes, and the interconnections between them. Design at this
level requires knowledge of switch-level implementation details.
●​ Uses transistor-level switch primitives (nmos, pmos)
●​ Only for specialized VLSI models
Verilog allows the designer to mix and match all four levels of abstractions in a design.
If a design contains four modules, Verilog allows each of the modules to be written at a
different level of abstraction. As the design matures, most modules are replaced with
gate-level primitives
RTL -> behavioural + dataflow constructs
5. Language Elements
(From “Basic Concepts”, Chapter 3, page 27 onwards)
5.1 Whitespaces
●​ Blankspaces (\b)
●​ Tabs (\t)
●​ Newlines (\n)
5.2 Comments
●​ Single-line: // comment
●​ Multi-line: /* comment */
Used to improve readability and maintainability.
5.3 Operators
There are three types - unary , binary , ternary
// a = ~b;
●​ Unary -> precede the operand
●​ Bindary -> in between two operands
// a = b && c;
●​ Ternary -> two separate operators that separate three operands // a= b ? c: d;
5.4 Number specification
Number specification describes how constants (numeric literals) are written in Verilog.​
This is essential because Verilog supports:
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Multiple bases
Sized and unsized numbers
Signed/unsigned values
4-state logic (0,1,x,z)
1. General Format (Very Important for Exams)
Verilog uses the format: <size>’<base><number>
Where:
1. Size
●​ Specifies how many bits the number occupies.
●​ Example:
○​ 4 → 4-bit number
○​ 8 → 8-bit number
2. Base
Written after an apostrophe '.
Symbol
Base
Meaning
'b
binary
digits 0,1,x,z
'o
octal
digits 0–7,x,z
'd
decimal
digits 0–9
'h
hex
digits 0–F,x,z
3. Number
●​ May contain 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f
●​ Case-insensitive
●​ Underscore _ allowed for readability
Examples
4'b1010
// 4-bit binary
8'hAF
// 8-bit hexadecimal
6'o25
// 6-bit octal
12'd255
// 12-bit decimal
2. Unsized Numbers
If no size is specified, number is at least 32 bits (or tool-dependent).
Examples:
255
// unsized decimal, automatic width
'hF
// unsized hex
3. Signed and Unsigned Numbers
●​ By default: Unsigned
●​ signed keyword makes a vector signed:
reg signed [7:0] a;
Signed arithmetic follows 2’s complement rules.
4. Using x and z in Numbers
Verilog supports unknown (x) and high-impedance (z) in literals:
4'b1x0z
8'hxF
12'dz
Used for:
●​ RTL modeling
●​ Don’t-care optimization
●​ Testbench stimulus
5. Negative Numbers
Written only in decimal:
-25
// decimal only
Cannot write:
-4'b0011
// INVALID
But this is valid:
-(4'b0011)
6. Real Numbers
Written using decimal format:
3.14
0.001
1e-3
Real numbers cannot be used in hardware synthesis, only simulation.
7. Underscore for Readability
You can insert _ anywhere except at the beginning:
32'hFF_FF_AA_10
8'b1010_0101
Improves readability; value unchanged.
Quick Integrated Examples
1. Represent 10 in:
Binary: 4'b1010​
Hex: 4'hA​
Decimal: 4'd10
2. Represent unknown 8-bit value - 8'bxxxx_xxxx
3. Represent tri-state 4-bit bus - 4'bzzzz
5.5 Identifiers
Identifiers are names given to objects so that they can be referenced in the design.
Rules:
●​ Start with letter or underscore
●​ Alphanumeric or underscore and dollar sign ( $ ) allowed​
Example: a1, _temp, sum_out
Escaped identifiers:
Begin with backslash character and end with whitescape.All characters between backslash
and whitespace are processed literally.Any printable ASCII character can be included in
escaped identifiers
Example: /a+b-c
5.6 Keywords
●​ Keywords are special identifiers reserved to define the language constructs.
●​ Keywords are in lowercase
Reserved words with fixed meaning.​
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Examples: module, assign, always, if, case, endmodule.
5.7 Value Set
Verilog uses a 4-value logic system:
●​ 0 → logic low
●​ 1 → logic high
●​ x → unknown
●​ z → high-impedance (tri-state)
Essential for modeling real digital hardware.
5.8 Data Types
1. Nets (wire, tri)
Nets are one bit values by default unless they are declared explicitly as vectors.
The default value of net is z, trireg is x
●​ Represent physical connections (wires)
●​ Must be driven continuously
●​ Cannot store values​
Used with continuous assignments and gate outputs.
Example : wire a;
2. Registers (reg)
A reg stores a value until modified.​
It represents variables used inside procedural blocks (always, initial).​
It does not imply a hardware register unless used inside clocked logic.
Syntax
reg a;
reg [3:0] data;
// 4-bit register
3. Vectors
Vectors represent multibit signals using a range.
reg [7:0] A; mem [0:255];
4. Arrays and Memories
Array of registers (2-D data type).
Syntax
reg [7:0] array_name [0:15];
This means: 16 elements, each 8 bits.
Example
reg [7:0] mem [0:3];
// 4 x 8-bit
initial begin
mem[0] = 8'hA1;
mem[1] = 8'hB2;
mem[2] = 8'hC3;
mem[3] = 8'hD4;
end
Memories are modeled using arrays of reg.
Syntax
reg [7:0] RAM [0:255];
// 256 x 8-bit memory
Writing & Reading
always @(posedge clk)
RAM[address] <= data_in;
assign data_out = RAM[address];
Models RAM blocks.Used to model ROM/RAM.
5. Integers, real, time-types
Used in simulations and algorithms.
Integer type Default width 32 bit signed
integer i;
Real type Used to represent floating-point numbers (simulation only; not synthesizable).
real pi;
Time type Used for storing simulation time. Typically 64-bit.
time t1;
5.10 Constants
Format (size’basevalue):
●​ Bases: b (binary), h (hex), d (decimal), o (octal)
Examples:
●​ 4'b1010
●​ 8'hAF
●​ 16'd255
5.11 Strings
Verilog stores strings as an array of 8-bit ASCII values.
Syntax
reg [8*12:1] str;
// 12-character string
Example
reg [80*8:1] message;
initial begin
message = "Hello Verilog";
$display("%s", message);
end
5.12 Parameter
Parameters are compile-time constants used to make modules configurable.
Example:
parameter WIDTH = 8;
System tasks start with $ and are used for display, monitor, and controlling simulation.
$display
Prints formatted output once.
Syntax $display("format", variables);
Example $display("Sum = %d", sum);
$monitor
Continuously prints values whenever any variable in the list changes.
Syntax $monitor("A=%b B=%b Y=%b", A, B, Y);
Example
initial
$monitor("time=%0t A=%b B=%b", $time, A, B);
$stop
Pauses the simulation and returns control to the simulator console (debugging).
Example
if (error_flag)
$stop;
$finish
Ends the entire simulation.
Example
initial begin
#100;
$finish;
end
6. Dataflow Modeling
Dataflow modeling uses continuous assignments to represent combinational circuits.
6.1 Continuous Assignment
Syntax: assign out = expression;
Properties:
●​ Executed whenever RHS changes
●​ Represents concurrent operations
●​ Used for combinational logic
Example: assign sum = a ^ b;
6.2 Implicit Continuous Assignment
Combine declaration + assign:
wire carry = a & b;
Used for cleaner code.
6.3 Delays in Continuous Assignment
1) Inertial Delay
Default delay → filters pulses shorter than delay.
assign #5 y = a & b;
2) Transport Delay
Used to model actual propagation delays (discussed in Timing & Delays chapter).
Purpose: model real hardware timing behavior.
7. Design Examples using Dataflow
Modeling
Example 1: Half Adder
assign sum
= a ^ b;
assign carry = a & b;
Example 2: Full Adder
assign sum
= a ^ b ^ cin;
assign carry = (a & b) | (a & cin) | (b & cin);
Example 3: 2-to-1 Multiplexer
assign y = s ? d1 : d0;
Example 4: Comparator
assign eq = (a == b);
assign gt = (a > b);
assign lt = (a < b);
MODULE SUMMARY (Ready for
last-minute revision)
●​ Verilog is a HDL used for modeling digital circuits at multiple abstraction levels.​
●​ Popular because of simplicity, C-like syntax, fast simulation, and widespread tool
support.​
●​ Module is the fundamental design unit; supports hierarchical design.​
●​ Modeling styles: Behavioral, Dataflow, Gate-level, Switch-level.​
●​ Language basics include identifiers, keywords, data types, constants, parameters.​
●​ Dataflow modeling uses continuous assignments (assign).​
●​ Delays model hardware timing.​
●​ Common examples include adders, multiplexers, comparators.