Tiling in Software
Tiling (also called loop tiling or blocking) is a loop transformation technique used to
improve cache performance by restructuring how data is accessed in memory.
The Core Idea
Instead of iterating over a large dataset in a way that causes frequent cache misses, you
break the iteration space into smaller "tiles" (blocks) that fit in cache, and process each
tile completely before moving to the next.
The tile size T is chosen so the working set fits in a cache level (L1, L2, etc.).
Why It Matters for NPUs/ML Hardware
Tiling is central to neural network accelerator design:
 Matrix multiplications in FC layers and attention are tiled to fit in on-chip SRAM
(scratchpad memory)
 Convolutions are tiled across input channels, output channels, and spatial dims
 The dataflow (weight-stationary, output-stationary, row-stationary) dictates which
tile stays resident and which streams through
 Hardware systolic arrays (like in TPUs) are essentially a physical implementation
of a tiled computation
TileLink — Completely Different
TileLink is a chip-level cache-coherent interconnect protocol, developed as part of
the RISC-V/Chisel/RocketChip ecosystem (UC Berkeley / SiFive).
It defines how tiles (CPU cores, accelerators, memory controllers) communicate with
each other on-chip — think of it as an on-chip bus/NoC protocol, analogous to ARM's
AXI/ACE or Intel's CCI.
They share the word "tile" but are completely unrelated concepts. In NPU work you'll
likely encounter both — tiling when thinking about compute scheduling, and TileLink if
you're integrating with a RISC-V SoC fabric in Chipyard.