THE CITY COLLEGE OF NEW YORK
Department of Electrical Engineering
EE210 (S) — Switching Systems — Spring 2026
_________________________________________________________________
DESIGN PROJECT REPORT
Due: 05/12/26
Name: Fanta Kante
Professor: A. Cano Martinez
Table of Contents
1. Objective ................................................................................................................................ 3
2. System Description................................................................................................................ 3
2.1 Inputs, Outputs, and Function ................................................................................................... 3
2.2 Mathematical Interpretation ...................................................................................................... 3
3. Experimental Procedure and Implementation ................................................................... 3
Step 1: Build the Main Digital Timing Circuit ............................................................................... 4
Work Performed ................................................................................................................................... 4
Verification .......................................................................................................................................... 4
Step 2: Design and Build a 7-Segment Display Driver .................................................................. 4
Algebraic Expressions via Combinational Analysis ............................................................................ 5
Boolean Expressions for Segments a–g ............................................................................................... 6
Verification of Minimization ................................................................................................................ 7
K-Map Groupings (Figures 4–11) ....................................................................................................... 8
Circuit Implementation and Testing .................................................................................................... 9
Integration into the Main Circuit ...................................................................................................... 11
Step 3: Design and Build a 1-Bit Full Adder ................................................................................ 13
Truth Table and K-Map Analysis ....................................................................................................... 14
Boolean Expressions (S and Cout) .................................................................................................... 15
Circuit Implementation and Testing .................................................................................................. 16
Step 4: Design and Build a 2-Bit Multiplier ................................................................................. 16
Truth Table and K-Map Analysis ....................................................................................................... 18
Boolean Expressions (w, x, y, z) ......................................................................................................... 18
Circuit Implementation and Testing .................................................................................................. 19
Using a Splitter for Constant Inputs.................................................................................................. 20
Step 6: Final Design Verification .................................................................................................. 21
Connection Check .............................................................................................................................. 22
Simulation Testing ............................................................................................................................. 23
Step 7: Analysis and Discussion ................................................................................................... 24
State Table for Complete System ....................................................................................................... 24
Timing Trace Correspondence........................................................................................................... 25
Oscilloscope Timing Analysis ............................................................................................................ 25
Observed Behavior ............................................................................................................................ 25
8. Conclusion ........................................................................................................................... 25
1. Objective
This report details the design, implementation, and testing of a 1-bit moving
average system using Logisim simulation software Version 3.9.0. The system
computes the arithmetic average of two consecutive 1-bit input values, producing a
1-bit output Z = (A+B)/2. The design process involved creating multiple
subcircuits (7-segment display driver, 1-bit full adder, and 2-bit multiplier) and
integrating them into a main timing circuit with clock synchronization.
2. System Description
A 1-bit moving average system has:
•
Input: 1-bit binary signal (A)
•
Output: 1-bit binary signal (Z)
•
Function: Z = (A + B)/2, where B is the previous input value
•
Behavior: Output is HIGH (1) only when both current and previous inputs
are HIGH (1)
Mathematical Interpretation:
•
(0+0)/2 = 0 → Output: 0
•
(0+1)/2 = 0.5 → Output: 0 (rounded down)
•
(1+0)/2 = 0.5 → Output: 0 (rounded down)
•
(1+1)/2 = 1 → Output: 1
3. Experimental Procedure and Implementation
Step 1: Build the Main Digital Timing Circuit
Work Performed:
The main digital timing circuit was constructed with the following components:
•
•
•
•
A Clock component for clear visual observation
A Random Generator produces 1-bit input A
A D Flip-Flop with D input connected to signal A and clock to system clock
A Digital Oscilloscope shows A, B, and Z timing
Verification:
An initial simulation was run and the oscilloscope confirmed that signal B was a
one-cycle-delayed copy of signal A, updating precisely on the rising edge of each
clock pulse. This verified that the D flip-flop correctly captured and stored the
previous input value. Whenever A transitioned from 0 to 1 or from 1 to 0, B
adopted that value on the following clock edge, consistent with expected D flipflop behavior.
Figure 1: Main timing circuit.
Step 2: Design and build a 7-Segment Display Driver
Algebraic Expressions using Combinational Analysis:
I used Logisim's Combinational Analysis tool to efficiently derive the
minimized Boolean expressions for the 7-segment display driver. I entered the
truth table from Table 2.6 (p. 36) with inputs W, X, Y, Z and outputs a through g.
For inputs 1010 through 1111 (10-15), I set them as "don't care" (X) conditions to
enable maximal minimization.
The input variables (W, X, Y, Z) and output variables (a through g) were defined as
shown below.
Figure 2: Input and Output Variables
Figure 2: Truth Table Input into Combinational Analysis
Results from Combinational Analysis:
The tool automatically generated minimized Sum of Products expressions for each
segment:
Figure 3: Sum of Product expressions for each segment
Segment a: a = X'Z' + W + Y+ XZ
Segment b: b = X' + Y'Z' + YZ
Segment c: c = X + Z + Y'
Segment d: d = X'Z' + X'Y+ XY'+ YZ'
Segment e: e = Z'(X' + Y)
Segment f: f = Y'Z' + W + X
Segment g: g = XY' + X'Y + W + YZ’
Verification of Minimization:
The minimized expressions were cross-verified by substituting several input
combinations and comparing the results against the original truth table, confirming
correctness for all tested cases.
Visualization of K-Map Groupings:
The K-map groupings used to derive the minimized expressions are shown below
for each segment output a to g
Figure 4: K-map of 7-Segment display output
Figure 5: Segment a K-Map
Figure 6: Segment b K-Map
Figure 7: Segment c K-Map
Figure 8: Segment d K-Map
Figure 9: Segment e K-Map
Figure 10: Segment f K-Map
Figure 11: Segment g K-Map
Circuit Implementation and Testing:
Using the expressions generated by Combinational Analysis, I created a new
Logisim circuit named display_driver with 4 input pins (W, X, Y, Z) and 7 output
pins (a-g). I implemented each Boolean expression using the appropriate logic
gates:
•
AND gates for product terms
•
OR gates for sum terms
•
NOT gates for complemented inputs
I connected a 7-Segment Display to the outputs and tested all decimal digits 0-9 by
applying the corresponding binary inputs (0000 through 1001). The display
correctly showed each digit according to the mapping.
Figure 12: Diagram circuit generated by Combinational Analysis
Figure 13: Testing with 7-Segment display
Integration into the Main Circuit
Three instances of the display_driver subcircuit were added to the main
moving-average circuit to visualize the values of A, B, and Z on separate 7segment displays, as shown in Figure 2.
•
•
Display for A:
The 1-bit signal A was connected to the Z (LSB) input of the display_driver.
The remaining inputs W, X, Y were tied to logic 0, forming the 4-bit
value 000A for proper decoding on the 7-segment display.
Display for B:
The delayed signal B (output of the D flip-flop) was also connected to the Z
•
(LSB) input of its display_driver instance, with W, X, Y grounded.
This ensures the driver interprets the value as 000B.
Display for Z:
The output of the moving-average system, Z, was connected to the Z
(LSB) input of the third display_driver, again grounding W, X, Y to
display 000Z.
Each display_driver output was routed to a separate 7-segment display
component, allowing real-time visualization of the values 0 and 1 during
simulation.
Figure 14: Adding Display_driver to the main circuit
Step 3: Design and build a 1-Bit Full Adder
Algebraic Expressions and K-Maps:
I referred to the truth table in Table 1.5 (p. 10) for a 1-bit full adder. I constructed
two K-maps, one for Sum (S) and one for Carry-out (Cout)
Truth Table (Table 1.5 from textbook):
A
B
Cin
S
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
K-Map Solutions:
Circuit Implementation:
I created a new Logisim circuit named one_bit_full_adder with three inputs (A,
B, Cin) and two outputs (S, Cout). I tested then added one instance to the main
circuit, connecting A and B from the timing circuit and setting Cin to ground (0) as
specified.
Figure 15: 1-bit full adder diagram circuit
Figure 16: Testing the 1-bit full adder with display_driver circuit
Figure 17: Adding and connecting 1-bit full adder to the main circuit
Step 4: Design and build a 2-Bit Multiplier
Truth Table and K-Map Analysis:
A complete truth table was constructed for the multiplication of two 2-bit operands
(a, b) and (c, d), producing a 4-bit product (w, x, y, z). Four K-maps were then
derived, one for each output bit, to obtain minimized Boolean expressions.
Truth Table of 2-Bit Multiplier
a
b
c
d
w
x
y
z
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
K-Map Solutions:
Circuit Implementation:
Figure 18: Diagram circuit of 2-Bit Multiplicator
Testing:
The multiplier was verified by connecting the four output bits to 7-segment display
drivers and exhaustively testing all 16 input combinations, confirming correct
products in every case.
Figure 18: Testing 2-Bit multiplicator circuit
Figure 19: Adding 2-Bit Multiplicator circuit
Figure 20: Connecting 2-Bit Multiplicator circuit
Using a Splitter
Since Logisim doesn't have a direct 2-bit constant component, we use a Splitter to
break a multi-bit constant into individual bits:
Figure 22: the constant, splitter, and multiplier connections
Step 6: Final Design Verification
Connection Check:
All wiring was systematically verified against the reference schematic (Figure 1).
Connections were confirmed for every major subsystem: the clock source, random
generator, D flip-flop, 1-bit full adder, 2-bit multiplier, and all three 7-segment
display drivers.
Simulation Testing:
I ran an extended simulation and observed:
•
Oscilloscope showed correct timing relationships
•
Z was HIGH only when both A and B were simultaneously HIGH
•
7-segment displays correctly showed decimal 0 or 1 for A, B, and Z
Figure 23: Complete Circuit
Step 7: Analysis and Discussion
State Table for Complete System:
Present State (B)
Input (A)
Next State (B)
Output (Z)
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
Timing Trace Correspondence:
The oscilloscope waveforms are consistent with the state table predictions:
•
When B=0 and A=1: Next state becomes B=1, output Z=0
•
When B=1 and A=1: Next state remains B=1, output Z=1
•
Each transition occurs on the clock edge, matching state table predictions
Oscilloscope Timing Analysis
The oscilloscope screenshot shows:
•
Top trace = A (random bit)
•
Middle trace = B (A delayed by one cycle)
•
Bottom trace = Z (average output)
Observed Behavior
1. B always matches the previous value of A, confirming the D-flip-flop works.
2. Z rises only when A and B are both 1, consistent with the truth table.
3. The waveforms align exactly with the expected timing relationships.
This verifies that the system behaves correctly under real-time simulation.
8. Conclusion
In this project, a fully functional 1-bit moving average system was designed
and implemented in Logisim using only basic digital components and custom
combinational circuits.
All required subcircuits—the 1-bit full adder, 2-bit multiplier, and 7-segment
display drivers—were constructed from Boolean expressions derived via truth
tables and K-map minimization.
The oscilloscope output confirms correct timing:
•
B is always the delayed version of A
•
Z correctly outputs the moving average bit
The completed system satisfies all design specifications and demonstrates core
principles of both combinational and sequential digital logic design.