Computer Architecture & Assembly
Language
William Stallings Computer Organization and Architecture 10th Edition
Lecture 5 →Chapter 4
—Cache Memory
By Dr Hussein Omran, akhbar El Yom Academy, Egypt 2020
2-associative Mapping memory to cache
Cache mapping options – 8 cache slots
01234567
Fully associative
19 mod 1 = set 1 (All slots)
All memory line map to any available line in cache
Tag=Address length= n
01234567
.......
19
w
31
Associative Mapping
• A main memory block can load into any line of
cache
• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
• Cache searching gets expensive
Fully Associative Cache Organization
Example: fully Associative Mapping Address Structure
• 16MBytes main memory=224Byte →n= 24 bit address
Word 2 bit
Tag 22 bit
• Cache block length of 4 bytes =22Byte w=2
—i.e. cache lines has 4 bytes per lines
— 22 bit tag stored with each 32 bit block of data
(4byte=4x8=32) L=22 bit
• e.g.
— Address
— FFFFFC
Tag
FFFFFC
Data
24682468
Cache line
3FFF
Example, system with 64KB of main memory and 1KB
cache memory, 8 words per line/block
• Main memory: 64kB=26x210=216B
n=ln 216 =16
• Line/block size=8 byte=23
w=3
• Tag=n-w=16-3=13 bit
Tag=Address length= n-w=13 w
13 bits
Frame
8 bytes/frame
0
1
Line number
0
1
2
3
4
5
8 bytes/line
Cache
…
127
2
3
4
5
…
8191
Tag area
Comparator
Tag
Data Area
Hit/Miss
Word
Main memory
Address (A)
Bits in main memory address: 16
Problem-01: Consider a fully associative mapped cache of size 16 KB with block size 256 bytes.
size of main memory is 128 KB. FindNumber of bits in Tag directory size
Solution1-Size of main memory = 128 KB = 217 bytes
Thus, Number of bits in physical address =n= 17 bits
2- Cache line block size = 256 bytes= 28 bytes “word”
Thus, ward identifier for word number = 8 bits = W
3- Number of bits in tag=bits in physical address– bits in block offset →tag=n-w=17 bits – 8 bits
= 9 bits
• Number of bits in tag = 9 bits
Tag directory size
number of lines in cache=Cache size/Line size
=16KB/256 bytes = 214 bytes / 28 bytes = 26 lines→ L=6
Tag directory size= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag= 26 x 9 bits
= 576 bits= 72 bytes Thus, size of tag directory = 72 bytes
Associative Mapping Summary
• Number of lines in cache = undetermined
• Size of tag = n-w bits
Tag=Address length= n-w
w
3-Set Associative Mapping
• Cache is divided into a number of sets
• Each set contains a number of lines
• A given block maps to any line in a given set
— e.g. Block B can be in any line of set i
• e.g. 2 lines per set =2 way associative mapping
— A given block can be in one of 2 lines in only one set
0 1 2 3 4 5 6 7 Cache mapping options – 4 sets---block size =4 lines
Set# 0
1
2
0 1 2 3 4 ..........
3
2-way set associative where it has 4 sets
Set number=19 mod 4 = set 3 (slots 6 or 7)
Mem blocks 3,7,11,15,19,23,27,31 map to set 3
19
31
Main
memory
blocks
Example Set Associative Mapping
• 13 bit set number i.e. the set address with 13 bit
• Block number in main memory is modulo 213 (set
number)
• 000000, 00A000, 00B000, 00C000 … map to same
set
Set Associative Mapping
Address Structure
Tag 9 bit
Set 13 bit
Word
2 bit
• Tag=bits main memory address-(bits of sets address
in cash – bits of word address)
• Use set field to determine cache set to look in
• Compare tag field to see if we have a hit
• e.g
—Address
—1FF 7FFC
—001 7FFC
Tag Data Set number=of address13 bit
1FF 12345678 1FFF
001 11223344 1FFF
Mapping From Main Memory to Cache:
k-way Associative K=number of lines in each set
Set Associative Mapping Summary
• Address length = (n + w) bits
• Number of addressable units = 2n+w words or
bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2d
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (n – d) bits
Problem-01: Consider a 2-way set associative mapped cache of size 16 KB with block size
256 bytes. The size of main memory is 128 KB. Find- Number of bits in tag and Tag
directory size
Solution1-Number of Bits in Physical AddressSize of main memory= 128 KB= 217 bytes
Thus, Number of bits in physical address = n=17 bits
2-Number of Bits in Block Offset- We have,
Block size= 256 bytes= 28 bytes Thus, Number of bits in block offset = 8 bits
3-Number of Lines in Cache=Cache size/Line size=16KB/256B=214/28=64 lines
Thus, Number of lines in cache = 64 lines
4-Number of Sets in Cache (2-way set =2)= number of lines in cache / Set size=
64/2= 32 sets = 25 sets→ Thus, Number of bits in set number = 5 bits
5-Number of bits in tag= Number of bits in physical address – (Number of bits
in set number + Number of bits in block offset)= 17 bits – (5 bits + 8 bits) =
=17 bits – 13 bits = 4 bits
Thus, Number of bits in tag = 4 bits
6-Tag directory size = Number of tags x Tag size
= Number of lines in cache x Number of bits in tag= 64x4 bits= 256 bits=32B
Thus, size of tag directory = 32 bytes
Assynment
Problem-02: Consider a 8-way set associative mapped cache of size
512 KB with block size 1 KB. There are 7 bits in the tag. Find- Size of
main memory Tag directory size
SolutionProblem-03: Consider a 4-way set associative mapped cache with block
size 4 KB. The size of main memory is 16 GB and there are 10 bits in
the tag. FindSize of cache memory Tag directory size
SolutionProblem-04: Consider a 8-way set associative mapped cache. The size
of cache memory is 512 KB and there are 10 bits in the tag. Find the
size of main memory.
SolutionProblem-05:Consider a 4-way set associative mapped cache. The size
of main memory is 64 MB and there are 10 bits in the tag. Find the size
of cache memory.
Solution- consider that the memory is byte addressable.
Direct and Set Associative Cache
Performance Differences
• Significant up to at least 64kB for 2-way
• Difference between 2-way and 4-way at 4kB much
less than 4kB to 8kB
• Cache complexity increases with associativity
• Not justified against increasing cache to 8kB or
16kB
• Above 32kB gives no improvement
• (simulation results)