EE 3331
Homework #4
Due: Friday March 27
Problem #1 – Consider the Class A BJT output stage discussed in class with ±9V power supplies and a dc current
of 50 mA. The output voltage range of the amplifier is ±6V.
a) If the load resistance RL = 200 Ω and the peak output voltage is 6 V, find the average power delivered to the
load and the average power drawn from the supplies (neglect losses in the diode connected transistor Q3). Also
find the efficiency.
b) For the conditions in a), find the maximum and the minimum values of the emitter current in the CC transistor.
c) What is the minimum value of RL for which the stage work properly (for the output voltage range specified in
the problem statement).
Problem #2 – Consider a BJT class B output stage with ±10V power supplies, a sinusoidal input, and a 100 Ω load
resistance. Include the effect of VCE,sat in your calculations.
a) If the output stage operates at maximum peak output voltage: find the power delivered to the load, the average
power drawn from the supplies, and the power conversion efficiency. What is the average power dissipated in
each transistor for this output?
b) For an output signal half the amplitude of the output in a), find the power delivered to the load, the average power
drawn from the supplies, and the efficiency. What is the average power dissipated in each transistor for this
output?
Problem #3 Consider a class AB BJT circuit with VCC = 15 V, IQ = 2 mA and RL = 100Ω. Assume Qn and Qp to be matched and
IS = 10-13 A.
a) Determine VBB
b) Compute iL, iN, iP, vBE1 = vBE,npn, vEB2=vEB,pnp, and vI for vO = 0
c) Compute iL, iN, iP, vBE1 = vBE,npn, vEB2=vEB,pnp, vI and vO/vI (this is the large signal gain) for vO = 1V
Problem #4 - For the op-amp in Fig. 4: kn’ = 25 µA/V2, kp’ = 10 µA/V2, |VT| = 1 V, and λ = 0.017 V-1 for all
transistors. The W/L ratios of the transistors are shown in the figure.
a) Find the dc currents I1, I2, and I3. Neglect λ for this part. What type of output stage is used in this amplifier?
b) Find the differential voltage gain. Use vid = v1 – v2 and assume that the gain of the output stage is ~1.
Problem #5 - For the three-stage amplifier in Fig. 6, β = 100 for all transistors. Neglect the Early effect. For the DC
analysis assume IB2 << IC1 and IB3<< IC2.
a) Find the dc bias current in each of the three transistors. Also find the dc voltage at the output. Assume |VBE| = 0.7
V. Find the input resistance and the output resistance of the amplifier.
b) Find the voltage gain vo/vi.
VDD= 10 V
Q3
80/1
I2
Q4
80/1
I3
+10 V
Q5
120/1
v1
Q1
40/1
Q2
40/1
v2
75µA
vo
I1
5/1
Q9
10/1
Q8
-VDD= -10 V
Figure 4
Q10
15/1
Q7
25/1
+10 V
5.1 kΩ
4.5 kΩ
82 kΩ
Q6
10/1
Q11
5/1
+10 V
+10 V
C
Q2
Q3
V
Q1
i
C
Vo
10.6 kΩ
C
10 kΩ
100 kΩ
9.5 kΩ
-10 V
-10 V
-10 V
Figure 5
(Practice) Problem #6: For the op-amp in Problem #4, find the common-mode voltage gain.
-10 V