EC311: Introduction to Logic Design
Verilog Intro
Prof. Tali Moreshet
Simulation/
Functional Verification
Design Process
VHDL / Verilog
compilation/
synthesis
mask layout patterns
find wire routes
design schematics
device layout
• Design development is facilitated using Computer-Aided Design (CAD) tools
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Implementation
tapeout
mask layout patterns
mask writer
printing
test and
packaging
chip
masks
dice
die
wafer
A Few Terms
• HDL – Hardware Description Language
– E.g. Verilog, VHDL
• ASIC – Application Specific Integrated Circuit
– Custom designed and fabricated
• FPGA – Field-Programmable Gate Array
– Pre-manufactured, programmable hardware
• CAD – Computer-Aided Design
– Synthesize HDL code to the logic
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Design Process Steps
• Spec
• Behavioral/ Structural Verilog (hierarchical)
– Functional verification, simulation
• Synthesis to gate-level netlist and mapping
– Design validation, simulation, timing verification
• Test generation and fault simulation
• Place and route
• Tape-out
Design Process Steps
• Spec
• Behavioral/ Structural Verilog (hierarchical)
– Functional verification, simulation
• Synthesis to gate-level netlist and mapping
– Design validation, simulation, timing verification
• Test generation and fault simulation
• Place and route
• Tape-out
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Behavioral/Structural Design
• Structural Verilog (hierarchical)
– Netlist / Gate-level
– Individual gates/components and connections
• Behavioral Verilog
– Describe hardware as the behavior of the circuit in
response to inputs
– Looks a lot like C
– CAD tools synthesize to netlist
• Testing and verification
– Testbench
– Simulation
FIGURE 3.35
Example Circuit
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Hierarchical Design
• Modules include interface and structural or
behavioral description of functionality
• Modules can then be instantiated into other modules
• The inputs and outputs of the instantiated module
are connected to nets in the local model
Example 3.1: Gate-Level/Structural
In file named
Simple_Circuit.v
required keyword
module name
port list (inputs & outputs)
//Verilog module: Simple_Circuit
module Simple_Circuit (
output
D, E,
input
A, B, C);
wire
w1;
Semicolon
Single-line comments //
Multi-line comments /* … */
and G1 (w1, A, B); // optional gate instance name
not G2 (E, C);
Instances of modules
or
G3 (D, w1, E);
NO Semicolon
endmodule
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Gate Primitives
• “Built-In” standard logic gates
and
or
not
xor
nand
nor
xnor
• Using Gate Primitives:
and g1(y, a, b, c, d);
Output
Inputs (variable number)
– Why is the output listed first?
a
b
c
d
y
4-Valued Logic
• 0 – logic zero, false
• 1 – logic one, true
• x – unknown or ambiguous value
– Due to a conflict, or lack of initialization
• z – high impedance, no value
– ‘floating’, nothing driving the signal
• Verilog is case sensitive
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Number Representation in Verilog
• <size>'<base><number>
– <size> : number of bits
– <base> : b – binary, d – decimal, o – octal, h – hex
– <number> : the actual number
• Examples:
– 4’b0000 or 4’b0 is the 4-bit binary number 0000
– 2’b11 is the binary number 11
Propagation Delay
• Propagation delay is the time between the transition
of an input and the resulting transition of the output
• Gate propagation delay can be specified in time units
– and #30 G1(w, A, B);
– or #20 G2(D, C, w);
• The delays only affect simulation
• After synthesis gates will be mapped to library gates,
and those have associated delays
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Example 3.2: Gate-Level/Structural with delays
//Verilog model of simple circuit with propagation delay
module Simple_Circuit_prop_delay (
output
D, E,
input
A, B, C);
wire
w1;
These are not synthesizable
and #(30) G1 (w1, A, B); // optional gate instance name
Need to test this circuit!
not #(10) G2 (E, C);
or
#(20) G3 (D, w1, E);
endmodule
Testbench
• Testbench is an HDL module with no ports that
– Provides stimulus (inputs) to a design
– Outputs information about the results
• Time units are proportional to a timescale
• A testbench includes:
– An instance of the module to be verified
– Inputs are declared with keyword reg
– Outputs are declared with keyword wire
• Input stimulus:
– initial keyword declares a block of statements to be
executed at the beginning of the simulation
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Example 3.3:
The testbench
//Testbench for Simple_Circuit_prop_delay
‘timescale 1 ns / 100 ps
// time unit / time precision
module t_Simple_Circuit_prop_delay;
wire
D, E;
// outputs for unit under test
reg
A, B, C
// inputs for unit under test
Simple_Circuit_prop_delay M1 (D, E, A, B, C); // Instance name
//
required
initial
begin
A = 1’b0; B = 1’b0; C = 1’b0;
// at 0ns
#100 A = 1’b1; B = 1’b1; C = 1’b1;
// at 100ns
end
endmodule
FIGURE 3.36
Simulation output of HDL Example 3.3
#30
#20
#10
10
w1
30
100 110
130
150
xxxxxxxxxx
xxxxxxxxxx
xxx
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Data Types – Vectors
• Wires or reg data types can be declared as vectors
• If a bit width is not specified, the default is scalar (1 bit)
wire a;
wire [7:0] b;
wire [31:0] A,B,C;
reg clock;
// scalar wire, default
// 8-bit bus
// 3 buses of 32-bit width
// scalar register, default
• For vector declarations, it is possible to address bits or parts of
vectors:
A[4]
A[2:0]
A[3:1]
// bit # 4 of vector A
// three least significant bits of A
// bits 3, 2, and 1 of A
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Verilog Operators
• Bitwise operators: ~ (negation), &, |, ^ (xor)
– Ex: a=4’b1011, b=3’b010
~a =
a&b =
a|b =
a^b =
a~&b =
• Logical operators: ! (negation), &&, ||, ==, !=
– Zero = false, non-zero = true
– Usually used in conditional statements
(e.g. if (a==4’b0) && (b==1’b1))
Verilog Operators – cont
• Shift: <<, >>
– Ex: a=4’b1011, b=3’b010
– c = a << 3 =
• Concatenation: {A,…,B}
– Ex: c = {a, b[1:0], 1’b1} =
• Conditional assignment: A ? B : C
– Ex: c = (a == 4’b0) ? 2’b1 : 2’b0;
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Example 3.1: Dataflow/Behavioral
// Verilog model: Simple_Circuit_Boolean
module Simple_Circuit_Boolean(
output
D, E,
input
A, B, C);
assign E = ~C;
assign D = (A & B) | (~C);
endmodule
Continuous assignments
Run concurrently
Left hand side must be a wire (or output)
Hierarchy Example
In file named
module my_two_input_AND(
my_two_input_AND.v
output
C,
input
A, B);
and G1(C, A, B);
// AND primitive gate instance named G1
endmodule
2 x my_two_input_AND module instances
module my_three_input_AND(
input in1, in2, in3,
In file named
output out);
my_three_input_AND.v
wire w;
// two my_two_input_AND module instances
// note order ports
my_two_input_AND AND1(.A(in1), .B(in2), .C(w));
my_two_input_AND AND2(.A(w), .B(in3), .C(out));
// alt: my_two_input_AND AND2(out, w, in3);
endmodule
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