ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / OVERVIEW
Session 33 Overview: Components for Beyond 100GHz
RF SUBCOMMITTEE
Session Chair: Jeremy Dunworth
Qualcomm Technologies Inc.
San Diego, CA
Session Co-Chair: Hiroshi Hamada
NTT
Atsugi, Japan
Session Co-Chair: Mona M. Hella
Rensselaer Polytechnic Institute
Troy, NY
(1971-2025)
Systems operating in the frequency range above 100GHz continue to face challenges associated with output power, tuning range,
power consumption, and integration levels. This session explores circuit techniques, advanced transistor technology options, and
package integration and co-design that address such challenges. The session includes an amplifier-multiplier chain with high
output power above 200GHz, a highly integrated GaN PA MMIC and module, two D-band phase shifters, and a G-band VCO. These
papers enable applications in high resolution radars, sensing, spectroscopy, ultra-high speed communications, and others.
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33.1
1:30 PM
A 232-to-260GHz CMOS Amplifier-Multiplier Chain with a Low-Cost, Matching-Sheet-Assisted Radiation Package
and 11.1dBm Total Radiated Power
Jinchen Wang, Massachusetts Institute of Technology, Cambridge, MA
In Paper 33.1, the Massachusetts Institute of Technology describes a 232-to-260GHz amplifier-multiplier-chain (AMC)
array in the Intel16 CMOS process radiating 11.1dBm. This is achieved due to a high-power RF FinFET transistor
technology and a patterned dielectric matching sheet to replace the conventional silicon lens.
33.2
1:55 PM
A 216-to-226GHz Watt-Level GaN Solid-State Power Amplifier with Multiband Large-Signal Impedance Correction
and Circuit-Package Co-Design Technique
Kai Li, Tianjin University, Tianjin, China
In Paper 33.2, the National Key Laboratory of Solid-State Microwave Devices and Circuits, Nanjing Electronic Device
Institute, and Tianjin University demonstrate a solid-state power amplifier with a maximum output power of 1.54W at
223GHz achieved by combining 32 GaN MMICs co-designed with the package. The GaN MMIC PAs are enhanced by
carefully designed AlN/GaN heterojunction (fT/fMAX=180GHz/420GHz), and the design procedure utilizes a multiband
large-signal impedance-correction technique.
33.3
2:20 PM
A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS with Outphasing Gain and Phase Corrections
Lorenzo Piotto, University of Pavia, Pavia, Italy
In Paper 33.3, the University of Pavia showcases a hybrid active/passive phase shifter in 55nm SiGe BiCMOS. The
phase shifter achieves 360-degree range across 125-to-170GHz band using an outphasing gain and phase calibration.
The output 1dB compression point is above 2dBm with 31mW DC power consumption, corresponding to a 5× power
efficiency enhancement against previous works.
33.4
2:45 PM
A Wideband Bidirectional Calibration-Free Frequency/Switching-Staggering 360° D-Band Phase Shifter with
Frequency-Invariant Codes Achieving <2.38°/0.63dB RMS-Errors Over 24% Bandwidth
Basem Abdelaziz Abdelmagid, ETH Zürich, Zürich, Switzerland
In Paper 33.4, ETH-Zurich presents a bidirectional phase shifter featuring 11.25° resolution and achieving a calibrationfree fractional bandwidth of 24% with <2.38°/0.63dB rms phase and gain errors across the 110-to-140GHz band in
22nm SOI.
33.5
3:00 PM
A 224GHz 19.9% TR Varactor-less VCO Utilizing a Multi-Section Switch-Loaded Coupled-Line Resonator
Ahmed Elmenshawi, Rensselaer Polytechnic Institute, Troy, NY
In Paper 33.5, Rensselaer Polytechnic Institute demonstrates a nearly 20% tuning range G-Band VCO (202.1 to
246.8GHz) with a varactor-less multisection switch-loaded coupled-line resonator responsible for the extended tuning
range and improved quality factor (>10) across the band in 22nm FDSOI.
DIGEST OF TECHNICAL PAPERS • 541
33
ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / 33.1
33.1
A 232-to-260GHz CMOS Amplifier-Multiplier Chain with a
Low-Cost, Matching-Sheet-Assisted Radiation Package and
11.1dBm Total Radiated Power
Jinchen Wang, Daniel Sheen, Xibi Chen, Steven F. Nagle, Ruonan Han
Massachusetts Institute of Technology, Cambridge, MA
Terahertz (THz) signal sources and radiators are essential for a variety of future applications,
such as high-resolution radar imaging [1], molecular spectroscopy, and clocks [2], as well
as high-speed or miniature-platform communications [3]. For over a decade, the growing
interest in CMOS-based compact THz radiation sources has been driven by their small form
factor and integration with other analog/digital systems. However, the total radiated power
of prior CMOS THz sources was still only several mW, not only due to the limited fmax and
breakdown voltages of the CMOS transistors, but also due to the inefficient on-chip radiation
approaches. Front-side radiation, typically based on a patch antenna implemented using
the CMOS BEOL, allows for low-cost packaging and reliable heat dissipation. However, the
small metal and dielectric thicknesses cause low radiation efficiency (ηrad) and narrow
radiation bandwidth (fBW/f0) (ηrad≈25% and fBW/f0≈5% in the 200-to-300GHz band). To
address these issues, back-side radiation is commonly adopted as an alternative, where the
THz waves are radiated from, for example, slot and dipole antennas, into the silicon substrate
and are eventually emitted from the back of the chip. However, due to the large dielectric
constant contrast between the silicon (εSi=11.9) and air (εair=1), the radiated waves undergo
strong reflection at the silicon-air interface, and with a small outward angle of 17°, total
internal reflection occurs. To alleviate this problem, cm-sized, high-resistivity silicon lenses
affixed to the chip back have been used [1]. However, they dramatically increase the cost
and size of the overall assembly. In this paper, we introduce a CMOS THz amplifier-multiplier
chain array generating radiation between 232 and 260GHz. Instead of using a silicon lens,
a patterned dielectric matching sheet is applied onto the flipped-chip back, which enhances
the wave coupling from silicon to air and enables low-cost and planar packages. That, in
conjunction with broadband gain-peaking power amplifiers built with a high-power RF
FinFET (HyPowerFF) transistor technology in the CMOS process, enables a measured peak
total radiated power of 11.1dBm.
The system diagram and circuit schematic are shown in Fig. 33.1.1. Two arrays of on-chip
amplifier-multiplier-chains (fifteen in each array) are used to generate a set of 130GHz
signals, which are subsequently frequency-doubled by two arrays of doublers. The array
size is determined by the chip area. The final outputs from the doublers are then radiated
by a linear array of 15 broadband bowtie-shaped slotline antennas located in the center of
the chip. Broadband Gmax and impedance matching are achieved through the embedding of
multi-ring resonators (MRRs) in the cascode power amplifiers (PAs). Each PAs eventually
drives the 260GHz doubler with a push-push topology.
Figure 33.1.2 shows the details of the matching-sheet-assisted radiation. The bowtie-shaped
slot antenna provides broadband matching from 220 to 300GHz, with the antenna elements
connected to a global Vds of the THz doubler and separated by λ/2 transmission lines. As
shown in Fig. 33.1.2, at each end of the antenna array, a λ-long broadband steppedimpedance resonator creates short termination at 260GHz, so that the connection to Vdd
does not affect the THz operations. The two petals of the bowtie are concurrently driven by
a pair of 260GHz doublers, leading to downward radiation with polarization in the x-direction.
Figure 33.1.2 also explains the mechanism of backside radiation towards varying directions.
As mentioned previously, with normal exposed chip back, most diverging waves are
reflected by the silicon-air boundary. To address this, we propose using a dielectric sheet
with a dielectric constant of εsheet=(εSiεair)0.5 =3.35 and a thickness of λSheet/4=0.15mm at the
backside of the silicon substrate. Similar to optical impedance-matching films, that
effectively reduces the wave reflection and enhances the coupling into the air. Figure 33.1.2
presents the calculated transmissivity of the s-polarized (SP, dominant in our case due to
the beam collimation in the x-direction) and p-polarized (PP) modes, showing that within
the total internal reflection angular range, the additional matching sheet reduces the radiation
loss by ~2dB. To reduce costs, a commercial RO4003C substrate with εr=3.55 is used as a
matching sheet. Since the dielectric constant of this substrate is higher than the desired
value, a sub-wavelength grating pattern is added through laser cutting to compensate for
the small dielectric constant difference, as shown in Fig. 33.1.2. The simulated overall
radiation efficiency, including the bowtie loss itself, the loss inside the doped silicon, and
the loss inside the matching sheet is 41.8% at 260GHz, which is similar to that obtained
through silicon lenses.
line employed in peak-gain cores are proved to be effective in realizing broad Gmax in singlestage driving amplifiers [4], but broadband matching in a cascode PA is still a challenge.
To that end, the broadband topology of our cascode PA is depicted in Fig. 33.1.3. A pair of
high-performance (HP) NMOS transistor arrays (with high fmax) are employed for commonsource amplification. The transistor layout is designed using the round-table method to
mitigate high-frequency losses and mismatches. By properly allocating four transmission
poles of the multi-ring resonator (MRR) and the transmission line YF, the high-order passive
network [YMFeq] is designed to track the relaxed gain-boosting condition Kf=1 with changing
θ and the frequency-dependent Yout to the common-gate amplifiers over the operating range.
Figure 33.1.3 also shows the simulated maximum available gain of the proposed broadband
peak-gain core in comparison with other types of peak-gain cores. Note that in this
simulation, the core comprises only single-stage HP transistors without any cascode
topology assuming an ideal constant load. The proposed approach achieves a flat maximum
gain with a trade-off between the bandwidth and peak maximum gain, but it is still 3 to 4dB
higher than the original Gms/Gma. Next, high-power RF HyPowerFF transistors provided in
this CMOS process [5], which have a high breakdown voltage of 6.3V and fmax of 290GHz
[5], are utilized in the common-gate stage of the cascode structure. Considering that the
fmax of the HP transistor exceeds that of the HyPowerFF, we use HP transistors for higher
gain of the first CS stage, where voltage swing is not high, and then a HyPowerFF for higher
voltage swing in the second CG stage. To increase the stability, a drain-source neutralizationcapacitor (D-S NC) technique [6] is also adopted. Finally, the simulated saturated output
power (Pout) and power-added efficiency (PAE) of the proposed cascode PA are shown in
Fig. 33.1.3. The simulated gain of the PA is higher than 10dB over the operating range. With
the simulated THz doubler load, one-way peak output power of 14.9dBm is achieved at
120GHz with a DC voltage of 3.3V, and the PAE exceeds 4% over the frequency range from
110 to 150GHz.
Figure 33.1.7 shows the die micrograph and PCB. The chip was fabricated using Intel16
CMOS process and has a die size of 10.4mm2. It is directly flip-chip bonded (as shown in
Fig. 33.1.4) to a 0.1mm-thick Rogers 5880 PCB (εr=2.2) with an in-house custom packaging
flow. The black lines on the back of the matching sheet in Fig. 33.1.4 are mainly the substrate
that has been scorched by a laser, and the actual width of slots are narrower. Two 1-to-16
on-PCB Wilkinson power dividers (with one output terminated at 50Ω) are used to split the
input RF signal into 15 channels and feed into the chip at its two edges. The matching sheet
is attached on the backside of the chip, as shown in Fig. 33.1.4. The simulated thermal
performance of the assembly using Ansys Icepak is also presented, where the maximum
chip temperature is 68°C when using a heat sink and a fan.
Figure 33.1.5 shows the measured results based on the testbench illustrated in Fig. 33.1.4.
A VDI subharmonic mixer was used for radiation pattern and spectrum tests, and an Erikson
PM5 power meter was used for absolute power measurement. A diagonal horn antenna
(Gant=26dBi), with 15cm distance from the chip (i.e. far-field region of the antennas), was
used in both setups. As previously analyzed, adding the matching sheet improves the
radiated power by 2.1dB. The measured radiation pattern at 260GHz indicates a beamwidth
of 28° and 16° in the azimuth (Φ=0°) and elevation (Φ=90°) directions, respectively. The
measured EIRP with the matching sheet is 24.5dBm, and after de-embedding the simulated
radiation directivity of 13.4dB, the total radiated power of the chip is estimated to be
11.1dBm at 260GHz. Figure 33.1.5 also shows the measured radiated power versus
frequency. The presented THz radiator has a 3dB output bandwidth from 232 to 260GHz
(fBW/f0=11.4%). Peak radiated power was obtained with a DC power of 5.5W and a DC-THz
radiation efficiency of 0.23%. The radiated power is not saturated because further increasing
the DC power damages the sample. This may be due to the voltage swing being higher than
the breakdown voltage or the current exceeding the maximum current density. Figure 33.1.6
includes the measured performance summary and a comparison to the prior arts. While
using a low-cost radiator package, our THz radiator achieves the highest radiated power in
the table.
Acknowledgement:
The chip is fabricated through the Intel University Shuttle Program. This work is partially
supported by Jet Propulsion Laboratory (JPL), NASA via their Strategic University Research
Partnerships Program and by MIT Center of Integrated Circuits and Systems (CICS). The
authors would like to thank Dr. Lin Yi from JPL, NASA, Eunseok Lee, and Dr. Yong Hu from
MIT for technical discussions and supports.
For THz amplifier-multiplier chains, low amplifier power gain prior to the final multiplier
stage is typically the bottleneck for the final THz output power and efficiency. Peak-gaincore techniques based on embedding networks have been used to realize maximum
achievable gain (Gmax), which is approximately four times greater than of the unilateral power
gain (U) [13]. However, traditional peak-gain-core theory is narrowband since Gmax is
achieved only when the stability factor Kf is 1 and the phase θ of the two-port PA network
A=[Y21]/[Y12] is 180°. Frequency-dependent inductance characteristics of the transmission
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Figure 33.1.1: System diagram and circuit schematic of the CMOS sub-THz radiator
Figure 33.1.2: Back-side radiation using the impedance-matching sheet.
chip.
Figure 33.1.3: Schematic and analysis of the 130GHz cascode PA using broadband Figure 33.1.4: Simulated thermal performance, measurement setup, and the flip-chip
package with backside dielectric matching sheet.
peak-gain core and HyPowerFF transistors.
33
Figure 33.1.5: Measurement results.
Figure 33.1.6: Performance summary and comparison with prior-art radiation sources.
DIGEST OF TECHNICAL PAPERS • 543
ISSCC 2025 PAPER CONTINUATIONS AND REFERENCES
Figure 33.1.7: Die micrograph.
References:
[1] S. M. H. Naghavi, et al., ″A 250GHz Autodyne FMCW Radar in 55nm BiCMOS with Micrometer Range Resolution,″ IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,
pp. 320-322, Feb. 2021.
[2] Wang, Cheng, et al., ″Sub-THz CMOS molecular clock with 43ppt long-term stability using high-order rotational transition probing and slot-array couplers,″ IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 448-450, Feb. 2020.
[3] E. Lee, et al., ″A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface,″ IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig.
Tech. Papers, pp. 226-228, Feb. 2024.
[4] S. Park, et al., ″A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS,″ IEEE Journal of Solid-State Circuits, vol. 57, no.
7, pp. 2114-2129, Jul. 2022.
[5] Lee, H-J., et al., ″Implementation of high power RF devices with hybrid work function and OxideThickness in 22nm low-power FinFET technology,″ IEEE International Electron
Devices Meeting (IEDM), 2019.
[6] S. V. Thyagarajan, Ali M. Niknejad, and Christopher D. Hull, ″A 60 GHz drain-source neutralized wideband linear power amplifier in 28 nm CMOS,″ IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 61, no. 8, pp. 2253-2262, Aug. 2014.
[7] C. Wang, et al., ″A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS,″ IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 415417, Feb. 2024.
[8] L. Chen, A. Cathelin and E. Afshari, ″A High-Efficiency High-Power 170-176-GHz Frequency Stabilized Quadrature Radiator,″ IEEE Journal of Solid-State Circuits, vol. 59, no.
1, pp. 243-252, Jan. 2024.
[9] X. Li, H. Wu, S. Li, W. Chen and Z. Feng, ″A 160-GHz FMCW Radar Transceiver with Slotline-based High Isolation Full-duplexer in 130nm SiGe BiCMOS Process,″ IEEE Radio
Frequency Integrated Circuits Symposium (RFIC), pp. 249-252, 2023.
[10] K. Guo, C. H. Chan and D. Zhao, ″Analysis and Design of a 0.3-THz Signal Generator Using an Oscillator-Doubler Architecture in 40-nm CMOS,″ IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 69, no. 6, pp. 2284-2296, Jun. 2022.
[11] L. Wu, S. Liao and Q. Xue, ″A 312-GHz CMOS Injection-Locked Radiator With Chip-and-Package Distributed Antenna,″ IEEE Journal of Solid-State Circuits, vol. 52, no. 11,
pp. 2920-2933, Nov. 2017.
[12] R. Han, et al., ″A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems,″ IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2015.
[13] R. Han and E. Afshari, ″A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOS,″ IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, pp. 138-139, Feb. 2013.
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ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / 33.2
33.2
A 216-to-226GHz Watt-Level GaN Solid-State Power Amplifier
with Multiband Large-Signal Impedance Correction and
Circuit-Package Co-Design Technique
Weibo Wang*1,2, Zhe Li*3, Kai Li3, Haifeng Cheng1,2, Fangjin Guo1,2, Yibin Zhang1,2,
Keping Wang3
National Key Laboratory of Solid-State Microwave Devices and Circuits, Nanjing, China
Nanjing Electronic Device Institute, Nanjing, China
3
Tianjin University, Tianjin, China
1
2
*Equally Credited Authors (ECAs)
Compact and integrated 220GHz solid-state power amplifiers (SSPAs) are important in
enabling future high-data-rate wireless communication, imaging, and radar systems. Silicon
(CMOS and SiGe) and III-V (GaAs and InP) technologies have been widely used to design
PAs at frequencies >200GHz [1-3]. However, due to the low operating voltage of these
devices (typically <2V for a single stacked transistor), the final stage of the PA is often in a
low-voltage and high-current mode. The equivalent impedance is very low, which limits the
bandwidth and output power density [4-6]. Due to their wide bandgap characteristic, higher
voltage tolerance, and high electron saturation drift velocity, GaN HEMTs are becoming a
promising candidate for G-band PAs [7-9].
Although the industry recognizes a GaN HEMT as an ideal technology for PAs, no PAs
operating at frequencies of 220GHz and above have been reported [7-11]. There are three
main reasons. First, in order to suppress the short channel effect of the GaN HEMT at THz
frequencies, a thinner barrier layer is often required, which leads to an increase in parasitic
resistance and severe limitations on the output power. Second, a precise large-signal model
is often required to perform power matching. However, due to the lack of the load-pull test
system at 220GHz and above, the optimal power impedance (ZOPT) of the device cannot be
determined. Third, it is difficult to achieve a watt-level output power with lossy on-chip
power combing networks at THz frequencies. Due to the influence of waveguide processing
accuracy, assembly, and bonding, it is also difficult to ensure the ideal 50Ω matching for
module-level power combing, resulting in reduced output power and efficiency [12,13].
Figure 33.2.1 depicts the block diagram of the proposed SSPA and the schematic of the
packaged GaN PA MMICs. The SSPA includes four PA modules, one 4-way splitter and one
4-way combiner. Each module consists of eight packaged GaN PA MMICs with two 4-way
splitters and one 8-way combiner, and the eight packaged GaN PA MMICs are driven by
two GaN PA MMICs. In order to overcome the above-mentioned issues, this paper reports
a watt-level GaN HEMT SSPA that achieves a peak output power of 1.5W at the frequency
of 223GHz by using the following techniques. First, the thickness of the AlN barrier layer in
the AlN/GaN heterojunction is carefully designed and the secondary epitaxial process is
used to increase the fT/fmax of the GaN HEMT. Second, we propose a multiband large-signal
impedance correction technique by fitting the output impedance at several measured
maximum output powers from W- and D-band PAs as the equivalent ZOPT. Third, we propose
the circuit-package co-design technique to cancel the large-signal impedance (ZOPT)
mismatch caused by the waveguide processing accuracy, assembly and bonding.
In order to enable the PA MMICs to operate at higher frequencies, it is necessary to enhance
the fT, fmax, and power density of GaN HEMT. Figure 33.2.2 (top left) illustrates a typical
equivalent circuit model of a GaN HEMT at high frequencies, and Fig. 33.2.2 (top right)
shows a schematic that integrates the device structure with the material epitaxial structure,
primarily showing the physical origins of the intrinsic and parasitic elements in the
equivalent circuit. It is known that fT is proportional to the ratio of the device
transconductance (gm) to the input capacitance (Cin≈Cgs). To increase the gm, an AlN thin
barrier is used to enhance the gate control over the channel, while n+GaN regrown process
is employed to reduce the device ohmic contact resistance Rs. To reduce the Cgs and Cgd,
a 50nm floating T-gate self-aligned process is utilized. Since fmax is proportional to the ratio
of the device output impedance to input impedance, a 0.5μm source-drain spacing is
adopted to lower the channel parasitic resistance Rs and Rd, thereby reducing the loss of
output signals. To enhance the device output power density, an AlN/GaN strongly polarized
heterojunction is used to generate a higher two-dimensional electron-gas (2DEG)
concentration. The thickness of the AlN barrier layer is optimally designed to increase carrier
mobility, and high-quality SiN passivation layers are grown by an ALD technique, which
increases the Rgd and raises the device operating voltage. Figure 33.2.2 (bottom left) shows
that the measured fT of the 2×20μm GaN HEMT device can reach 180GHz, and the measured
fmax is about 420GHz. Figure 33.2.2 (bottom right) depicts that the device maximum
measured gm is about 880mS/mm.
The distributed GaN HEMTs are based on the scalable model, which can ensure small-signal
accuracy at high frequency [14]. For the initial setup (also means at the first-round tapeout),
three peaking Pouts (ZL1, ZL2, ZL3) at W-band and two peaking Pouts (ZL4 and ZL5) at D-band
were recorded with broadband output-matching networks. Then, we correct the large-signal
model for other frequencies to flatten the large signal bandwidth. As shown in Fig. 33.2.3
(bottom left), after only one-time correction, the all-band Pout is significantly improved.
Figure 33.2.3 (bottom right) shows the measured and simulated impedances of the smalland large-signal models of the HEMTs. The simulation of linear model was extrapolated
from the measurement of the linear model below 220GHz. The simulation of nonlinear model
was extrapolated from the measurement of the nonlinear model below 90GHz.
Figure 33.2.4 shows the EM model of all passive devices in GaN PA MMIC and package,
the effect of the electromagnetic band-gap (EBG) package structure on the cavity isolation,
and the output power of the packaged PA. The waveguide cavity, bond wire, and probe
microstrip transition structures are co-designed to avoid the impedance variations due to
the non-50Ω transition between them. In addition, in order to eliminate the in-band
resonance formed by the high-order mode in the cavity, metal nails are used to form an
EBG electromagnetic bandgap structure on the top of the cavity, which suppresses the
transmission of high-order modes and improves the isolation of the cavity and the overall
stability of the PA. As shown in Fig. 33.2.4 (bottom left), the package cavity without the
EBG package structure generates two resonant points, while the package cavity with the
EBG package structure shows more than 35dB isolation optimization between the input and
output ports in the frequency range from 216 to 226GHz. Moreover, in order to reduce the
influence of the bond wire between the GaN PA MMIC and the microstrip to waveguide
transition structure, a compensation circuit is added at the end of the transition structure
and close to the microstrip to absorb the parasitic inductance of the bond wire, achieving
smooth impedance transformation and good signal transmission within the frequency of
interest.
The proposed PA MMIC utilizes a 7-stage 2×20μm common-source HEMT-amplification
dual-path power-combining structure, achieving broadband impedance matching through
multiple stages of high- and low-impedance microstrips. The input-output network
completes power dividing or combining while performing impedance matching. Under
Vds=8V and Ids=287mA, the measured results of the packaged PAs (4 samples) indicate
that the average output power is 55mW within the frequency range from 216 to 226GHz,
with a maximum output power reaching 70mW. Ultimately, eight packaged PA chips are
employed for power combining to achieve a single power module of 350mW.
The proposed SSPA is cascaded with four identical 350mW power modules and the 4-way
power combiner and splitter, which is composed of over-mode waveguide T-junctions and
3dB coupling bridges. Figure 33.2.5 (top) shows the measured small-signal S-parameters,
the saturated output power, and the PAE of the GaN PA MMICs. All external power losses
beyond the packaged PA were de-embedded across the frequency band of interest, and a
power meter Ceyear 87115SA was used to measure the output power. As shown in Fig.
33.2.5 (top left), the GaN PA MMIC achieves a peak |S21| of 23dB at 213GHz and smallsignal 3dB bandwidth of 38GHz (190 to 228GHz). The peak performance of the GaN PA is
measured at 216GHz with PSAT of 20.4dBm and a PAE of 2.3% (Fig. 33.2.5 top right). The
power density of the device is extrapolated to be 1.35W/mm at 216GHz, based on two
2×20μm common-source GaN HEMTs with more than 1.5dB of real losses in the final-stage
matching network and packaging at 216GHz. The output power and power gain of the SSPA
module are shown in Fig. 33.2.5 (bottom left). The SSPA achieves output power of >1W in
the frequency range from 216 to 226GHz and a peak output power of 1.54W at 223GHz.
The power gain is greater than 9dB in the range from 216 to 226GHz.
A comparison table with other designs is shown in Fig. 33.2.5 (bottom right) and Fig. 33.2.6.
Among these works, the proposed GaN PA MMIC shows superior PSAT and PAE. According
to our survey [7-11], the GaN PA MMIC achieves the highest output power of 100mW at
216GHz and the power density of >1.35W/mm at 216GHz. For SSPA, the maximum
efficiency with the 32-way power combining network reaches 48.7% at 223GHz, and SSPA
achieves an output power of greater than 1.5W at 223GHz. Compared with other designs
[1-3, 12-13], the SSPA achieves an output power exceeding 1W in the frequency range of
216 to 226GHz. The die micrograph of the GaN PA MMIC and SSPA are shown in Fig. 33.2.7.
Acknowledgement:
This work was supported in part by the National Natural Science Foundation of China under
Grants 62371332. Corresponding author: Keping Wang.
Figure 33.2.3 shows the block diagram of the large-signal impedance correction technique
for the GaN HEMT. To clarify the large-signal performance of the GaN HEMT at the G-band,
W- and D-band PAs based on the distributed GaN HEMTs were initially designed to
determine ZOPT without requiring load-pull measurements, as shown in Fig. 33.2.3 (top).
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Figure 33.2.1: Block diagram of the proposed SSPA and the schematic of the packaged Figure 33.2.2: Equivalent circuit model of a unit GaN HEMT, epitaxial structure of a
GaN HEMT, measured fT and fMAX, measured gm and drain current vs. gate voltage.
GaN PA MMIC.
Figure 33.2.3: 2×20µm unit GaN HEMT distributed model, schematic of the W- & D- Figure 33.2.4: EM model of all passive devices of the GaN PA MMIC and package,
band PA, measured Pout of W- & D-band PA, diagram of the large-signal impedance simulated isolation of the EBG vs. frequency, and simulated output power of packaged
PA vs. frequency.
correction.
33
Figure 33.2.5: Measured S-parameters, PSAT, PAE vs. frequency of the PA MMIC,
measured output power, gain vs. frequency of the SSPA, comparison of output power. Figure 33.2.6: Performance summary and comparison to prior works.
DIGEST OF TECHNICAL PAPERS • 545
ISSCC 2025 PAPER CONTINUATIONS AND REFERENCES
Figure 33.2.7: Die micrograph of the GaN PA MMIC and SSPA.
References:
[1] D. Gritters et al., “200-260GHz solid state amplifier with 700mW of output power,” IEEE IMS/MTT-S, pp. 1-3, 2015.
[2] J. -M. Rollin et al., “A Polystrata® 820 mW G-Band Solid State Power Amplifier,” IEEE CSICS, pp. 1-4, 2015.
[3] H. Kazemi et al., “350mW G-band medium power amplifier fabricated through a new method of 3D-copper additive manufacturing,” IEEE IMS/MTT-S, pp. 1-3, 2015.
[4] J. Hacker, et al., “InP HBT amplifier MMICs operating to 0.67 THz,” IEEE IMS/MTT-S, pp. 1-3 2013.
[5] H. Hamada et al., “475-GHz 20-dB-Gain InP-HEMT Power Amplifier Using Neutralized Common-Source Architecture,” IEEE IMS/MTT-S, pp. 1121-1124, 2015.
[6] T. Soma, et al., “A 160-GHz, 10-dBm power amplifier for D-band communication in 0.1-μm GaAs pHEMT,” IEEE PAWR, pp. 7-9, 2023.
[7] M. Ćwikliński et al., “First Demonstration of G-Band Broadband GaN Power Amplifier MMICs Operating Beyond 200 GHz,” IEEE IMS/MTT-S, pp. 1117-1120, 2020.
[8] M. Ćwikliński et al., “190-GHz G-Band GaN Amplifier MMICs with 40GHz of Bandwidth,” IEEE IMS/MTT-S, pp. 1257-1260, 2019.
[9] M. Ćwikliński et al., “D-Band and G-Band High-Performance GaN Power Amplifier MMICs,” IEEE TMTT, pp. 5080-5089, 2019.
[10] R. Weber et al., “A Beyond 110 GHz GaN Cascode Low-Noise Amplifier with 20.3 dBm Output Power,” IEEE IMS/MTT-S, pp. 1499-1502, 2018.
[11] E. Camargo et al., “F-Band, GaN Power Amplifiers,” IEEE IMS/MTT-S, pp. 753-756, 2018.
[12] J. Schellenberg et al., “W-band, 5W solid-state power amplifier/combiner,” IEEE IMS/MTT-S, pp. 240-243, 2010.
[13] J. Schellenberg et al., “37 W, 75-100 GHz GaN power amplifier,” IEEE IMS/MTT-S, pp. 1-4, 2016.
[14] W. Wang et al., “A W-Band Power Amplifier with Distributed Common-Source GaN HEMT and 4-Way Wilkinson-Lange Combiner Achieving 6W Output Power and 18% PAE
at 95GHz, “ IEEE ISSCC, pp 376-377, 2020.
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ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / 33.3
33.3
A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS
with Outphasing Gain and Phase Corrections
Lorenzo Piotto, Guglielmo De Filippi, Andrea Mazzanti
University of Pavia, Pavia, Italy
Advancements in silicon technologies are opening the way to sub-THz phased-array
transceivers, enabling high-resolution radar sensors, and wireless communications with a
fiber-like transport capacity.
Programmable phase shifters (PSs), not yet deeply investigated, are crucial components
in such systems. At the RX side, the PS follows a low-noise amplifier (LNA), with both low
noise and high linearity being key to maintain the dynamic range. Conversely, on the TX
side, the PS drives a power amplifier (PA), and high output power at 1dB gain compression
(OP1dB) for the PS is highly desirable to relax PA requirements and improve system
efficiency.
Most of the PSs in D-band rely on the vector-sum principle, where signals in quadrature
are weighted by variable-gain amplifiers (VGAs) and combined to achieve the desired phase
shift [1-3]. This architecture grants fine phase resolution, but the need for VGAs with a wide
range of gain-control compromises the linearity, limiting the OP1dB. Linear PSs based on
passive components have also been investigated. [4] presented a 140GHz PS based on a
digitally tapped delay line. The remarkably high OP1dB=3.4dBm comes with 10dB attenuation
and a narrow bandwidth (10GHz only), limited by the parasitic capacitances of the CMOS
switches along the line. [5] proved broadband operation by routing the signal through
transmission lines of different lengths, at the expense of a 20dB insertion loss, coarse phase
control, coverage of 0° to 360° only in the lower D-band portion, and large chip size.
This paper presents the hybrid (passive/active) vector-sum PS architecture in Fig. 33.3.1,
comprising wideband programmable passive networks and amplifiers that compensate for
the insertion loss. The architecture removes VGAs for weighting the vectors to be summed
and replaces them with two amplifiers that are biased at the optimal condition for maximum
OP1dB with constant gain. Experimental results on a SiGe BiCMOS test chip demonstrate
wideband operation (125 to 170GHz) with 0-to-360° phase control in 9° steps. Compared
to active vector-sum PSs in the D-band, measurements show comparable gain, phase
resolution, noise figure (NF), and power consumption (PDC) but with a higher OP1dB, leading
to 5× enhancement of the power efficiency (η =OP1dB/PDC).
The operation principle of the proposed PS is explained by Fig. 33.3.1. Looking at the block
diagram (top-left), the input signal S is split in two quadrature paths (I/Q). Then, the two
quadrature signals feed a pair of blocks, referred to as Δφ,, which introduce a
programmable phase shift in a range of (at least) 0° to 90° with fine-enough resolution.
Assuming the phase shifters are controlled by the same digital word (Δφ=Δφ=Δφ), the
outputs on the I and Q paths are (S/√2)𝑒 and 𝑗(S/√2)𝑒, respectively. The two
components are then fed to 0°/180° phase shifters controlled by 1b signals, swI, swQ, and
are eventually summed at the output of two identical amplifiers (with gains G). Assuming
lossless passive networks, the overall PS gain, G=S/S and phase (𝐺) are
summarized in the table of Fig. 33.3.1, showing that with Δφ ∈ [0° to 90°] and a proper
combination of swI, swQ, the input-output phase shift spans the 0°-to-360° range, with the
resolution set by Δφ. It is worth noticing that in each path the phase shift is programmable
across two quadrants only (0° to 90° and 180° to 270°), limiting the implementation
complexity of the required networks. The insertion loss of the passive networks is
nevertheless dependent on the phase settings, thus programmable loss compensation is
needed to produce an output with a variable phase but constant amplitude. To avoid VGAs,
regulation of the gain is performed by independently controlling the phase shifts in the I/Q
paths Δφ, Δφ. The concept, illustrated in Fig. 33.3.1 (top-right), is the same as that
exploited in outphasing amplifiers [6]. The two quadrature signals produce an output with
phase φ. By properly varying the relative phase between the two vectors (Δφ =Δφ-δφ,
Δφ=Δφ+δφ), it is possible to change the amplitude by δG but not φ. The independent
control of Δφ, Δφ is also leveraged to correct for deviations from quadrature of the two
vectors being summed, due for example to a phase error of the I/Q input splitter or
deviations from the 0°/180° of the phase-inversion blocks. The situation is depicted in Fig.
33.3.1 (bottom-right). The quadrature error δφ leads to an error δφ on φ, nulled by
Δφ =Δφ and Δφ=Δφ-δφ.
546 • 2025 IEEE International Solid-State Circuits Conference
The detailed schematic of the realized PS is drawn in Fig. 33.3.2. The input splitter is a
quadrature hybrid, realized with coupled lines of 245μm length, corresponding to λ/4 at
150GHz. The programmable phase shifters, ΔφI, ΔφQ, are implemented by cascading four
band-pass filters with center frequency tunable by a digitally switched capacitor bank. The
programmable range of the phase shift is purposely selected greater than 90° to support a
rotation of the output vector over one quadrant with a margin to be used for gain and phase
corrections. The simulated input-output phase shift (Fig. 33.3.3, left) is programmable over
a range of 130° at 125GHz and 166° at 170GHz in 17 steps with a thermometric control.
The insertion loss spans 5 to 9.5dB in the 125-to-170GHz band. The networks for phase
inversion (0°/180°) are realized as two-state reflective-type phase shifters using quadrature
hybrids. The signals SA,I/Q are equally split at the CPL/DIR ports, terminated by the NMOS
switches controlled by swI, swQ, with reflection coefficients ΓSW,on/off ideally ±1
(ΓSW,on/off=(ZSW,on/off-Z0)/(ZSW,on/off+Z0), with Z0 the characteristic impedance of the hybrid and
ZSW,on/off the on- and off-state impedance of the switches). The signals reflected by the
switches sum at the ISO port, making the outputs SB,I/Q with a gain magnitude and a relative
phase shift equal to ΓSW,on/off. Inductors (Lsw) shunt the NMOS switches to resonate out the
parasitic capacitance, and the transistors are sized (W/L=50μm/55nm) to achieve
|ΓSW,on|≈|ΓSW,off| at 150GHz, giving the same network insertion loss in the on and off states.
|ΓSW,on/off|≈0.7 results in ≈3dB loss, which sums to 0.8dB loss of the couplers. The simulated
phase shift across frequency (Fig. 33.3.3, right) ranges from 146° at 125GHz to 211° at
170GHz. The relatively large phase deviation from 180° at the band edges is finally
compensated by properly selecting ΔφI, ΔφQ. The signals SB,I/Q feed a pair of cascode
amplifiers with input-matching networks MN1. All the HBTs, (8μm×0.2μm emitter area) are
biased with ≈8mA from a 2V supply. The collectors of Q2 are shorted to sum the I/Q paths
and inject their currents into the shared network MN2, which performs a step-up
transformation of the 50Ω off-chip termination to raise the gain.
The PS was realized in a SiGe BiCMOS 55nm technology with a footprint of 800×250μm2.
The chip was wire-bonded on a PCB that provides biasing, supply, and digital signals to an
on-chip serial interface. S-parameters measurements were acquired using an Agilent
E8361C VNA coupled to VDI WR6.5-VNAX extension modules and Infinity waveguide 75μmpitch GSG probes. The setup was de-embedded up to the probe tips using an external TRL
cal kit. Measurement results (S21, S11) in all possible PS configurations are shown as grey
curves in Fig. 33.3.4. An offline calibration was applied to select the configurations giving
the minimum rms phase error from the ideal curves over a target bandwidth, with a
maximum gain variation within ±1dB. The procedure was applied within three sub-bands,
centered at 138GHz, 152GHz, and 165GHz, to reduce the rms errors across a larger
bandwidth. The selected S21 curves are drawn in red, yellow, and blue colors in Fig. 33.3.4.
Figure 33.3.5 (top) shows the polar plot (with the magnitude in a linear scale) at the three
center frequencies. The bottom plot in Fig. 33.3.5 shows the rms magnitude and phase
errors over frequency, which are within 0.8dB and 5° respectively, across the 125-to170GHz band. The simulated noise figure, extracted at center frequency (150GHz) across
the 0°-to-360° phase shift, spans 16 to 18dB.
Large-signal measurements were obtained using an ELVA-1 DPM-06 D-band power meter.
Figure 33.3.6 shows the measured OP1dB (top-left) and efficiency (top-right) at three
frequency points for a 0°-to-360° phase shift. The OP1dB is always greater than 2dBm and,
with power consumption nearly constant (PDC=31mW), the power efficiency, η=OP1dB/PDC,
ranges from 5.2% to 7.1%. The measured results are finally summarized in the table of Fig.
33.3.6 and compared against previous works in similar frequency bands. Fully passive PSs
are narrowband [4] or display excessive insertion loss and die size [5]. Compared to the
active vector-sum PSs, the presented chip shows comparable or better performance on
most of the aspects. By removing the VGAs in the proposed architecture, the PS achieves
an OP1dB significantly higher than in previous works, and when normalized to the power
consumption gives the highest reported efficiency, at least 5× better than other PSs working
above 100GHz in Fig. 33.3.6. The die micrograph is shown in Fig. 33.3.7.
Acknowledgement:
This work was supported in part by SHIFT from the Chips Joint Undertaking and its
members through the National Authorities under Grant 101096256.
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ISSCC 2025 / February 19, 2025 / 2:20 PM
Vb
ΔφI
Sin 0°
SWI
0°
180°
Lsw
G
je
Sout
SWI
jΔφ
90°
ΔφQ
φout
G
δφI
e
DIR
IN
ISO
jΔφ
IN
0°/180°
MN1
ISO
δφout
to
φout
-φ ERR
SB,Q
SA,Q
CPL
to
DIR
ΓSW,Q
Lsw
ejΔφ
=
δφ Q
to
Q
δG
je
to
MN2
DIR
IN
+φ ERR
SOUT
MN1
SWQ
ISO
SB,I
CPL
Δφ
jΔφ
Q1
CPL
SA,I
I
SIN
δφQ
0°
180°
Lsw
ΓSW,I
δG
Lsw
SWQ
4×
b0
b2
b3
VCC
b1
Figure 33.3.2: Schematic of the implemented phase shifter.
Figure 33.3.1: Block diagram and operation principle of the phase shifter.
|Sxy| [dB]
0
SW
|S21| [dB]
|S21| [dB]
Q2
Lf
I,Q =
0
SW
|S21|
-5
|S11|
-10
I,Q =1
-15
0
166°
-200
-300
130°
146°
SWI,Q=1
S21 [°]
S21 [°]
-100
S21 [°]
0
211°
SWI,Q =
0
-500
-400
120
130
140
150
160
170
Frequency [GHz]
-1000
120
130
140
150
160
170
Frequency [GHz]
Figure 33.3.3: Simulated insertion gain and phase of the fine-step tunable tanks (left) Figure 33.3.4: Measured S-parameters. The curves selected after calibration are
highlighted.
and reflective-type phase inverter (right).
138GHz
152GHz
165GHz
η [%]
OP1dB [dBm]
130GHz
150GHz
170GHz
[7]
[1]
Vector-Sum
μ
μ
μ
Frequency
Rms
Rms
33
§
Simulated value
Figure 33.3.5: Polar plot at the calibration frequencies (top) and corresponding rms Figure 33.3.6: Measured OP1dB and efficiency at three frequencies vs. phase settings
(top). Performance summary and comparison (bottom).
phase and amplitude errors across frequency (bottom).
DIGEST OF TECHNICAL PAPERS • 547
I/Q Hybrid
250μm
ISSCC 2025 PAPER CONTINUATIONS AND REFERENCES
0°/180°
∆φ
Amp.
800μm
Figure 33.3.7: Die micrograph.
References:
[1] A. Moradinia, Y. A. Mensah, W. Lim, S. Lee and J. D. Cressler, “A 110-145-GHz SiGe HBT D-Band Vector Modulator Phase Shifter Utilizing Differential Quadrature Delay Lines,”
in IEEE Solid-State Circuits Letters, vol. 6, pp. 117-120, 2023, doi: 10.1109/LSSC.2023.3267715.
[2] W. Lee, J. Tao, J. S. -C. Chien and J. F. Buckwalter, “A 5.4 mW G-Band Phase Shifter in 90-nm SiGe HBT With One-Hot Encoding,” in IEEE Solid-State Circuits Letters, vol. 6,
pp. 189-192, 2023, doi: 10.1109/LSSC.2023.3294172.
[3] D. d. Rio, I. Gurutzeaga, R. Berenguer, I. Huhtinen and J. F. Sevillano, “A Compact and High-Linearity 140 - 160 GHz Active Phase Shifter in 55 nm BiCMOS,” in IEEE Microwave
and Wireless Components Letters, vol. 31, no. 2, pp. 157-160, Feb. 2021, doi: 10.1109/LMWC.2020.3037162.
[4] M. Abbasi and W. Lee, “A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control,” in IEEE Journal of Solid-State Circuits, vol. 59, no. 5, pp. 13711380, May 2024, doi: 10.1109/JSSC.2024.3357738.
[5] A. Karakuzulu, W. A. Ahmad, D. Kissinger and A. Malignaggi, “A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a
130-nm BiCMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 58, no. 5, pp. 1310-1322, May 2023, doi: 10.1109/JSSC.2022.3232948.
[6] H. Chireix, “High Power Outphasing Modulation,” in Proceedings of the Institute of Radio Engineers, vol. 23, no. 11, pp. 1370-1392, Nov. 1935, doi:
10.1109/JRPROC.1935.227299.
[7] H. Li et al., “W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication,” in IEEE Journal of Solid-State Circuits,
vol. 57, no. 9, pp. 2685-2701, Sept. 2022, doi: 10.1109/JSSC.2022.3188917.
[8] K. Smirnova, M. v. d. Heijden, D. Leenaerts and A. Ulusoy, “Bidirectional 6-Bit Active Phase Shifter in W-Band,” in IEEE Solid-State Circuits Letters, vol. 7, pp. 175-178, 2024,
doi: 10.1109/LSSC.2024.3398779.
• 2025 IEEE International Solid-State Circuits Conference
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ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / 33.4
33.4
A Wideband Bidirectional Calibration-Free
Frequency/Switching-Staggering 360° D-Band Phase Shifter
with Frequency-Invariant Codes Achieving <2.38°/0.63dB
RMS-Errors Over 24% Bandwidth
Basem Abdelaziz Abdelmagid, Yuqi Liu, Hua Wang
ETH Zürich, Zürich, Switzerland
With the increasing need for high data-rate and channel throughput, the D-band (110 to
170GHz) has been actively explored for beyond-5G and 6G wireless communication,
sensing, and radar applications [1,2]. To overcome the severe free-space path loss at
D-band, large-scale phased arrays are essential to focus and steer the radiation beams
[3-5]. As summarized in Fig. 33.4.1 (top), D-band phased arrays come with a list of system
challenges, which affects the design requirements of the front-end building blocks, in
particular the phase shifters (PSs). First, the array element should fit into a ~λ/2×λ/2 grid
dictated by the antenna spacing (1mm×1mm at 150GHz). This requires compact PSs with
a desired bidirectional ability to enable PS sharing between a transmitter and receiver of
each element. Second, due to the narrow beamwidth of large-scale phased arrays, accurate
beamforming is essential, requiring PSs with 360° phase range, accurate phase control
(low rms phase error), and sufficiently fine resolution (~4 to 6b). Third, to simplify the
phase/gain calibration of the array elements for fast beam forming/steering, PSs with
minimum gain variations across phase states (low rms gain error) and phase codes
independent of frequency are highly desirable. Fourth, with the compact element area of
D-band arrays, low element-level power consumption is necessary to lower thermal density.
This either requires active PSs with low DC power or zero-power passive PSs with low
insertion loss (IL). Finally, supporting large data-rates demands wideband front-ends,
requiring PSs that can achieve all the aforementioned desirable features across wide
bandwidths.
Although several D-band PSs and true-time-delay (TTD) designs have been reported
[6-14], none of these designs simultaneously meets all aforementioned desired features.
The vector-modulator (VM) active PSs reported in [6-10] achieve a 360° phase range and
a reasonable loss at the cost of unidirectional operation, extensive calibration to generate
the optimum phase codes, and large rms phase and gain errors across band. The hybrid
PSs in [11,12] combine passive and active stages and achieve a 360° phase range and a
reasonable loss but at the expense of large area, complex calibration, large rms phase errors,
and unidirectional and narrowband operation. The passive TTD circuit reported in [13]
achieves bidirectional and wideband operation over the whole D-band yet with a large IL
(>20dB), a large chip area, and a large rms gain error across the band. The compact
transmission-line (T-line) based 360° passive PS design reported in [14] achieves
bidirectional and calibration-free operation, low rms errors across band, and a 12.3dB
average loss with zero DC power. However, the T-lines severely limit the design fractional
bandwidth (FBW) to 7.1%.
The reflective-type PS (RTPS) topology has been well explored at mm-wave frequencies
for large phase range with high-order loads [15], low rms gain error [16], and wideband
operation [17]. Few D-band PSs partially using the RTPS topology have been reported
[11,12]. However, they require extensive calibration due to the use of analog varactors and
are unidirectional if active 1b 0°/180° phase inverters are employed. In addition, their design
methodologies only focus on optimizing the PS performance at the center frequency, ending
up with narrow bandwidth and large rms phase errors.
Consequently, for the total phase response of the five RTPS stages, they exhibit an overall
wideband flat phase response with minimum phase variations. In addition, to reduce the
phase variations for all PS states across the band, the five RTPS stages are sequentially
switched in a staggered fashion as shown in Fig. 33.4.2 (bottom). More specifically, moving
from a given phase state to the next state involves switching a different RTPS stage, instead
of switching the same RTPS stage, to average out the phase errors across band.
As an example, the implementation of the third RTPS stage (center frequency at 125GHz)
and the wideband 0°/180° phase stage are shown in Fig. 33.4.3. Each RTPS stage is based
on a compact 90° 3dB stacked coupled-line coupler occupying an area of 150μm×60μm.
Across 110 to 140GHz, the coupled-line coupler achieves >25dB return loss, an IL <0.3dB,
a magnitude imbalance of ±0.6dB, and a phase imbalance of ±0.5°. In Fig. 33.4.3(left), the
third RTPS stage achieves a phase range of 33.97°, 34.52°, and 32.2° at 110, 125, and
140GHz, respectively, exhibiting a local minimum at 125GHz as intended by its design. In
addition, the average IL is 1.9dB with a 0.4dB variation across the four states. Note that the
other RTPS stages have similar performance except for a shift in the center frequency for
the intended frequency staggering. The implementation of the wideband 0°/180° phase
stage is shown in Fig. 33.4.3(right) with a compact area of 140μm×60μm. Over 110 to
140GHz, the phase difference between the two states is 180° with an error <0.52° and the
IL is <3.8dB.
A prototype of the proposed 360° D-band PS was fabricated in a 22nm CMOS SOI process.
The die micrograph is shown in Fig. 33.4.7 with a core area of 130μm×480μm. On-wafer
characterization was performed to measure the S-parameters of the PS design using a
Keysight PNA-X N5247B, GGB GSG D-band probes, and VDI frequency extenders. The
measurement setup was calibrated up to the tips of the probes using SOLT calibration on
a GGB calibration substrate CS-15. Figure 33.4.4 summarizes the S-parameters
measurements of the 32 states of the PS, covering the 360° phase range with a 5b resolution
(11.25° step). For the 32 states, S11 is lower than -13dB for the whole D-band. At the center
frequency (125GHz), S21 varies from -14.11dB to -12.57dB with an average IL of 13.37dB
and a peak deviation from average of 0.74dB. Further, the rms phase and gain errors are
0.95° and 0.45dB, respectively. Across the target bandwidth from 110 to 140GHz with the
same frequency-invariant phase codes, the average IL is lower than 14.32dB and the
variation of the average IL is lower than 1dB. In addition, the peak rms phase and gain errors
are 2.38° and 0.63dB, respectively, without any calibration. Figure 33.4.5 shows the
measured S21 polar plots of the PS at 110, 120, 125, 130, 135, and 140GHz. Again, all these
polar plots are generated without any calibration to the PS and while using the same phase
codes at all frequencies.
Figure 33.4.6 summarizes the performance of the proposed bi-directional, calibration-free,
and wideband D-band PS in comparison to the prior-art D-band PSs and TTD circuits.
Although the VM-based active PSs reported in [9,10] achieve wide fractional bandwidth of
30% and 27.5%, respectively, they require calibration to determine the optimum phase
codes, and their rms phase and gain errors are as large as 8° and 1.2dB across the band.
In addition, a 30% fractional bandwidth in [9] is divided into 3 sub-bands with different
phase codes requiring further calibration. The TTD circuit reported in [13] achieves a wide
fractional bandwidth of 42.9%. However, the design is bulky (>1mm2), the IL is high
(>20dB), and the rms gain error is as large as 1.55dB across the band. Although the passive
PS reported in [14] achieves bidirectional and calibration-free operation with reasonable
rms phase and gain errors across the band, the fractional bandwidth is limited to only 7.1%.
The proposed passive PS achieves the bidirectional and calibration-free advantages of [14],
while achieving ~3.3× larger fractional bandwidth with comparable loss, size, and rms phase
and gain errors.
To address these limitations of reported D-band PSs, this work presents a 360° passive
D-band PS in Fig. 33.4.1 (bottom). In comparison to other D-band PSs, it uniquely achieves
simultaneous bidirectional, calibration-free, and wideband operation with a compact size
and low rms phase/gain errors across the band. The presented 110-to-140GHz PS is based
on a 5-stage RTPS (with capacitive reflective loads) that employs frequency/switchingstaggering techniques for wideband operation and a 1b wideband and bidirectional 0°/180°
phase stage. Each RTPS stage provides a phase range of 33.75° with a step of 11.25° (2b
resolution). Therefore, combined with the 1b 0°/180° phase stage, the PS provides a 360°
phase range with a step of 11.25° (5b resolution excluding duplicate phase states). The 1b
bidirectional 0°/180°-phase-stage schematic is shown in Fig. 33.4.1 (bottom right). It
consists of a first balun to convert the RF signal from the single-ended to differential format,
straight/cross switches to provide a 0°/180° phase control, and a second balun to convert
the RF signal back to the single-ended format. The two baluns are based on doubly tuned
transformers and are also frequency staggered for wideband operation. The five RTPS
stages are designed, as shown in Fig. 33.4.1 (bottom left), with thermometer-coded
switchable metal-oxide-metal (MOM) capacitors to avoid calibration and low-quality-factor
analog varactors. In addition, as shown in Fig. 33.4.2 (top left), they are frequency
staggered, with each stage being designed at a different center frequency, for wideband
operation. That is, the capacitor values of each RTPS stage are chosen to satisfy the design
equations listed in Fig. 33.4.2 (top right) at its target center frequency such that the target
phase value is achieved with a flat phase response around that center frequency.
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Figure 33.4.1: Requirements of D-band PSs (top) and proposed passive calibration- Figure 33.4.2: Proposed 5-stage RTPS frequency/switching-staggering techniques for
wideband operation.
free 110-to-140GHz 360° PS (bottom).
Figure 33.4.3: Implementation of the proposed 360° D-band passive phase shifter with Figure 33.4.4: Measurement results of the proposed wideband and calibration-free
D-band phase shifter.
simulation results.
33
Figure 33.4.5: Measured calibration-free S21 polar plots with the same frequency- Figure 33.4.6: Comparison with the prior-art D-band phase shifters and true-time-delay
circuits.
invariant codes across 110 to 140GHz.
DIGEST OF TECHNICAL PAPERS • 549
ISSCC 2025 PAPER CONTINUATIONS AND REFERENCES
Figure 33.4.7: Die micrograph with a core area of 480μm×130μm.
References:
[1] T. S. Rappaport et al., “Wireless Communications and Applications Above 100 GHz: Opportunities and Challenges for 6G and Beyond,” IEEE Access, vol. 7, pp. 78729-78757,
June 2019.
[2] J. -B. Dore et al., “Technology Roadmap for Beyond 5G Wireless Connectivity in D- band,” IEEE 2nd 6G SUMMIT, pp. 1-5, March 2020.
[3] M. Elkhouly et al., “Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules,” ISSCC, pp. 76-78, Feb. 2022.
[4] A. Ahmed et al., “A 140 GHz Scalable On-Grid 8×8-Element Transmit-Receive Phased-Array with Up/Down Converters and 64QAM/24 Gbps Data Rates,” RFIC, pp. 93-96, June
2023.
[5] J. Zhang et al., “A Scalable 134-to-141GHz 16-Element CMOS 2D λ/2-Spaced Phased Array,” ISSCC, pp. 414-416, Feb. 2024.
[6] S. Afroz et al., “A D -Band Two-Element Phased-Array Receiver Front End With Quadrature-Hybrid-Based Vector Modulator,” MWCL, vol. 28, no. 2, pp. 180-182, Feb. 2018.
[7] P. V. Testa et al., “A 160-190-GHz Vector-Modulator Phase Shifter for Low-Power Applications,” IEEE MWCL, vol. 30, no. 1, pp. 86-89, Jan. 2020.
[8] D. d. Rio et al., “A Compact and High-Linearity 140-160 GHz Active Phase Shifter in 55 nm BiCMOS,” IEEE MWCL, vol. 31, no. 2, pp. 157-160, Feb. 2021.
[9] L. Piotto et al., “A 20mW 130-175GHz Phase Shifter with Meandered λ/2 TLINEs in BiCMOS 55nm,” ESSCIRC, Sep. 2023.
[10] A. Moradinia et al., “A 110-145-GHz SiGe HBT D-Band Vector Modulator Phase Shifter Utilizing Differential Quadrature Delay Lines,” IEEE SSCL, vol. 6, pp. 117-120, April
2023.
[11] R. B. Yishay et al., “D-Band 360° Phase Shifter with Uniform Insertion Loss,” IMS, pp. 868-870, June 2018.
[12] S. G. Rao et al., “A D-Band Reflective-Type Phase Shifter Using a SiGe PIN Diode Resonant Load,” IEEE MWCL, vol. 32, no. 10, pp. 1191-1194, Oct. 2022.
[13] A. Karakuzulu et al., “Broadband 110 - 170 GHz True Time Delay Circuit in a 130-nm SiGe BiCMOS Technology,” IMS, pp. 775-778, June 2020.
[14] M. Abbasi et al., “A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control,” IEEE JSSC, vol. 59, no. 5, pp. 1371-1380, May 2024.
[15] T. -W. Li et al., “A Millimeter-Wave Fully Integrated Passive Reflection-Type Phase Shifter With Transformer-Based Multi-Resonance Loads for 360° Phase Shifting,” IEEE
TCASI, vol. 65, no. 4, pp. 1406-1419, April 2018.
[16] P. Gu et al., “Geometric Analysis and Systematic Design of a Reflective-Type Phase Shifter With Full 360° Phase Shift Range and Minimal Loss Variation,” IEEE TMTT, vol.
67, no. 10, pp. 4156-4166, Oct. 2019.
[17] C. Fang et al., “A 22.5-33.5-GHz Hybrid Phase Shifter With Low Phase and Amplitude Error for 5G and Satellite Communication,” IEEE TMTT, vol. 72, no. 5, pp. 3001-3015,
May 2024.
• 2025 IEEE International Solid-State Circuits Conference
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ISSCC 2025 / SESSION 33 / COMPONENTS FOR BEYOND 100GHZ / 33.5
33.5
A 224GHz 19.9% TR Varactor-less VCO Utilizing a Multi-Section
Switch-Loaded Coupled-Line Resonator
Ahmed Elmenshawi1, Sriram Muralidharan2, Mona M. Hella1
Rensselaer Polytechnic Institute, Troy, NY
Analog Devices, Beaverton, OR
1
2
THz and sub-THz waves are key enablers for novel sensing and imaging solutions. THz gasphase spectroscopy, hyperspectral imaging, and high-speed communication are among
many applications that harness the unique characteristics of THz waves. Wide bandwidth,
beamforming, and/or beam steering, as well as adequate power levels are required.
However, low-cost silicon-based electronics fall short of delivering the needed performance
at these frequencies due to the limited fT/fMAX of transistors as well as the low Q factor of
passives. Such limitations are particularly pertinent to tunable circuits such as passive phase
shifters [1] and Voltage-Controlled Oscillators (VCOs), where tunable elements, such as
varactors and switches, are employed. Varactors have a very low Q factor at frequencies
>100GHz [2], as well as a limited capacitance-tuning range, being dominated by parasitics.
Switches, on the other hand, have a trade-off between the OFF-state capacitance (COFF) and
the ON-state resistance (RON). The capacitance of the conventionally used switchedcapacitor banks are typically dominated by COFF with a low Q factor.
Several approaches were proposed to extend the VCO frequency-tuning range (FTR). Mode
switching between coupled oscillators has been proposed to extend the FTR [3,4]. However,
the overall FTR is still limited by the tuning range of each oscillator core, in addition to the
loss incurred by the mode-switching network. Switched inductors and artificial transmission
lines [5-7] have been proposed for coarse tuning, with varactors providing fine tuning.
Variable inductors based on magnetic tuning is another approach for coarse and/or fine
tuning [8]. The magnetic flux through an inductor is tuned by controlling the load (typically
a switch) of another coupled inductor. The Q factor is maximum when the switch is fully
ON (QON) or OFF (QOFF) and reaches a minimum (QMIN) as the switch transitions from OFF to
ON, making this approach mostly suitable for coarse tuning. Split transformers [9], where
the primary inductor is coupled to multiple switch-loaded secondary inductors, can improve
QMIN over a wider FTR. However, the parasitic capacitance between the primary and
secondary inductors as well as the coupling between secondary inductors tend to reduce
QMIN and FTR.
Conventional magnetic tuning could be extended to higher frequencies by modeling the
coupled inductors as coupled transmission lines (CTL) as shown in Fig. 33.5.1. The switchloaded CTL could be viewed as an LC resonator instead of a variable inductor, where the
switch RON and COFF as well as the input load capacitance (CL) are accounted for. In the ONstate, the CTL appears as a transmission line (TL) in parallel with CL. The CTL acts as a
parallel tank with resonance frequency fp2. In the OFF-state, COFF appears in series with TL1
and both in parallel with TL2. Assuming the series resonance frequency of COFF and TL1 (fs)
is much larger than the parallel resonance frequency of COFF + CL and TL2 (fp1), the resonator
appears as a parallel tank with resonant frequency fp1. As long as fs > fp1 and fp2, the switchloaded CTL acts as a parallel tank with a tunable resonance frequency from fp1 to fp2. RON
has the effect of reducing the tuning range and the Q factor of the resonator. It is thus
desirable to minimize Ron, which can be done by increasing the size of the switch. However,
this leads to a higher COFF, which lowers fs. The tuning range becomes discontinuous when
the series resonance frequency falls between the two parallel resonant frequencies fp1 < fs
< fp2 as explained in Fig. 33.5.1.
In order to further improve the Q factor and extend the FTR, we note that the series
resonance of the resonator is dominated by that of the first section as long as the series
resonant frequencies of the sections are close enough to each other. This suggests that the
sizes of the switches can be progressively increased without disturbing the continuity of
the frequency tuning. The decreased RON improves the Q factor and increases fOSC in the
ON-state, while the increased COFF decreases fOSC in OFF-state leading to an overall increase
in the FTR. It is worth noting that the split-transformer approach in [9] achieves a similar
behavior by coupling the primary inductor to multiple secondary inductors (of the same
inductance as the primary) with low coupling coefficients (k). This can lead to higher
parasitic capacitance, which lowers fs and degrades FTR. It also becomes difficult to scale
this approach to a higher number of sections. Our proposed approach couples sections of
the primary inductor to secondary inductors (of the same inductance as that of primary
section) with high k, leading to a more compact design with less parasitics and easily scaled.
A prototype push-push VCO with a 4-section resonator was designed in a GlobalFoundries
22nm FDSOI technology. As shown in the schematic in Fig. 33.5.3, the VCO core is a crosscoupled pair with capacitive degeneration (Cs) to boost the gain and the negative resistance.
Inductor Ls at the common-mode node resonates with Cs, presenting a low impedance at
the source at the second harmonic to boost the second-harmonic power generation. Two
resonators are connected to the cross-coupled core. The output terminals of the two
resonators are shorted, creating a virtual ground for the fundamental. The second harmonic
is extracted at the virtual ground point to avoid loading. Each section of the resonator is a
15μm long 3-conductor coupled line. The signal line is on one of the top thick Cu layers,
while the coupled lines are on all the layers below to reduce the resistance of the connection
between the coupled lines and the FET switches. Figure 33.5.4 shows the EM simulated
tank impedance and the Q factor. The tank exhibits a single resonant peak for each control
setting, with a Q factor > 10.
The output of the fabricated chip was probed with a GSG waveguide probe, and the
frequency tuning range and phase noise were measured using VDI WR-05 and WR-03 SAX
downconverters along with a Keysight PXA Spectrum Analyzer. The second harmonic output
power is measured using an Erickson PM5 power meter. All losses from the measurement
setup were de-embedded from measurements. The measurements are plotted and
compared to the simulation results in Fig. 33.5.5. Good correlation between measurements
and simulation can be observed. A continuous FTR of 19.9% from 202.1 to 246.8GHz was
measured, with a peak output power of -7.6dBm at 203GHz, with a 4.9dB power variation.
The measured best-case phase noise is -100.8dBc/Hz at 202.1GHz. The VCO draws 19.0 to
22.2 mA from a 0.8V supply. The design is compared to the prior-art in Fig. 33.5.6. The
proposed approach proves to be a viable tuning technique and could be utilized in other
tunable circuits such phase shifters. The die micrograph is shown in Fig. 33.5.7.
Acknowledgement:
The authors would like to thank Analog Devices Inc. for supporting this work,
GlobalFoundries for chip fabrication through the 22FDX University Program, and Keysight
Technologies for assistance with measurement equipment.
To improve the resonator Q factor and FTR, while addressing the problematic series
resonance, this paper proposes a multi-section switch-loaded CTL resonator with tapered
switch sizes as shown in Fig. 33.5.2. As opposed to the conventional single-section
resonator loaded with switches of size Wsw, the proposed resonator is divided into n identical
sections, loaded with switches of size n × Wsw. The sections are turned ON sequentially,
where the last section Sn is the first to turn ON. Since only a single section is turned on at
a time and this section is loaded with larger switches (lower RON), QMIN is significantly
improved as can be seen from the numerical simulations in Fig. 33.5.2. For example, the Q
factor for 8 sections is higher than that of a single section case throughout the tuning range.
In addition, QMIN is almost doubled (5.75 for 8 sections vs 3.0 for a single section). The
average quality factor (QAVG) significantly increases from 4.8 for a single section to 14.6 for
8 sections. The Q factor of a multi-section resonator with infinite number of sections thus
approximates a monotonically decreasing curve between QON and QOFF for the single section
case. In addition, the tuning range is roughly unchanged since the overall COFF and RON are
the same. As the inductance of each section is scaled by a factor 1/n and the switch
capacitance by a factor n, fs is almost constant. Thus, the undesired series resonance in
the multi-section case does not fall within the tuning range by using the large switches of
size n × Wsw, as long as Wsw is sized to avoid the undesired series resonance in the singlesection case.
550 • 2025 IEEE International Solid-State Circuits Conference
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ISSCC 2025 / February 19, 2025 / 3:00 PM
180
Osc. Freq. (GHz)
160
140
120
100
80
60
0
0.2
0.4
0.6
Normalized Vctrl (V)
0.8
1
Figure 33.5.1: Model of magnetically tuned CTL (top). Discontinuous FTR due to series Figure 33.5.2: Schematic and simulation of the proposed resonator, showing the
improvement in Q factor and FTR due to sectioning and switch-size tapering.
resonance (middle). Q factor reaching a minimum as the switch turns ON (bottom).
Figure 33.5.4: Small signal simulations of the VCO core admittance (top-left), tank
Figure 33.5.3: Schematic of the prototype VCO utilizing a differential 4-section switch- susceptance (top-right), tank impedance (bottom-left), and loaded tank Q (bottomright).
loaded CTL. The second harmonic is extracted at the output.
33
Figure 33.5.5: Measured vs simulated VCO performance. FTR (top-left), output power
Figure 33.5.6: Comparison with prior-art wideband VCOs.
(top-right), PN across TR (bottom-left), and PN at 202.1GHz (bottom-right).
DIGEST OF TECHNICAL PAPERS • 551
ISSCC 2025 PAPER CONTINUATIONS AND REFERENCES
Figure 33.5.7: Die micrograph.
References:
[1] M. Abbasi and W. Lee, “A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control,” IEEE JSSC, vol. 59, no. 5, pp. 1371-1380, May 2024.
[2] A. Mostajeran and E. Afshari, “An ultra-wideband harmonic radiator with a tuning range of 62GHz (28.3%) at 220GHz,” IEEE RFIC, pp. 164-167, June 2017.
[3] Y. Shu, H. J. Qian and X. Luo, “A 169.6-GHz Low Phase Noise and Wideband Hybrid Mode-Switching Push-Push Oscillator,” IEEE TMTT, vol. 67, no. 7, pp. 2769-2781, July
2019.
[4] R. Kananizadeh and O. Momeni, “A 190-GHz VCO With 20.7% Tuning Range Employing an Active Mode Switching Block in a 130 nm SiGe BiCMOS,” IEEE JSSC, vol. 52, no.
8, pp. 2094-2104, Aug. 2017.
[5] T. LaRocca, J. Liu, F. Wang, D. Murphy and F. Chang, “CMOS digital controlled oscillator with embedded DiCAD resonator for 58-64GHz linear frequency tuning and low phase
noise,” IEEE IMS, pp. 685-688, June 2009.
[6] T. Tapen and A. Apsel, “Ultrawideband Frequency Synthesis Using the Compact Tunable Transmission Line (CTTL),” IEEE TMTT, vol. 70, no. 7, pp. 3374-3384, July 2022.
[7] A. Tang, Y. Kim, Y. Zhang, R. Huang and M. . -C. F. Chang, “A W-Band FMCW Radar System-on-Chip Employing Synchronized Switching Digitally Controlled Artificial Dielectric
for Chirp,” IEEE IMS, pp. 677-679, June 2019.
[8] X. Liu and H. C. Luong, “Analysis and Design of Magnetically Tuned W -Band Oscillators,” IEEE TVLSI, vol. 30, no. 6, pp. 732-743, June 2022.
[9] Z. Huang and H. C. Luong, “An 82-107.6-GHz Integer- N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling
Delta-Sigma TDC,” IEEE JSSC, vol. 54, no. 2, pp. 358-367, Feb. 2019.
[10] H. Jalili and O. Momeni, “A 0.34-THz Wideband Wide-Angle 2-D Steering Phased Array in 0.13- μ m SiGe BiCMOS,” IEEE JSSC, vol. 54, no. 9, pp. 2449-2461, Sept. 2019.
• 2025 IEEE International Solid-State Circuits Conference
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