03/24/2011
ECE 332
Mid Term
30 points total
Name: _______________________________________________________
I have not given help or taken help from anyone during the exam.
SIGNATURE: _____________________________________DATE:_______________
For Instructors Use only
Check all that are verified
Software Section
(a) Source code compiled [ ]
(b) Test bench compiled [ ]
(c) Results Verified [ ]
Hardware section
(a) Results Verified for F1 [ ]
(b) Results Verified for F [ ]
Signature ______________________________
Part 1:
this section contains 12 points
Given the following functions
F1 = (a.b) + (b.c) + (a'.c)
F2 = (b'.c) + (a’.c) + (a’.b’.c)
F = F1 + F2
Deliverables for part 1:
1) Implement the function F1 using TTL gates and trainer kit. Show the result to the
instructor (3 points)
2) Write a simplified Boolean expression for F and minimize the expression to the
minimum number of gates possible.(show your steps) (2 points)
3) Write down the truth table for F1 and F. (2 points)
4) Draw the logic circuit of F (using AND and OR gates) and its equivalent using only
NAND gates. (2 point)
5) Implement the function F using TTL (NAND) gates and trainer kit. Show the result
to the instructor (3 points)
NOTE : A ‘ indicates an inverter (NOT gate) in the above expressions. Also a table for
the IC numbers and their corresponding gates is provided below.
IC
Number Gates
74LS00
74LS02
74LS04
74LS08
74LS32
74LS86
4 NAND with 2 inputs each
4 NOR with 2 inputs each
6 Inverters
4 AND with 2 inputs each
4 OR with 2 inputs each
4 XOR with 2 inputs each
Part 2:
This section contains 16 points + 1 bonus point.
Design a circuit that can take 4 bit input and displays the corresponding hex-decimal
value to the complement of the input four times on all four seven segment display.
Numbers from 10 to 15 should be displayed as "A","b","C","d","E" and "F".
Deliverables for part 2:
1) Write down the minimized expressions for each segment (a,b,c,d,e,f and g). (Show
Steps) (3 point)
2) Write down VHDL codes to simulate and implement the above circuit on CPLD
a) Source code containing entity and architecture declaration. (4 point)
b) Test bench for the source code. (3 point)
c) Simulate the model using behavior simulation and print the waveform. (2 point)
d) Write a UCF file to implement it on CPLD. (1 point)
e) Show the working circuit as expected to the instructor. (3 point)
f) An extra bonus point will be given if you write the VHDL code with concurrent
statements (When-Else statement). (1 Bonus point)
Instruction:
1) after you are done, create a folder called “yourname_midterm”.
2) This folder should contain your VHDL source code(s), test bench, .ucf file and your
waveform in .wcfg format.
3) Zip this folder and email it to me: asalman@gmu.edu from your gmu account with
subject "your name midterm exam".
Part 3:
this section contains 2 points
What should be the values of Unused pins such that the operation of the circuit remains
un-affected by its value.
Unused can take values from: ‘0’ (ground), ‘1’ (VCC), ‘X’ (Don’t Care)
Z
Unused 1 = __________
Unused 2 = __________
Unused 3 = __________