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1
Analysis of UCIe 48/64 GT/s Electrical Links
Zuoguo Wu, Sr Member, IEEE and Jong-Ru Guo, Member, IEEE
Abstract The Universal Chiplet Interconnect Express (UCIe) standard, developed with significant contributions from the
authors, has emerged as a key solution for chiplet-based architectures, offering enhanced scalability, efficiency, and
performance. This paper presents an analysis of UCIe electrical links operating at data rates of 48 and 64 GT/s. Leveraging our
experience in the UCIe standard since its inception, we explore the technical advancements that enable these data rates, including
improvements in signal integrity and power efficiency. The analysis provided in this paper served as critical data inputs for the
UCIe consortium, leading to the subsequent evolution of the standard. We examine link performance and reliability through
detailed modeling of failure probability distributions, highlighting the challenges and solutions associated with error
management and fault tolerance. Design considerations for extending UCIe data rates are discussed, along with future directions
for the standard.
Index Terms— artificial intelligence (AI), chiplet-based architectures, die-to-die (D2D) interconnects, error management, highperformance computing (HPC), machine learning (ML), physical layer (PHY), power efficiency, signal integrity, UCIe.
M
I. INTRODUCTION1
ACHINE Learning (ML) and Artificial Intelligence
(AI) applications are rapidly expanding across
various industries, driving transformative changes in how
data is processed and utilized. The exponential growth of
machine generated data has created an unprecedented
demand for scalable data processing infrastructure, exerting
significant pressure on both computational power and the
connectivity between compute units within data centers [1],
[2], [3]. To address these demands, computing architectures
must satisfy three key requirements: (1) low-latency, highbandwidth connections in modular designs, (2) scalability
and flexibility in architecture, and (3) high manufacturing
yield. Consequently, chiplet-based architectures have
become a promising solution for high-performance
computing (HPC). The Universal Chiplet Interconnect
Express (UCIe), introduced in 2022, is increasingly adopted
as a standard for chiplet applications [4], [5].
UCIe was established as an industry standard for die-todie (D2D) interfaces, facilitating efficient chiplet
integration and supporting data rates of up to 32 GT/s while
accommodating various protocols, including PCI Express
(PCIe), Compute Express Link (CXL), and custom data
streaming. Since its introduction, UCIe has improved
reliability across protocols, added usage model for
1
Submitted to IEEE Open Journal of the Solid-State Circuits Society
Special Issue on Chiplet Interconnect and Architectures on June 24th, 2025.
Zuoguo Wu is with Intel Corporation, Santa Clara, CA 95054 USA (email: zuoguo.wu@intel.com).
Jong-Ru Guo is with Intel Corporation, Hillsboro, OR 97124 USA (email: jong-ru.guo@intel.com).
automotive applications, introduces a standardized system
architecture for manageability, and included a DFx
architecture for vendor-agnostic interoperability. As
package integration technology continues to advance
(Figure 1) the UCIe specification is evolving to support
even higher data rates of 48 and 64 GT/s.
Figure 1 Packaging Technologies
This paper is organized as follows: Section II provides a
high-level overview of UCIe, highlighting their distinct
features and applications for both standard and advanced
packages. Section III discusses the technical advancements
that support increasing data rate to 48 and 64 GT/s,
reflecting the original analytical work by the authors that
informed these enhancements. Section IV focuses on
analyzing link performance and physical layer (PHY)
reliability, providing an in-depth examination of failure
probability distributions through detailed modeling, which
played a crucial role in shaping the UCIe specification.
Section V presents practical examples of UCIe design
implementations. Section VI concludes the paper by
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summarizing the key findings and exploring future
directions and potential developments.
II. HIGH-LEVEL OVERVIEW OF UCIE
The UCIe specification employs a layered approach to
achieve industry-leading key performance indicators (KPIs)
while ensuring interoperability and future scalability [6],
[7], [8]. It consists of three primary layers: the protocol
layer, the D2D adapter layer, and the physical layer.
In the protocol and D2D adapter layers, UCIe primarily
supports CXL and PCIe to facilitate data transmission,
coherence, and memory-related operations. Additionally,
UCIe accommodates data streaming from various custom
protocols, enabling rapid scalability for CPU, GP-GPU, and
switch architectures that utilize smaller dies. Further details
are available in the UCIe 2.0 specification [9].
The physical layer supports both 2D and 2.5D in-package
chiplet integrations through UCIe-S and UCIe-A [10].
UCIe-S uses a standard package to integrate multiple
known-good dies (KGDs), supporting longer channel
lengths (~25 mm) with package redistribution distribution
layer (RDL) metals while maintaining low manufacturing
costs. UCIe-A supports shorter channel lengths (~2 mm)
with smaller metal size and spacing available in a silicon
process, providing significantly higher bandwidth density.
UCIe-A utilizes advanced packaging technologies to
connect KGDs, including: (1) silicon interposer, which uses
the silicon die as an interposer to connect KGDs with metal
wires [11], [12]; (2) silicon bridge, which uses silicon die as
a bridge embedded in a package, such as Intel’s Embedded
Multi-die Interconnect Bridge (EMIB) [13]; and (3) silicon
bridge integrated within Fan-Out package assemblies [14].
The physical characteristics of both standard and advanced
package integrations are summarized in Table I.
Table I Physical Characteristics of UCIe-S and UCIe-A
UCIe-S
UCIe-A
Type of Package
Standard
Advanced
Organic
Interposer,
Substrates
Si Bridge, Fanout
Cost
Lowest
High / Medium
Routing Density
Lower
Higher
Bump Pitch (µm) 100 to 130
25 to 55
Flexibility
Flexible, longer
Strict, shorter
The unit building block of the UCIe architecture is a
module that comprises N single-ended data lanes, where N
equals 16 for UCIe-S and 64 for UCIe-A, along with two
signals for phase-1 and phase-2 forwarded clocks [10], [15].
Other values of N are also possible, such as half-width
modules. Figure 2 illustrates a 64-data-lane UCIe module,
and Figure 3 details the UCIe PHY circuit architecture.
Additionally, in each module there is one signal for "Valid,"
indicating data validity status, one signal for "Track," used
to monitor clock edge deviation due to voltage and
temperature fluctuations, and sideband signals for link
initialization, configuration, training, and protocol
handshaking. Multiple UCIe modules can be configured to
extend the desired bandwidth target. Source-synchronous
clocking and matched clock/data delay paths are utilized to
optimize noise rejection [16], [17]. UCIe accommodates
both 2-way and 4-way interleaving designs and allows for
the two forwarded clocks to be set up either as a differential
pair or as in-phase and quadrature (I/Q) clocks.
Figure 2 UCIe Layers and Module
Figure 3 UCIe PHY Architecture
To meet performance requirements, transmitter deemphasis and receiver continuous time linear equalization
(Rx CTLE) are implemented. Transmitter de-emphasis is up
to 2.2 dB, while Rx CTLE provides a maximum 3 dB DC
attenuation with a 1 dB gain attenuation step.
To evaluate whether a UCIe interconnect channel meets
specifications, channel signal integrity (SI) analysis with
rectangular eye mask is proposed. The mask defines the eye
height (EH) and eye width (EW), which are used to
determine pass/fail conditions. For data rates between 4 and
16 GT/s, the required values are EH/EW = 40 mV / 0.75
UI, and for data rates between 24 and 32 GT/s, the required
values are EH/EW = 40 mV / 0.65 UI. Equivalent insertion
loss and crosstalk metrics can be derived based on the SI
analysis [9].
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III. ENABLERS FOR 48 AND 64 GT/S
While UCIe-S and UCIe-A have provided scalable
interconnect solutions up to 32 GT/s, the increasing demand
for higher bandwidth in ML, AI, and HPC applications has
necessitated even faster interconnect speeds. To address
this, the UCIe consortium has introduced enhancements that
push data rates to 48 GT/s and 64 GT/s.
Pulse amplitude modulation with 4 levels (PAM-4) is a
popular signaling method for high-speed I/O, including
PCIe 6.0/7.0 and Ethernet over 50 GT/s. It offers reduced
channel loss due to its lower Nyquist frequency. However,
PAM-4 requires a higher signal-to-noise ratio (SNR)
because of its multi-level signaling. Fundamentally, PAM-4
is closer to the Shannon Capacity limit than non-return-tozero (NRZ), making it a suitable solution for systems where
channel bandwidth is limited. Reference [18] provides a
detailed SNR table and a plot comparing PAM-4 to the
Shannon Capacity, illustrating these characteristics.
However, UCIe operates with shorter channels than offpackage I/O and demands much lower power dissipation,
making it more in the domain of power-limited systems,
even at 64 GT/s. In such power-limited scenarios, NRZ
often remains the optimal choice. Additionally, other
factors must be considered; for instance, the achievable bit
error rate (BER) of PAM-4 is often around 1E-6 or higher,
necessitating Forward Error Correction (FEC), which can
add significant latency to the link.
As development progressed, significant challenges
emerged, particularly in signal integrity. To overcome these
challenges, enhancements were made to the performance of
transmitter feed-forward equalization (Tx FFE), as
illustrated in Figure 4, and Rx CTLE, while maintaining
low power efficiency targets to ensure stable link operation.
3
determines its optimality based on the received signal’s eye
height and eye width. While the link may be re-trained if
the error rate exceeds certain thresholds, continuous Tx
FFE adaptation is not mandatory.
Table II Tx FFE Coefficient Presets
Accuracy
P0
P1
P2
P3
P4
P5
0
-0.05
0
-0.05
0
-0.05
1
0.95
0.9
0.85
0.8
0.75
0
0
-0.1
-0.1
-0.2
-0.2
+/- 0.025
+/- 0.025
+/- 0.025
+/- 0.025
+/- 0.025
For data rates of 48 and 64 GT/s, employing Rx
equalization in conjunction with Tx equalization is required
to facilitate proper link operation. The Rx equalization, as
outlined in the UCIe specification as a reference behavioral
model for channel analysis, adheres to the following design
criteria:
1) Transfer function: Utilizes a simple 1-zero, 2-pole
configuration.
2) Adjustable parameterized DC gain: Has a gain value
less than unity (negative in dB).
3) Consistent peak gain: Is fixed at 0 dB, regardless of
the DC gain level.
4) Peak gain frequency: Is aligned with the Nyquist
frequency, independent of DC gain adjustments.
The frequency response of the Rx equalizer is captured
by the following closed-form equations:
(1)
(2)
Figure 4 Single-Ended Tx 3-tap FFE
Tx FFE includes three taps (pre-cursor, main cursor, and
post-cursor), which help mitigate the channel's InterSymbol Interference (ISI). Six predefined presets, P0
through P5, have been introduced to accommodate various
channel conditions, as shown in Table II. When Tx FFE is
enabled, a preset is selected, and the link training algorithm
(3)
where
,
is the DC gain value, and is the
peak frequency, set at 24 GHz and 32 GHz for 48 GT/s and
64 GT/s, respectively.
It is recommended to provide a minimum of seven CTLE
settings to span the DC gain range from -6 dB to 0 dB, with
increments of 1 dB. Figure 5 shows the reference Rx CTLE
responses for 64 GT/s. Additionally, designers have the
option to implement a 1-tap Decision Feed Equalizer (DFE)
alongside the CTLE, which can potentially enhance signal
integrity at a data rate of 64 GT/s.
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This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
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Figure 5 Reference Rx CTLE for 64 GT/s
The rectangular eye mask is easy to implement and
provides direct timing and voltage mapping, making it a
popular choice for its simplicity, including UCIe up to 32
GT/s. However, it is also conservative, as real signals have
sloped edges (finite slew rates), which can result in many
channels failing to clear the corners of the eye mask for
higher data rates. To address this issue, the authors
proposed a diamond-shaped eye mask for 48 and 64 GT/s to
the UCIe consortium.
To achieve the lowest BER, a study was conducted
comparing various signaling schemes. The findings indicate
that NRZ signaling outperforms PAM-4 and other higherorder PAM schemes for data rates of 48 and 64 GT/s. As
part of the study, the channel eye mask requirements were
revised to a diamond shape. The updated specifications
include an eye width of 0.65 UI and a maximum eye height
of 65 mV at the horizontal center of the eye. Figure 6
presents the SI analysis of representative UCIe channels
across two different transmitter output swings; further
details of the channel models are available through the
UCIe consortium. The result for UCIe-A operating at 64
GT/s with 0.4V (spec minimum) output is borderline
between pass and fail. This suggests that further channel
optimization may be necessary to ensure consistent
performance, and improvements are being made at the time
of this paper’s writing. Alternatively, operating the link
with a slightly higher output than the minimum specified
could provide the necessary margin.
Figure 6 Representative UCIe Channel Eye Diagrams
IV. LINK PERFORMANCE AND PHY RELIABILITY ANALYSIS
Although the diamond eye shape provides increased
solution space, a statistical approach is necessary to analyze
the full link, encompassing channel variation and
distribution, circuit jitter, and voltage noise sources. For
example, eye height varies depending on the data sampling
position, so the interaction between voltage noise and
timing jitter must be considered. The BER target for 48
GT/s remains at 1E-15, whereas the target for 64 GT/s has
been adjusted to 1E-12. At these rates, both UCIe-S and
UCIe-A configurations require Rx termination to maintain
signal integrity. The fixed termination power results in a
smaller overhead in terms of pJ/b at higher data rates,
estimated to be less than 0.05 pJ/b at 64 GT/s. To simplify
clocking options, the 48/64 GT/s configuration employs a
quarter-rate free-running clock, with two forwarded clock
signals operating continuously and separated by 90 degrees
in phase. The decision regarding the forwarded clock
phases is based on a trade-off between available phases
(transmitting I and Q phases), common mode noise
(transmitting differential single phase), and the number of
forward clock pins (transmitter differential I and Q phases,
which incurs additional pin costs).
In terms of area and power, compared to UCIe designs
operating at 32 GT/s and below, the 48 to 64 GT/s UCIe
achieves 1.7 to 2 times shoreline bandwidth density
(reaching 1975 to 2634 GByte/s/mm for UCIe-A and 278 to
370 GByte/s/mm for UCIe-S) and 1.3 to 1.6 times area
bandwidth density (reaching 1235 to 1646 GByte/s/mm 2 for
UCIe-A and 144 to 192 GByte/s/mm2 for UCIe-S). For
UCIe-S, further optimizations to achieve even higher linear
and areal bandwidth density are possible. Table III shows
the power target at different data rates, with power
distribution approximately divided into 40% for the
transmitter, 40% for the receiver, and 20% for common
circuits.
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5
Table III Power Efficiency Target (pJ/b)
Data Rate (GT/s)
UCIe-S
UCIe-A
4,8,12
0.5-1.0
0.25-0.5
16
0.5-1.0
0.3-0.6
24,32
0.75-1.25
0.3-0.6
48,64
0.75-1.25
0.5-0.75
At a high level, the UCIe specification remains fully
compatible with existing 24 to 32 GT/s systems, requiring
no changes to the Valid and Track signals, sideband
communication, re-try mechanism, or other established
features. The logic layer is augmented to support enhanced
equalization and I/Q clock training.
A. FIT Rate
For highly reliable systems, especially in large-scale
AI/ML computing, a Failure-in-Time (FIT) rate
significantly less than 1 is required for I/O components. FIT
rate is defined as the number of failures in one billion hours
of operation. The Valid signal must be extremely robust, as
any failure can lead to many data errors and unrecoverable
losses. To address this, in addition to re-try mechanism,
Hamming distance
encoding is utilized for the Valid
signal. A block code with minimum Hamming distance
can detect up to
errors and correct up to
errors
[19]. In practice double error detection and single error
correction is often implemented. This approach aims to
minimize the frequency of link re-training events caused by
Valid framing errors while ensuring a sufficiently low
probability of failure. Single error is corrected, while
double errors cause the link to re-train. True failure occurs
when there are 3 or more errors. Since the probability of 4
or more errors is negligible compared to that of 3 errors due
to low BER, the FIT rate due to Valid can be calculated as:
(4)
The result at 64 GT/s is 1.6E-12 which exceeds the
requirement by many orders of magnitude.
We also evaluate the FIT due to the main band data,
where data lanes are protected by cyclic redundancy check
(CRC). UCIe employs a 128-byte message (n = 1024) and
initiates a re-try when an error is detected. A hard failure
occurs when an error escapes CRC detection. The UCIe
CRC,
with
the
generator
polynomial
of,
can detect single, double, triple, all
odd number of errors, and a single error burst up to 16 bits
[19], [20].
It is important to recognize that not all data errors occur
independently. For instance, jitter induced by power supply
noise, often dominated by package resonance frequencies
ranging from tens to hundreds of MHz, can lead to error
correlation due to its much lower frequency compared to
the data rate. Additionally, jitter in the forwarded clock can
affect multiple data lanes simultaneously, resulting in error
correlation among data bits. Since CRC is computed across
all the data within the message block, we can think of it as a
form of spatial error correlation.
We construct the following error model:
Correlated Term: A common jitter distribution
applied to all data simultaneously, with one random
variable drawn from
for all data bits.
Uncorrelated Term: An independent jitter distribution
for each data bit, resulting in
random variables
drawn.
Total jitter for each data bit is
. Errors occur when
total jitter exceeds a certain limit, denoted .
The probability of errors is:
(5)
Where function 𝜓 is defined by:
(6)
is implicitly determined by BER:
(7)
Consider the case of Dual-Dirac
:
(8)
Integral
can be rewritten as:
(9)
The upper bound of
can be evaluated by:
(10)
The above derivation is based on the common DualDirac jitter distribution model. To accommodate more
general scenarios and allow for some guard band, we now
introduce “correlation adjustment factor”
(where the
Dural-Dirac distribution is the special case of
):
(11)
For
, fast convergence is achieved in
equation (11). We evaluate UCIe 64 GT/s x64 link with
different values of . As shown in Table IV,
is
achieved across a wide range of values.
Table IV Data Lane FIT Rate of UCIe 64 GT/s x64
correlation factor s
2
10
1000
Re-Try Rate
1.02E-09 1.02E-09
1.02E-09
per 128B
Re-Try #
4.10
4.10
4.10
per second
FIT after CRC
5.25E-15 6.56E-13
6.56E-07
The analysis presented in the "FIT Rate" section is original
work by the authors and represents part of our contribution
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content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2025.3605558
to the UCIe standard. This method was presented to and
adopted by the UCIe Electrical Workgroup as part of the
standard's development.
B. DFE Error Propagation
Error causes by DFE requires special attention due to
error propagation. One can think of it as temporal error
correlation, where an error in one bit can affect the error
probability of many subsequent bits. Typically, in highspeed SerDes, a worst-case error propagation is assumed,
and FEC is designed to correct for the maximum length
error burst [21]. However, this usually leads to a strong
FEC that can correct many errors. The power and silicon
area overhead for a strong FEC may be prohibitive for a
lower power high-density link like UCIe. Our goal is bound
the DFE coefficients such that the link FIT rate is not
limited by DFE error propagation.
We devise a mathematical model to calculate the error
propagation probability. While currently UCIe uses NRZ
and 1-tap DFE, the model is applicable for general PAM
and multi-tap DFE, anticipating future data rate scaling.
Additionally, it can be utilized in other high-speed, lowlatency I/O applications where a lightweight FEC may be
advantageous.
C. Error Propagation Mathematical Model
The probability of a -th UI error extending to
(denoted ) for -level PAM signaling is:
With a finite number of DFE taps, the sequence reaches
geometric convergence after terms. Hence, we obtain:
(17)
Finally, by the definition of error propagation, FBER is
related to BER by:
(18)
Equation set (12-18) facilitates the evaluation of the DFE
error burst probability of any length, i.e. computing all
and
terms. This information, combined with linkspecific CRC and any supported lightweight FEC, provides
the necessary information to define the DFE boundary
conditions for the link to meet the reliability requirements.
The analysis presented in the "DFE Error Propagation"
section is original work by the authors and represents part
of our contribution to industry standards. This method was
presented to and adopted by both the PCI SIG Electrical
Workgroup and the UCIe Electrical Workgroup as part of
the PCIe and UCIe development.
V. DESIGN CONSIDERATIONS
UI
(12)
Here,
are the coefficients of -tap
DFE, β is a metric for Dual-Dirac bounded noise, and is
defined as:
(13)
The First Bit Error Rate (FBER) is the bit error rate
without accounting for any burst error [22]. The parameter
is related to FBER by:
(14)
The series product
represents the conditional
probability of an error burst of length
UI, after the
first error occurred (
):
(15)
The probability of a burst length exceeding (denoted
) can be computed by summing all probabilities of burst
lengths greater than :
(16)
The UCIe standard is designed to provide a scalable and
efficient interconnect solution for chiplets, yet several
design challenges arise when implementing it in real-world
systems [23][24]. These challenges primarily stem from
physical and electrical design considerations that impact
performance and scalability.
1) Design Architecture and Process Variability:
Variations in manufacturing processes can lead to physical
discrepancies that affect electrical performance. Achieving
optimal latency while maintaining high speed and
bandwidth is a significant challenge. Scaling to a multichiplet
architecture
further
complicates
routing,
necessitating a balanced trade-off between bandwidth and
power efficiency.
2) Signal Integrity and Power Integrity (PI): As UCIe
operates at higher speeds, optimizing the channel to
minimize insertion loss, reflection, and crosstalk becomes
critical. On the power integrity side, meticulous power
management is required to avoid peak-to-peak voltage
fluctuations and switching noise, as well as to prevent
potential hotspots when delivering power to chiplets. Cooptimization of circuit architecture, SI, and PI is essential.
3) Fault Tolerance and Test-Validation: D2D links
must address failure scenarios in die integration and provide
robust redundancy mechanisms for lane repairs in highdensity interconnects. The lack of exposed probe points
complicates testing and debugging, necessitating more
complex test and validation methodologies.
While the UCIe standard does not mandate a specific
implementation, several design approaches are worth
considering for extending data rates to 64 GT/s:
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1) Distributed Effects at High Speed: Pay attention to
distributed effects at high speeds, particularly at 64 GT/s.
These effects can be leveraged for improved performance,
as total capacitance is often less than the sum of individual
components.
2) Pad Capacitance (Cpad) Mitigation: Device
capacitance, metal routing and electrostatic discharge
(ESD) protection diodes can add up significant total Cpad.
Utilize T-coil benefits, which are applicable to both Tx and
Rx, to achieve broadband Cpad reduction, as shown in
Figure 7(a) and (b) [25], [26]. Theoretically, "Ce" can be
completely cancelled if the conditions in Figure 7(c) are
met, though practical factors may influence results. An
alternative solution, shunt-series peaking as shown Figure
7(d), can also be very effective.
7
Figure 9 Matched Rx Front End
5) Considering Low Power Clocking Circuit Building
Blocks. Below are some examples [28]:
a. Inverter-based delay line and phase interpolator
b. Inverter-based duty cycle correction
c. Digital control loops
Furthermore, uncorrelated random sampling technique
can be used to measure duty cycle, phase difference, and
other timing related parameters [29].
These approaches aim to address the challenges
associated with extending UCIe data rates while optimizing
performance and efficiency.
VI. SUMMARY AND FUTURE DIRECTIONS
Figure 7 Cpad/ESD Mitigation
3) Minimizing High-Speed Nodes: For example,
consider a 4-phase combination at the Tx pad shown in
Figure 8 [27]. For power optimization, explore high swing
NMOS-only drivers with boosted pre-driver power rails, as
various voltage rail boost circuit techniques exist.
Figure 8 Tx Driver/Pre-driver Example
4) Matched Rx Front End: Figure 9 shows a matched
Rx reference design for an inverter-based amplifier to
minimize power. Use tuned inverters/buffers for Rx delay
training. Process, voltage, and temperature (PVT)
compensation can also be included by utilizing the Track
signal.
The UCIe standard has firmly established itself as a
robust interconnect solution for chiplet based architectures,
offering significant advantages in scalability, efficiency,
and performance. With a yearly release cadence, the
standard has continually expanded its capabilities,
positioning UCIe as a critical enabler for high-performance
computing and ML/AI systems. Looking ahead, several
future directions for UCIe are anticipated:
1. Continued Data Rate Scaling: As data rates continue
to increase, changes in circuit architecture may become
necessary. For example, the overhead associated with
maintaining a 'matched' architecture between data and
forwarded clock increases with the data rate. Implementing
a combination of matched and unmatched architectures
could be beneficial across a wide range of data rates. At
some point, NRZ signaling may no longer be optimal,
necessitating careful studies to evaluate trade-offs between
circuit complexity, power, latency, and interoperability.
2. Expansion to 3D Integration: Another order of
magnitude increase in KPIs can be achieved through 3D
integration, which is already well-defined in the current
UCIe specification [18], [30], though not covered in this
paper. Continued increases in density and data rate are
expected over time.
3. Optical UCIe: As data center systems evolve, the
proportion of total system power consumed by I/O is
increasing. Optical I/O presents new opportunities for
scaling, yet there remains a need for low-power, low-
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This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2025.3605558
latency, high-bandwidth short-reach electrical I/O. UCIe is
particularly well-suited for co-packaged optics (CPO), as its
KPIs ensure the full realization of optical I/O potential. A
re-timer feature is already defined, and further expansion
and optimization in this area are anticipated.
4. Further Power Optimization: With the increasing
I/O bandwidth demand of specialized ML/AI systems,
power efficiency is becoming ever more critical. UCIe is
likely to expand its profiles to include significantly more
energy-efficient options (compared to Table III) for
controlled environments where general interoperability is
not an absolute requirement.
5. Extension to More Packaging Technologies and
Usage Models: Currently, UCIe supports standard (100130 µm bump pitch), advanced (25-55 µm bump pitch), and
3D package types. The circuit architecture is applicable to
bump pitches outside these ranges, and enhancements to the
physical and logical layers could support more usage cases.
For example, there is no fundamental limitation requiring
Tx and Rx to have the same bandwidth, making it
conceivable for UCIe to extend to asymmetrical bandwidth
applications such as memory interfaces.
These future directions highlight the potential for UCIe
to continue evolving and adapting to meet the demands of
emerging technologies and applications.
ACKNOWLEDGMENT
The authors would like to thank Swadesh Choudhary,
Debendra Das Sharma, Sashank Krishnamurthy, Mozhgan
Mansuri, Susnata Mondal, Peter Onufryk, Gerald Pasdast,
Zhiguo Qian, Sathya Tiagaraj, Duye Ye, and the members
of UCIe Consortium Electrical Workgroup for valuable
discussions and contributions.
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This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2025.3605558
> OJ-SSCS-25-0015 <
Zuoguo Wu (S’90–M’94–SM’23) earned his Bachelor of Science degree
in physics from the University of Science and Technology of China, Hefei,
Anhui, China, in 1987, where he was part of the Special Class for the
Gifted Young, entering college at the age of 13. He received his Ph.D. in
electrical engineering from Texas A&M University, College Station,
Texas, USA, in 1993.
He is currently with Intel Corporation, Santa Clara, CA, USA, serving
as a Senior Principal Engineer and I/O Circuit Architecture Manager. He is
a principal author of the Universal Chiplet Interconnect Express (UCIe)
specification, having defined its physical layer architecture and circuit
approach. He has also been a key contributor to every generation of the
PCI Express (PCIe) specification since version 3.0. Before joining Intel, he
held positions at Texas Instruments, Microtune, Utmost Technologies, and
Micropac Industries, where he designed integrated circuits for computer
disk drives, wireless, and optical communication systems.
Dr. Wu holds 162 patents worldwide and has authored over 50 papers,
including both external publications and Intel-internal papers. He co-chairs
the Electrical Workgroup within the UCIe Consortium and has been an
invited speaker at various conferences including ISSCC, ISLPED, EPEPS,
and ISQED.
Jong-Ru Guo (M’03) earned his master’s degree in electrical engineering
from National Tsing-Hua University, Hsinchu, Taiwan, in 1996. He
received his Ph.D. in electrical engineering from Rensselaer Polytechnic
Institute, Albany, New York, USA, in 2005.
He is currently with Intel Corporation, Hillsboro, Oregon, USA, as a
Senior Staff Engineer since 2012. He works on developing industry
standards such as PCIe and UCIe, focusing on electrical specification
development, including I/O architecture and circuit feasibility study and
development. He also delivered the CXL disaggregated memory system
design to support the latest high performance computing function. Prior to
joining Intel, he was an Advisory Engineer with High-Speed Serial link
(HSS) design group in IBM at E. Fishkill, NY, starting in 2005. During
this time, he developed the key circuits in the high-speed serial I/Os
operating at the data rates ranging from 6.4 Gbps to 28/32 Gbps in both
CMOS and SOI-CMOS technologies. He holds more than 40 patents and
has published papers in IEEE conferences such as Transactions on VLSI
Systems, CICC, JSSC, Photonics Journal, Proceedings of the IEEE, and
Journal on Exploratory Solid-State Computational Devices and Circuits.
Dr. Guo was the co-recipient of 2011 IEEE Custom Integrated Circuits
Conference (CICC) Best Regular Paper Award, as well as the other Intel
internal awards.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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