2025
ALWAYS ON REAL TIME CLOCK
[AON-RTC]
MICROARCHITECTURE SPECIFICATION
RAZI MUDASSIR-241213
1
Contents
1.
Features ................................................................................................................................................ 2
2.
Block diagram........................................................................................................................................ 2
3.
4.
5.
1.1
Level 0 Diagram:............................................................................................................................ 2
1.2
Level 1 Diagram:............................................................................................................................ 3
1.3
Block level architecture:................................................................................................................ 4
Functional description .......................................................................................................................... 6
3.1
Configuring RTC............................................................................................................................. 6
3.2
Reading time value........................................................................................................................ 6
3.3
Data synchronization between MCU and RTC: ............................................................................. 6
3.4
Event generation:.......................................................................................................................... 8
3.5
Timing calculations: ...................................................................................................................... 9
3.6
Timer accuracy: ........................................................................................................................... 10
Block description ................................................................................................................................. 10
4.1
APB sub ....................................................................................................................................... 10
4.2
REG BANK HS............................................................................................................................... 11
4.3
REG BANK LS ............................................................................................................................... 11
4.4
Timer ........................................................................................................................................... 12
4.5
CH0, CH1, CH2 ............................................................................................................................. 12
Register description ............................................................................................................................ 14
Register map for RTC: ............................................................................................................................. 14
CTL Register:............................................................................................................................................ 14
EVFLAGS register:.................................................................................................................................... 16
SEC register ............................................................................................................................................. 16
SUBSEC register....................................................................................................................................... 16
SUBSECINC register: ................................................................................................................................ 17
CHCTL register: ........................................................................................................................................ 17
CH0CMP register ..................................................................................................................................... 18
CH1CMP register ..................................................................................................................................... 18
CH2CMP register ..................................................................................................................................... 18
CH2CMPINC register ............................................................................................................................... 19
CH1CAPT register .................................................................................................................................... 19
SYNC register:.......................................................................................................................................... 19
2
1. Features
The always-on real-time clock or AON_RTC has▪
▪
▪
▪
▪
▪
70-bit incrementing counter
Programmable increment support for ppm adjustment for precise time-keeping
Three general purpose channels with support for generating delayed events
Runs on 32KHz clock
APB configurable registers
Synchronization between MCU and RTC
2. Block diagram
1.1
Level 0 Diagram:
Figure 1: Top level diagram of RTC
3
1.2
Level 1 Diagram:
Figure 2: Level 1 diagram for RTC
4
1.3
Block level architecture:
Figure 3: block level architecture of RTC
5
3. Signal description
Signal description for the I/O ports of RTC is as follows:
Type
APB
interface
RTC
Signal
Width
Direction
pclk
1
input
presetn
1
input
psel
1
input
pwrite
1
input
penable
1
input
paddr
32
input
pwdata
32
Input
pready
1
Output
prdata
32
Output
Sclk
Rtc_reset
Capture
Ch0_event
Ch1_event
Ch2_event
Ch0_del_event
Ch1_del_event
Ch2_del_event
Comb_event
1
1
1
1
1
1
1
1
1
1
Input
Input
Input
Output
Output
Output
Output
output
Output
Output
Description
System clock signal with a frequency
of 48MHz.
System reset signal (Active LOW).
APB selection signal, high means the
completer is required to do a transfer.
APB write signal, used to select read
or write operation. Low indicates a
read operation and high indicates
write.
Enable signal used to initiate access
state, data is read or written when it’s
high.
Address bus for the register.
Data bus driven by the requester to
write in the timer registers.
Indicates if the device is ready to
make a transfer. HIGH value indicates
the completer is ready to make a
transfer.
Read data bus, driven by the
completer when there is a read
request by the requester for a specific
value.
RTC clock, running at 32.768KHz.
Reset signal for RTC. Active low
Input capture event for the RTC
Channel 0 event output.
Channel 1 event output.
Channel 2 event output.
Channel 0 delayed event output.
Channel 1 delayed event output.
Channel 2 delayed event output.
Combined event output
6
4. Functional description
4.1 Configuring RTC
RTC has configurable registers that are used to control the behavior of the timer in different manner.
These registers can be configured using APB protocol. The MCU side has an APB interface which works
at 48MHz clock. It takes data from the APB, stores it and synchronizes it with the slower, 32KHz RTC
clock.
4.2 Reading time value
Reading time value can be done by reading the SEC and SUBSEC registers. Reading SEC value latches the
value of SUBSEC register.
4.3Data synchronization between MCU and RTC:
Data synchronization is a highly crucial feature in the RTC. As the RTC runs on a slower clock (32KHz) and
the MCU runs at 48MHz, there needs to be a mechanism to transfer data between the two clock domain
avoiding data-corruption and metastability. A Basic transfer from the MCU to RTC is as follows:
Figure 4: MCU & RTC side register data transfer circuit
The RTC has two types of registers. Non-updatable registers (CTL, SUBSECINC, CHCTL,
CH0CMP, CH1CMP, CH2CMPINC) are not updated at RTC, hence they don’t need to be sent back to
the MCU for it to read. Reading from these registers can be done directly from the MCU side registers.
7
Figure 5: Timing diagram for sampling data from MCU side to RTC
Total delay due to synchronization is = 2 sclk cycle + time from data write to first sclk-posedge. So, in this
design the maximum delay can be 3 sclk cycle and minimum of 2 sclk. Data can NOT be written during
sync_ack HIGH.
Updatable registers (SEC, SUBSEC, EVFLAGS, CH2CMP, CH1CAPT) need to send data to the
MCU side as they change their value for the APB sub to read the up-to-date value. Due to
synchronization, the value at the MCU side is 2 pclk clock cycle delayed.
Figure 6: Updatable registers with 32bit 2-ff synchronizers
Figure 7: Data transfer from RTC side to MCU side
8
The function of SYNC register is to synchronize data between the MCU and RTC by halting the busy
when reading data from it until the synchronization is complete. The SYNC register does not return any
value to the APB bus until all the write requests are completed. The APB sub gets synchronization status
from the MCU side of the RTC and if the data is being synchronized, it halts the bus.
4.4 Event generation:
RTC events are generated by comparing programmable compare values with SEC[15:0] and
SUBSEC[31:16] bits. When the timer value matches or passes the compare value, an event is generated
in the respective channel provided that the channel is enabled.
Figure 8: Event generation for channel 0. ch0cmp = 0x12, event delay=4 cycles
Channel 1 has a capture mode in which it latches the timer value when an external event is triggered.
Figure 9: capture feature in channel 1
Figure 10: Event generation at channel 1 when passing compare value. (event delay-4cycles)
Channel 2 has a continuous compare mode in which when the timer value passes the compare value,
the compare value is increased by a programmable amount.
9
Figure 11: Increment of channel 2 compare value when timer matches or passes ch2cmp
Events can trigger subsequent delayed events by a programmable amount. When an event is triggered,
a delayed event is also scheduled to occur after a given number of cycles. Disabling the channel doesn’t
stop the delayed event generation. To prevent a delayed event from being triggered, the respective
event flag must be cleared.
4.5 Timing calculations:
RTC has two registers for storing rea time value- SEC and SUBSEC. Both are 32-bit registers. The SEC
register holds the value of number of seconds in the timer and SUBSEC holds the value of the ½32 𝑡ℎ
of a second. It also contains a hidden 6-bit accumulator to accommodate the 6 LSB from the
SUBSECINC register. So, the counter is a 70-bit counter. The way the counter increments its value is as
follows:
Figure 12: Increment of SEC and SUBSEC register in RTC
The default value of the SUBSECINC register is 0x00800000 which, for 32Khz (32768Hz) clock increases
1
𝑡ℎ of a second in the SUBSEC register. SUBSECINC is a 24bit register, its 6 LSB bits are
32768
accumulated in a hidden register. SUBSECINC [23:6] are used to increment the value in the SUBSEC
register and the carry of the hidden accumulator is taken as carry in the SUBSEC adder. Omitting the 6bits, the remaining bits (SUBSECINC [23:6]) has a default value of 0x00020000 which corresponds to
the above-mentioned time increment in seconds.
1
0𝑥00000001 ≡ { 32 } 𝑡ℎ 𝑜𝑓 𝑎 𝑠𝑒𝑐𝑜𝑛𝑑.
2
1
0𝑥00020000
1
∴ 0𝑥00020000 ≡ ( 32 ) . (
) 𝑡ℎ 𝑜𝑓 𝑎 𝑠𝑒𝑐𝑜𝑛𝑑 =
𝑡ℎ 𝑜𝑓 𝑎 𝑠𝑒𝑐𝑜𝑛𝑑
2
0𝑥00000001
32768
10
This is when the input clock is running at exactly 32.768KHz which might not always be the case. For that
scenario, we can adjust the value of the SUBSECINC register so that it takes into account the timing
error in the counter and outputs an accurate time value.
𝑆𝑈𝐵𝑆𝐸𝐶𝐼𝑁𝐶 =
238
𝑓𝑛𝑒𝑤
Where 𝑓𝑛𝑒𝑤 is the new input frequency.
4.6 Timer accuracy:
Considering deviation from the ideal case where the clock speed is exactly 32.768KHz. This results in a
value of 0x800000. The minimum amount of frequency deviation that can be adjusted using
subsecinc is –
∆𝑓 =
238
− 32.768 = 3.91 ∗ 10−3 𝐻𝑧
0𝑥800001 ∗ 103
This is the frequency difference between two clocks that will result in a difference of 0x01 in the
subsecinc adjustment. The amount of accuracy of the RTC is106 . |
1
1
−
| = 3.6414717 𝑝𝑝𝑚
32.768𝐾 32.768𝐾 + ∆𝑓
As the operating frequency gets higher, the error due to frequency deviation reduces.
5. Block description
5.1 APB sub
The apb_sub block is used to maintain the APB protocol to read and write data to timer registers. The
block ensures the maintenance of the protocol. It has a single bit flop to hold its current state. wr_en
and rd_en signals are input to the register bank to access read and write registers. wr_bsy signal is used
to halt the bus during synchronization.
Figure 13: APB subordinate block diagram
11
5.2 REG BANK HS
Register bank at the high-speed side. As the MCU runs on a higher clock speed, the APB write could be
corrupted or missed if the registers are configured using a slower clock of the RTC. To prevent this
situation, there is a register bank running on 48MHz which receives the data from the APB bus and then
transfers it to the RTC side registers. This register bank has to parts. One is updatable and the other is
non updatable. Updatable registers need to sync data back and forth with the low-speed registers
because their values are updated in the RTC side. On the other hand, non-updatable registers are not
updated in the RTC. They can only be changed through APB interface, hence no need to update value
from the low-speed side.
Figure 14: updatable High speed register bank
Figure 15: non-updatable high speed register bank
5.3 REG BANK LS
Register bank at the low-speed side. The RTC runs on 32KHz because its always-on (AON) feature, that
requires it to be power efficient. This register receives its data from the high-speed side. Synchronization
needs to be done in order to pass data securely. For this purpose, there is a sync-request and syncacknowledgement signals that ensure the safe transfer of the data. Register bank has two types of
registers. Updatable and non-updatable registers. SEC, SUBSEC, EVFLAG, CH2CMP values are
updated in the RTC domain which are read through APB interface. They need to be synchronized with
the high-speed side of the RTC to be able to transfer read data. Non-updatable registers are not updated
in the RTC side and have a constant value throughout the operation. They change their value only when
there is a write request to the registers from the APB interface. So, they need not to be synchronized.
12
Figure 16: updatable low-speed register bank
Figure 17: non-updatable low-speed register bank
5.4 Timer
Timer block increments the value of SEC and SUBSEC registers and keep the RTC timer up-to-date.
Timer is the core of operation in RTC which operates at 32KHz. It consists of three adders. The 6 bit
adder acts as a hidden accumulator.
Figure 18: Block diagram of timer
5.5CH0, CH1, CH2
Channel 0, 1 and 2 output of the RTC. Their function is similar but varies slightly. Channel 0 compares
timer value to ch0cmp and triggers an output when the value is equal to or passes it. Channel 1 does the
same with ch0comp but it also has a event capture mode in which it latches the time of input event.
13
Channel 2 has a continuous event generation method by incrementing the compare value by
ch2cmpinc amount when an event occurs.
Figure 19: Channel 0 block diagram
Figure 20: channel 1 block diagram
Figure 21: channel 2 block diagram
14
6. Register description
Register map for RTC:
Offset
0h
4h
8h
Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
Acronym
CTL
EVFLAGS
SEC
SUBSEC
SUBSECINC
CHCTL
CH0CMP
CH1CMP
CH2CMP
CH2CMPINC
CH1CAPT
SYNC
Register name
Control
Event flags, RTC status
Second counter, integer part
Second counter, fractional part
Sub-seconds increment
Channel configuration
Channel 0 compare value
Channel 1 compare value
Channel 2 compare value
Channel 2 compare value auto-increment
Channel 1 capture value
AON synchronization
CTL Register: Control register that is used to control the event mask, event delay and enabling the
RTC.
Bit
Name
Access
Reset
value
31:19
RESERV
ED
R
0x0
18:16
COMB_
EV_MAS
K
R/W
0x0
15:12
RESERV
ED
11:8
EV_DEL
AY
7
RESET
6:3
RESERV
ED
2
RTC_4K
HZ_EN
1
RTC_UP
D_EN
0
EN
R
0x0
R/W
0x0
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
EV_MASK [18:16]: Event mask selecting which delayed events that form the combined event. 0h = No
event is selected for combined event. 1h = Use Channel 0 delayed event in combined event 2h = Use
Channel 1 delayed event in combined event 4h = Use Channel 2 delayed event in combined event.
15
EV_DELAY [11:8]: Number of SCLK_LF clock cycles waited before generating delayed events. (Common
setting for all RTC cannels) the delayed event is delayed
0
1
2
3
4
5
6
7
8
9
A
B
C
D
No delay
1 clock cycle
2 clock cycles
4 clock cycles
8 clock cycles
16 clock cycles
32 clock cycles
48 clock cycles
64 clock cycles
80 clock cycles
96 clock cycles
112 clock cycles
128 clock cycles
144 clock cycles
RESET [7]: RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when
reset takes effect.
RTC_4KHZ_EN [2]: RTC_4KHZ is a 4KHz reference output, tapped from SUBSEC .VALUE bit 19 which is
used by AUX timer.
0: RTC_4KHZ signal is forced to 0
1: RTC_4KHZ is enabled (provided that RTC is enabled EN)
RTC_UPD_EN [1]: RTC_UPD is a 16KHz signal used to sync up the radio timer. The 16Khz is SCLK_LF
divided by 2
0: RTC_UPD signal is forced to 0
1: RTC_UPD signal is toggling @16 kHz
EN [0]: Enable RTC counter
0: Halted (frozen)
1: Running
16
EVFLAGS register:
This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to
the corresponding bitfield.
Bit
Name
Access
Reset
value
31:17
RESERVED
R
0x0
16
CH2
R/W
0x0
15:9
RESERVED
R
0x0
8
CH1
R/W
0x0
7:1
RESEVED
R
0x0
0
CH0
R/W
0x0
CH0, CH1, CH2: Channel flags. Value is set to 1 when channel is enabled and the timer value matches or
passes channel compare value.
SEC register:
Second counter value, integer part. Unsigned integer representing real time clock in seconds when
reading this register. When this register is read, the value of SUBSEC is simultaneously latched.
Bit
Name
Access
Reset
value
31:0
SEC
R/W
0x0
SUBSEC register:
Second counter value, fractional part. Unsigned integer representing Real Time Clock in fractions of a
second (VALUE/2^32 seconds) at the time when SEC register was read.
Bit
Name
Access
Reset
value
31:0
SEC
R/W
0x0
17
SUBSECINC register:
Sub-seconds Increment Value added to SUBSEC.VALUE on every SCLK_LFclock cycle.
Bit
Name
Access
Reset value
31:24
RESERVED
R
0x0
23:0
VALUEINC
R/W
0x0
This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value
can be found as
238
, where freq is SCLK_LF clock frequency in Hertz This value is added to
𝑓𝑟𝑒𝑞
SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition,
bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a
hidden 6-bit register that generates a carry into the above-mentioned addition on overflow.
CHCTL register:
Channel configuration register.
Bit
Name
Access
Reset
value
31:19
RESERV
ED
R
0x0
18
CH2_CO
NT_EN
R/W
0x0
17
RESERV
ED
R
0x0
16
CH2_EN
R/W
0x0
15:10
RESERV
ED
R
0x0
9
CH1_CA
PT_EN
R/W
0x0
CH2_CONT_EN: Set to enable continuous operation of Channel 2.
CH2_EN: RTC Channel 2 Enable
0: Disable RTC Channel 2
1: Enable RTC Channel 2
CH1_CAPT_EN: Set Channel 1 mode
0: Compare mode (default)
1: Capture mode
CH1_EN: RTC Channel 1 Enable
0: Disable RTC Channel 1
1: Enable RTC Channel 1
CH0_EN: RTC Channel 0 Enable
0: Disable RTC Channel 0
1: Enable RTC Channel 0
8
CH1_EN
R/W
0x0
7:1
RESEVE
D
R
0x0
0
CH0_EN
R/W
0x0
18
CH0CMP register:
Channel 0 compare value. RTC Channel 0 compare value. Bit 31 to 16 represents seconds and bits 15 to
0 represents sub-seconds of the compare value. The compare value is compared against SEC.VALUE
(15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is
generated when {SEC.VALUE(15:0), SUBSEC.VALUE (31:16)} is reaching or exciting the
compare value.
Bit
Name
Access
Reset
value
31:0
value
R/W
0x0
CH1CMP register:
Channel 1 compare value. RTC Channel 1 compare value. Bit 31 to 16 represents seconds and bits 15 to
0 represents sub-seconds of the compare value. The compare value is compared against SEC.VALUE
(15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 1 event is
generated when {SEC.VALUE(15:0), SUBSEC.VALUE (31:16)} is reaching or exciting the
compare value.
Bit
Name
Access
Reset
value
31:0
value
R/W
0x0
CH2CMP register:
Channel 2 compare value. RTC Channel 2 compare value. Bit 31 to 16 represents seconds and bits 15 to
0 represents sub-seconds of the compare value. The compare value is compared against SEC.VALUE
(15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 2 event is
generated when {SEC.VALUE(15:0), SUBSEC.VALUE (31:16)} is reaching or exciting the
compare value.
Bit
Name
Access
Reset
value
31:0
value
R/W
0x0
19
CH2CMPINC register:
Channel 2 compare value auto-increment. If CHCTL.CH2_CONT_EN is set, this value is added to
CH2CMP.VALUE on every channel 2 compare event.
Bit
Name
Access
Reset
value
31:0
VALUE
R/W
0x0
CH1CAPT register:
Channel 1 Capture Value If CHCTL.CH1_EN = 1 and CHCTL.CH1_CAPT_EN = 1, capture occurs on
each rising edge of the event selected in AON_EVENT: RTCSEL.
Bit
Name
Access
Reset
value
31:16
SEC
R
0x0000
15:0
SUBSEC
R
0x0000
SYNC register:
AON Synchronization This register is used for synchronizing between MCU and entire AON domain. This
register will always return 0, however it will not return the value until there are no outstanding write
requests between MCU and AON.
Note: Writing to this register prior to reading will force a wait until the next SCLK_LF edge. This is
recommended for syncing read registers from AON when waking up from sleep. Failure to do so may
result in reading AON values from prior to going to sleep.
Bit
Name
Access
Reset value
31:1
RESERVED
R
0x0
0
WBUSY
R/W
0x0