This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
1
How To Design a Differential CMOS LC Oscillator
Asad A. Abidi, Life Fellow, IEEE, and David Murphy, Member, IEEE
Abstract—CMOS oscillators that produce high frequencies with
good spectral purity or low jitter are almost always realized
as differential LC oscillators. The paper gives a comprehensive
treatment of this circuit for the practitioner who must make design
choices and tradeoffs, and for the newcomer who wants to learn to
do so. Phase noise is presented in the form of transfer functions
from various noise sources, leading to compact, accurate expressions
that guide design. Best practices for IC layout and operation at
low voltages are given.
A. AM & PM
Sidebands around the oscillation frequency will appear frequently as a result of the analysis that follows. We must
distinguish between sidebands that represent modulation of the
oscillation amplitude without affecting its phase and sidebands
that modulate the phase or frequency of the oscillation without
affecting its amplitude. These distinctions are most clearly
observed with phasors (Fig. 1). The oscillation V0 cos ω0t is
represented by the horizontal phasor of magnitude V0 . If to this we
add the balanced pair Vam of phasors at two frequencies ω0 ± ωm
(Fig. 1(a)), where the phasor pair is formed by scaling down V0
by two conjugate complex numbers, m exp(+ jyA ), m exp(− jyA )
then as time elapses they remain conjugate and modulate the
amplitude of the oscillation sinusoidally with frequency ωm
and depth m = 2VAM /V0 . This is true for any m < 1. Next,
consider the balanced pair with magnitude VPM at the same
image offset frequencies, where the two phasors are formed by
multiplying the V0 phasor with anti-conjugate complex numbers p exp(+ jyP ), −p exp(− jyP ) (Fig. 1(b)). This will modulate
the phase of the oscillation with an index of approximately
p = 2VPM /V0 rad. This relation between the voltage (or current)
phasor magnitude and the oscillation phase uses the small-angle
approximation. In the literature on phase noise measurement, it is
said to have a satisfactory accuracy when ∆φ ≤ 0.2 rad. Beyond
this upper limit, the two sidebands will gradually relate to phase
through the arctan function and will also modulate the amplitude.
A phasor diagram clearly shows that the amplitude and
(pure) phase modulation are orthogonal; that is, each occurs
independently of the other with no coupling between the two.
With the constraints of conjugacy and anticonjugacy, the AM
and PM phasors offer two freely selectable phasor variables; that
is, they are a basis function for any two unrelated phasors, C+
and C− one each at the frequency pair ω0 ± ωm (Fig. 1(c)). Thus,
I. I NTRODUCTION
Differential LC oscillators are almost exclusively used in RFCMOS. Every RF chip needs a custom-designed oscillator, which
by all accounts is developed today using circuit simulators such
as SPECTRE-RF that compute waveforms and noise in periodic
steady state, and on-chip inductors are taken from foundrysupplied libraries or developed with specialized EM simulators.
This design process works well enough for innumerable commercial ICs to successfully meet specifications. However, it is
unsatisfactory because of excessive reliance on the simulator,
which leaves the oscillator designer on a weak footing to explain
satisfactorily the basis of the circuit choices and the finally
achieved performance.
This paper presents in a consistent framework the results of
analyses of the workings of this oscillator that have been scattered
so far across the literature. It differs from a similar paper that
has previously appeared in these pages [1] in two ways:
• It focuses exclusively on the differential LC oscillator which
is nearly ubiquitous, and develops this oscillator into variants
with useful practical properties. It does not attempt to catalog
other oscillator topologies.
• In clear contrast to [1] it develops compact transfer functionlike complete expressions for all properties of the oscillator,
especially phase noise. We have not found any unique
insight emerging from the impulse response approach
C+ = Vpm +Vam
Vpm = 21 (C+ +C− )
advanced by [1] and others. In the design of linear time=⇒
(1)
Vam = 21 (C+ −C− )
C− = V pm −V am
invariant circuits, the transfer function dislodged the impulse
response because the former proved useful in many more
We note that if an AM phasor pair is multiplied by j it
ways. Indeed, our transfer function-based approach reveals
transforms into a PM phasor pair, because j exp(+ jy), j exp(− jy)
physical mechanisms that would otherwise remain elusive
are, in fact, anticonjugate.
and which we show can often be mitigated by design.
Using the equation-based approach, a first-cut design of a
state-of-the-art LC is possible within a few hours of manual B. Discrete Approximate Noise Spectrum
The power spectral density of white noise is a constant
calculations. This can be verified and fine-tuned on a simulator,
and further refined with the extraction of layout parasitic, as the across −∞< f <+∞, with an autocorrelation function N 2 δ (t).
We will discretize this [2] over infinitesimal frequency intervals
last section of this paper discusses.
(1 Hz wide for convenience), which converts it into a two-sided
II. P RELIMINARIES
spectrum of closely packed sinewaves, each with a constant
We will use some ideas throughout this paper, which we will expected power and random phase that lies uniformly in the
interval (−π, +π]. Since any noise waveform is a real voltage
summarize first.
or current, the two-sided spectrum is hermitian, i.e. N[i] = N[−i]
Asad Abidi is with the Electrical & Computer Engineering Department, University
at discrete frequency [i] Hz (Fig. 2). For voltage noise at the
of California, Los Angeles, CA 90095 USA (e-mail: abidi@ee.ucla.edu). David
Murphy is with Broadcom Inc., Irvine, CA 92612 USA
terminals of a resistor R, ⟨N 2 [i]⟩ = 2kT R V2 , ∀i.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
V0
-ωm
+ωm
V AM
θ
(a)
-ωm
C–
(c)
+ωm
V0
+ωm
C+
V0
2
V PM
(b)
L
-ωm
I0
Fig. 1. Phasors indicating (a) AM, (b) PM, and (c) arbitrary sidebands at
ω0 ± ωm .
Re
N[–2]
N[–1]
Im
N[–3]
N[+1]
N[+3]
N[+2]
Fig. 2. Spectral density of white noise discretized over uniform intervals into
sinewaves with constant variance and random phase.
C. Differential Circuits
Fig. 3. Classic NMOS differential oscillator circuit. The pair of coupled inductors
is an equivalent circuit for a center-tapped on-chip symmetrical spiral inductor.
L is the self-inductance of one half of the spiral, and k the coupling coefficient
to the other half.
Groszkowski effect, first described in [4] for differential LC
oscillators. A static shift in frequency is benign because it will
be corrected in typical use by the phase-locked loop that servos
the oscillator to a stable reference frequency.
III. P HASE N OISE
The most important design specification for an oscillator is
its frequency tuning range. The most important performance
specification in communication systems is its close-in-phase
noise or jitter1 . We have long advocated for a phasor-based
understanding of phase noise in LC oscillators [4] [5]. In addition
to giving a clear understanding of how thermal noise in resistors
and FETs gives rise to phase noise, the method leads to compact
expressions for the final phase noise in terms of circuit variables
that guide design. We have also used these expressions to
successfully predict the phase noise of oscillators in the published
literature whose power consumption is known, or vice versa. All
that is needed is the true quality factor Q of the on-chip tuning
inductor [6]. This can be estimated from the dimensions taken
from the chip micrograph and some key fabrication details [6].
The analysis presented in [4] [5] is circuit-based, invoking
Kirchhoff’s laws for oscillation and feedback. In this paper, we
develop a more phenomenological, or behavioral, analysis that
applies to every oscillator, less dependent on the details of its
circuit topology.
Fig. 3 shows a classic NMOS differential oscillator. This is one
of several variants that we have chosen because it is convenient
to illustrate what we have to say in this paper. The cross-coupled
FETs give a negative conductance when a differential voltage is
applied at their free terminals. They give zero conductance when
a common voltage is applied at the same terminals. Thus, when
an LC resonator is connected across the two terminals as shown
and the magnitude of the negative conductance is greater than a
certain minimum, the poles of the circuit move to the right half
s-plane, and the circuit bursts spontaneously into a differential
oscillation at the parallel resonant frequency ω0 . The voltage
amplitude of the oscillation builds up until it reaches a steady
state V0 limited by the non-linearity of the circuit. This is the
desired steady-state output of the oscillator circuit.
A single FET’s ID -VG characteristic is defined by a squarelaw rectifier function. A large sinewave passing through this
characteristic will be accompanied by all harmonics of ω0 . The
odd harmonics will flow as differential currents in the circuit. But
even harmonics, by symmetry, must flow in common mode. That A. Noise Pulls Oscillation Frequency
is, even harmonics will appear as identical waveforms in both
A free-running oscillator is an autonomous circuit. This means
FETs, and therefore in the symmetric pairs of branches of the that only one independent source of energy connects to it, the DC
entire circuit. Since the inductor offers an increasing reactance power supply. In a periodic steady state, the phasor voltages and
to harmonics, whereas the capacitor offers a decreasing one, the currents inside the circuit must satisfy Kirchhoff’s laws exactly.
second and higher harmonics will prefer to flow through the That is, the magnitudes and phases of node currents and loop
capacitors. The DC bias current flows as the 0th (even) harmonic voltages must balance precisely. Every oscillator will operate
in common mode.
in a nonlinear regime that limits the steady-state amplitude, so
In a perfectly symmetric circuit, even harmonic voltages and Kirchhoff’s laws must be satisfied separately at the fundamental
currents cannot be observed through differential measurements. frequency and the harmonics. This is a useful and precise reBut, as we will explain later, their presence can have important statement of the Barkhausen criterion.
consequences on differential behavior.
A fundamental property of any resonator, whether it is a oneIf the symmetry is upset because of, say, FET mismatch, some port or two-port, is that the phase of its transfer function changes
fraction of the common mode will couple into the differential
1 In power-constrained applications, the specification is on phase noise-per-unit
mode. This cross-coupling has been described in detail for a
supply current. For example, Bluetooth operates most of the time in receive
symmetric regenerative circuit in [3]. The small differential 2nd
mode when to save power, it allows worse LO phase noise compared to the
harmonic can cause a corresponding small shift in ω0 via the
transmit mode.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
+I0
–I0
in
0
L
C R
3
+
v0
–
Fig. 6. Noise (in ) injected into LC oscillator.
Fig. 4. Typical phase-shift vs. frequency for any resonator.
f0
+I0
–I0
+
v0
–
L
C
R
3f0, 5f0, ...
Fig. 5. Loops of current flow in the equivalent circuit of any current-limited LC
oscillator at oscillation frequency f0 and its harmonics.
sharply with frequency at the resonant frequency ω0 (Fig. 4). For
a parallel LCR one port,
dθ
2Q
=−
dω
ω0
(2)
Now consider a simple oscillator circuit (Fig. 5), consisting
of a two-terminal parallel LCR circuit with an active element
in the form of a nonlinear voltage-controlled current source
attached to its two terminals. A “bang-bang” characteristic is a
good working model for the active circuit in practical differential
oscillators. This two-terminal model switches the polarity of a
constant current I0 when the voltage across it crosses zero. In
an NMOS differential oscillator, only half of I0 is switched into
the resonator. The steady state of the circuit is uniquely defined,
in the first approximation, by the fundamental frequency of the
square wave current flowing through R and its 3rd and higher
odd harmonics flowing into C Fig. 5. We select the time origin
so that the voltage across the circuit is
v0 (t) = π2 I0 R cos ω0t where ω0 = √1LC
(3)
or V0 = π2 I0 R in phasor notation
(4)
injection is at a small offset frequency fm from f0 , the circuit
remains highly, although not infinitely, sensitive to it.
Suppose in (t) is a white noise current. Then, using the discrete
approximation to a constant spectral density, consider a pair of
phasors C− and C+ at image offset (positive) frequencies f0 ± fm .
From (1) the two noise phasors can be decomposed into a
pure PM pair at the image frequencies and a pure AM pair. If
the oscillation phasor itself rotates because of an added positive
or negative phase, the AM and PM phasors will rotate with it.
However, each noise phasor is independent of the oscillation.
This means that their decomposition into AM and PM according
to (1) will change over time. However, the mean square value
of AM and PM, which is equal for Vam and Vpm in (1), remains
unchanged or invariant.
Now, let us apply this decomposition to the current noise
source in (t) that disturbs the oscillator, which we assume is in a
steady state at ω0 with phasor voltage V0 . C− and C+ are random
phasor magnitudes, but of equal variance ⟨C2 ⟩ = kT R [V2 ]. Using
(1) they can be decomposed into PM phasors, VPM cos(ω0 ± ωm )t.
These force the phase of the oscillation phasor periodically as
θ (t) =
2VPM
cos ωmt, where Vpm = 12 (C+ +C− )
V0
(6)
When the phase of the oscillating voltage shifts, the restoring
current from the active circuit responds instantaneously. But
to absorb the quadrature phase contained in the independent
current In , the oscillation frequency must shift off-resonance by
an amount, according to (2):
f (t) =
f0
θ (t)
2Q
(7)
The time-varying frequency changes the phase of the oscillation
as
Z t
φ (t) =
f (t) dt
0
ω0
←→ Φ( jωm ) =
Θ( jωm )
(8)
Suppose that an independent current source, in = In sin ω0t is
j2Qω
m
2
now turned on (Fig. 6), indicated by the phasor In = − jε π I0 ,
ε ≪ 1. Since v0 (t) cannot respond instantly due to inertia in Converting both sides to spectral densities, and using (6) and
the reactances, the total current entering the LCR resonator will (7),
be phase shifted by arctan(ε) relative to the voltage across it.
f0 2
f0 2 2 2
Sφ ( f m ) =
Sθ ( fm ) =
SVpm ( fm ) (9a)
This phase difference between the resonator voltage and the
2Q fm
2Q fm
V0
sum of the two currents will, according to (2), initially shift
2 2
f0
2
the frequency from ω0 . The sustaining current generated by the
=
× 14 × 8kT R from VPM in (6) (9b)
2Q fm
V0
nonlinear controlled source will track this frequency, driving the
circuit to its new steady state where all currents balance. Then
kT
f0 2
= 2
(9c)
(V0 /8R) 2Q fm
v0 (t) = 2 (1+ε)I0 R sin ω0t.
(5)
π
So, in a steady state, the large oscillation aligns in phase with
the small injected current. Since ε can be arbitrarily small, the
oscillator is infinitely sensitive to out-of-phase perturbations at
the oscillation frequency. It is reasonable to assume that if the
An interpretation of the last expression that also serves as a
useful mnemonic is
Noise power/Hz available from resonator
f0 2
Sφ ( fm )=
Signal power available from resonator
2Q fm
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This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
4
Complex
Real
M1
M2
0
Fig. 9. Windowed white noise treated as a convolution in the frequency domain.
M3
Fig. 7. Cross-coupled differential pair, and its differential I-V characteristic.
1
0
Fig. 8. Large oscillation voltage sweeps differential pair through its active region
on zero crossings. Differential pair injects noise in time windows τ wide.
(9c) accounts for the noise arising in the resonator’s loss
resistance, modeled as a single parallel R. When the inductor
contains many sources of loss as described in [6], including loss
in the capacitor, a single effective parallel R captures their total
noise contribution. In general, R may be a function of frequency,
but across typical fm ≪ f0 it remains almost constant.
The last term in the product (9b) is 2kT R, half the one-sided
spectral density of the voltage noise in R. This is because, from
(1), the other half of the noise power injected into a parallel
LCR resonator goes into AM noise. When, in the sections that
follow, we add to this the noise injected by the active devices
into the resonator, we will represent the net phase noise by some
appropriate noise factor F > 1 that scales up 2kT R.
As the notation implies, Sφ ( fm ) is a baseband spectrum; that is,
it signifies the fluctuations in phase versus fluctuation frequency
fm , where fm ≪ f0 . We have shown that the oscillator is more
sensitive to slow fluctuations as fm →0. This is consistent with
the presence of fm in the denominator of the expression (9c) for
Sφ . In bandpass applications where this noisy oscillator mixes
with a narrowband information channel centered on a carrier,
it is customary to allocate half of Sφ ( fm ) to the frequencies
above f0 (the upper sideband), and half to the lower sideband.
Single sideband phase noise (SSB-PN) L( fm ) = ½ Sφ ( fm ) is the
universally used specification for oscillators.
Suppose that the switching action between ±½I0 is modeled by
three piecewise segments that capture the essential dependence
of a differential pair’s current on a large differential input voltage
(Fig. 7). Then the effective transconductance in the switching
interval is constant at Gm , and the differential voltage for complete
switching is I0 /Gm . The spectral density of the differential
current noise during the transition is Sind = 4kT γ Gm [A2 Hz−1 ].
γ is unspecified for now2 , but in practice it lies somewhere
between 0.67 for long channel FETs to 2.2 for short channel
FETs operating at high voltages.
There are two ways to model time-windowed noise, leading to
the same result. In the frequency domain, its two-sided spectral
density is found by a convolution between a periodic train of
time windows and Sind . In the time domain, it is straightforward
to calculate the autocorrelation function of the windowed noise,
whose Fourier transform will give the two-sided spectral density.
We will use the latter approach.
The window τ is defined by the oscillator output that drives
the gates of the differential pair (Fig. 8). Since we know the
differential voltage required to switch the current completely
and the rate of change of the oscillator output voltage that is
responsible for switching, it follows that
τ=
I0 /Gm
1
=
because ω0V0 = 2π f0 (2/π)I0 R
ω0V0
4Gm R f0
So as not to ignore an enhancement that has been presented in
the literature [7], if an ideal step-up transformer of ratio 1 : M
is inserted between the oscillator output and the gates of the
differential pair, τ will be lowered by M. However, this will
make little difference to total phase noise unless the dominant
source is first mitigated, as described below.
The autocorrelation of white noise current of constant spectral
density passing through windows τ that are periodic at 2 f0 , and
its Fourier transform, are:
Rind (u) = 2kT γ Gm δ (u) × 2 f0 τ/M
F.T.
←→ S( f ) = 2kT γ Gm × 2 f0 τ/M
B. Noise from Differential Pair
The FET differential pair switched by the large oscillation
commutates a current through the resonator. Since the resonator
is differentially connected across the pair, noise from these FETs
only enters the resonator when both FETs are in their active
region.
To predict phase noise from the differential pair, we model
their net noise current with the source in (t) as in Fig. 6. A burst of
differential noise current appears while the bias current switches
from one FET to the other, but otherwise this noise is zero. Using
a simple model, we can relate the window over which the noise
appears to its spectral density.
(10)
(11)
This is a two-sided spectral density. The one-sided density is
twice as large:
Sind ( f ) = 4kT γ Gm ×2 f0 τ/N = 2kT γ/MR
(12)
Will this current produce PM, AM, or both? Common sense
says that if the differential pair is switching a noiseless current
into the resonator, then the noise in the pair’s FETs will modulate
only the switching instants but not the amplitude of the current.
Strictly speaking, this is true when τ ≪ 1/ f0 , otherwise the
2 [5] gives a more rigorous derivation for S
ind which leads to a similar result.
The treatment here is more intuitively appealing.
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This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
Complex
Real
0
Fig. 10. Commutated white noise treated as a convolution in the frequency
domain.
varying duty cycle of switched current will lower its amplitude
at the fundamental frequency. We can show this formally. The
Fourier spectrum of a periodic train of windows where one
window is centered on t = 0 (Fig. 9) consists of tones at ℓ f0 , ℓ∈Z
with amplitudes sinc(ℓ f0 τ). For small ℓ, the amplitudes are almost
all equal to 1. After convolution with a constant spectral density
N[i], for any fm < f0 ,
C+ = N⌊ f0 − fm ⌉ + N⌊− f0 − fm ⌉ = N⌊ f0 − fm ⌉ + N⌊ f0 + fm ⌉
C− = N⌊ f0 − fm ⌉ + N⌊ f0 + fm ⌉ =⇒ C+ = C−
(13)
It follows from (1) that Vam = 0. We conclude that noise passing
through narrow windows (the assumption of small ℓ) contributes
PM phasors only3 around f0 .
Now that we know all of ind causes phase noise, then
combining (12) with (9c) leads to
f0 2
kT F
Sφ ( f m ) = 2
where F = (1+γ /M) (14)
(V0 /8R) 2Q fm
C. High Frequency Noise from Tail Current
5
current creates only (AM) amplitude fluctuations. As [8] shows, a
voltage-sensitive varactor can convert noisy AM into phase noise.
So when an analog varactor is used, this mechanism converts
low-frequency noise into phase noise around f0 . This important
consideration guides how the varactor should be biased for the
lowest AM-PM conversion. Other voltage-dependent capacitors
can also convert AM into PM and cannot be ignored during
design.
We will use an expression that relates the oscillation amplitude
to the bias current. For least phase noise, the amplitude should
be as high as possible while the oscillator operates in the currentlimited mode [4] and thereby does not load the intrinsic Q of the
resonator. The commutating differential pair creates a differential
current of (2/π)I0 that flows through R, the parallel resistance
of the resonator. The voltage on one side of the oscillator can
swing down from its bias at VDD to close to zero, limited by the
compliance voltage of the current source FET in the tail. The
other side will swing up close to 2VDD . This, then, is the largest
differential voltage amplitude. Thus, πVDD = RI0 (max).
After commutation, the phase noise-producing current entering
the resonator is, from (15),
4kT γ 4 2 4πVDD
4 2
(16a)
Sin = 4kT γgds0 3π
×2 =
3π
R
(VGb −Vt0 )
2kT
γVDD
≈
× 4.6
(16b)
R
(VGb −Vt0 )
where Vgb is the gate voltage on the tail FET that is biased at I0 ,
gds0 is the noise-setting conductance of that FET if it were in
deep triode, and we assume that the I0 is adjusted to reach the
highest amplitude.
Now we can write an expression for the noise factor of the
oscillator that includes all sources of thermal noise.
Current noise in the tail current FET is first commutated by
γ
4.6γVDD
F = 1+ +
(17)
the differential pair and then injected into the resonator.
M (VGb −Vt0 )
Once again, it is convenient to analyze this process first in
A cursory examination of (17) shows that the third term is the
the time domain. We assume that the switching differential
largest
by far. For example, if VDD = 1 V, γ = 1 and (VGb −Vt0 ) =
pair is noiseless, so the waveform of the white-noise current is
0.2
V,
the
third term is 23. This salient fact was pointed out in
periodically inverted in polarity. Its autocorrelation function is
[9],
which
went on to show a filtering method that strips off
unchanged, and therefore so is its spectral density, which remains
noise
at
2
f
constant.
0 to drive the largest (third) term in (17) to nearly
zero,
thereby
reaching the lowest possible phase noise for a
In the frequency domain (Fig. 10), noise with a constant
differential
oscillator
with a certain unloaded resonator Q.
spectral density modeled as tones 1 Hz apart, is convolved with
Since
that
publication,
many circuit variations on the basic
the Fourier spectrum of the commutating square wave. If the
oscillator
have
been
published,
including, for instance, ones that
oscillator output is cos ω0t, then it will create a commutating
4
1
lower
the
second
term
with
transformers.
[10] has surveyed 15
waveform whose Fourier series is ( π )(cos ω0t − 3 cos 3ω0t + · · · ).
years
of
these
publications
and
it
reports
that
none has exceeded
After commutation, this will be convolved with the phasors
the
phase
noise
figure-of-merit
of
[9];
the
best
have equaled it.
N[0], N[2+], N[2−], . . . and their conjugates that model the spec(17),
an
outcome
of
the
phasor-based
analysis,
makes
it eminently
tral density of noise, respectively, at DC, 2 f0 + fm , 2 f0 − fm , . . . and
clear
why
these
circuit
variations
did
not,
in
the
end,
deliver
their counterpart negative frequencies. Then after convolution,
noteworthy improvements to phase noise. With a few exceptions,
Freq. Phasor at that freq. From (1), AM and PM
they did not tackle its dominant source.
f0 + fm
f0 − fm
2
1
π (N[0]+N[2+]− 3 N[2−])
2
1
π (N[0]+N[2−]− 3 N[2+])
1
2
AM: π (2N[0]+ 3 (N[2+]+N[2−]))
4
PM: 3π (N[2+]−N[2−])
(15)
Thus we see that noise frequencies in the vicinity of 2 f0 create
only (PM) phase noise at f0 . Low-frequency noise in the tail
3Windowing or commutation preserves the constant spectral density of white
noise, but introduces correlation at every frequency. This is easily overlooked,
although its consequences, as here, may be profound.
IV. C OMPLEMENTARY D IFFERENTIAL O SCILLATOR
This variation of the differential LC oscillator is often used
and must be included in this discussion. It is called the
CMOS oscillator because it substitutes in the oscillator we have
considered so far cross-coupled CMOS inverters for the crosscoupled NFET or PFET differential pair (Fig. 11(a)). The inductor
L can now be placed, in principle, between the inverters to define
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content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
(a)
(a)
(b)
Fig. 11. (a) The CMOS fully differential LC oscillator. (b) Equivalent circuit of
the resonator over time intervals away from the CMOS inverter’s transition.
their DC bias. It is tuned by a capacitance that, in practice, must
always be a pi network consisting of FET capacitors connecting
each terminal of L to the substrate and a floating capacitor that
serves as an analog or digital varactor4 .
With commutating switches on either side of the tuning
inductor, the entire bias current I0 now enters the resonator. This
improves the power efficiency of the oscillator by 2×. When
power is at a premium, this circuit is preferred over the NMOS
differential oscillator.
But its phase noise performance cannot be better than in the
NMOS oscillator for two reasons. The maximum amplitude of
the oscillation is half that of the NMOS. This oscillator reduces
the Q of the resonator by loading it with the resistance of the
FET switch.
Whereas the inductor in an NMOS oscillator is biased at
VDD and can swing unimpeded above the power supply, in the
CMOS oscillator there is an FET between the inductor and the
supply, which limits the voltage at either inductor terminal to the
supply. Balanced CMOS inverters give the optimal bias point at
½VDD and as one terminal of the inductor swings to the lowest
voltage close to 0 the other rises to the highest, VDD . This limits
the differential oscillation amplitude to VDD , half of the NMOS
oscillator.
This brings us to the question of loaded Q of a resonator.
An inductor’s own Q is limited by four independent sources of
loss that are somewhat complicated to model with an equivalent
circuit, as [6] shows. However, no matter how well optimized the
geometry of an on-chip inductor may be, when it is embedded
in an oscillator circuit, the Q can still be reduced by the circuit
elements that surround the inductor. Let us see how this happens
in the CMOS oscillator.
The differential oscillation voltage toggles both inverters when
it crosses zero. This happens when the voltage at each output
node is equal to VDD −VGS (½I0 ) and all the resonator energy is
in the inductor. The differential capacitor C1 contains zero energy
and the grounded capacitors C2 do not contain resonator energy,
although, with a non-zero voltage, they may contain energy
taken from the supply. The PFET’s strength will determine what
happens next.
If the PFET is of moderate strength, as is typical, then it
will have some average resistance RPFET from one end of the
inductor to the supply (Fig. 11(a)). Every half cycle, the two
4 This is a consequence of the isotropic nature of electric fields. The lumped
capacitance equivalent of the fields between two electrodes above ground must
define a three-element pi network.
6
(b)
Fig. 12. (a) Approximate equivalent circuit of an on-chip inductor in a resonator,
taken from [6, Fig. 13(c)]. (b) Narrowband equivalent at frequencies where Rsub
determines substrate currents.
PFETs exchange roles. Fig. 11(b) shows an equivalent circuit.
Over a narrowband around resonance, this transforms into a
second-order LCR circuit. The PFET resistance lowers the overall
resonator Q
p
L(C1 +C2 )
1
1
1
QPFET =
=⇒
=
+
(18)
C2 RPFET
Q QPFET QL
where QL is the true quality factor of the inductor alone [6].
This final Q is the loaded quality factor of the resonator. This
explains why, in practice, the phase noise of a CMOS oscillator
is never better than that of an NMOS oscillator. If, for example,
QPFET ≈ QL , the loaded Q would be halved. The situation is
rarely so dire in a well-designed circuit. We assume that the
tail current source presents a very high resistance throughout
the oscillation, which prevents the NFET that is pushed into
triode by the differential voltage exceeding Vt0N from loading
the resonator. However, a nonzero C2 will indirectly enable some
resonator loading by the PFET in the triode region. The resonant
frequency of this complementary oscillator is
p
ω0 = 1/ L(C1 +C2 /2).
(19)
This is true for RPFET > 1/(ω0C2 ).
In other words, the CMOS oscillator reaches its full amplitude
with half the bias current that the NMOS oscillator demands.
If inductors are allowed to be scaled, the CMOS and NMOS
oscillators can offer the same phase noise at the same current.
This is discussed in great detail in Sec. V-A2.
V. S CALING O SCILLATOR FOR P HASE N OISE
What factors are within the circuit designer’s control that
enable him or her to take a given oscillator circuit and alter
it to reach a specified phase noise at a given ω0 ? Fig. 12,
which replicates [6, Fig. 13(c)], gives the equivalent circuit of
an inductor configured as a resonator. This absorbs the selfcapacitance of the inductor into the resonator and includes the
substrate capacitance and resistance. At ω0 , this is equivalent to
L in series with RS forming a loop with Ceff = Ca +Cc in series
with Reff = R(Ca /(Ca + Cc )) (provided Rsub ≪ 1/ω0 (Ca ∥ Cc ),
where x ∥ y ≜ (xy)/(x + y)). The two resistors in series are now
denoted as RL .
The resistor R that appears in the expression for phase noise
(14) was placed in parallel with L to model all the dissipation
(Fig. 6). In a narrow band around ω0 , it is related to RL in Fig. 12
as R = Q2 RL . Thus, (14) may be modified as follows:
kT F
f0 2
1
L ( f m ) = 2 Sφ ( f m ) = 2
V0 /4R 2Q fm
2
RL
f0
=⇒ L( fm ) = 2 × kT F
(20)
fm
V0
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7
number, while the total bias current increases. The oscillator
figure-of-merit remains constant.
+I0
+I0
+I0
–I0
–I0
–I0
A. NMOS vs. CMOS: Which Oscillator is Better?
Before starting the development of the circuit, its designer
is confronted with a choice of two oscillator topologies. Since
(a)
(b)
(c)
the oscillator is almost always a differential circuit, the key
decision is the following. NMOS/PMOS or CMOS? Many times,
Fig. 13. (a) An inductor with half a turn realized by (b) two one-turn inductors
in parallel. (c) A symmetrical realization partitions the active circuit equally this decision will be influenced by prior familiarity or hearsay.
between the two inductors in parallel.
We want to provide a systematic and quantitative method for
evaluating the relative merits of the two.
This design decision is based on a complex of considerations.
Assuming
that the requirement on tuning range is met, should
So, there are only two variables under the designer’s control.
the
oscillator
deliver the lowest phase noise irrespective (within
First, the bias current, which should be large enough to bring
reason)
of
power
consumption? Should it deliver the lowest phase
the amplitude of oscillation on each output close to the supply
noise
per
unit
of
power dissipation? Should its resonant inductor
VDD , and the supply voltage should be as large as the IC process
occupy
the
smallest
chip area?
allows for reliable operation. Second, the effective resistance in
A
well-designed
oscillator
should operate at the largest possible
series with the inductor should be as small as possible. This is a
useful expression for phase noise that we will turn to repeatedly amplitude because this quadratically lowers its phase noise
because it resolves many circuit parameters into the inductor (see (20)). So, an NMOS oscillator should be designed for a
series resistance RL and the oscillation amplitude. Q is implicit differential sinewave of peak voltage 2VDD , whereas the CMOS
in the relation between RL and V0 but there is no need to invoke oscillator will operate at a peak of VDD . We will now use the
it since we know that the desired amplitude is equal to the supply analysis to compare the two circuits in terms of their key aspects
of performance.
VDD . [11] has also noted the usefulness of this formulation.
Suppose that the CMOS oscillator employs a net differential
The smaller the number of turns in the inductor, the lower its
inductance
of LD that resonates at ω0 with a net differential
series resistance. But, as [6] shows, the resistance of a single
capacitance
CD . An effective resistance RLD , in series with LD ,
turn depends in many ways on the width of the metal trace, its
models
loss
in the inductor; we assume the capacitor’s loss is
thickness, the inner diameter of the turn and to some extent on
negligible
by
comparison. The oscillator is biased at current ID .
the doping of the substrate, as well as on ω0 . If the geometric
1)
Supply
Current:
If the resonator is transformed in a narrow
quantities are chosen to minimize RL and the oscillation frequency
band
around
ω
into
a
parallel
LCR circuit, then during oscillation,
0
is set by capacitors with a higher intrinsic Q, the oscillator will
the
commutated
bias
current
flows through the parallel resistor
deliver the lowest possible phase noise in a particular CMOS
and
defines
the
amplitude.
The
parallel equivalent resistance is
technology. Of course, with this small RL the bias current must be
L
/(C
R
)
over
a
narrow
frequency
band. After commutation
D
D
LD
large to reach the maximum amplitude, but this only emphasizes
by
the
CMOS
oscillator,
the
amplitude
of the current at ω0
the fundamental trade-off between low noise and high power.
flowing through this resistance is (4/π)ID . So at maximum
What if the oscillator phase noise is still too high? An inductor
amplitude,
must have at least one turn to define an enclosed flux, so it is
LD
futile to think in terms of defining an inductor with a fraction
CMOS: V0 = π4 ID
(21)
C
D RLD
of a turn of metal wiring. However, we can exploit the notion
π VDD RLD
that two inductors in parallel will halve the total inductance. So,
=⇒ ID =
.
(22)
4 (LD /CD )
two one-turn inductors in parallel will give the inductance of a
Compare this with an NMOS oscillator tuned to the same
hypothetical half-turn. Furthermore, if a smaller inductance is
desired, they can be coupled such that their fluxes negate, but at frequency with LN , CN , and equivalent series loss resistance RLN .
the cost of lower Q. Fig. 13(a) and (b) show how two inductors in This circuit commutates half its bias IN into a differential current.
parallel would make an oscillator. By splitting the active circuit Therefore, the amplitude and the bias current to reach maximum
into two halves, each scaled to maintain the amplitude which is amplitude are, respectively,
set by the effective parallel resistance (L/C)/RL that depends
LN
NMOS: V0 = π2 IN
(23)
on the inductance, a symmetric circuit is obtained comprising
CN RLN
two identical oscillators in parallel (Fig. 13(c)). This is helpful
π 2VDD RLN
.
(24)
=⇒ IN =
when a very symmetrical IC layout is sought. But what matters
2 (LN /CN )
for phase noise according to (20) is series resistance, which is
2) Phase Noise and FOM: We apply the expression (20) to
not affected by magnetic coupling.
the phase noise in the CMOS oscillator, and to its figure of merit
It is possible to think of this arrangement as two identical (FOM) which is a measure of phase noise per unit supply current:
oscillators that synchronize to a single waveform due to the FOM ≜ L( fm )( fm / f0 )2VDD I0 , the lower the better.
strong coupling [12]. But it is not clear whether it is useful to do
2
RLD
f0
so. The idea of parallel inductors may be extended, in principle,
CMOS:
L( fm ) = 2 kT F
(25)
fm
VDD
to 3, 4, or any number of single-turn inductors, connected in
parallel at their terminals and driven by identical unit active
RLD
R2LD
=⇒ FOM(D) = 2 kT F ×VDD ID = kT F π4
(26)
circuits. The phase noise should decrease proportionally to this
(LD /CD )
VDD
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content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
The corresponding quantities for the NMOS oscillator are
2
RLN
f0
NMOS:
L( fm ) = 2 kT F
(27)
fm
4VDD
R2LN
RLN
kT F ×VDD IN = kT F π4
=⇒ FOM(N) =
(28)
2
(LN /CN )
4VDD
8
the cost of the second on-chip inductor with its associated large
chip area to realize a lossless lowpass filter may have been a
disincentive.
[10] contributed a solution with an elegant use of the
resonator’s inductor to also act as this noise filter. A single
inductor serves two functions. We will now explain its principle.
Before doing so, we must discuss a frequently overlooked
The two oscillators might commutate different currents but the
topic:
the flow of harmonic currents in the differential oscillator
magnitude of F is the same for both because as Fig. 1(b) reminds
(or
in
any
bilateral symmetric nonlinear circuit). One can design a
us, what matters for phase noise is the relative size of noise to
satisfactory
oscillator by treating the LC resonator as high enough
the oscillation amplitude. The amplitude may be smaller in the
Q
so
that
the
capacitor absorbs harmonic currents necessarily
CMOS oscillator, but the noise in the resonator produced by
generated
by
the non-linear active device (Fig. 5), with no
the FETs also scales down proportionally. We neglect the slight
observable
consequence
on the purity of oscillator waveform
worsening of F in the CMOS oscillator caused by the PFET’s
which
resembles
an
almost
pure sinewave.
switch resistance (Fig. 11(b)).
However,
a
differential
circuit
operates in two modes which are
Let us use these expressions to compare the two oscillaindependent
in
that
they
can
carry
completely different waveforms.
tor topologies. Suppose both use the identical resonator, i.e.
These
are
the
differential
and
the
common modes, also known,
LD =LN =⇒ RD =RN and CD =CN . Then (27) tells us that the
perhaps
more
usefully
for
the
discussion
at hand, as the odd and
NMOS phase noise is 4× lower owing to twice the oscillation
even
modes.
Bartlett’s
bisection
theorem
developed for linear
amplitude when compared to CMOS (25). But (24) shows that
circuits
with
bilateral
symmetry
tells
us
that
when driven by
the NMOS oscillator also uses 4× the bias current of CMOS
identical
inputs,
the
branches
at
the
line
of
symmetry
carry no
(22).
current
but
support
some
voltage.
Whereas
driven
by
equal
and
This is why the figure of merit is the appropriate comparison
opposite
inputs,
those
branches
are
at
zero
voltage
but
carry
a
nonbecause it normalizes phase noise to the bias current. We see
from (26) and (28) that, when tuned with identical resonators, zero current. This can be generalized to nonlinear circuits with
bilateral symmetry. Specifically, when driven by large equal and
the FOM is equal for both.
How does FOM compared to the CMOS oscillator change if opposite inputs (odd functions, in the sense that their waveforms
in the NMOS oscillator we scale the resonator elements, that trace out equal and opposite values in time), the branches at the
is, the resonator impedance while maintaining its ω0 ? Thus, line of symmetry can respond with an even function waveform,
in the sense that the response is the same if the two inputs
suppose LN = κL
pD =⇒ CN = CD /κ which scales the resonator
impedance to κ LD /CD Ω. Since the equivalent series resistance are interchanged. In a bilateral symmetric nonlinear circuit, the
that captures the various sources of loss in an on-chip spiral does odd waveforms still exist in differential mode, whereas even
not scale simply with inductance [6], we introduce a coefficient waveforms exist in common mode.
A sinusoidal oscillation voltage appears differentially across
ν to account for it so RLN = νκRLD . After scaling, the new
the
resonator. It is an odd-mode waveform. The 3rd, 5th and all
expressions are now:
odd harmonics are also odd waveforms that can exist only in
VDD RLD 4ν
Scaled NMOS:
IN = π4
(29) differential mode. The 2nd, 4th, and even harmonics, including
(LD /CD ) κ
DC levels, comprise even waveforms; they will be identical at
2
f0
νκ RLD
both nodes of the resonator relative to ground. They exist only in
kT F
=⇒
L( f m ) =
(30)
2
common mode. A differentially connected resonator is unaware
4 VDD
fm
2
that they are present. Even harmonics are created by the FETs
RLD
=⇒ FOM(Nκ ) = ν 2 π4
kT F
(31) and their configuration in the circuit. Consider the large signal
(LD /CD )
relationship between a differential input to a differential pair of
The Q of well-designed on-chip spiral inductors developed FETs in saturation and the voltage at the common sources that lie
with electromagnetic simulators to operate at a certain frequency on the line of symmetry. This relation is parabola-like, consistent
tends not to change much over a fair range of inductance. This with the extension of Bartlett’s bisection theorem for nonlinear
suggests that, as a starting point for design, we may assume that circuits. Thus, a large sinewave differential input voltage will
ν ≈ 1. Then, after comparing (31) with (28), it appears that the produce a voltage waveform with even harmonics only on the
FOM of the NMOS oscillator remains constant independently line of symmetry. This is not due to the square-law characteristic
of the scaling of its resonator. This allows us to say, without of FETs, because a BJT differential pair would show a scaled
further calculation, that for the same supply current the NMOS version of the same parabolic characteristic. Rather, it has to
and CMOS oscillators, despite their maximum amplitudes that do with the behavior of any transistor pair configured in this
differ by 2×, still give the same phase noise.
particular topology.
This gives a design freedom that is illustrated in Sec. VIII.
Fig. 14 shows the common-mode paths that even harmonics
will take through a perfectly symmetric circuit. The FETs are
VI. O NE I NDUCTOR T UNES F REQUENCY, F ILTERS N OISE IN shown as ideal switches that will commutate the currents flowing
B IAS C URRENT, AND S UPPRESSES F LICKER N OISE
in the common-mode loops. So the chain of cause and effect is
Although [9] showed that stripping the noise in the tail as follows: the small-signal negative conductance of the crosscurrents at frequencies around 2 f0 is the single most important coupled FETs starts up a differential oscillation; the amplitude of
intervention to lower phase noise in the differential LC oscillator, the oscillation grows until limited by nonlinearity or exhaustion
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
9
k
(a)
(a)
(b)
(c)
Fig. 15. (a) Two identical LC resonators that are magnetically coupled. (b)
Bisected T-equivalent circuit for common mode, when V1 = V2 , both phasors
measured relative to dots that indicate coupling. (c) Bisected circuit for differential
mode, when V1 = −V2 .
k
L
(b)
Fig. 14. Second harmonic currents imposed by FET and circuit nonlinearity
must flow in common mode in a symmetric circuit. (a) Tail-biased oscillator. (b)
Top-biased oscillator re-drawn to resemble tail-bias. (Only autonomous circuits
can be redrawn in the absence of independent sources or FET substrate that are
connected to system ground.)
(a)
(b)
(c)
Fig. 16. (a) Top-biased differential LC oscillator. (b) Equivalent circuit that
represents coupled inductors as three uncoupled inductors, and C3 to filter noise in
current source. Fundamental and 2nd harmonic waveforms shown. (c) Equivalent
circuit showing flow of 2 f0 current when FET load is in parallel resonance at
that frequency.
of the bias current; the differential pair when subject to the
large oscillation generates harmonics, whereby voltages at even
harmonics dropping across finite impedances cause currents to
flow in common mode. The FETs that operate as switches
a circuit with bilateral symmetry, common-mode and differentialwill commutate these currents flowing in circuit loops. The
mode currents flow in different subcircuits. This means that
commutation of the current at 2 f0 will produce components at
the resonator in a typical differential oscillator may display
the fundamental frequency ( f0 ). This product of commutation
two different resonant frequencies for currents flowing in the
must flow in a differential path through the resonator. Whether
two modes. Fig. 15 recapitulates the two modes in a pair of
it produces AM or PM depends on the relative phases.
coupled bilaterally symmetric resonators. If an oscillation exists in
In a real-life oscillator circuit, even one without varactors,
common mode and its amplitude is balanced on either side of the
another mechanism is present that converts AM into PM. Briefly,
line of symmetry, that is, phasors V1 =V2 , then coupled resonators
the 2nd harmonic (2 f0 ) voltage across linear capacitors can
can be bisected into two identical resonators Fig. 15(b) with
convert, after commutation of the quadrature capacitive current,
effective inductance L0 (1+k), capacitance C0 , and resistance R0 .
into a quadrature current at f0 . This must flow differentially
Whereas if an oscillation is in differential mode and its amplitude
into the resonator because it is at the fundamental frequency
is balanced, that is, phasors V1 = −V2 , then the bisected circuit
and it adds to the main fundamental current. Noise sources will
Fig. 15(c) contains an effective inductance L0 (1−k), capacitance
modulate the oscillation amplitude with a different index than
C0 and
p resistance R0 . The resonant frequency changes by the
they modulate the amplitude of the voltage component at 2 f0 ,
ratio (1+k)/(1−k). As k→1, this ratio grows arbitrarily large.
so, after commutation, AM becomes PM. One such noise source
Applying this to the NMOS differential oscillator Fig. 3, the two
is flicker noise, which can produce fluctuations in I0 and thus
resonant frequencies are
V0 , while it affects the 2nd harmonic differently; that is, not
√
proportionally. Through this means, flicker noise converts into
Comm. Mode
ω0C = 1/ (L(1 + k)(2C1 +C2 ))
(32)
√
phase noise.
Diff. Mode
ω0D = 1/ (L(1 − k)C2 )
(33)
If the external load in series with the FETs was infinite at
2 f0 , it would block the flow of second harmonic currents in Obviously ω0D < ω0C , which raises the possibility that by
common-mode loops. There would be no AM-PM conversion, introducing additional tunable capacitors ω0C could be adjusted to
as just described. This phenomenon was observed early in exactly 2ω0D . Thus, in differential mode, the resonator determines
the development of differential oscillators, although it took a the oscillation frequency at its parallel resonance; whereas in
long time to identify the physical mechanism. [9] mentions common mode, the same resonator presents a very large load to
this towards the end, then [13] shows the suppression of the FETs at the second harmonic arising from the oscillation,
flicker noise in measurements and a method to track a second- thereby blocking the flow of current at that frequency. However,
harmonic blocking circuit as the oscillator is tuned. [14] explains the expressions are incomplete because they neglect the coupling
qualitatively the mechanism mentioned above and shows partial between the two half-inductors on either side of the center tap
suppression of flicker noise, which appears only over a certain [15, Fig. 2(b)]. The coupling coefficient k gives another degree
band of frequency offsets. [10] shows a clear suppression of of freedom.
flicker noise upconversion over a large band of offset frequencies.
Fig. 16 shows the equivalent circuit of a center-tapped solenoid
It is also well known from Bartlett’s bisection theorem that in of total self-inductance 2L, whose two half-inductors are magnetiThis work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
cally coupled. Its equivalent T network in Fig. 16(b) contains three
fictitious inductors, all uncoupled, where the central element −kL
is negative. The coupled inductor tunes a top-biased oscillator
[16], whose amplitude-setting current source I0 is inserted into the
center tap of the inductor. As Fig. 14(b) shows, by re-assigning the
ground terminal (ignoring the FET substrate which is connected
to “hard” ground) this is equivalent to the familiar tail-biased
oscillator; the FETs commutate the (common-mode) DC I0 and
inject it differentially into the resonator to sustain oscillation at
ω0D .
Fig. 16(b) shows a large capacitor C3 across the PFET current
source. It is there to shunt the noise current at 2 f0 (and other
even harmonics) from entering the oscillator core, where, after
commutation by the FETs, it would create phase noise. For now,
we will assume that the FETs are voltage-controlled current
sources. Then, by inspection
√
ω0D = 1/ (L(1+k)(C2 + 2C1 ))
(34)
√
1
ω0C = 1/ L(1−k)(C2 ∥ 2 C3 )
√
≈ 1/ (L(1−k)C2 ) when C3 ≫ C2 .
(35)
The Q of both resonances is limited by the effective series
resistance of L.
This configuration acts as a second-order lowpass filter for the
noise current to the oscillator output nodes. Specifically, at ω0C ,
much of the noise current is shunted into C2 . The remaining
current creates a common-mode voltage across the two oscillator
output nodes that drives the FETs equally. However, the FETs
are loaded at their drains with a parallel LC circuit resonant at
2 f0 , which presents a high impedance Fig. 16(c). This attenuates
the second harmonic noise current flowing through the FETs, and
after commutation, it results in an equally small differential phase
noise current at the oscillation frequency ω0D . Thus, the third
term in the oscillator noise factor (17) which would dominate
the other two, is suppressed.
Since a small current flows through the switching FETs at
the 2nd harmonic, the upconversion of flicker noise is also
suppressed [10]. However, baseband flicker noise on the bias
current continues to produce AM noise, and voltage-dependent
capacitances can still convert it into phase noise. The only way
to avoid this is to eliminate the tail current source FET, as in
[10].
For both these reasons, by design
10
Fig. 17. Center-tapped differential inductor, with two additional taps that divide
it into four equal uncoupled inductors. An active circuit is shown that induces
the differential mode of oscillation, where VL = VR = −VC .
[10] realizes C1 and C2 with digitally controlled capacitor banks
that follow these constraints.
We conclude that this oscillator topology is the most compact
in chip area and gives the best phase noise of other topologies.
There should be a good reason not to use it. Scaling up the chip
area and power dissipation can improve phase noise even more,
as described in Sec.,V. Ultimately, the most powerful means is
to use resonators with higher Q. To that end, oscillator designers
will welcome any improvements technology can offer to realize
better inductors, including the attachment of off-chip inductors.
VII. W IDER T UNING R ANGE BY R ECONFIGURING I NDUCTOR
The discussion above on the separate differential and commonmode properties of a center-tapped inductor suggests another
possible use: that of widening the oscillator tuning range. As
noted above, the capacitor arrays tune f0 . The arrays can be made
of reasonably large spread until they compromise the resonator Q.
But when an even larger tuning range is sought, the inductance of
the resonator can be switched from one value to another simply
by changing the mode of oscillation from differential to common
[17].
We refer again to Fig. 15, where C represents a switch-selected
capacitor array. In one oscillation mode, C will give a continuous
frequency tuning curve with discrete steps. Switching to the
second mode will give another tuning curve as C is swept. When
the two curves overlap, the frequencies can be tuned without a
ω0C = 2 × ω0D
(36a) gap in a ratio as large as p(1+k)/(1−k) ×C (max)/C (min).
0
0
L(1+k)(C2 + 2C1 )
2C1
3 − 5k
How can this be realized? We view the center-tapped differ=⇒
= 4 so
=
(36b)
L(1−k)C2
C2
1+k
ential inductor as two coupled half-inductors with a common
In this way, a single inductor tunes the oscillator, filters phase lead. This three-terminal element is connected to one of two
noise due to the bias current, and blocks 2nd harmonic currents active circuits, each designed to maintain oscillation in one of
the two modes. From this perspective, consider the familiar
from flowing in the commutating FETs.
(36b) requires that for the capacitors to be positive and differential NMOS LC oscillator circuit Fig. 3. Oscillation in
therefore realizable, k < 35 = 0.6. This leads to a reasonable range the common (even) mode relative to the dots in the coupled
of k which places constraints on the planar inductor geometry. inductors means that the phasors V1 =V2 . The differential pair
As [10, Fig. 13] shows, it may take a determined effort not to circuit produces a sustaining current that is an odd function of
V1 − (−V2 ). This current would be zero for the differential (odd)
let k exceed this limit.
These properties must remain intact across the oscillator’s mode, where V1 + V2 = 0, that is, this active circuit can only
tuning range. L and therefore k are fixed, so capacitances tune sustain the common mode. From symmetry and linearity, the
the oscillator. The analysis above concluding in (36b) tells us inductor’s center tap in this mode remains at a constant voltage.
that as the frequency of oscillation ω0D is tuned by changing
Fig. 17 shows the same inductor connected to another active
2C1 +C2 as given by (34), while keeping the ratio C1 /C2 constant. circuit designed to maintain oscillation in the differential mode.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
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11
At the same time, the circuit must suppress any common-mode B. Amplitudes Can Be Equal in Both Modes
oscillation. The FETs in the active circuit respond to their gate
It is reassuring to learn that, in theory, normalized phase
voltages relative to their grounded substrate terminals. Therefore, noise does not degrade but improves for oscillation in the
to understand its operation, we label the important voltages at seldom-deployed differential mode. However, in practice, as
the three terminals of the differential inductor to ground VL , the frequencies approach 10 GHz, the normalized phase noise
VR , and VC . Balanced oscillation in differential mode requires is seen to worsen. The cost in the figure of merit of switching
phasors VL = VR = −VC . The cross-coupled FET pairs will switch between modes is estimated by comparing the equivalent parallel
the tail current with the correct polarity to maintain this mode. resistances RPC and RPD that determine V0 in each mode.
By symmetry, the switched tail current will divide into equal
L(1+k) 2
amplitudes that flow into each half of the inductor.
RPC =
(37)
C1 + 2C2 RL
In the common mode, balanced oscillation requires that phasors
1
L(1−k) 2
VL = −VR and VC = 0. At any instant, the largest of these three
(38)
RPD = 2 1
RL
sinusoidal voltages will steer all the tail current. Except for the
2 C1
instants of time when all three oscillation voltages are equal, C gives a degree of freedom to balance operation between the
2
this current will flow entirely in the central branch. Since no two modes [18]. If C /C = (1−k)/k, then R = R ; now I
PD
1
2
0
PC
differential current can now flow into the resonators, the circuit produces the same amplitude in both modes. Since normalized
will not oscillate in common mode.
phase noise is smaller in differential mode, I0 could be reduced
To form a multi-mode oscillator, a single symmetrical to maintain uniform performance between both modes.
inductor—which dominates the chip area—is coupled to two
The coupling coefficient k can be designed to suppress noise
active circuits, which occupy a very small area. Fig. 3 and Fig. 17 in 2 f0 currents or to maintain uniform performance; but it cannot
show the active circuits. The bias current to either one of the two do both simultaneously. But, as we have shown, suppression of
active circuits is turned on. The FET capacitance of the inactive 2 f0 is essential to obtain the highest figure of merit. The next
circuit remains attached to the inductor. FET switches connect section presents methods that do this with additional inductors
three taps that divide the inductance of the spiral equally to the at the cost of chip area. Of course, these methods must track
supply VDD . Their switch resistance is not part of the differential changes in f0 : this may become cumbersome when the tuning
current flow path and therefore does not degrade the resonator range is very wide.
Q.
VIII. P RACTICAL C ONSIDERATIONS FOR AN O N -C HIP LC
O SCILLATOR
A. Phase Noise in Multi-mode Oscillation
The preceding phase noise theory might be relatively involved,
We have derived an expression for the phase noise of this but one can develop from it a set of simple design steps suitable
oscillator in common mode (20). It is now straightforward to for practice. Two assertions are helpful in this endeavor. First, as
extend the analysis to oscillation in the differential mode. In this theory shows, a differential oscillator with tail tuning or commonmode, the oscillator disassembles into two identical oscillators mode resonance is a near-optimum topology and should be the
that are effectively in parallel. We have seen this before in Fig. 13 default choice in most cases. Other topologies introduce only
when we chose to interpret the oscillator pair as a single oscillator complexity, with no significant improvement in FOM. Second,
tuned by a resonant circuit comprising half the inductance and oscillator design is typically driven by a specification on phase
twice the capacitance, sustained by the full bias current. Let us noise, e.g., spot noise in the case of Bluetooth or cellular
follow this path.
applications, or integrated jitter in WiFi standards. Specifications
The two half-oscillators can be merged into one in Fig. 17 by on the tuning range and others are typically less impactful.
folding half of the circuit around the center line of symmetry to
the other half. Now this looks like the conventional differential A. Figure of Merit
oscillator but it isn’t: it is the bisected half-circuit of the oscillator
Given these assertions, we start design with the FOM, that
in differential mode. We assume that if it is designed to oscillate
is, normalized phase noise per unit power, to establish a link
at a frequency approaching the upper limit of what the technology
between the bias current and phase noise:
allows, the inductor will resonate with the FET capacitances. To
2
f0
maintain the same current density as in a single differential pair,
fm
the FETs in the two merged pairs are each sized half as wide.
I0 [mA] ×VDD [V] =
(39)
L( fm ) × FOM
Thus, the capacitance to ground is 12 C1 . When oscillating in the
common mode, each half of the coupled differential inductor A literature review of FOM shows that the best executed nearappears as an uncoupled inductor LD = L(1−k).
optimum designs [9], [10], [19] do not exceed a FOM of 195 dB,
Of course, the series resistance RL is not influenced by so, after allocating some margin for process and temperature
magnetic coupling, so it remains unchanged. The two halves variations, a reasonable target for FOM is 192 dB. At maximum
around the center tap of the inductor appear in series when amplitude and after currents in common mode are blocked for low
oscillating in common mode, but they are in parallel in differential phase noise, the efficiency (η) of an oscillator will be > 80% [10].
mode. Thus, if the amplitude is the same in both cases, it follows This efficiency compares the power dissipated by the oscillation
immediately from (20) that normalized to ( f0 / fm )2 the phase in the lossy resonator with the DC power consumed by the entire
noise will be in the ratio of series resistances so, in differential oscillator circuit. These macroscopic considerations lead to a
mode, will be 4× smaller.
first-cut estimate of resonator inductance.
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
12
gain should be chosen based on desirable PLL dynamics rather
than only to cover the discrete steps from the switched capacitor
array; the steps should, in any case, be small enough so that the
chosen varactor can easily cover them. Regardless of frequency,
the varactor is always biased near the point that minimizes the
conversion of AM noise to PM [8].
4L
L
E. FET size
Fig. 18. Assuming maximum achievable swing, CMOS and NMOS oscillators
with tail tuning have identical FOM. Inductance must be scaled 4× for the same
phase noise. NMOS oscillator uses thick-oxide FETs for reliable operation with
large amplitude.
The differential pair should be large enough to hard-switch the
bias current [10]. An undersized differential pair can reduce
efficiency and compromise the tuning of the 2 f0 blocking
resonator, leading to a degradation of the FOM. A good rule of
thumb is to size the FETs so that the loop gain, Gm ω0 LQ > 10.
F. Suppressing Second Harmonic Current
B. NMOS or CMOS Oscillator
The NMOS or CMOS oscillator is equally feasible (Fig. 18)
because, as discussed in Sec. V-A, they operate at nearly the same
FOM. Suppose that the CMOS circuit oscillates at its maximum
amplitude VDD . Then,
2
VDD
where RP = ω0 LQ
RP
VDD
=⇒ L(CMOS) =
2ηI0 ω0 Q
or L(NMOS) = 4L(CMOS)
ηVDD I0 = 12
(40)
(41)
(42)
The last expression uses the condition given in Sec. V-A for the
NMOS and CMOS oscillators to become equivalent, that is, they
produce the same phase noise with the same bias current.
C. Inductors
The required inductance will now decide whether the CMOS
or NMOS topology is used. Assume the achievable value of,
say 12, for inductor Q. If the inductor geometry is too small,
destructive magnetic coupling between turns can lower its Q [20].
In this respect, the NMOS oscillator will be preferred because it
uses a larger inductor by 4×. However, a large inductor suffers
from a lower self-resonant frequency [6], which can limit the
tuning range. For these reasons, the CMOS oscillator might be
used.
Another point of note is that the larger swing of an NMOS
oscillator necessitates using I/O (or thick oxide) FETs in the
differential pair, VCO buffer, varactor, and switched capacitor
banks. These FETs will give long-term reliability but at the cost
of their larger capacitance. Therefore, extremely high-frequency
designs, or designs with an exceptionally wide tuning range will
use a CMOS oscillator. If this requires a very small inductance
in the resonator, coupled oscillators must be considered [20], as
discussed in the text accompanying Fig. 13.
D. Tuning Capacitors
Once the inductance and circuit topology are determined, the
tunable capacitance is designed. Typically, the tuning is divided
between a coarse and fine bank of switchable linear capacitors
[21] that preserve resonator Q and linearity of the reactance. The
size of the continuously tunable varactor which sets the VCO
An LC circuit in the tail can be used to impede the flow of the
common mode current at 2 f0 , provided its resonant impedance
is comparable to the main resonator. An explicit fixed or tunable
linear capacitor is better than the poorly controlled junction and
gate capacitance of the differential pair to accurately tune the
blocking resonator. If inductance and tuning range requirements
permit, the tail and main resonant tanks can be combined into
a center-tapped inductor as discussed in Sec. VI. To maximize
amplitude in low-voltage processes, it is advisable to eliminate
the current source because it takes up precious voltage headroom.
The tail current source can be replaced by an LC resonator, as
shown in Fig. 19(b). This has no adverse effect because, in a
bilateral symmetric oscillator, the current flowing in a branch of
the symmetry line comprises only DC, 2 f0 , . . . . The bias current
is now defined by the supply voltage. This requires a good lownoise LDO to prevent supply-pushing from upconverting noise
onto the oscillator frequency. The bias current, and thus the
oscillation amplitude is controlled by tuning the LDO reference
through a replica bias [20] or otherwise.
G. Miscellaneous
A self-biased inverter usually makes a good buffer at the
oscillator output.
At this point, like for any circuit, iteration is needed to optimize
the design: for example, if phase noise comfortably meets the
specifications after the first cut, a larger inductance can lower
power consumption. As another example, for mm-wave designs,
older technologies, or oscillators with very wide tuning ranges,
some adjustment may be needed to compensate for the losses
from the capacitor bank, i.e., the degraded phase noise relative
to prediction will necessitate the use of a smaller inductor in a
design iteration to increase current and recover noise performance.
Of critical importance in this iterative process is the correct
modeling of the return path of common mode currents on the
chip [10]. CMOS oscillators are better in this respect because
the supply and ground can be physically adjacent, whereas in
NMOS oscillators they are further apart on the chip (Fig. 19). In
either case, it is helpful to use magnetic field solvers to capture
the effect of routing.
Finally, most published oscillators were evaluated in benign
environments, i.e. test chip oscillators with little other on-chip
activity. In reality, an oscillator will likely be subject to unwanted
interference when deployed in a hostile environment, such as a
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(a)
13
Like all other circuits, the designer of an oscillator circuit
should be able to explain, using simple expressions, why FETs
of a certain size were chosen, why a certain inductor was used,
and justify why its performance is near optimum for the given
power dissipation. At that point, the differential LC oscillator
can be said to be well understood. This paper was written to aid
the circuit designer in reaching this goal.
On-Chip LDO
On-Chip LDO
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
(b)
Fig. 19. On-chip return path for even harmonics current is shorter and easier to
model (a) on a CMOS oscillator than (b) on an NMOS oscillator. The resonator
labeled “2 f0 block” comprises a second on-chip inductor and a tunable capacitor.
A large decoupling capacitor connects the supply to ground. The other light
elements in the return path are layout parasitics.
system-on-chip. Some immunity is gained by replacing the classic
spiral inductor with a bowtie geometry, which nulls magnetic
coupling to other inductors situated on the axis orthogonal
through the bowtie’s centroid. This may be at the price of higher
phase noise [22].
We assume a differential oscillator with blocked commonmode current flow. The tail current source is removed to
maximize swing. We know from theory that this is a nearoptimal topology, and we know from literature that our target
is FOM > 192 dB.
Step 1 Determine required phase noise specification from
system model of radio and PLL, or otherwise.
Step 2 Use phase noise specification and FOM > 192 dB
target in (39) to specify oscillator current, I0 .
Step 3 Assuming η > 80 %, using (40)(41)(42) determine
the inductance for a CMOS or NMOS oscillator that
can support this I0 .
Step 4 Choose between CMOS or NMOS topology on
practical considerations of inductor size.
Step 5 For the selected inductance, design the digital switch
capacitor bank to cover the required tuning range.
Continuous varactor size should be chosen for PLL
bandwidth.
Step 6 Ensure hard switching of the differential pair and
good efficiency by choosing FET size for 1/gm at
most 1/10× the resonator impedance at oscillation
frequency.
Step 7 Iterate design. If phase noise is too high due to
the large tuning range, follow (20) to reduce the
size of the inductor and allow more current into the
differential pair to maintain amplitude.
IX. D ISCUSSION
The differential LC oscillator is a simple circuit that, in
principle, should be understood as thoroughly as the differential
amplifier. But this is not so. The question of phase noise has been
shrouded in mystery for much longer than the state of knowledge
warrants. It is one of our goals to weaken the folklore surrounding
phase noise and offer crisp design-oriented expressions that have
been verified in the literature time and again against simulation
and measurement to establish satisfactory accuracy.
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This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
This article has been accepted for publication in IEEE Open Journal of the Solid-State Circuits Society. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/OJSSCS.2024.3524493
Asad A. Abidi received a B.Sc. degree (with honors)
from Imperial College, London, U.K., in 1976 and
an M.S. and Ph.D. in electrical engineering from the
University of California, Berkeley, in 1978 and 1981,
respectively.
From 1981 to 1984, he was with Bell Laboratories,
Murray Hill, NJ, as a Member of the Technical Staff in
the Advanced LSI Development Laboratory. Since 1985,
he has been with the Electrical Engineering Department,
University of California, Los Angeles, where he is a
Distinguished Professor. His research interests span
circuit design fundamentals, RF CMOS circuits, high-speed analog circuits, and
data conversion.
From 1992 to 1995, Dr. Abidi was Editor-in-Chief of the IEEE Journal of
Solid-State Circuits. He has received an IEEE Millennium Medal, the 1988
TRW Award for Innovative Teaching, the 1997 IEEE Donald G. Fink Award, the
2007 Lockheed-Martin Award for Excellence in Teaching, and the 2008 IEEE
Solid-State Circuit Society’s Donald O. Pederson Award. He was named one of
the top ten contributors to the ISSCC in its first 50 and 60 years, and one of the
top 50 in the conference’s history. He is co-recipient of the 2012 and 2022 Best
Paper Award from the IEEE Journal of Solid-State Circuits. The University of
California, Berkeley recognized him in 2015 as a Distinguished EECS Alumnus.
He has been elected Fellow of IEEE, a Member of the US National Academy
of Engineering, and a TWAS-The World Academy of Sciences Fellow.
David Murphy received the B.E. and M.Eng.Sc.
degrees from University College Cork, Cork, Ireland,
in 2004 and 2006, respectively, and the Ph.D. degree in
electrical engineering from the University of California,
Los Angeles, CA, USA, in 2012. Since 2012, he has
been employed as a design engineer with Broadcom Inc.,
Irvine, CA, USA. His work and research has focused
on CMOS RF design, with an emphasis on oscillators,
phase locked loops, and receiver architectures.
He is a co-recipient of the JSSC Best Paper Award
(2012 and 2024), the Best Invited Paper Award at the
CICC (2013), the Jack Kilby Award for Outstanding Student Paper at ISSCC
(2013), and the Distinguished Technical-Paper Award at ISSCC (2012).
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14