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Contact info:
chakravarthibmithun@gmail.com
Mithun Chakravarthi Bungatavala | LinkedIn
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Day 1: 7458 Chip, Reversing a Vector2
Day 2: Implementation of Carry Look Ahead Adder1
Day 3: Binary to Gray Converter, Gray to Binary Converter
Day 4: 2’s Complementor using Multiplexers and Adders
Day 5: 4 Bit Comparator using 2 Bit Comparator
Day 6: Priority Encoder
Day 7: Verilog Code for Circuit
Day 8: Zeros Counter, Ones Counter
Day 9: Minority Detector
Day 10: Seven Segment Display7
Day 11: Carry Select Adder
Day 12: 4 Bit Binary Multiplier8
Day 13: 4 Bit Barrel Shifter9
Day 14: Designing of ALU with 16 Operations10
Day 15: Clock Divider using a Counter
Day 16: Circuit that Divides Clock Frequency by Odd Number
Day 16B: CREATE A CLOCK WITH FREQUNCY 50 MHz , 16 MHz, 8 MHz.
Day 17: Implementation of SR, D, T, JK Flip Flops
Day 18: Conversion of Flip Flops
Day 19: D Latch from 2x1 Multiplexer12
Day 20: Verilog Code with Test Bench313456
Day 21: SISO, SIPO, PISO, PIPO in Behaviour Modelling
Day 22: Linear Feedback Shift Register11
Day 23: Bi Directional Shift Register
Day 24: Universal Shift Register
Day 25: Single Port RAM
Day 26: Fixed Point Arbiter
Day 27: Round Robin Arbiter
Day 28: Up Down Counter
Day 29: Ring Counter
Day 30: Johnson Counter
Day 31: Booth Multiplier
Day 32: Serial 2’s Complementor
Day 33: CN Flip Flop
Day 34: Greatest Common Divisor
Day 35: Verilog Module Equivalence
Day 36: Full Case vs Parallel Case
Day 37: POS Edge Detector
Day 38: 1010 Sequence Detector by Moore Machine
4
Day 39: 1001 Sequence Detector by Mealy Machine14
Day 40: 1011 Sequence Detector Mealy Machine (Overlap)15
Day 41: 2 x 2 Vedic Multiplier
Day 42: Implementation of 15 x 15 ROM16
Day 43: Simple Pulse Width Modulation
Day 44: Computation of Square Root and Cube Root
Day 45: Parity Generator
Day 46: Implementation of a Simple Dual Port RAM
Day 47: Clock Phase Changer
Day 48: LED Blinker
Day 49: Designing of Synchronous FIFO17
Day 50: Implementation of 4 Bit Carry Save Adder
5
DAY 1
6
Code for the circuit:
b) Reversing a vector
7
SIMULATION WAVEFORM:
8
DAY 2
IMPLEMENTATION OF CARRY LOOK AHEAD ADDER
VERILOG CODE WITH TESTBENCH:
SIMULATION WAVEFORM:
9
DAY 3
1.IMPLEMENTATION OF BINARY TO GARY CONVERTER
VERILOG CODE WITH TESTBENCH
SIMULATION WAVEFORM:
10
2. IMPLEMENTATION OF GRAY TO BINARY CONVERTER
VERILOG CODE WITH TESTBENCH
SIMULATION WAVEFORM
11
DAY-4
DESIGN A CIRCUIT FOR 2’S COMPLEMENTOR USING MULTIPLEXERS AND ADDERS
12
VERILOG CODE FOR HALF ADDER,FULL ADDER,MULTIPLEXER
13
INSTANTIATING THESE BLOCKS ACCORDING TO LOGIC DISCUSSED BEFORE
OUTPUT SIMULATION WAVEFORM:
14
DAY-5
a. DESIGN A 4 BIT COMPARATOR USING 2 BIT COMPARATOR
15
VERILOG CODE THE THE DESIGN:
SIMULATION WAVEFORM:
16
DAY6
PRIORITY ENCODER
TRUTH TABLE
Verilog code
17
OUTPUT SIMULATION WAVEFORM:
18
Day-7
1.WRITE A VERILOG CODE FOR THE CIRCUIT
19
VERILOG CODE WITH TESTBENCH
OUTPUT SIMULATION WAVEFORM
20
2. Adder Subtractor using a control input
VERILOG CODE WITH TESTBENCH
21
OUTPUT SIMULATION WAVEFORM:
22
DAY-8
ZEROS COUNTER,ONES COUNTER
VERILOG CODE WITH TESTBENCH
OUTPUT SIMULATION WAVEFORM:
23
24
DAY-9
IMPLEMENTATION OF MINORITY DETECTOR
VERILOG CODE WITH TESTBENCH
OUTPUT SIMULATION WAVEFORM
25
DAY 10 SEVEN SEGMENT DISPLAY
VERILOG CODE WITH TESTBENCH
OUTPUT SIMULATION WAVEFORM
26
DAY-11 CARRY SELECT ADDER
27
VERILOG CODE WITH TEST BENCH
28
TRANSCRIPT WINDOW
OUTPUT SIMULATION WAVEFORM
29
DAY-12
4 BIT BINARY MULTIPILER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TEST BENCH
30
SCHEMATIC CIRCUIT
31
DAY 13 4 BIT BARREL SHIFTER
A. 4X1 MULTIPLEXER
B. BARREL SHIFTER USING MULTIPLEXER
32
C. TEST BENCH
D. CONSOLE WINDOW
33
RTL SCHEMATIC OF BARREL SHIFTER
34
DAY 14 DESIGNING OF ALU WITH 16 OPERATIONS
VERILOG CODE
35
TEST BENCH:
CONSOLE RESULT:
36
DAY 15
CLOCK DIVIDER USING A COUNTER
VERILOG CODE WITH TEST BENCH
OUTPUT SIMULATION WAVEFORM
NOTE:
TO DIVIDER CLOCK BY SOME OTHER DIVISOR . JUST CHANGE PARAMETER VALUE.
37
DAY 16
CREATE A CIRCUIT THAT DIVIDES CLOCK FREQUNECY BY ODD NUMBER
(HERE I AM DOING IT WITH 3)
VERILOG CODE :
TESTBENCH:
38
OUTPUT SIMULATION WAVEFORM:
CIRCUIT:
39
DAY 16 -B
Q. CREATE A CLOCK WITH FREQUNCY 50 MHz , 16 MHz, 8 MHz.
To do this we should be clear about timescale derivative.
a.
b.
c.
d.
50 MHz means it has a time period of 20 ns (i.e. Half time period 10ns)
16 MHz means it has a time period of 62.5 ns (i.e. Half time period 31.25ns)
8 MHz means it has a time period of 125 ns (i.e. Half time period 62.5ns)
So we need a precision of 2 bits
So our time scale derivative should be
`timescale 1ns/1ps
Which means 10^-9∕10^-12 =10^3 i.e. we have a precision of 3 bits.
i.e. Till a precision of 3 bits after decimal we can specify our value.
VERILOG CODE :
OUTPUT SIMULATION WAVEFROM
40
DAY 17
A. IMPLEMENTATION OF SR,D,T,JK FLIP FLOPS
1. SR (SET-RESET FLIP FLOP)
VERILOG CODE WITH TEST BENCH:
41
2. D (DATA FLIP FLOP)
VERILOG CODE WITH TEST BENCH:
42
3. T FLIP FLOP
VERILOG CODE WITH TEST BENCH:
43
4. J K (JACK KILBY) FLIP FLOP
VERLIOG CODE WITH TEST BENCH:
44
DAY 18
CONVERSION OF FLIP FLOPS
1. D to JK flip flop
Verilog code for D_ ff
Conversion of D to JK
Test Bench
Output simulation Waveform:
45
2. CONVERSION OF SR TO TFLIP FLOP
VERILOG CODE FOR SR FLIP FLOP
VERILOG CODE FOR CONVERSION OF SR TO T FLIP FLOP:
TEST BENCH:
46
OUTPUT SIMULATION WAVEFORM
CONVERSION OF ALL FLIP FLOPS
YOU CAN CONVERT FLIP SLOPS FROM ONE TO OTHER BY USING THESE AS INPUTS.
THESE CAN BE DERIVEDD FROM WRITINF TRUTH ABLE AND EXCITATION TABLES.
47
DAY-19
A. D_LATCH FROM 2X1 MULTIPLEXER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TEST BENCH
48
b. D_FLIP FLOP USING MULTIPLEXER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TEST BENCH
49
DAY-20
50
VERILOG CODE WITH TEST BENCH
TESTBENCH
51
OUTPUT SIMULATION WAVEFORM
RTL SCHEMATIC
52
DAY 21
IMPLEMENTATION OF SISO ,SIPO,PISO,PIPO IN BEHAVIOUR MODELLING
1.
SERIAL IN SERIAL OUT SHIFT REGISTER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TEST BENCH
53
2. SERIAL IN PARALLEL OUT SHIFT REGISTER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TEST BENCH
54
3. PARALLEL IN PARALLEL OUT SHIFT REGISTER
VERILOG CODE
TEST BENCH
OUTPUT SIMULATION WAVEFORM
55
4. PARALLEL IN SERIAL OUT SHIFT REGISTER
VERILOG CODE
OUTPUT SIMULATION WAVEFORM
TESTBENCH
56
DAY 22
LINEAR FEEDBACK SHIFT REGISTER
TRUTH TABLE FOR 4 BIT RANDOM SEQUNECE GENERATOR:
57
VERILOG CODE
TESTBENCH:
OUTPUT SIMULATION WAVEFORM:
58
DAY 23
BI DIRECTIONAL SHIFT REGISTER
This shift register shifts the contents of the flip flop to
a. Right if mode=1
b. Left if mode=0
59
VERILOG CODE:
TEST BENCH:
60
OUTPUT SIMULATION WAVEFORM:
61
DAY 24
UNIVERSAL SHIFT REGISTER
A Universal shift register is a register which has both the right shift and left shift
with parallel load capabilities. Universal shift registers are used as memory
elements in computers. A Unidirectional shift register is capable of shifting in only
one direction. A bidirectional shift register is capable of shifting in both the
directions. The Universal shift register is a combination design of bidirectional shift
register and a unidirectional shift register with parallel load provision.
WHEN MODE IS
S1
S0
0
0
0
1
1
0
1
1
VERILOG CODE
OPERATION
NO CHANGE
RIGHT SHIFT
LEFT SHIFT
LOAD
62
TEST BENCH:
OUTPUT SIMULATION WAVEFORM:
63
DAY 25
SINGLE PORT RAM
VERILOG CODE:
64
TEST BENCH
65
OUTPUT SIMULATION WAVEFORM
66
NORMAL PACTICE:
67
68
UP_DOWN COUNTER
VERLOG CODE
TEST BENCH
OUTPUT SIMULATION WAVEFORM
69
DAY-26
FIXED POINT ARBITER
VERILOG CODE
70
TEST BENCH
OUTPUT SIMULATION WAVEFORM
71
DAY-27
ROUND ROBIN ARBITER
VERILOG CODE:
72
73
TEST BENCH
74
OUTPUT SIMULATION WAVEFORM:
75
DAY-28
UP_DOWN COUNTER
VERILOG CODE:
Counter acts as Up_counter if (up_down=1)
Down_counter if (up_down=0)
TEST BENCH
OUTPUT SIMULATION WAVEFORM
76
DAY-29
RING COUNTER
VERILLOG CODE:
TEST BENCH:
77
OUTPUT SIMULATION WAVEFORM:
78
DAY-30
JOHNSON COUNTER
VERILOG CODE:
TEST BENCH:
79
OUTPUT SIMULATION WAVEFORM:
Difference Between Ring Counter and Johnson Counter
The difference between the ring counter and johnson counter is, the inverter
output of the last flip-flop is connected back as the input to the first flip-flop.
In-ring counter, the no.of input clock pulses given to the flip-flops are equal to
the no.of stages. That means the MOD of the n-bit ring counter is ‘n’.
In johnson’s counter, the no.of input clock pulses divide by a factor of twice
equal to the no.of stages. That means the MOD of the n-bit johnson counter is
‘2n’.
Advantages
•
The johnson counter counts the no.of stages twice equal to the no.of
clock pulses given to the flip-flops.
• It counts the events in a continuous closed loop within the circuit.
• It can be designed by using D and JK flip-flops
• It can be used as a self-decoding circuit.
Disadvantages
It cannot be used to count the binary sequence
It doesn’t utilize all the stages equal to the no.of stages in the counter.
It needs only half the no.of flip-flops on half the no.of timing signals
It is used in any timing sequence.
Applications
•
•
•
•
•
•
•
•
•
Johnson counters are used as frequency dividers and pattern
recognizers.
It is used as a synchronous decade counter and divider circuit
It can be used to create complicated finite state machines in hardware
logic design.
The 3-bit johnson counter is used as a 3-phase square wave generator
to produce 120 degrees phase shift
The frequency of the clock signal is divided by varying their feedback.
80
DAY-31
BOOTH MULTIPLIER
VERILOG CODE
TEST BENCH
81
OUTPUT:
A. 7*3 = 21 (0001_0101)
B. 7*-3= -21 (1110_1011)
BOOTH’S ALGORITHM
82
DAY-32
Give the state machine for serial 2’s complementor and design the same
using D-Flip Flop.
83
Verilog code:
Test Bench:
84
Output Simulation Waveform:
Schematic:
85
Day-33
A CN flip-flop has four operations: no change, clear to 0, no change, complement,
when inputs C and N are 00, 01, 10, and 11, respectively.
(a) Tabulate the characteristic table.
(b) * Derive the characteristic
equation.
(c) Show how the CN flip-flop with a D flip-flop and 2X1 Multiplexer.
86
Implementation of Change No Change Flip Flop using 2 x 1 multiplexers.
Verilog code of 2x1 Mux:
Verilog code of D-Flip Flop:
Verilog code of Change- No Change flip flop:
Test Bench:
87
Output Simulation Waveform:
88
Day -34
Implementation of Greatest Common Divisor in behaviour level.
Verilog code:
89
Test Bench:
90
Output simulation waveform:
91
92
DAY-35
Write a Verilog module to illustrate the equivalence between @(a or b) and @(a | b).
•
In Verilog, @( ) is used to trigger a simulation event based on the values of signals given
inside it.
•
The @(a or b) syntax uses the logical operator or to specify that the simulation event will be
triggered when either signal a or signal b changes value. Similarly, the @(a | b) syntax uses
the bitwise OR operator |, but in Verilog, the bitwise OR operation is the same as the logical
OR operation for single-bit signals, so it's equivalent to @(a or b).
VERILOG MODULE:
93
CONSOLE WINDOW:
94
DAY-36
Write a Verilog module to demonstrate the difference between full case and parallel case.
Verilog Module:
Console Window:
95
In Verilog, "full case" and "parallel case" are terms used to describe different
ways of writing case statements to describe the behaviour of a specific input
condition. These terms pertain to the structure and style of the case statement.
Full Case:
A "full case" style of writing a case statement includes all possible input
conditions explicitly. In other words, each possible value of the control
expression is listed along with its corresponding set of actions. If any value is
not explicitly listed, it is assumed to have no effect.
case (ctrl)
2'b00: action_00;
2'b01: action_01;
2'b10: action_10;
2'b11: action_11;
endcase
In this example, all four possible 2-bit values of ctrl (00, 01, 10, and 11) are
listed along with their respective actions.
Parallel Case:
A "parallel case" style of writing a case statement groups together actions that
share common behaviour for certain input conditions. In other words, multiple
input values may result in the same set of actions, and those actions are
grouped together.
Here's an example of a parallel case statement:
case (ctrl)
2'b00, 2'b01: action_0x; // Both 00 and 01 cases trigger action_0x
2'b10: action_10;
2'b11: action_11;
endcase
In this example, both 2'b00 and 2'b01 cases trigger the action_0x behaviour. In
summary: "Full case" style includes all possible input conditions explicitly.
"Parallel case" style groups together input conditions that have the same
behaviour.
96
DAY-37
POS_EDGE DETECTOR
Test Bench:
97
Output Simulation Wave form:
98
DAY-38
1010 SEQUENCE DETECTOR BY MOORE MACHINE
99
100
TEST BENCH:
OUTPUT WAVEFORM:
101
DAY-39
1001 SEQUENCE DETECTOR BY MEALY MACHINE
VERILOG CODE:
102
TEST BENCH:
OUTPUT SIMULATION WAVEFORM:
103
DAY-40
1011_SEQUENCE DETECTOR MELAY MACHINE(OVERLAP):
VERILOG CODE :
104
TESTBENCH:
OUTPUT SIMULATION WAVEFORM:
105
DAY-41
2 X 2 VEDIC MULITPLIER:
VERILOG CODE:
106
TEST BENCH:
OUTPUT SIMULATION WINDOW:
CONSOLE:
107
DAY 42
IMPLEMENTATION OF 15 X 15 ROM
A ROM, or Read-Only Memory, is a type of digital memory device that stores data permanently.
Unlike RAM (Random Access Memory), ROM retains its contents even when the power is turned
off, hence the term "read-only." This means that the data stored in ROM cannot be modified or
overwritten after it has been programmed.
VERILOG CODE:
108
TEST BENCH:
109
OUTPUT SIMULATION WAVFORM:
110
DAY-43
CREATION OF SIMPLE PULSE WIDTH MODULATION of different duty cycles.
VERILOG CODE:
TEST BENCH:
OUTPUT SIMULATION WAVEFORM:
111
DAY-44
COMPUTATION OF SQAURE ROOT AND CUBE ROOT OF A NUMBER:
VERILOG CODE:
112
TEST BENCH:
OUTPUT SIMUATION WAVEFORM:
113
DAY-45
PARITY GENERATOR:
Assigns result 1 if number of 1’s in input is odd.
Assigns result 0 if number of 1’s in input is even.
VERILOG CODE:
TEST_BENCH:
114
OUTPUT SIMULATION WAVEFORM:
115
DAY-46
IMPLEMENTATION OF A SIMPLE DUAL PORT RAM
VERILOG CODE:
OUTPUT:
116
TEST BENCH:
117
118
DAY – 47
CLOCK PHASE CHANGER
VERILOG CODE:
119
TEST BENCH:
OUTPUT SIMULATION WAVEFORM:
120
DAY -48
LED BLINKER
VERILOG CODE:
121
OUTPUT SIMULATION WAVEFORM:
LED turns on after 50000000 ps and turns off after 50000000 ps.
122
DAY-49
DESIGNING OF SYNCHRONOUS FIFO
VERILOG CODE:
123
OUTPUT WAVEFORM:
124
DAY-50
IMPLEMENTATION OF 4 BIT CARRY SAVE ADDER
VERILOG CODE FOR FULL ADDER:
VERILOG CODE FOR CARRY SAVE ADDER:
125
TEST BENCH:
OUTPUT SIMULATION WAVEFORM:
THANK YOU
B.MITHUN CHAKRAVARTHI