Introduction to Analog Integrated Circuit Design Fall 2025 MOST Physics Yung-Hui Chung MSIC Lab DECE, NTUST Understanding MOS Transistors Mixed-Signal IC Laboratory Quantum mechanics Solid-state physics Semiconductor device physics Device modeling Design of circuits CMOS Transistors Why CMOS? Yung-Hui Chung Current formula Basic Operation and MOS Physics Short-Channel Effects Second-Order Effects Design of circuits, … MOST Physics 2 MOS Device Structure Mixed-Signal IC Laboratory • 2D-device: planar CMOS transistors – Source/Drain: Diffusion – Substrate/Well : p-sub/n-well – Gate oxide: SiO2, tox – Poly Gate HKMG (High-K and Metal Gate) in nanometer CMOS • 3D-device: FinFET MOS Transistors Yung-Hui Chung MOST Physics 3 MOS Device Structure Mixed-Signal IC Laboratory Basic p/nMOS Transistors (pMOST and nMOST in CMOS VLSI) • • Twin-Well Process Deep-Nwell Process • Various device types (by its threshold voltage or … ): – SP_LVT; SP_RVT; SP_HVT; Zero-VT; Native; … Yung-Hui Chung MOST Physics 4 FinFET (3D-MOS Transistors) Mixed-Signal IC Laboratory https://www.circuitbread.com/ee-faq/what-isa-finfet Yung-Hui Chung MOST Physics 5 FinFET (3D-MOS Transistors) Mixed-Signal IC Laboratory L gate • L < 20 nm => FinFET era (TSMC, Samsung, Intel, … ) • In fact, FinFET I/V characteristics are close to square-law behavior, making our simple large-signal mode relevant again • Channel width: W = WF + 2HF (fixed) W’ = Nf*W, Nf is # of Fins • The spacing between the fins, SF, also plays a significant role in the performance Yung-Hui Chung MOST Physics 6 FinFET Transistors: SEM Image Mixed-Signal IC Laboratory Tilt view SEM image of Samsung 14 nm FinFET transistors (Source: Samsung 14 nm Exynos 7 7420 Logic Detailed Structural Analysis, TechInsights) Yung-Hui Chung MOST Physics 7 FinFET Transistors: SEM Image Mixed-Signal IC Laboratory Plan view image of Samsung 14 nm FinFET transistors (Source: Samsung 14 nm Exynos 7 7420 Logic Detailed Structural Analysis, TechInsights) Yung-Hui Chung MOST Physics 8 FinFET Transistors: Roadmap Mixed-Signal IC Laboratory https://www.tomshardware.com/news/imec-reveals-sub-1nm-transistor-roadmap-3d-stacked-cmos-20-plans Yung-Hui Chung MOST Physics 9 MOSFET Control 1 𝐼 = 𝜇 𝐶 2 Mixed-Signal IC Laboratory 𝑊 𝑉 𝐿 −𝑉 1 + 𝜆𝑉 VGS vs. VDS Yung-Hui Chung MOST Physics 10 A MOSFET Driven by a Gate Voltage Mixed-Signal IC Laboratory Positive ions (Qdep) VGS varies from zero to a high voltage: (a) Off region (VGS = 0) (b) Subthreshold region (VGS < VTH) (c) Neutralization point (VGS = VTH) (d) Strong Inversion region (VGS > VTH +200mV) Yung-Hui Chung MOST Physics 11 A MOSFET Driven by a Gate Voltage Mixed-Signal IC Laboratory Description in textbook, Yung-Hui Chung MOST Physics 12 MOSFET in “OFF” Region Mixed-Signal IC Laboratory Positive ions (Qdep) VGS is much less than VTH: • Some negative ions in channel region • There is no active charges from source to drain • The MOSFET can be seen disabled • But, it is not really inactive => leakage issue Yung-Hui Chung MOST Physics 13 MOSFET in “Subthreshold” Region Mixed-Signal IC Laboratory Depletion layer VGS is approaching to VTH (from zero voltage): • The “mobile” charges are negative ions, not electrons (current is by diffusion manner) • These negative ions are contributed from the p-substrate and attracted by a positive gate voltage Yung-Hui Chung MOST Physics 14 MOSFET at “Neutralization” State Mixed-Signal IC Laboratory Depletion layer Neutralization (電中性) VGS is equal to VTH: • The attracted negative ions are equal to the majority carriers (positive ions). It means VGS = VTH • Now, the position below gate oxide is floating => up is a Cox and down is a Cdep => Q: Cgb=? Yung-Hui Chung MOST Physics 15 MOSFET in “Strong Inversion” Region Mixed-Signal IC Laboratory Depletion layer Inversion layer VGS is larger than VTH by a certain voltage: • The mobile charges are electrons, moved from source to drain. The conduction path is called “inversion channel”. • Inversion means the charges on the channel are “positive => negative” Yung-Hui Chung MOST Physics 16 MOSFET Summary by VGS Mixed-Signal IC Laboratory Positive ions (Qdep) • • tox=20Å to get Cox~17.25fF/m2 Native device (VTH ~ 0), how? – Adjusting the doping (Nsub) to change VTH • PMOS have similar phenomenon but majority carrier is “hole” Yung-Hui Chung MOST Physics 17 MOSFET Summary by VGS Mixed-Signal IC Laboratory While we ask “MOSFET is at ON or OFF mode”, it means VGS is large or small. (ON: strong or weak inversion) 100mV strong inversion Yung-Hui Chung While we ask “the MOSFET is triode or saturation region”, it means VDS is large enough or not? MOST Physics 18 MOSFET: Drain Current Mixed-Signal IC Laboratory Channel Charge Model in triode region Drift Velocity 𝑣 = 𝜇𝐸 𝐸 𝑥 = −𝑑𝑉/𝑑𝑥 Qd where x: 0 ~ L Note: Qd: 線電荷 (Q/L) Yung-Hui Chung 𝐼 =𝜇 𝐶 MOST Physics 𝑊 𝐿 𝑉 −𝑉 𝑉 1 − 𝑉 2 19 MOSFET: Drain Current Mixed-Signal IC Laboratory Channel Charge Model in triode region Drift Velocity 𝑣 = 𝜇𝐸 𝐸 𝑥 = −𝑑𝑉/𝑑𝑥 𝐼 =𝜇 𝐶 𝑊 𝐿 𝑉 −𝑉 𝑉 1 − 𝑉 2 This current conduction is true before the pinch-off effect occurs!! 𝑉 𝐼 , Yung-Hui Chung MOST Physics =𝑉 −𝑉 1 = 𝜇 𝐶 2 𝑊 𝑉 𝐿 −𝑉 20 Channel Charge vs. VDS Mixed-Signal IC Laboratory VGS is constant Triode region VDS ~ 0 Saturation region VDS=VGS-VTH Yung-Hui Chung MOST Physics 21 Pinch-off Behavior Yung-Hui Chung Mixed-Signal IC Laboratory MOST Physics 22 Pinch-off Behavior Mixed-Signal IC Laboratory Ldep 1 𝐼 = 𝜇 𝐶 2 𝑊 𝑉 𝐿 −𝑉 Channel Length Modulation The real channel length is L - Ldep Yung-Hui Chung MOST Physics 23 MOSFET as a Resistor Mixed-Signal IC Laboratory Deep Triode Region 𝐼 =𝜇 𝐶 𝑊 𝐿 𝑉 −𝑉 𝑉 1 − 𝑉 2 𝐼 ≈𝜇 𝐶 𝑅 𝑊 𝑉 𝐿 −𝑉 𝑉 1 = 𝜇 𝐶 𝑊 𝑉 𝐿 −𝑉 A voltage-controlled resistor Yung-Hui Chung MOST Physics 24 MOSFET as an Amplifier Mixed-Signal IC Laboratory gm Representation 𝜕𝐼 𝑔 = 𝜕𝑉 𝑔 =𝜇 𝐶 Yung-Hui Chung . 𝑊 𝑉 𝐿 −𝑉 𝑔 = 2𝜇 𝐶 MOST Physics 𝑊 𝐼 𝐿 2𝐼 𝑔 = 𝑉 −𝑉 25 MOSFET: Nonideal Effects 1 𝐼 = 𝜇 𝐶 2 𝑊 𝑉 𝐿 −𝑉 Mixed-Signal IC Laboratory 1 + 𝜆𝑉 • Body Effect – VTH ~ f(VSB) • Channel-Length Modulation – ro ~ f(L, VDS) • Subthreshold Conduction – VGS ~ VTH • Voltage Limitation – High VDD Yung-Hui Chung MOST Physics 26 Body Effect (1) Mixed-Signal IC Laboratory VSB > 0 VSB 0 Note: Cox = Cgate/WL Yung-Hui Chung 𝑉 𝛾= =𝑉 +𝛾 2𝑞𝜖 𝑁 2Φ /𝐶 MOST Physics +𝑉 − 2Φ ( = 0.3 ~ 0.4, by process) 27 Body Effect (2) Mixed-Signal IC Laboratory An ideal voltage follower: Vin-Vout=constant Nonideal voltage follower 1 𝐼 = 𝜇 𝐶 2 𝑊 𝑉 −𝑉 𝐿 −𝑉 We may conclude that the body effect causes a nonlinear error (distortion) in this nMOST source follower Yung-Hui Chung MOST Physics 28 Channel-Length Modulation 𝐼 = Mixed-Signal IC Laboratory 1 𝜇 𝐶 2 𝑊 𝑉 𝐿′ −𝑉 𝐿′ = 𝐿 − Δ𝐿 (pinch-off effect) 1 1 1 1 1 ∆𝐿 = = ~ 1+ 𝐿′ 𝐿 − ∆𝐿 𝐿 1 − ∆𝐿/𝐿 𝐿 𝐿 ∆𝐿與VDS有關 nanometer NMOS Transistors 1 𝐼 ~ 𝜇 𝐶 2 𝑊 𝑉 𝐿 −𝑉 𝑔 =𝜇 𝐶 𝑉 −𝑉 = 2𝜇 𝐶 1 + 𝜆𝑉 1 + 𝜆𝑉 𝑊 ⁄𝐿 𝐼 1 + 𝜆𝑉 ⇒ 𝜆與𝐿有關!! Example (2.7) Yung-Hui Chung MOST Physics 29 Subthreshold Conduction ID = 0 if VGS < VTH ? The answer is not!! 1 𝐼 = 𝜇 𝐶 2 𝑊 𝑉 𝐿 Mixed-Signal IC Laboratory VGS-VTH MOSFET Model: • BSIM vs. EKV −𝑉 200mV 100mV 0 • Strong Inversion • Moderate Inversion • Weak Inversion • Subthreshold • Deep-subthreshold Subthreshold Current Model 𝐼 =𝐼 𝑒 𝐼 2𝐼 𝑔 = = 𝜉𝑉 𝑉 −𝑉 Yung-Hui Chung 𝑉 −𝑉 = 2𝜉𝑉 80 mV (@27C) where 1.5 MOST Physics => Subthreshold boundary 30 MOSFET Small-Signal Model Mixed-Signal IC Laboratory • gm: transconductance, given VGS to yield IDS • ro: by CLM effect, • gmb: by Body effect, Yung-Hui Chung MOST Physics 31 MOSFET Small-Signal Model Mixed-Signal IC Laboratory Use source node as the reference (common ground) (That’s why we call the back-gate effect) Yung-Hui Chung MOST Physics 32 MOS Capacitor Model Mixed-Signal IC Laboratory 以物理結構來看 空乏電容 平板電容 𝐶 = 𝑊𝐿𝐶 𝐶 = 𝐶 = 𝑊𝐿 𝐶 空乏電容 𝐶 = 𝑊𝐿 𝑞𝜀 𝑁 Yung-Hui Chung For C5 and C6, = 𝑊𝐶 / 4𝜑 MOST Physics 𝐶 = 𝐶 / 1 + 𝑉 /𝜑 𝐶 =𝐶 / 1 + 𝑉 /𝜑 𝑚 = 0.3~0.4 33 MOS Capacitor Model Mixed-Signal IC Laboratory 以電路運作來看 CGS and CGD V V >V <V +V −V *CGB: *CDS: Yung-Hui Chung MOST Physics 34 MOS Capacitor Model 𝐶 = 𝑊𝐿𝐶 Mixed-Signal IC Laboratory 𝐶 = 𝐶 / 1 + 𝑉 /𝜑 𝐶 = 𝑊𝐿 𝑞𝜀 𝑁 / 4𝜑 𝐶 𝐶 = 𝐶 = 𝑊𝐿 𝐶 = 𝑊𝐶 𝑚 = 0.3~0.4 Yung-Hui Chung MOST Physics =𝐶 / 1 + 𝑉 /𝜑 35 MOSFET Small-Signal Model Yung-Hui Chung MOST Physics Mixed-Signal IC Laboratory 36 Summary of Lecture 1 Mixed-Signal IC Laboratory • MOSFET: 2D vs. 3D • MOSFET control: VGS and VDS – VGS: OFF, Subthreshold, Weak Inversion, and Strong Inv. – VDS : Triode or Saturation region • Current Equation • MOSFET can be configured as – Switch, VCCS, Amplifier, Resistor, Capacitor • MOSFET Small-Signal Model – gm, gmb, ro – Cgs, Cgd, Cdb, Csb, Cgb, Cds Yung-Hui Chung MOST Physics 37 MOSFET as a Capacitor Mixed-Signal IC Laboratory • Accumulation mode – Hole concentration is increased if VGS is more negative (plate is formed by a hole layer) • Depletion mode – Hole concentration is decreased and electron concentration is increased if VGS is from negative to positive (acts like a floating point) • Inversion mode Low-freq High-freq Depletion cap included Yung-Hui Chung – Inversion layer is formed to act as a plate. For high-frequency gate variations, layer is not formed in time (>1MHz); for low-freq gate variation, layer is always formed (<100Hz) Non-Quasi Static (NQS) Effect MOST Physics 38 SPICE Models Mixed-Signal IC Laboratory 𝛾= 𝐶 2𝑞𝜖 𝑁 /𝐶 = 𝜀 /𝑡 𝐶 = 𝐶 / 1 + 𝑉 /𝜑 𝐶 =𝐶 / 1 + 𝑉 /𝜑 𝑚 = 0.3~0.4 1 𝐼 = 𝜇 𝐶 2 𝑉 Yung-Hui Chung MOST Physics =𝑉 𝑊 𝑉 𝐿 +𝛾 −𝑉 2Φ +𝑉 1 + 𝜆𝑉 − 2Φ 39 Threshold Voltage vs. Temperature Yung-Hui Chung MOST Physics Mixed-Signal IC Laboratory 40 Reduction of gate resistance Mixed-Signal IC Laboratory Folding structure to reduce the gate resistance RG W/L • The resistance on drain and source can be reduced by the same concept!! • Don’t use too wide transistors. For example, W=20u, L=0.2u • Using multiplier (m) or finger (nf) to implement a wide transistor Yung-Hui Chung MOST Physics 41 Appendix: MOSFET Simple Description Mixed-Signal IC Laboratory Detail information is shown on page 6-10 0 0 < VG < VTH VG = 0 VG = VTH VG > VTH *Physically, it is driven by “energy band model, changed by VG” Yung-Hui Chung MOST Physics 42
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