STATIC
TIMING
ANALYSIS
 Major Differences in Technology Nodes (From Initial to Present)
Nodes
Transistor Type
Major Changes & Improvements
180nm - 65nm
Planar CMOS (2D Transistor)
Basic CMOS transistors, high power consumption,
lower density.
45nm - 20nm
Advanced Planar CMOS
Improved power efficiency, but leakage becomes a
major issue.
16nm - 10nm
FinFET (3D Transistor)
Introduced FinFET to reduce leakage, improved
power and performance.
7nm - 3nm
Advanced FinFET
Higher transistor density, extreme scaling, better
energy efficiency.
2nm & Beyond
Gate –All – Around(GAA)
Nanosheet
Full control over current, better power efficiency,
next-gen performance.
 Why is FinFET being replaced by GAA (Nanosheet Transistors)?
 FinFET struggles with extreme scaling below 3nm. GAA provides better electrostatic control by
surrounding the channel on all sides.
STATIC TIMING ANALYSIS
 Where timing analysis starts (before STA) depends upon design flow?
 RTL & design verification do not involve detailed timing analysis because timing is dependent on
synthesized gates & Layout.
 Real timing analysis starts from synthesis & becomes accurate after routing.
 Synthesis stage (first timing consideration): Timing analysis starts here with logical optimization.
 Tool optimized setup, hold time & clock constraints using wire load models (not real values).
 Floorplan stage (Physical Timing begins): After synthesis, macro placement, pin placement & power planning are done.
 Timing analysis is performed here to check macro placement, blockages & early congestion impact.
 Placement stage ( Pre-CTS timing analysis): Before CTS, timing is analyzed with estimated delay values.
 Tool optimizes placement to reduce the setup violations.
CTS stage: Timing analysis is done with actual clock tree to check skew, insertion delay & hold time issues.
Post Routing stage: After routing, a full STA is done.
 Checks for setup/hold violations, clocks uncertainty and delays.
 Why STA after routing?
 Before routing, wire delays are estimated(virtual).
 After routing, Actual RC delays(parasitic delays) are extracted to make accurate timing analysis.
 Clock tree is fully built and actual skew, insertion delay, and uncertainty are considered.
 STA ensures there are no setup & hold violations with real interconnect delays.
STATIC TIMING ANALYSIS
 Static Timing Analysis: STA checks static delay requirements of the circuit without any i/p or o/p vectors.
 We can’t achieve the clock speed without STA.
 It doesn’t check for logic functionality of the design.
 It analyzed the best &worst cases simultaneously for all timing paths.
 It cannot be applied Asynchronous & Loop paths.
 It is not suitable for designs having clock cross multiple domains.
INPUTS OF STA: Gate level netlist(.v)  it have circuit description.
 Constraints (.sdc)  it contains all the timing related information about the design. Includes the clock
definition (create clock, generated clock, virtual clock), uncertainty (jitter, skew, margin), I/O delays,
False paths, Multi-cycle paths, max trans, max cap, max fanout.
 Timing library(.lib)  every cell delay are present in the library.
 Standard Parasitic Exchange Format(.spef)  Parasitic of the design extracted from PD tools.
OUTPUTS: Different timing paths REPORTS, which can be used for debugging.
 STA involves three steps
1
Break the design into sets of timing paths.
2
Calculate the delay of each path.
3
Check all path delays to see if the given timing constraints are met or not.
 DTA vs STA ?
DTA
STA
Checks for both timing & functionality.
Checks for only timing.
Dependent on input data (Test Vectors).
Independent of data.
Slower because it also checks the functionality.
Faster & takes less time.
 In ICC2 are any tool the universal command for checking is “ report_timing “.
Recovery & Removal : Recovery refers to SETUP TIME & Removal refers to HOLD TIME.
 For synchronous clocks we do setup & hold timing analysis.
 For Asynchronous clocks we do Recovery & Removal analysis.
 Single Cycle Path:
 A timing path that completes in one clock cycle.
 Data propagates from one flip-flop to another, all clocked by the same clock.
 Tools generally consider all paths as single cycle by default.
TIMING PATHS
Timing paths: A timing path is a point – to – point path in a design which can propagate data from one flip – flop to
another.
 Each point has a start point & an end point.
 Start point:- Input ports or clock pin of flip – flops
 End points:- Output ports or data input pin of flip – flops.
COMBO
LOGIC
COMBO
LOGIC
RReg
IN
COMBO
LOGIC
RReg
IN
COMBO
LOGIC
OUT
OUT
 Timing paths grouped into 4 paths i.e,
1.
IN – REG.
2.
REG – REG.
3.
REG – OUT.
4.
IN – OUT.
Q
I
N
D
Clk
IN – REG Timing analysis:Setup Slack (ss) = RT – AT
 (Tclk + Tcapture_clk – Tsetup – Tuncertainty) –
( Tlaunch_clk + Tclk-q + Tcomb)
 Rearranging the eq:
 SS = (Tclk + Tcapture_clk – Tun – Tsu) – (Tlaunch_clk + Text + Tcomb_int)
Similarly Hold Eq: HS = AT – RT
HS = (Tlaunch + Text + Tcomb_int ) – (Tcapture + Tun +Thold).
REG – OUT path : SS = RT – AT
 (Tclk + Tcapture – Tsu – Tun ) –
Q
(Tlaunch + Tclk-q + Tcomb_int + Tcomb_ext)
 (Tclk + Tcapture – Tsu – Tcomb_ext – Tun ) –
(Tlaunch + Tclk-q + Tcomb_int)
Rearrange the eq:SS = Tclk +Tcapture – Text – Tun – ( Tlaunch + Tclk-q + Tcomb_int)
HS = Tlaunch + Tclk-q + Tcomb_int – ( Tcapture – Text + Tun )
O
U
T
D
 Multi-Cycle Path:
 A timing path that takes more than one clock cycle for data propagation.
 You need to specify the launch and capture clock edges in the SDC (Synopsys Design Constraints) file.
 Half-Cycle Path:
 A half cycle path is a timing path where data is propagated during both the rising and falling edges
of the clock (half a cycle each).
 Tools can automatically detect it, so you don’t need to specify the launch or capture edge in SDC.
 False Path:
 A path that exists physically but doesn’t carry any functional data (it’s inactive).
 False paths are excluded from timing analysis because they don’t impact the circuit’s performance.
Clock Skew : Clock skew is the difference in arrival time of the clock signal at two flip-flops in a design.
Tskew = Tlaunch – Tcapture.
• Here , Tlaunch = Arrival time of the clock at the launch flop.
• Tcapture = Arrival time of the clock at the capture flop.
Positive Skew : If the capture clock comes late then the launch clock.
•
it means Launch clock  Early & Capture clock  Late.
Tlaunch < Tcapture  good for setup violation.
Negative Skew : If capture clock comes early then the launch clock.
Tlaunch > Tcapture  Hold for setup violation.
Equation for setup:• Tsetup with Skew
DAT < DRT  Tlaunch_clk + Tclk-q + Tcomb < Tcapture_clk – Tsetup + Skew
• Thold with Skew
DAT > DRT  Tlaunch_clk + Tclk-q + Tcomb > Tcapture_clk + Thold + Skew
 Here, Positive skew helps setup timing by effectively giving more time for data propagation(DAT
takes more time).
 Negative Skew helps hold timing by reducing the risk of data arriving too early.
DAT & DRT ? Means
DRT  Data Required Time
• The latest time by which data must arrive at the capture flop.
DRT = Tcapture_clk – Tsetup
DAT  Data Arrival Time
• The actual time taken by the data to arrive at the capture flop.
DAT = Tlaunch_clk + Tclk-q + Tcomb
• Tlaunch_clk = clock arrival time of the launch flop.
• Tclk-q = clock to Q delay of the flop.
• Tcomb = Delay through the combo logic.
Zero Skew : When the capture clock & launch clock arrives at the same time is known as Zero Skew( ideally, it is
not possible).
Local Skew : Difference in arrival time of clock at two consecutive pins of flops.
 It can either positive or negative.
Global Skew: Difference between longest path delay & shortest path delay( min insertion delay & max insertion
delay).
Global skew = L2 –L1( L2  longest path & L1  shortest path)
Max insertion delay :• Delay of the clock signal takes to propagate to the farthest leaf cells in the design.
• Leaf cells  lowest level cell in the design(sequential cells).
Min insertion delay:• Delay of the clock signal takes to propagate to the nearest leaf cells in the design.
Useful Skew: If clock is skewed intentionally to resolve violations.
Benefits of Useful Skew
• Timing Optimization: By adjusting the clock arrival times, designers can meet setup and hold time.
• Load Balancing: Useful skew can help balance the load across different parts of the circuit, reducing
the maximum current draw and improving power distribution.
• Clock Tree Synthesis (CTS): During CTS, useful skew can be used to minimize clock tree depth and
reduce clock distribution network complexity.
• Reducing Critical Path Delays: By skewing the clock, critical path delays can be minimized,
improving overall circuit performance.
Slack : The difference between the required time & arrival time.
Slack = RT – AT
• Positive slack is good for setup.
• Negative slack is good for hold.
 For Setup timing equations:-
Setup  Data arrives too late at the capture flop.
Hold  Data arrives too early, so it overwriting
the previous data.
DRT > DAT ( slack = DRT – DAT >0 )
DRT = Tcapture_clk – Tsetup.
DAT = Tlaunch_clk + Tcomb + Tclk-q.
Tsetup_slack = DRT – DAT
 Tcapture_clk –Tsetup – ( Tlaunch_clk + Tcomb + Tclk-q)
 Tsetup_slack > 0  setup timing is met.
 For Hold timing equations:DRT < DAT (slack = DAT – DRT > 0)
DRT = Tcapture_clk + Thold.
Thold_slack = DAT – DRT > 0
 Tlaunch_clk + Tcomb + Tclk-q > Tcapture_clk + Thold
 Thold_slack > 0
Latency: The delay difference from the clock generation point to the clock endpoints.
On – Chip Clock source :- clock is generated inside the chip, typically by a PLL (Phase-Locked Loop)
or an oscillator.
Clock Definition point
PLL
• Here, PLL to Clock Definition point  SOURCE LATENCY.
• Clock Definition Point to Clk pin of Flop  NETWORK LATENCY.
Off – Chip Clock Source :- clock is generated outside the chip, such as by an external crystal oscillator
or a system clock module.
Clock port
PLL
• PLL is external source
On – Chip Clock Source
Off – Chip Clock Source
Clock source is inside the chip(PLL)
Outside the chip.
Internal Clock tree delay only.
Includes external + internal delays
Skew & Jitter controlled.
High skew & jitter due to external factor.
Better synchronization & Efficiency.
Higher latency may reduce the
performance
• Latency are 2 types.
1.
Source latency.
2.
Network latency.
Source latency :• The delay from clock generation point ( Clk source) to the Clk definition point.
• Ex:- PLL or External Clk Source.
• Command:- Set_clock_latency 1.9 –source ( i.e source latency = 1.9)
Network latency:• The delay from the Clk definition point to the Clk pin of flip-flop.
• Before CTS, these are estimated delay values.
• After CTS, Actual delay values come to picture
• Command:- Set_clock_latency 0.8
• Total Latency = Source latency + Network Latency.
• Source vs Network
Source Latency
Network Latency
Fixed & stays the same after CTS.
Used only before CTS as estimate.
Applied to both On-Chip & Off-Chip
Clock Sources.
After CTS, it is replaced by the actual
clock delay values.
• For Setup:- Total Clk latency impacts the calculation of DRT at the capture flop.
• For Hold:- Latency mismatches between the launch & capture Clk paths.
Equations:Tcomb ≤ Tclk – Tsetup + ( Capture Latency – Launch Latency)  Setup.
Tcomb > Thold + ( Capture Latency – Launch Latency)  Hold.
(Tclk is considered, because hold is within same clock edge or clock cycle).
Insertion Delay(ID):• Insertion delay is the clock latency, but it is after CTS.
• ID is physical delay & latency is virtual delay.
Clock Uncertainty:• Variations in clock arrival time due to multiple factors like as skew, jitter, OCV, cross talk & other
margins.
• It is a pessimism factor used in timing analysis to improve the design to meets timing requirements
even in the worst scenarios.
Types of uncertainty:
1.
Static clock uncertainty:-
•
Doesn’t vary or varies very slowly with time.
•
Slow or fixed variations like skew or process mismatches.
Ex:- Uneven wire delays in the clock network.
Sources:1.
Clock skew.
2.
OCV(On Chip Variation).
3.
Load variation.
Dynamic Clock Uncertainty:• Varies with time or Time varying issues like jitter or voltage changes.
Ex:- Small clock signal fluctuations caused by power noise.
Sources:1.
Jitter.
2.
Voltage drop.
3.
Temperature Variations.
Pre CTS uncertainty
Post CTS uncertainty
• Clock skew.
• Jitter.
• Margins for PVT.
• Clk jitter.
• Margins.
Usage of Uncertainty for setup & hold: Setup timing:
• Clock uncertainty reduces the clock period or available time of data to propagate.
Ex:- Clock uncertainty is 0.2ns  it means the usable clock period is decreased by 0.2 ns.

Effective clock period = Tclk – Uncertainty.
Command:- Set_clock_uncertainty –setup 0.2 [ get_clocks clk_name]
Reduces the clock period for setup timing analysis by 0.2 ns.
 Hold timing :
• Clock uncertainty is added as an additional margin that the design must met. (OR) Adds margin of
safety to prevent short path issues.
Ex:- Clock uncertainty is 0.05 ns,  it means the hold timing checks include these margin
Command:- Set_clock_uncertainty –hold 0.05 [ get_clocks clk_name]
Adds a margin of 0.05 ns for hold timing.
Equations for setup & hold :
 For setup  Tcomb +Tsetup ≤ Tclk – Tuncertainty
 For Hold  Tcomb ≥ Thold + Tuncertainty
 Why Clock Uncertainty is Important?
•It reserves some time in the clock period for unexpected variations.
•Ensures that setup and hold timing are met in worst-case conditions
 What is Margin?
 A margin is an extra buffer or safety time added in timing analysis to account for uncertainties and
variations in the design and environment.
 It ensures that the design is robust under worst-case conditions and operates reliably.
 Why Do We Need Margins?
•Timing analysis is based on simulations and estimations, but real-world conditions can introduce
unexpected variations.
•Margins help account for these differences, ensuring the design meets timing even in the worst scenarios.
SLEW(Transition):• A signal changes between two voltage levels like from 0 to 1 or 1 to 0.
• A fast change means  high slew rate.
• Slow change means  low slew rate.
 Transition is inversely proportional to slew rate.
Slew rate =
V/
T ( Rate of change of the voltage w.r.to time).

V  Change in voltage ( 0 to 1 or 1 to 0 ).

T  Time it takes for the signal to transition between those voltages.
 Faster Transition = Higher Slew rate = Low Transition time.
 Slower Transition = Lower Slew rate = High Transition time.
Rise Time: During rising edge, the time takes for the signal to Transition from 20 % to 80% of its maximum
value (VDD).
Rise time = T of 80% - T of 20%
Fall time: During Falling edge, The time takes for the signal to transition from 80% to 20% of its maximum
VDD.
Fall time = T of 20% - T of 80%
Problems :
Problem 1: Setup Timing with High Clock Uncertainty
1.
Scenario:
A design has a clock period of 2 ns. The setup uncertainty is 0.5 ns, and the combinational path delay
is 1.6 ns. The setup time of the flip-flop is 0.2 ns. Determine if the design meets setup time?
• Given that Tclk = 2ns.
• Tsetupuncertainty = 0.5ns.
• Tcomb = 1.6ns.
• Tsetup = 0.2ns.
For setup  Tcomb +Tsetup ≤ Tclk – Tuncertainty
1.6 + 0.2 ≤ 2 – 0.5
 1.8 ≤ 1.5 (fails setup timing because the available clock period after uncertainty (1.5 ns) is less
than the total delay 1.8ns).
Hold Timing with Skew-Induced Uncertainty
2.
Scenario:
The hold time of a flip-flop is 0.1 ns. The data path delay is 0.15 ns. The hold uncertainty due to clock
skew is 0.08 ns. Does the design meet hold timing?
Equation for Hold: Tcomb ≥ Thold + Tuncertainty
• Given Thold = 0.1ns.
• Tcomb = 0.15ns.
• Tuncertainty = 0.08ns.
0.15 ≥ 0.1 + 0.08
 0.15 ≱ 0.18 (fails hold timing because the data path delay (0.15 ns) is less than the required minimum
delay 0.18ns).
Multi-Clock Domain Setup with Jitter.
3.
Scenario:
Two flip-flops are in different clock domains with a 3 ns period each. The clock domains have a clock
skew of 0.3 ns and a jitter of 0.2 ns. The setup time is 0.3 ns, and the data path delay is 2.4 ns. Does it
meet timing?
Equation for Multi-Domain Setup:
• Pre CTS Clock uncertainty = Skew + jitter + Margin
• Post CTS Clock Uncertainty = Jitter + Margin
 Tcomb + Tsetup ≤ Tclk – Uncertainty
 Uncertainty = Skew + Jitter
Rearrange the eq = Tcomb + Tsetup ≤ Tclk – ( Skew + Jitter)
 2.4 + 0.3 ≤ 3− ( 0.3 + 0.2)
 2.7 ≤ 2.5 (fails setup timing due to excessive skew and jitter).
CTS Uncertainty Impact
4.
Scenario
Before clock tree synthesis (CTS), the setup uncertainty is modelled as 0.4 ns due to skew, jitter, and
margins. After CTS, skew is reduced to 0.1 ns, but jitter remains 0.2 ns. How does the uncertainty
change, and what is its impact on timing?
• Pre CTS Clock uncertainty = Skew + jitter + Margin .
• Post CTS Clock Uncertainty = Jitter + Margin.
• After CTS, the uncertainty reduces by 0.1 ns, increasing the available clock period.
Clock Jitter: Jitter refers short – term violation in the timing of a clock signal compared to its ideal timing.
Ex:- Imagine a clock pulse expected to arrive every 1ns.
• Due to jitter, the clock pulse might arrive slightly earlier or late (like 0.95ns or 1.05ns).
• This variations impacts the clock period, it causes synchronization issues in the circuits.
Source of jitter:
 Internal circuitry of PLL.
• Noise or imperfections in PLL circuits can introduce variations.
 Thermal noise in crystal oscillators.
• Heat can cause small fluctuations in the frequency of oscillators
 Transmitters & Receivers.
• Signal transmission paths can also introduce timing variations.
 When we are using clock signal, there are 2 phases in the design i.e
1. Ideal clock. 2. Propagated clock.
Ideal Clock:• In the first stage, during RTL design, Synthesis & placement  Clock is IDEAL.
• The ideal Clock has no distribution tree.
• It is directly connected at the same time to all flop clock pins.(so no delay or no violations)
Propagated Clock:• After CTS, the clock travels through a tree of buffers to reach the flip flop.
• Actual delays are introduced due to routing & buffers.
 Clock latency term using when the clock is in ideal mode.
 It is the delay that exists from the clock source to the clock pin of the flop.
 This delay is not real value  specified by the USER.
When comes to Propagated clock ,  After CTS
 Actual delay comes into the picture then it is called as insertion delay.
 Insertion Delay is a real & measured delay path through a tree of buffers.
How Jitter Affects the Design
 Setup Violations:
• If jitter reduces the effective clock period, data might not be ready in time.
 Hold Violations:
• If jitter causes the clock edge to arrive earlier, data might not have been held long enough.
 Signal Integrity Issues:
• Large jitter can disrupt timing relationships across flip-flops.
Types of Jitter (What They Are)
 Absolute Jitter → Signal arrives earlier or later than expected.
 Cycle-to-Cycle Jitter → One clock cycle length changes compared to the next.
 Periodic Jitter → Jitter happens at regular intervals due to interference.
 Random Jitter → Unpredictable, caused by thermal noise or power fluctuations.
 Deterministic Jitter → Caused by specific, known factors (like crosstalk or power noise).
Methods to Reduce Jitter (How to Fix It)
 Use low-jitter clock sources (for Absolute & Cycle-to-Cycle Jitter).
 Use jitter buffers (for Absolute & Periodic Jitter).
 Filter out power noise with capacitors (for Periodic & Random Jitter).
 Improve PCB design & shielding (for Deterministic Jitter).
Ex:-DDR RAM in a High-Speed Design
• Imagine designing a motherboard where DDR4 RAM communicates with the CPU.
•
If jitter is too high:  Data errors → System crashes.
 Slow performance
 By applying the above methods (good clock, clean power, short traces, differential pairs), we reduce
jitter and ensure fast, error-free communication!
Why the Clock Doesn't Always Arrive Exactly After One Clock Cycle?
or
Why does the clock not always arrive exactly after one clock period?
1. Insertion Delay and Skew
 Insertion Delay:
The time it takes for the clock signal to travel from the clock source to the flip-flop clock pin.
 Skew:
If the insertion delay to the launch clock (starting flip-flop) and the capture clock (destination flipflop) are different, the clock edges won't align.
• Example: If the capture clock arrives earlier than the launch clock, this difference is called
negative skew. If it arrives later, it is positive skew
2. Clock Jitter
 The clock period is not constant.
• Some cycles might be slightly longer or shorter due to variations in the clock source (like a PLL or
oscillator).
• This random fluctuation in clock period is called jitter.
• Effect: Jitter makes it hard to predict exactly when the next clock edge will occur.
3. On-Chip Variation (OCV)
 Different parts of the chip may behave differently due to changes in PVT ( process, voltage, or
temperature).
 This can make the clock slower or faster in some areas, increasing the difference in timing.
 Why MCMM (Multi-Corner Multi-Mode) is Important?
MCMM analysis ensures a chip works correctly under all conditions by considering:
1. Multi-Corner (PVT Variations)
• Process: Fabrication variations affect transistor performance.
• Voltage: Supply voltage fluctuations impact speed and power.
• Temperature: The chip must work from -40°C to 125°C (extreme conditions).
 Prevents failures due to process, voltage, and temperature variations.
2. Multi-Mode (Different Functional Scenarios)
• Functional Mode (normal operation)
• Test Mode (DFT scan & testing)
• Low-Power Mode (power-saving state)
 Why MCMM is NECESSARY?
 Ensures timing closure across all PVT conditions.
 Prevents setup & hold violations.
 Avoids chip failures in real-world applications.
 Improves yield, reliability, and silicon success.
 MCMM is Related to STA?
 STA checks timing across all MCMM scenarios to ensure the chip works under all conditions.
 Setup & Hold Timing Closure: Different corners and modes can affect timing margins, so STA ensures
no violations.
 Clock Skew & Uncertainty: STA considers worst-case delays across PVT variations to avoid timing
failures.
 Signoff Requirement: Modern chips must pass STA for all MCMM cases before tapeout.
 Why MCMM Essential in STA?
 Ensures chip works across all voltage, temperature, and process variations.
 Avoids failures in different operating conditions.
 Reduces ECOs (Engineering Change Orders) by catching violations early.
 Improves silicon yield and performance reliability.
 Without MCMM in STA, a chip might pass in one condition but fail in another!
Propagation delay : Propagation delay is the time taken for a signal to travel through the combinational logic (gates and
interconnects) between the launching flip-flop and the capturing flip-flop.
 This delay depends on:
• The logic complexity in the path.
• Interconnect delays (RC delays).
• PVT variations (Process, Voltage, Temperature).
Setup : Min time that the input (Data) must be stable before the clock edge ( Usually the Falling & Rising
edges, depending upon the design) in order to be correctly captured by the flip-flop.
 Data must be stable before the clock edge.
 If setup time violation occurs when the data input changes too close to the clock edge, it might
incorrect data capture.
Setup time = DRT ≥ DAT ( No setup violations)
Tclk ≥ Tsetup + Tclk-q + Tcomb
Hold : Min time that the input (Data) must remain stable after the clock edge so it ensures the correct
operation of flip-flop.
 Data must be stable after the clock edge.
 If hold time violation occurs when the new data arrives too early, it might corrupt the currently
captured value.
Hold time = DRT ≤ DAT ( No hold violations)
Thold ≤ Tcomb + Tclk-q
Launch and Capture:
 Launch Flip-Flop: Flip-flop where the data is sent out (launched).
 Capture Flip-Flop: Flip-flop where the data is received (captured).
 Launch Edge: Clock edge that triggers data launch.
 Capture Edge: Clock edge that triggers data capture.
 Select the correct equation for setup time requirement ?
Tc2q – clock to Q FF delay, Tcomb – combinational delay, Tsetup – Setup time, Tclk – Clock Period,
Tskew – Clock skew
 a) Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew
b) Tc2q + Tcomb + Tsetup > Tclk + Tskew
c) Tc2q + Tsetup ≤ Tclk + Tskew + Tcomb
d) None of the above.
Metastability : Metastability occurs when a flip-flop receives an input signal too close to the clock edge, causing it to enter
an unstable state. This can result in unpredictable behavior, leading to timing failures in a design.
 How to Prevent Metastability?
 Use Two-Stage Synchronizers – Add extra flip-flops to allow enough settling time.
 Increase Setup & Hold Time Margins – Ensure signals arrive well before the clock edge.
 Use Proper Clock Domain Crossing (CDC) Techniques – Prevent data corruption when transferring
signals between different clock domains.
Clock Domain Crossing (CDC): CDC happens when a signal moves from one clock domain to another with a different frequency or phase.
Problem:
 If not handled properly, CDC can cause data corruption or metastability, leading to design failures.
Solutions to CDC Issues:
 Two-Flip-Flop Synchronizer → Used for single-bit control signals like resets and enables.
 FIFO (First-In-First-Out Buffer) → Used for multi-bit data transfer between different clock domains.
 Handshake Protocols → Ensures safe data transfer using request/acknowledge signals.
 Gray Code Counters → Used in asynchronous FIFOs to avoid metastability in read/write pointers.
 During Placement Stage:
 Fixing Setup Violations (Data is too slow)
1.Timing Path Groups – Prioritize paths that need optimization.
2.Create Bounds – Restrict cell movement to improve timing.
3.Placement Optimization – Use high-effort placement to reduce delays.
4.Floorplan Changes – Adjust macro placement, spacing, and pin orientation.
After Placement Stage:
1.Increase Drive Strength – Use stronger gates to speed up data propagation.
2.Use Lower Vt Cells – Swap high-threshold cells with lower-threshold ones to reduce delay. ( LVT 
SVT & HVT)
3.Insert Buffers – Helps improve transition times and reduces wire delays.
4.Reduce Excess Buffers – Too many buffers can increase delay; optimize them.
5.Use Higher Metal Layers – Reduces wire resistance and delay.
6.Replace Buffers with Inverters – Improves signal transition time.
7.Play with Clock Skew – Intentionally delay the clock to help meet setup timing.
 Fixing Hold Violations (Data is too fast)
Use Higher Drive Strength Gates – Sometimes, stronger gates slow transitions by increasing
capacitance.
Use Higher Vt Cells – Slower threshold cells delay signal propagation.(HVT  LVT)
Insert or Remove Buffers – Adding buffers increases delay, while removing unnecessary buffers can
balance timing.
Use Higher Metal Layers – Helps optimize wire delay.
Increase Clock-to-Q Delay – Adjusting the launching flip-flop can slow down data arrival.
Clock push & pull  launch flop  pushing & capture flop  pulling.(here increasing &
decreasing the delays)
Crosstalk: Cross talk is unwanted interference between two neighbouring wires or nets in a circuit.
 It happens because of coupling capacitance between them.
 It can effect the functionality or timing.
AGGRESSOR
 A net can be VICTIM or AGGRESSOR.
 High Switching or Affecting signal AGGRESSOR.
 Experienced unwanted affects or Affected signal  VICTIM.
VICTIM
 Why Does Coupling Capacitance Cause Crosstalk?

Coupling capacitance (Cc) is the capacitance between two adjacent wires.
 When the signal (voltage) in one wire (aggressor) changes, it induces a voltage in the nearby wire
(victim) through this coupling capacitance.
 This results in:
• Crosstalk Noise or Glitch : Voltage spikes (glitches) on the victim wire.
• Crosstalk Delay : Delayed or accelerated signal transition on the victim wire.
Types of Crosstalk: Crosstalk Noise Or Glitch.
 Crosstalk Delay.
Crosstalk Noise or Glitch: It happens when the aggressor net switches, but the victim net remains constant.
 This causes a spike(glitch) in the victim net.
• Types of Glitches:1.
Rise Glitch  Victim is low(0) , Aggressor rises.
2.
Fall Glitch  Victim is high(1), Aggressor falls.
3.
Overshoot  Victim is high(1), Aggressor rises further.
4.
Undershoot  Victim is low(0), Aggressor falls further.
 Overshoot :- Signal voltage goes too HIGH, exceeding its expected max level(above VDD).
 Undershoot :- Signal voltage drops too LOW, below its expected min level(below VSS).
Crosstalk Delay: It happens when both Aggressor & Victim nets are switching.
 It can either slow down or speed up the victim net transition based on the relative switching
direction.
 There are 2 types of crosstalk delays.
1
Positive cross talk delay.
2
Negative cross talk delay.
Positive cross talk delay: Aggressor switches in the opposite direction of the victim  Victim slows down.
Negative cross talk delay: Aggressor switches in the same direction as the victim  Victim speeds up.
Effects of Crosstalk
1. On Noise: It creates unexpected signal spikes, disrupting functionality.
2. On Timing: It can cause data to arrive too early or too late, affecting setup and hold timing checks.
Impacts on Timing Analysis:Crosstalk affects Setup & Hold timing:
1. Data path Crosstalk:
• Same Direction (Negative Crosstalk):
 Victim transition  Faster, Good for setup & Bad for Hold.
• Opposite Direction(Positive Crosstalk):
 Victim transition  Slower, Bad for setup & Good for Hold.
2.
Clock path Crosstalk:
• Same Direction:
 Victim clock  Faster, Bad for Setup & Good for Hold.
• Opposite Direction:
 Victim clock is  Slower, Good for Setup & Bad for Hold.
Reduce the Crosstalk:
 Increase Wire Spacing(NDR rules):
 Reduces coupling capacitance between aggressor and victim nets.
 Use Higher Metal Layers:
 Higher layers have wider wires and lower coupling.
 Buffer Insertion:
 Splits long nets to minimize crosstalk.
 Shielding:
 Place power (VDD) or ground (VSS) lines between critical signals to absorb noise.
 Adjust Drive Strength:
 Increase the victim net's drive strength or reduce the aggressor net's drive strength.
 Use Multiple Vias:
 Reduces resistance and RC delay, minimizing interference
PBA & GBA
 PBA  Path Based Analysis.
 GBA  Graph Based Analysis.
Path Based Analysis(PBA) :-
 Pessimism = Worst-case assumptions (extra safety margin).
 GBA: Introduces pessimism to ensure no timing violations
are overlooked.
 PBA: Removes pessimism for more accurate, realistic timing
in critical paths
 Analyses individual paths one by one.
 Measures signal delay on each path & checks if it meets the Required Time(RT).
 High Accurate, But Slower because it checks every possible path.
Graph Based Analysis: Analyses the entire design as Graph.
Calculation:
 Arrival Time (AT): When the signal arrives.
 Required Arrival Time (RAT): When the signal is needed.
 Slack: RAT - AT (to check timing margin).
 Faster, but less accurate because it doesn’t examine every path in detail.
Do We Prefer PBA in Real-Time STA?
 Yes, PBA (Path-Based STA) is preferred for sign-off in real-time chip design.
 But GBA (Graph-Based STA) is preferred for faster timing closure during early stages.
 Real-Time Industry Ex:
• Scenario:
1. Tape-Out of a Processor Chip (Intel, AMD, Qualcomm, etc.)
 During initial timing closure (Pre-layout STA):
 Engineers run GBA because it's fast and helps find timing violations quickly.
 If violations exist, they fix them with margin to be safe (even if pessimistic).
 Before sign-off (Final STA using Primetime STA, Cadence Tempus, or ICC2):
 Engineers run PBA to remove unnecessary pessimism and find actual delays.
 If GBA showed a violation, PBA might clear it, reducing unnecessary fixes.
 Final Validation: (PBA is final decision – maker before the design is sent for fabrication)
 Before tape-out, only PBA results are considered to ensure accuracy.
 This prevents false timing violations and unnecessary design modifications.
 Multi-cut Vias : It is like adding extra support to make connections more Reliability & Durable.
 After the layout design, when ever possible single via replaced with multi-cut vias to improve better
performance & Yield..
 Handle more current & improve functionality on wide metal.
 When to Use Multi-Cut Vias?
 High-current paths (Power & Ground Nets).
 Critical signal paths (Clock & High-speed data signals).
 Advanced nodes (e.g., 7nm, 5nm, 3nm) where single vias are unreliable.
 Chip corners & high-stress areas where via failure risk is higher.
 When NOT to Use Multi-Cut Vias?
 Non-critical paths where single vias are sufficient.
 Tight routing areas where space is limited
 Redundant Vias: It is like safety backup to ensure the connections stay strong & chip work reliability.
• Improve yield.
• Lower resistance  making signal faster.
• Avoid timing issues from Partial failures.
 Why Use Redundant Vias?
 Prevents Failure  If the main via fails, the extra one keeps the connection.
 Improves Reliability  Reduces the chance of open circuits.
 Better for Manufacturing  Helps avoid defects caused by process variations.
 When to Use Redundant Vias?
 Critical signal paths (Clock, Power, Ground).
 Areas with manufacturing variation risks.
 Smaller technology nodes (7nm, 5nm, 3nm) where via failures are more common.
Multi-cut Vias (Vs) Redundant vias ?
Multi-cut Vias
Redundant vias
Uses multiple vias in one place for a stronger
connection
Adds extra vias next to the main via as a backup
Reduces resistance & improves performance
Prevents via failure and improves reliability
High-current paths (power, ground, clock signals)
Areas where single vias might fail due to defects
Load spread across all vias
If the main via fails, backup via takes over
 Imagine you are designing a mobile processor chip (like in smartphones)
 Why Use Redundant Vias
 If one via fails, the extra via keeps the connection working.
 Prevents chip failure and improves reliability.
 Used in modern processors (5nm, 3nm) for better performance.
 In a smartphone chip, redundant vias help prevent power loss and improve battery efficiency.
 PVT (Process, Voltage & Temperature): A chip should work in all conditions—from freezing cold (-40°C ) to extreme heat.
 To ensure this, we simulate the chip under different PVT corners to check timing.
1.
Process Variation (P) – Changes During Manufacturing
 Transistor properties change due to manufacturing imperfections.
Ex: Some chips on a wafer may be fast, some slow due to variations in materials.
 Affects delay: Slow process → Higher delay.
Fast process → Lower delay.
2.
Voltage Variation(V) – Power Supply Instability
 Voltage is not always constant (e.g., 1V can fluctuate to 1.1V or 0.9V).
Causes:
 IR drop: Resistance in power lines reduces voltage.
 Supply noise: Inductance effects cause voltage spikes.
Affects delay: Higher voltage → Faster circuit (lower delay).
Lower voltage → Slower circuit (higher delay).
3.
Temperature Variation (T) – Heat Effects on Chip
 High temperature → Slower transistors (higher delay).
 Low temperature → Faster transistors (lower delay).
 BUT in very small transistors (<65nm), delay increases at lower temperatures, This is called
Temperature Inversion.
 Worst-Case PVT Corners in Timing Analysis:Check
Worst Case Condition
Why?
Setup Timing
Slow Process (SS),
Low Voltage,
& High Temperature.
Maximizes delay (data may arrive
too late)
Hold Timing
Fast Process (FF),
High Voltage,
&Low Temperature.
Minimizes delay (data may arrive
too early)
 PVT Impact on Timing: Cell Delay vs. Net Delay
 In chip design, timing analysis is important to ensure the circuit works at the desired speed.
 Timing is affected by cell delay and net delay, both of which change due to PVT variations.
•
Cell Delay (Gate Delay)
 What is it?
 The time taken by a logic cell (e.g., AND, OR, Flip-Flop) to process an input and produce an output.
 It depends on transistor switching speed inside the cell.
•
PVT Impact:
 Process Variation: Slower transistors increase cell delay.
 Voltage Drop: Lower voltage reduces transistor speed, increasing cell delay.
 High Temperature: Slows down transistors, increasing cell delay (except in sub-65nm nodes due to
temperature inversion).
Ex:
 A NAND gate may normally take 100ps to switch, but under slow process, low voltage, and high
temperature, it may take 120ps.
2.
Net Delay (Wire Delay / Interconnect Delay)
What is it?
 The time taken for a signal to travel through the wires (interconnects) connecting different cells.
 It depends on wire resistance (R) and capacitance (C) → RC Delay.
PVT Impact:
 Process Variation: Metal width variations change wire resistance (R), increasing RC delay.
 Voltage: Has minimal impact on net delay.
 Temperature:
 High temperature increases wire resistance, increasing net delay.
 Low temperature reduces wire resistance, decreasing net delay.
Ex:
 A long interconnect between two flip-flops might have a net delay of 50ps, but under high
temperature, resistance increases, making it 60ps.
3
Timing Paths & PVT Corners
 A timing path consists of:
Launch Flop → Combinational Logic (Cell Delay) → Interconnect (Net Delay) → Capture Flop
 Setup Timing (Data must arrive before clock edge):
 Worst case: Slow Process, Low Voltage, High Temperature (increases delay).
 Affected by cell delay (major impact) + net delay.
 Hold Timing (Data must not arrive too early):
 Worst case: Fast Process, High Voltage, Low Temperature (reduces delay).
 Affected by cell delay (major impact) + net delay.
 Cell delay is mainly affected by transistor behavior (PVT variations).
 Net delay is mainly affected by RC properties of wires.
 Both delays impact setup and hold timing, which must be checked at worst PVT corners.
Ex: Fixing Setup and Hold Violations in a Real Design
Let's consider a timing path in a digital circuit:
 Launch Flip-Flop (FF1) → Logic (Gates + Wires) → Capture Flip-Flop (FF2)
Timing analysis shows:
 Clock Period: 1ns (1GHz frequency)
 Setup Time Violation: Data arrives at 1.05ns (> 1ns)
 Hold Time Violation: Data arrives at 0.05ns (< Hold time)
 Fixing Setup Violation: Data arrive too Late
 Why it happens?
1. Slow process  Transistors switch slower.
2. Long net delay  Wire resistance / capacitance too high.
3. High Temperature  Increase delay of logic gates.
 Fixing Steps: Use stronger cells ( Reduce logic delay(Drive strength Increases)):
 Like replace AND2_X2 ( weak , slower)  AND2_X4 ( Faster, Stronger).
 Insert buffers (Reduce net delay):
 Insert a buffer to break a long wire into two shorter ones.
 Clock skewing (Borrow time for data arrival):
 Delay the clock at FF2 slightly, giving more time for data to arrive.
 New Data Arrival Time: 0.95ns (Now it meets the 1ns requirement).
2.
Fixing Hold Violation (Data Arrives Too Early)
Why It Happens?
Fast process: Transistors switch too quickly.
Short net delay: Signal reaches too soon.
Low temperature: Reduces wire resistance, speeding up data.
Fixing Steps:
 Use weaker cells (Increase logic delay or drive strength decreases):
 Replace INV_X4 → INV_X1 (slows down switching).
 Insert delay buffers (Increase net delay):
 Add extra buffer(s) in the data path.
 Clock skewing (Reduce available time for data to arrive early):
 Speed up the clock at FF2 slightly to reduce extra time.
 New Data Arrival Time: 0.10ns (Now it meets the hold requirement).
 RC Variations:
 What is RC Variation?
 RC variation refers to changes in resistance (R) and capacitance (C) due to fabrication process
deviations.
 It impacts interconnect delay, affecting setup and hold timing.
 Worst-Case Corners for Setup & Hold
Timing Check
Process
Voltage
Temperature
Impact
Setup Violation
Slow
Low
High
Data too slow (Max delay)
Hold Violation
Fast
High
Low
Data too fast (Min delay)
 Fixes for Setup & Hold Violations
 Fix Setup Violation (Data Too Slow)
 Increase drive strength (X2 → X4 → X8).
 Use higher metal layers (low resistance).
 Add repeaters (buffers) to reduce delay.
 Fix Hold Violation (Data Too Fast)
 Add delay buffers to slow data.
 Route on lower metal layers (higher resistance).
 Increase wire length (detour routing) to add delay.
 Critical corners for Setup & Hold
Check
Process (P)
Voltage (V)
Temperature (T)
Why?
Setup (Worst Case)
Slow (SS)
Min (Vmin)
Max T (or Min T for
temp inversion)
Ensures max delay
(slowest path)
Hold (Worst Case)
Fast (FF)
Max (Vmax)
Min T
Ensures min delay
(fastest path)
Power Analysis
Typical (TT) Nominal (Vnom) Room Temp (~25°C)
Used for power
estimation
 MC (Multi-Corner): Ensures the chip works across all PVT conditions.
Corner
Mode
Timing Check
SS, Min V, Max T
Functional Mode
Worst-case setup
FF, Max V, Min T
Functional Mode
Worst-case hold
SS, Min V, Max T
Scan Mode
Worst-case scan setup
FF, Max V, Min T
Scan Mode
Worst-case scan hold
TT, Nom V, Room Temp
Low-Power Mode
Power analysis
 Impact of RC Corners on Setup & Hold
Setup Timing (Data Too Slow):
 Worst RC (High R, High C) is the worst case for setup.
 If resistance and capacitance increase, wire delay increases, causing setup violations.
 Fix: Increase drive strength, use higher metal layers, add repeaters.
Hold Timing (Data Too Fast):
 Best RC (Low R, Low C) is the worst case for hold.
 If resistance and capacitance decrease, wire delay reduces, causing hold violations.
 Fix: Insert delay buffers, reroute signals on lower metal layers.
ON – CHIP VARIATION
On – Chip Variations(OCV): OCV refers to small, unpredictable differences in transistor properties within the same chip
due to:
 Manufacturing process variations  tiny differences in transistor size, doping, etc.
 Voltage fluctuations  power supply variations across the chip.
 Temperature variations  some areas heat up more than others.
Since modern chips contain billions of transistors, these small differences add up and affect chip timing,
performance, and power efficiency.
 Scenario: Designing a Processor Clock Path
 Imagine you're designing a processor where a signal travels from one logic gate to another within 1
nanosecond (ns).
However, due to OCV effects, different parts of the chip may have slight timing variations:
Gate A takes 0.95 ns instead of 1 ns (faster due to variation).
Gate B takes 1.05 ns instead of 1 ns (slower due to variation).
A
B
Result:
 The faster path may cause a HOLD timing violation (Data Arrives too early).
 The slower path may cause a SETUP timing violation (Data Arrives too late).
 This could lead to chip failures or reduced performance.
Reduce Techniques OCV impact:
 AOCV (Advanced On – Chip Variations).
 Applies different timing margins based on Path Depth.( Count of gates or Stages)
 POCV ( Parametric On – Chip Variations).
 Uses probability models instead of fixed margins for better accuracy.
 Modern chips are 7nm, 5nm  using POCV.
 Clock Skew Compensation  Adjusts the clock arrival time to balance variations.
 Adaptative Voltage Scaling (AVS)  Dynamically adjusts power to stabilize Performance.
 OCV is an unavoidable issue in modern chips, but careful design helps manage its effects.
 Ignoring OCV can lead to chip failures, performance drops, or excessive power consumption.
 Using techniques like AOCV and POCV improves chip reliability and efficiency.
• There are 2 types of variations
1. Global Variation.
2. Local Variation.
Global Variation:- ( Inter –Die Variation / Chip – to – Chip )
 Variations that effect the entire chip uniformly.
• Causes:
 Differences in manufacturing across different chips (DIE – to – DIE variations).
 All transistors on a chip experience similar changes in Process parameters.
EX: Two Chips from the same wafer may have different threshold voltages due to global
manufacturing variations.
 So One chip might be  faster than another chip because of Global doping Concentration
differences.
Local Variation (Intra-Die Variation / Within the Same Chip)
 Variations that occur Within the same chip, affecting different parts differently.
• Causes: Random fluctuations during fabrication, voltage drops, and Localized temperature changes.
• Effect: Some transistors or circuit paths becomes faster or slower than others within the same chip.
Ex: Transistors in one corner of the chip may have a slightly different threshold voltage than those in the
center.
 Some regions of a processor core may run hotter, affecting performance differently across the chip.
Global vs. Local Variations (Inter vs. Intra-Die)
Type
Scope
Cause
Effect
Global Variation( Inter –
Die )
Chip – to – Chip
Wafer –Level
Manufacturing
differences.
All transistors on a chip
behave similarly but
differ from another
chip.
Local Variation ( Intra –
Die)
Within the same chip.
Random fluctuations,
voltage drops, localized
heating.
Different regions or
transistors behave
differently within the
same chip.
AOCV – Advanced On – Chip Variations:
 AOCV is an improved version of traditional OCV (fixed derates) where depends on the path depth(
no. of logic gates).
 These method applies different derates based on how deep the logic path.
 Longer paths tends to have a more averaged variation (less variations)  because more no. of
gates are present in that path.
 Shortest path  Higher variations.
 So if we analysing Shortest path , it gets higher derates.( more variations)
 Similarly Longest path , it gets lower derates. ( less variations)
Ex: Shortest path  3 stages  higher derates ( more pessimism).
 Longest path  10 stages  Lower derates ( less pessimism).
 Problem: It overestimates delays for short paths and underestimates them for long paths.
Advantages & Disadvantages of AOCV
Advantages
Disadvantages
More accurate than OCV (reduces unnecessary
delays).
Still some pessimism (not fully optimized like
POCV).
Helps increase chip speed (higher frequency).
More complex to implement than OCV.
Saves power by reducing extra buffers.
Not as accurate as POCV for advanced nodes.
Faster timing closure than OCV.
Needs extra characterization effort.
Better for advanced technologies (7nm, 5nm, 3nm).
Not useful for older nodes (28nm, 16nm).
POCV – Parametric On – Chip Variations
 POCV is a more advanced version of OCV that uses statistical methods to model delay variations.
 Instead of applying fixed derates, it uses Gaussian (statistical) distributions to model delays.
 It considers the correlation between cells, making it more accurate.
 Each cells delay is modeled as a mean delay + standard deviation
 The final delay is calculated using statistical summation  Reducing pessimism.
Ex: Shortest path  3 stages  Higher variation ( Wider distribution).
 Longest path  10 stages  Lower variation ( Narrow distribution).
 Why use POCV?
 It provides the most accurate timing analysis by using statistical models, reducing pessimism and
improving performance.
 Why not always use POCV?
 It is complex, expensive, and harder to debug, so it’s mainly needed for advanced nodes like 7nm,
5nm, 3nm."
Advantages & Disadvantages of POCV
Advantages
Disadvantages
More Accurate Timing – Uses statistical models
instead of fixed margins.
Complex Implementation – Requires more
analysis than OCV/AOCV.
Reduces Pessimism – Avoids unnecessary delay
margins.
More Expensive – Needs advanced EDA tools.
Optimizes Performance – Enables higher clock
speeds by reducing over-design.
Difficult to Debug – Statistical variations make
debugging harder.
Lower Power Consumption – Fewer extra buffers
reduce power usage.
Not Always Needed – For older nodes (28nm,
16nm), OCV/AOCV may be enough.
Improves Chip Yield – More realistic timing
ensures better manufacturing success.
Requires Advanced Characterization – Needs
detailed process variation models.
Best for Advanced Nodes – Ideal for 7nm, 5nm,
3nm designs.
EDA Tool Support Needed – Not all tools fully
support POCV.
DERATES
 Derates  method of OCV.
 Adjust delays to model variations.
 Traditional OCV uses Fixed derates.
 AOCV improves it with Table – Based derates.
 POCV is the most accurate, Using Statistical derates.
 Derates are Multipliers applied to cell & interconnect delays to account variations like PVT.
Ex:- Imagine a logic gate has delay  1 ns (normal condition).
 Due to variations, it delay might increases or decreases.
 Instead of re – characterizing every variation, we use a Derate Factor to adjust the delay.
Types:1.
Fixed Derates ( Traditional OCV).
2.
AOCV  Table based Derates.
3.
POCV – Statistical Derates.
Fixed Derates: A constant multiplier is used for all paths.
Ex: 1.1 derate is applied, a 1ns delay, So it becomes 1 * 1.1 = 1.1 ns.
 Too pessimistic because it assumes the Worst – Case.
AOCV Derates: Uses predefined Look up tables to apply different derates, based upon Path depth.
 Longer path = no. of logic more = Higher derates.
POCV Derates: Uses probability distributions instead of Fixed values.
 Provide the most realistic variations & with less pessimism.
 Most accurate , especially for advanced nodes (7nm, 5nm..)
Advantages of Fixed OCV , AOCV & POCV derates
Method
Disadvantages
Advantages
 Simple to implement.
 Conservative (safe for worst –
Traditional OCV (Fixed Derate)
case design).
 Over pessimistic( leads to
unnecessary margins).
 Reduces chip performance &
increases power consumption.
AOCV
 More accurate than OCV (
Reduces pessimism for Long
paths).
 Easy to integrate into existing
timing tools.
 Still uses predefined margins(not
fully statistical).
 Less effective for ultra – deep
submicron ( %nm, 3nm) nodes.
POCV
 Most accurate ( uses statistical
models).
 Reduces unnecessary margins,
improving speed & power
efficiency.
 More complex to implement (
requires statistical timing
analysis).
 High cost in signoff
 For older nodes (45nm, 28nm, etc.)  OCV or AOCV is sufficient.
 For advanced nodes (7nm, 5nm, 3nm) → POCV is preferred due to higher accuracy and better performance
optimization.
 Derates related Setup & Hold:
 In OCV, The manufacturing process introduces variations, Where some cells may be Faster/Slower
than excepted.
 To account for these variation & prevent pessimism in timing analysis  DERATES are introduced.
 Multipliers applied to cell delays & net delays in timing checks.
Setup Analysis:- DRT > DAT.
 This checks if data arrives late and causes a problem when the clock signal is expected.
 So launch clock path gets a LATE DERATES( Increased cell delay)  it means, a little longer.
 Capture clock path gets an EARLY DERATES( Decreased cell delay)  Take less time.
Hold Analysis:- DRT < DAT.
 This checks if the data arrives too early, which can cause a problem by changing before the clock
signal is ready.
 Here, Launch clock path gets an EARLY DERATES (faster)  Arrives quickly.
 Capture clock path gets a LATE DERATES (slower)  Arrives slow.
For Setup
Late path
D
D
FF1
Clk
FF2
Clk
Early path
 Problem of Common Path Delay:
 If both launch and capture paths share a part of the clock tree (common path), applying different
derates (early and late) to the same path can create unrealistic delays.
 This results in extra pessimism, which can be removed using Clock Re-convergence Pessimism
Removal (CRPR) or Common Path Pessimism Removal (CPPR).
 set_timing_derate -max -early -net_delay 0.9  Apply early derate to capture path
 set_timing_derate -max -late -net_delay 1.1 Apply late derate to launch path
Derates in OCV methods:
Method
Setup Derate
Hold Derate
Accuracy
Traditional OCV
Fixed (e.g., 1.1 for setup)
Fixed (e.g., 0.9 for hold)
High pessimism
AOCV
Variable (depends on path depth) Variable (depends on path depth)
Less pessimism
POCV
Statistical
Most accurate
Statistical
 Setup derate increases data delay, making setup violations more likely.
 Hold derate decreases clock delay, making hold violations more likely.
 AOCV & POCV refine derates to reduce pessimism and improve timing closure.
 Common Path Pessimism:
 When analyzing a path from FF1 to FF2, the launch clock and capture clock share a portion of the
clock tree (B1, B2) and then diverge.
 The common path delays (shared by both clocks) are multiplied by different derates (early and late).
 This results in different delays for the same cells depending on the clock path. The same cell can't have
both maximum and minimum delay at the same time, leading to additional pessimism.
 To remove this pessimism, Clock Re-convergence Pessimism Removal (CRPR) or Common Path
Pessimism Removal (CPPR) is used
Note: CRPR removes pessimism by adjusting the delay in the common clock path
 In setup analysis, the CRPR value is added to the required time.
Setup = DRT + CRPR > DAT.
 In hold analysis, the CRPR value is subtracted from the required time.
Hold = DRT – CRPR > DAT.
 This helps to reduce pessimism and make the analysis more accurate.
ENGINEERING
CHANGE ORDER
(ECO)
Engineering Change Order (ECO):
 ECOs (Engineering Change Orders) are modifications made to the design after it has been
synthesized, placed, or routed.
 They are targeted changes that fix issues without requiring a full redesign, making them a timeefficient solution in VLSI design.
Example:
 Suppose you're working on a chip that has passed the synthesis stage, but timing violations are
detected.
 Instead of rerunning the entire design process, you apply a Timing ECO to adjust specific paths and
ensure the timing constraints are met.
Why is ECO Needed?
•Bug Fixes – Correct functional errors in the design.
•Timing Violations – Ensure the design meets timing constraints.
•Power Optimization – Reduce power consumption.
•Feature Updates – Add or modify functionality at a late stage.
 Types of ECOs
 Functional ECO: Fixing logic issues (e.g., a bug in the design).
 Timing ECO: Solving timing violations (e.g., delays in signal propagation).
 Power ECO: Reducing power consumption (e.g., clock gating or low-power cells).
 Metal ECO: Adjusting the physical routing (e.g., fixing shorts or congestion).
 Post-silicon ECO: Changes after the chip has been fabricated (e.g., bugs discovered during testing).
 Benefits of ECO
 Saves time and cost by avoiding full redesign.
 Reduces risk and speeds up chip production.
 Ensures last-minute fixes without starting from scratch.
ECO Implementation Process
 Identify the issue (functional, timing, power, etc.).
 Modify the netlist (add/remove logic gates, buffers, or changes in wiring).
 Verify the changes using simulations and formal verification.
 Update the physical design (layout modifications).
 Perform final checks (timing, power, DRC, LVS).
Where ECOs Can Be Applied:
 RTL (Register Transfer Level) Design
 ECOs applied here often involve functional changes (fixing bugs in logic) or
adjusting timing at the RTL level.
 Synthesis
 After synthesis, timing ECOs can be applied if there are timing violations in the
gate-level netlist.
 Floor planning
 Here, power ECOs or timing ECOs can be applied to optimize the power usage or adjust placements
for better performance.
 Placement
 Timing ECOs might be applied to move gates to improve signal path delays.
 Routing
 Metal ECOs can be applied at this stage to fix routing issues like short circuits or congestion, or
even to optimize the routing layers for better performance or lower power.
 Post-routing (Layout Verification)
 Timing and Power ECOs can be applied here to fine-tune the design before signoff and ensure the
final layout meets timing and power requirements.
 Post-silicon (After Fabrication)
 If any issues are found during the testing of the fabricated chip, a Post-silicon ECO is applied to fix
any problems in the physical design or logic.
Note:
 RTL → Functional ECO.
 Synthesis → Timing ECO, Power ECO.
 Floor planning → Timing ECO, Power ECO.
 Placement → Timing ECO.
 Routing → Metal ECO.
 CTS (Clock Tree Synthesis) → Timing ECO (if clock issues like skew are found).
 Post-silicon → Post-silicon ECO (for final fixes)
 Why ECOs in CTS are Less Common?
 CTS tools are designed to optimize the clock network efficiently, and in most cases, no additional
ECOs are required.
 If issues like clock skew or timing violations persist after the CTS stage, a Timing ECO might be
used, but this is less common compared to other stages like placement or routing.
 What are the challenges faced while applying ECO?
 ECO implementation can be challenging because it requires careful verification to ensure that
changes don’t introduce new issues, especially in complex designs.
 Verification Complexity: Ensuring that the ECO doesn’t break other parts of the design.
 Timing and Cost: Delays in applying ECOs can increase costs or delay product release.
 Impact on design: Changes need to be made without affecting the overall functionality of the chip.
 Can ECO be applied after the chip has been fabricated?
 Yes, Post-silicon ECO can be applied after the chip has been manufactured to fix issues discovered
during testing.
 However, post-silicon ECO is more expensive and time-consuming compared to pre-silicon fixes.
 Post-silicon ECO: Changes are made to the chip after fabrication if issues are found during testing.
 Common for critical bugs that are difficult to catch earlier.