Received 22 February 2020; revised 1 June 2020; accepted 24 June 2020. Date of publication 29 June 2020; date of current version 26 August 2020.
This article was recommended by Guest Editor S. Mirabbasi.
Digital Object Identifier 10.1109/OJCAS.2020.3005546
A Nano-Watt Dual-Output Subthreshold CMOS
Voltage Reference
JIE LIN
1,2,4 , LIDAN WANG
2,3 , YAN LU
AND CHENCHANG ZHAN
1,4 (Senior Member, IEEE),
2,3 (Senior Member, IEEE)
1 State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China
2 School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China
3 Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Beijing, China
4 Department of ECE, FST, University of Macau, Macau, China
CORRESPONDING AUTHORS: Y. LU AND C. ZHAN (e-mail: yanlu@um.edu.mo; zhancc@sustech.edu.cn)
This work was supported in part by Macao Science and Technology Development Fund (FDCT) SLK Fund, and in part by SZSTI under Grant
JCYJ20170817112233337 and Grant KQJSCX20180319114406851.
ABSTRACT A dual-output CMOS voltage reference is presented for ultra-low power applications that
require two or more different voltage references. The VREF1 is designed by employing the VTH difference
between two devices to compensate the temperature coefficient (TC) of the thermal voltage. The VREF2
is generated by feeding a current mirrored from the first reference voltage’s supply current into a diodeconnected-transistor load. In such a way, two different voltage references can be generated in one compact
and simple design to reduce the devices and chip area significantly, compared to two separate voltage
references in a conventional design. Fabricated in a 0.18-µm CMOS process, the proposed CMOS voltage
reference can provide two references of 331.8 and 660.3 mV with variation coefficients of 0.53% and
0.42%, respectively. The average TCs of VREF1 and VREF2 for a temperature range of −40 to 125◦ C are
measured as 41.7 and 24.5 ppm/◦ C, respectively. The line sensitivity (LS) of VREF1 is 0.0505 %/V with
0.6-1.8 V supply, and the LS of VREF2 is 0.114 %/V with 0.8-1.8 V supply. The measured results show
a competitive power supply ripple rejection, and the power consumption is only 4.12 nW with 0.8-V
minimum supply at 25◦ C, while the active area is 0.0108 mm2 .
INDEX TERMS Dual-output, CMOS voltage reference, subthreshold, ultra-low power.
I. INTRODUCTION
T
HE INTERNET-OF-THINGS (IoT) has open
a plethora of new applications like smart home,
smart city, and intelligent manufacturing, which change
the way people think and work, and make our life easier.
The power consumption is the main challenge of IoT
sensors in these applications. Therefore, all blocks in IoT
sensors should work with ultra-low power, especially for
the voltage reference block which should be turned-on
all the time. These IoT systems often include data acquisition and conversion modules, which require two or
more different voltage references. Most of the voltage
reference modules like Bandgap Reference (BGR) and
CMOS Voltage Reference (CVR) have only single-output
voltage reference independent of Process, supply Voltage
and Temperature (PVT) variations. Conventional BGR
generates a near temperature insensitive reference of about
1.2V [1], [2], which requires a high supply voltage and
power consumption. Compared to BGR, CVR working
in subthreshold region can provide a hundreds-of-mV
reference under a low voltage supply and consume only
sub-hundred-nanowatt power, which is more suitable for
IoT system. A 218-mV CVR in [3] employs an amplifier
and two resistors to improve the temperature insensitivity
and achieves an average temperature coefficient (TC) of
23.5 ppm/◦ C with the power consumption of 30.5 nW at
minimum supply voltage of 0.6 V. A 9.6-nW CVR proposed
in [4] could provide a reference of 210 mV and achieve
This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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a line sensitivity (LS) of 0.027%, and it can work with
a minimum supply of 0.4-V. However, the TC of 82 ppm/◦ C
is not optimized. The CVR proposed in [5] could generate
a reference of 756 mV with 23-nW power consumption.
But the VREF variation (σ/µ = 0.95%) and LS (0.524 %/V)
could be further improved. In [7], a nano-power voltage
reference is generated by feeding a dedicated current into
a diode-connected-transistor load, and 8 extra transistors are
required for the current generation. A192-pW voltage reference with a hybrid structure of BGR and CVR achieves the
benefits of both BGR and CVR, but it requires a minimum
supply voltage of 1 V to produce a reference voltage of
692.6 mV [11]. All these voltage reference designs are
good at low power consumptions due to the subthreshold
operation. However, to provide multiple voltage references
for IoT sensors, several single-output CVRs should be
combined, and the total power consumption is summed up
to be large and even exceeds 100 nW, considering that
a resistor divider cannot accomplish the goal with a small
chip area.
In this paper, a dual-output CVR is proposed for ultralow power multiple-voltage-reference applications. The first
reference is designed by employing the VTH difference
between the 1.8-V and the 3.3-V NMOS to generate the
complementary-to-absolute-temperature (CTAT) voltage that
compensates the positive TC of the thermal voltage. The second reference is generated by feeding a dedicated current that
is mirrored from the first reference voltage’s supply current
into a diode-connected-transistor load. In such a way, two
different reference voltages can be generated in one compact
and simple design. Compared to two separate voltage references that would otherwise be used in a conventional design,
the proposed dual-output CVR could reduce the device number and chip area significantly. To achieve an ultra-low power
consumption, the amplifiers and resistors are avoided, and
all the transistors work in subthreshold region. Compared to
the single-output CVR, the proposed CVR can provide two
different voltage references while the power consumption of
4.12 nW is at the same level as, or even lower than some
single-output CVRs.
This paper is organized as below. Section II presents
the operation principle and design details of the proposed
dual-output voltage reference. The measured results of the
proposed design are shown in Section III, and the conclusions
are drawn in Section V.
II. PROPOSED DUAL-OUTPUT CVR DESIGN
The topology of the proposed subthreshold dual-output CVR
is shown in Fig. 1. Transistors M1∼M3 and M4∼M5 are
the 1.8-V standard PMOS and NMOS devices in this process, respectively. M6 and M7 are the 3.3-V standard NMOS
devices. CO1 and CO2 are the output capacitors of VREF1 and
VREF2 , respectively. To achieve an ultra-low power consumption, a self-biased technology in [6] is adopted in this design.
amplifiers and resistors are avoided, and all the transistors
work in subthreshold region.
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FIGURE 1. Schematic of the proposed dual-output CVR (start-up circuit not shown).
A. PRINCIPLE OF THE FIRST REFERENCE
The I-V characteristics of an NMOS transistor operating in
subthreshold region is given by
VDS
VGS − VTH
1 − exp −
, (1)
ID = I0 K exp
mVT
VT
where K is the aspect ratio of the transistor (i.e., K = W/L).
m is the subthreshold slope factor. To simplify the analysis, m
is assumed to be the same for different transistors. VT = kT/q
is the thermal voltage, where k, T and q are the Boltzmann
constant, absolute temperature and the elementary charge,
respectively. VTH is the MOSFET threshold voltage, VGS
and VDS are the gate-source voltage and drain-source voltage
of the transistor, respectively. I0 is given by
I0 = μCOX (m − 1)VT2
(2)
in which µ is the carrier mobility, and COX is the oxide
capacitance per unit area. From (1), for VDS > 4VT ,
ID becomes almost independent of VDS , and could be
approximately expressed as
VGS − VTH
(3)
ID = I0 K exp
mVT
Consider the effect of temperature on VTH , the VTH can
be expressed as
VTH = VTH0 + α(T − 0)
(4)
where VTH0 is the threshold voltage at temperature T0 = 0 K.
α is the temperature coefficient (TC) of the threshold voltage.
The first voltage reference (VREF1 ) of the proposed dualoutput CVR as shown in Fig. 1, can be derived from (3)
and (4) as
VREF1 = VGS6 − VGS4
= (VTH06 − VTH04 ) + (α6 − α4 )T
I04 K4
,
+ mVT ln
I06 K6
(5)
in which VTH06 − VTH04 is a temperature-independent constant, and α6 −α4 has a negative TC in this case. So, the VTH
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LIN et al.: NANO-WATT DUAL-OUTPUT SUBTHRESHOLD CMOS VOLTAGE REFERENCE
FIGURE 2. Schematic of a simple voltage reference.
FIGURE 4. Monte-Carlo simulation results of (a) TC of VREF1 and (b) TC of VREF2
before trimming.
Therefore, the second voltage reference (VREF2 ) in Fig. 1 can
be designed based on the subthreshold operation.
The diode connected NMOS transistor M7 drains the current IC , which is replicated from IA by N times, and creates
VREF2 of the proposed dual-output CVR. Substituting (8)
into (6), the VREF2 can be derived as
FIGURE 3. Monte-Carlo simulation results of (a) VREF1 and (b) VREF2 before
trimming.
difference between M6 and M4 can generate a CTAT voltage. Therefore, the VREF1 could be generated by employing
the negative TC of VTH difference between M6 and M4 to
compensate the positive TC of thermal voltage. By carefully
adjusting the parameters in (5), zero temperature sensitivity
of VREF1 could be achieved.
B. PRINCIPLE OF THE SECOND REFERENCE
A simple reference could be generated by a current source
feeding an active load, as shown in Fig. 2, which has been
adopted
√ in [7]. However, the generated reference (VREF =
VTH + 2IBias /μCOX K) in [7] is higher than VTH that makes
the diode connected transistor working in saturation region.
In order to obtain a VREF lower than VTH and further reduce
the power consumption, the subthreshold operation of the
load transistor has been exploited in [8]. From (2) and (3),
the VREF in Fig. 2 can be given by
IBias
VREF = VGS = VTH + mVT ln
. (6)
KCOX (m − 1)μVT2
To ensure the subthreshold operation of the load transistor,
the bias current has been derived in [6] as
B + CT
2
,
(7)
IBias = AμT exp
DT
where A, B, C and D are constant with temperature.
Fortunately, such a bias current already existed in the
proposed dual-output CVR, which is the self-bias current
IA for VREF1 , and can be expressed as following
2
kT
IA = K5 COX (m − 1)μ
q
VREF1 − (VTH05 + α5 T)
× exp
(8)
m kT
q
102
VREF2 = (VTH07 − VTH05 ) + (α7 − α5 )T
NI05 K5
+ VREF1
+ mVT ln
I07 K7
(9)
Similar to (5), the CTAT voltage in (9) is generated by the
VTH difference between M7 and M5, and the thermal voltage
with proper scaling can provide the proportional-to-absolutetemperature (PTAT) voltage to compensate the negative TC
of the CTAT voltage. It should be noted that the expression
of VREF2 contains VREF1 , which brings the limitation that,
VREF2 is not a totally independent reference voltage, rather,
it partially depends on VREF1 . Nevertheless, since VTH07 −
VTH05 can be designed by choosing the device type and
dimension (e.g., VTH changes with channel length) of M7
and M5, some design freedom between VREF1 and VREF2 can
still be obtained. The TC performance of VREF1 will affect
that of VREF2 . Based on the optimized TC of VREF1 , the
TC of VREF2 can also be optimized by adjusting the current
ratio N, and the aspect ratios K5 and K7 . Furthermore, it
is apparent that by duplicating and re-sizing the M3 and
M7 branch, more than two reference voltages can be readily
generated using the proposed topology.
C. SIMULATION RESULTS AND TRIMMING CIRCUIT
The threshold voltage and the subthreshold current of transistors are sensitive to the process variation. As a result,
the CVR circuits generally show a relatively large process variation. Fig. 3 and Fig. 4 show the 200-case Monte
Carlo simulation results of VREF1 and VREF2 , and their TCs,
respectively. The standard deviations of VREF1 and its TC are
20 mV and 30 ppm/◦ C, respectively. The standard deviations
of VREF2 and its VREF2 are 46 mV and 18 ppm/◦ C, respectively. To obtain small variations for VREF1 and VREF2 , two
trimming schemes are adopted in the proposed dual-output
CVR design as shown in Fig. 5 and Fig. 6, respectively.
There are 4 switches used to control the trimming circuit
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FIGURE 5. Trimming circuit of M4 in the proposed dual-output CVR.
FIGURE 8. The current consumption of the proposed dual-output CVR measured
under 0.8-V and 1.8-V supply.
FIGURE 9. Measured LS of the proposed dual-output CVR at 25◦ C.
FIGURE 6. Trimming circuit of M3 in the proposed dual-output CVR.
FIGURE 7. Chip photo of the proposed dual-output CVR in 0.18-µm CMOS
technology.
FIGURE 10. Measured VREF1 vs. temperature of 16 samples with 1.8-V supply.
for VREF1 as shown in Fig. 5. Considering the chip area consumption, M4 rather than M6 is chosen for trimming. The
trimming scheme is based on tuning the aspect ratio of M4 to
adjust the thermal voltage (i.e., the PTAT voltage) ratio in
Equation (5). As shown in Fig. 6, there are 4 switches used
to control the trimming circuit for VREF2 . By controlling the
4 switches, there are 16 different channel widths of M3 for
PTAT voltage compensation. With the trimming schemes,
the proposed CVR can mitigate the process variation and
obtain optimized TC performance for VREF1 and VREF2 .
Fig. 7 shows the chip micrograph that measures an active
chip area of 0.0108 mm2 . One random chip was selected to
optimize the trimming configuration for a minimum TC. This
optimized trimming configuration was used in the totally
16 samples’ measurement in this work. The measured current
consumption varying with temperature under 0.8-V and 1.8V supply voltages with trimming is given in Fig. 8. At
0.8-V minimum supply voltage and 25◦ C, the total power
dissipation of the circuit is only 4.12 nW.
Fig. 9 shows the measured LS of two voltage references in
the proposed dual-output CVR at 25◦ C. The LS of VREF1 is
only 0.0505 %/V with the supply voltage in a range of 0.6 V
to 1.8 V, and the LS of VREF2 is 0.114 %/V with a supply
voltage from 0.8 V to 1.8 V. With the one-time trimming,
III. MEASURED RESULTS
The proposed dual-output CVR was designed and verified in
a standard 0.18-μm CMOS process using 1.8/3.3 V devices.
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LIN et al.: NANO-WATT DUAL-OUTPUT SUBTHRESHOLD CMOS VOLTAGE REFERENCE
FIGURE 11. Measured VREF2 vs. temperature of 16 samples with 1.8-V supply.
FIGURE 14. PSRR performance of VREF1 in the proposed dual-output CVR with
1.8-V supply.
FIGURE 12. Measured distribution of (a) VREF1 and (b) VREF2 at 25◦ C with 1.8-V
supply.
FIGURE 15. PSRR performance of VREF 2 in the proposed dual-output CVR with
1.8-V supply.
FIGURE 13. Measured distribution of (a) TC of VREF1 and (b) TC of VREF2 at 25◦ C
with 1.8-V supply.
Fig. 10 and Fig. 11 show the measured two voltage references
of 16 samples, VREF1 and VREF2 , with temperature varying
from −40◦ C to 125◦ C, respectively. The statistics of VREF1
distributions and VREF2 distributions are present in Fig. 12.
The average value of VREF1 at 25◦ C is 331.78 mV, with the
calculated standard deviation and variation coefficient σ /μ
of 1.75 mV and 0.527 %, respectively. The average value of
VREF2 is measured as 660.3 mV at 25◦ C, the calculated standard deviation and variation coefficient σ /μ are 2.79 mV and
0.423 %, respectively. Both VREF1 and VREF2 show small
variations in this design. The TC distributions of VREF1 and
104
VREF2 are measured with 1.8 V supply voltage as shown in
Fig. 13. The measured average TC of VREF1 is 41.67 ppm/◦ C,
with the calculated standard deviation and variation coefficient σ /μ of 6.03 ppm/◦ C and 14.48 %, respectively. The
average TC of VREF2 is measured as 24.48 ppm/◦ C, the calculated standard deviation and variation coefficient σ /μ are
4.33 ppm/◦ C and 17. 69 %, respectively.
The measured power supply ripple rejection (PSRR) of
VREF1 is given in Fig. 14. Under 1.8 V supply, the PSRR
are measured as −72.9 dB, −54.6 dB, −54.8 dB and
−54.5 dB, at 10 Hz, 1 kHz, 100 kHz and 1 MHz, respectively. Fig. 15 shows the measured PSRR of VREF2 , which
are −43.8 dB, −57.3 dB, −75.7 dB and −74.5 dB, at
10 Hz, 1 kHz, 100 kHz and 1 MHz, respectively. Intuitively,
since both VREF1 and VREF2 are generated based on feeding
a current source to a diode-connected transistor, their line
sensitivity and hence low-frequency PSRR is fairly good
(diode-connected transistor has much lower resistance than
the current source). For VREF1 , its low-frequency PSRR is
even better than VREF2 , as VREF1 is generated by further
dividing VB through M4 and M6, and a local negative feedback is helping stabilize VREF1 (e.g., when VB increases
due to the increasing supply, the common-source amplifier
M6 will attempt to decrease VREF1 which effectively lowers the increasing magnitude of VREF1 ). For high-frequency
VOLUME 1, 2020
TABLE 1. Measured performance comparison state-of-the-art works.
PSRR behavior, the filtering capacitor CO1 and CO2 , together
with the parasitic capacitance due to the chip PAD and measurement setup, contribute to poles in the PSRR formulas,
i.e., transfer functions with supply as input, and VREF1 or
VREF2 as output. For the PSRR of VREF1 , it has an extra lowfrequency zero due to the gate-drain capacitance Cgd of M5
and the local positive feedback loop made by M5, M1M2 and M4, M6, hence degrading its high-frequency PSRR
performance. The measurement shows a good capability of
the proposed dual-output CVR to reject the AC influence
from power supply.
The performance of the proposed design and the comparison with prior state of the art are summarized in Table 1.
The proposed CVR could provide two different voltage references with good variation performance, while the power
consumption is at the same level as, or even lower than
the listed single-output CVRs. Due to the compact and simple design, the proposed dual-output CVR reduces the chip
area significantly considering the dual-output voltage references. The proposed circuit also shows the good σ /μ, PSRR,
TC, LS and temperature range among these works.
IV. CONCLUSION
This paper present a dual-output subthreshold CMOS voltage
reference designed and fabricated in a 0.18-μm 1.8/3.3 V
CMOS process for ultra-low power multiple references application. The first reference is designed by employing the VTH
difference between 1.8-V NMOS and 3.3-V NMOS to generate the CTAT voltage and compensate the positive TC
of thermal voltage. The second reference is generated by
feeding a specific current mirrored from the first reference
voltage’s supply current into a diode-connected-transistor
load. Therefore, two different reference voltages can be generated in one compact and simple design to reduce the
number of devices and chip area significantly compared
to conventional two separate voltage references’ design. To
achieve an ultra-low power consumption, the amplifiers and
resistors are avoided, and all transistors work in subthreshold
VOLUME 1, 2020
region. The measurement results show a competitive power
consumption, chip area, PSRR, and LS for ultra-low power
multiple-voltage reference applications.
REFERENCES
[1]
X. Ming, L. Hu, Y.-L. Xin, X. Zhang, D. Gao, and B. Zhang, “A highprecision resistor-less CMOS compensated bandgap reference based
on successive voltage-step compensation,” IEEE Trans. Circuits Syst.
I, Reg. Papers, vol. 65, no. 12, pp. 4086–4096, Dec. 2018.
[2] V. B. Vulligaddala, R. Adusumalli, S. Singamala, and M. B. Srinivas,
“A digitally calibrated bandgap reference with 0.06% error for lowside current sensing application,” IEEE J. Solid-State Circuits, vol. 53,
no. 10, pp. 2951–2957, Oct. 2018.
[3] C. Huang, C. Zhan, L. He, L. Wang, and Y. Nan, “A 0.6-V minimumsupply, 23.5 ppm/◦ C subthreshold CMOS voltage reference with
0.45% variation coefficient,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 65, no. 10, pp. 1290–1294, Oct. 2018.
[4] Y. Liu, C. Zhan, L. Wang, J. Tang, and G. Wang, “A 0.4-V wide
temperature range all-MOSFET subthreshold voltage reference with
0.027%/V line sensitivity,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 65, no. 8, pp. 969–973, Aug. 2018.
[5] H. Zhang et al., “A nano-watt MOS-only voltage reference with highslope PTAT voltage generators,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, vol. 65, no. 1, pp. 1–5, Jan. 2018.
[6] Y. Wang, R. Zhang, Q. Sun, and H. Zhang, “A 0.5 V,
650 pW, 0.031%/V line regulation subthreshold voltage reference,” in
Proc. 44th IEEE Eur. Solid State Circuits Conf., Dresden, Germany,
2018, pp. 82–85.
[7] G. De Vita and G. Iannaccone, “A sub-1-V, 10 ppm/◦ C, nanopower
voltage reference generator,” IEEE J. Solid-State Circuits, vol. 42,
no. 7, pp. 1536–1542, Jul. 2007.
[8] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A
2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage
reference,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 465–474,
Feb. 2011.
[9] P. Luong, C. Christoffersen, C. Rossi-Aicardi, and C. Dualibe,
“Nanopower, sub-1 V, CMOS voltage references with digitallytrimmable temperature coefficients,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 64, no. 4, pp. 787–798, Apr. 2017.
[10] Z. Zhu, J. Hu, and Y. Wang, “A 0.45 V, nano-watt 0.033% line
sensitivity MOSFET-only sub-threshold voltage reference with no
amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 9,
pp. 1370–1380, Sep. 2016.
[11] Y. Ji, J. Lee, B. Kim, H.-J. Park, and J. Sim, “A 192-pW voltage reference generating bandgap–Vth with process and temperature
dependence compensation,” IEEE J. Solid-State Circuits, vol. 54,
no. 12, pp. 3281–3291, Dec. 2019.
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JIE LIN received the B.E. degree in electrical
and electronic engineering from the Southern
University of Science and Technology (SUSTech),
Shenzhen, China, in 2016. He is currently pursuing
the joint Ph.D. degree in electrical and computer
engineering with the University of Macau, Macau,
China, and SUSTech.
His current research interests include wireless
power transfer circuits and systems, inductive
switching power converters, and ultra-low power
voltage references.
LIDAN WANG received
the B.Sc. degree in
communication engineering from the Taiyuan
University of Science and Technology in 2005, the
M.Sc. degree in microelectronics and solid state
electronics from Beijing University of Technology
in 2008, and the Ph.D. degree in circuits and
systems from Southeast University in 2014.
From January 2015 to September 2018,
she was a Postdoctoral Research Fellow with
the Department of Electrical and Electronic
Engineering, Southern University of Science and
Technology (SUSTech), Shenzhen, China. From September 2018 to
January 2020, she was a Senior Research Fellow with the School of
Microelectronics, SUSTech, where she is currently an Research Associate
Professor. Her research interests include analog and mixed-signal integrated
circuit design and power management circuit and system design.
106
YAN LU (Senior Member, IEEE) received the Ph.D.
degree in electronic and computer engineering
from the Hong Kong University of Science and
Technology, Hong Kong, in 2013.
In 2014, he joined the State Key Laboratory
of Analog and Mixed-Signal VLSI, University
of Macau as an Assistant Professor. He has
coauthored more than 60 peer-reviewed technical
papers, one book entitled CMOS Integrated Circuit
Design for Wireless Power Transfer (Springer),
and edited one book entitled Selected Topics in
Power, RF, and Mixed-Signal ICs (River Publishers). His research interests
include wireless power transfer circuits and systems, low-power analog circuits, and next-generation power management solutions.
Dr. Lu was a recipient/co-recipient of the 2018 Macao Science and
Technology Award (2nd prize, with the 1st prize vacancy), the IEEE
Solid-State Circuits Society Pre-Doctoral Achievement Award from 2013
to 2014, the IEEE CAS Society Outstanding Young Author Award
2017, and the ISSCC 2017 Takuo Sugano Award for Outstanding FarEast Paper. He served as a Guest Editor of the IEEE TRANSACTIONS
ON C IRCUITS AND S YSTEMS –II: E XPRESS B RIEFS in 2018, and served as
a Track-Chair/Member of Technical Program Committee of several IEEE
conferences.
CHENCHANG
ZHAN
(Senior
Member,
IEEE) received the B.Sc. degree in electrical engineering and the M.Sc. degree
in microelectronics from Fudan University,
Shanghai, China, in 2004 and 2007, respectively,
and the Ph.D. degree in electronic and computer
engineering from the Hong Kong University of
Science and Technology (HKUST), Hong Kong,
China, in 2011.
From 2006 to 2007, he was an Intern Analog
Design Engineer with VeriSilicon, Shanghai.
From 2011 to 2012, he worked as a Postdoctoral Research Associate with
HKUST. From 2012 to 2014, he was with Qualcomm, Inc., San Diego, CA,
USA, as a Senior Engineer, focusing on the design of high-performance
power converters for future generations of mobile devices. He joined the
Southern University of Science and Technology (SUSTech), Shenzhen,
China, as an Assistant Professor in August 2014, where he is currently
an Associate Professor with the School of Microelectronics. His research
interests include the analysis and design of analog, mixed-signal, and
power management integrated circuits for a variety of applications.
Dr. Zhan received the Best Paper Award from IEEE ISIC in 2009, and
IEEE EDSSC in 2018, the Best Student Paper Award from IEEE EDSSC
in 2010, the Best Student Paper Award from IEEE ISCAS in 2011,
the 2018 SUSTech Young Faculty Research Award, the 2019 SUSTech
Excellent Teacher of the Year Award, and the 2019 SUSTech Excellent
Residential College Mentor of the Year Award. He served as a Review
Committee Member for IEEE APCCAS in 2014, a TPC Member for IEEE
ICTA in 2018 and 2019, a Guest Editor for Active and Passive Electronic
Components (Hindawi), a Session Chair/Co-Chair for IEEE ISCAS in
2018 and 2019, and in 2018, and a reviewer for many international
journals and conferences.
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