Digital Logic Design
譚 巽 言 Sun-Yen Tan
 電子系辦公室 Rm 106
 sytan@mail.ntut.edu.tw
 02-27386430 (H)
 02-27712171 # 2200
 0938569815

Course outline
Number Systems, Conversion, Codes and Arithmetic
 Boolean Algebra, Boolean algebra simplification
 Logic Gates, Implementations
 Karnaugh Map and Quine-McCluskey Minimization
 Combinational Circuit Design Principle



analysis, synthesis, Hazard, and Glitches
using MSI, PLD, timing diagram
Latches, Flip-Flops, Register and Counters
 Analysis of Synchronous/clocked Sequential Circuits
 Design of Synchronous/clocked Sequential Circuits


state assignment and state reduction
VHDL and simulation
 Examinations

Course outline
Number Systems, Conversion, Codes and Arithmetic
 Boolean Algebra, Boolean algebra simplification
 Logic Gates, Implementations

NOT, INV
2 transitors
AND Gate 6 , NAND 4, OR 6 ,
NOR 4 , XOR 14, NXOR 12 gates

Karnaugh Map and Quine-McCluskey Minimization

Combinational Circuit Design Principle



analysis, synthesis, Hazard, and Glitches
using MSI, PLD, timing diagram
Latches, Flip-Flops, Register and Counters
Analysis of Synchronous/clocked Sequential Circuits
 Design of Synchronous/clocked Sequential Circuits


state assignment and state reduction
VHDL and simulation
 Examinations

Course outline
Karnaugh Map and Quine-McCluskey Minimization
f= AB’ + A’B
A B f
---------------0 0 0
0 1 1
1 0 1
1 1 0
Truth Table
A
B 0
1
----------------
0
0
1
1
1
0
Course outline
Karnaugh Map and Quine-McCluskey Minimization


Combinational Circuit Design Principle


analysis, synthesis, Hazard, and Glitches
using MSI, PLD, timing diagram
Latches, Flip-Flops, Registers and Counters
_____
________
____|
|_______|
|______

Analysis of Synchronous/clocked Sequential Circuits
 Design of Synchronous/clocked Sequential Circuits


state assignment and state reduction
4 states
 2 FFs
22=4 2 variables
VHDL and simulation Verilog IEEE Standards
 Examinations Asynchronous circuits

Text book:
M. Morris Mano, M. D. Ciletti
Digital Design, 6th Ed., 2018,
Pearson Prentice Hall.
M. Morris Mano, M. D. Ciletti
Digital Design, 5th Ed., 2013,
Pearson Prentice Hall.
M. Morris Mano, M. D. Ciletti
Digital Design, 4th Ed., 2007,
Pearson Prentice Hall.
References:
Charles H. Roth, Jr,
Fundamentals of Logic Design, 5th Ed.,
Thomson Inc. , 2004.
Grading policy:

Midterm Exam 30 %

Final Exam

Homeworks and Assignments 40 %

Class participations (extra credits) 5 %

Quizs (extra credits)

Exam chp1 to Chp 6
30 %
5%