邏輯設計 (EECN30124)
Fundamental of Logic Design
林顯易
陽明交大 電控所
sofin@nycu.edu.tw
1
Course Description
• This course provides an introduction to the rudimentary
concepts and skills underlying the design of digital systems.
This course mainly focuses on the logic manipulation instead
of logic programming.
2
Textbook
• Jr. Charles H. Roth and Larry L Kinney, “Fundamentals of
logic design,” Cengage Learning,” 7th ed., 2020.
3
Syllabus (1/2)
Week no.
Date
Content
Week1
9/1-9/5
Introduction to Number Systems and Conversion
Ch1
Week2
9/8-9/12
Boolean Algebra
Ch2-3
Week3
9/15-9/19
Applications of Boolean Algebra Minterm and
Maxterm Expansions
Ch4
Week4
9/22-9/26
Karnaugh Maps
Ch5
Week5
9/29-10/3
Multi-Level Gate Circuits NAND and NOR Gates
Ch7
(Quiz 2)
Week6
10/6-10/10
Combinational Circuit Design and Simulation Using
Gates
Ch8
10/10, Holiday
Week7
10/13-10/17
Multiplexers, Decoders, and Programmable Logic
Devices
& Latches and Flip-Flops I
Ch9
(Quiz 3)
Week8
10/22
Mid-term 1 (Units 1, 2, 3, 4, 5, and 7)
Week9
10/27-10/31
Latches and Flip-Flops II & Registers and Counters I
* Quiz is always on Friday
(Quiz 1)
10:10am~12:10pm
10/24, Holiday
Ch11
期中與期末大會考
* 考卷上註明考試時不解釋題意，請學生依題目敘述回答。
4
* 若不能當天來考，補考成績以70%計算
Syllabus (2/2)
Week no.
Date
Content
Week10
11/3-11/7
Registers and Counters II
Ch12
Week11
11/10-11/14
Analysis of Clocked Sequential Circuits
Ch13
Week12
11/17-11/21
Derivation of State Graphs and Tables I
Ch14
Week13
11/24-11/28
Derivation of State Graphs and Tables II
Ch14
Week14
12/1-12/5
Reduction of State Tables State Assignments
Ch15
Week15
12/8-12/12
Sequential Circuit Design
Ch16
Week16
12/15-12/19
Final review
Week17
12/23
Final exam (Boolean algebra, combination logic,
latch/counter, and sequential logic)
* Quiz is always on Friday
(Quiz 4)
(Quiz 5)
(Quiz 6)
10:10am~12:40pm
* Excluded
6. Quine-McCluskey method.
10. Introduction to VHDL.
17. VHDL for sequential logic.
5
Grading Policy
• No roll-call points
• 6 Quizzes 30%
• Mid-term exams 35%
• Final exam 35%
• Average (A-,B) or (82,78)
• Cut off: (the last 5~7% of the class) AND (Quizzes + Mid-term + Final) < 60
6
Quizzes and Exams
• Quiz
• Two questions
• Materials after the previous quiz
• Revision from the selected problems in each chapter
Unit 1 Introduction Number Systems
• Mid-term exam
10
and Conversion
• Final exam
Unit 2 Boolean Algebra
Boolean algebra
Combinational Logic
Latch / Counter
Sequential logic
20
20
20
25
20
Unit 3 Boolean Algebra (Continued)
Unit 4 Applications of Boolean
30
Algebra Minterm and Maxterm
20
Expansions
Unit 5 Karnaugh Maps
Unit 7 Multi-Level Gate Circuits
20
NAND and NOR Gates
20
7
Office Hour
• EE749, 2pm~3pm Tuesday (With appointment, NOT acceptable
otherwise).
• Teaching Assistant: 陳享亨，郭晉霖
• TA Office hour: EE806, TBD
Handouts
• Posted on E3 platform before
the class of the week.
• Disclaimer on Use of Roth’s
Fundamentals of Logic Design
Materials
• Handouts are made available only
for enrolled students who have
purchased the book.
• Students are individually
responsible for complying with
copyright regulations. Any misuse,
reproduction, or distribution
outside the permitted scope may
result in legal consequences under
copyright law.
What can Logic Design do?
10
What can Logic Design do?
11
Any Questions?