DIGITAL DESIGN
ECE 251 Notes
Dr. Jacob Savir
New Jersey Institute of Technology
Editor:
Andrzej Strycharz
1
Digital logic circuits
Number representation:
bit – binary digit, either 0 or 1.
Review of base 10 representation:
…
0
1
2 digits in base 10
…
9
10
11
12
19
20
…
Count:
2
376 = 3×102 + 7×101 + 6×100
weights – progressive powers of 10
In binary:
Count:
0
digits in base 2
1
10
11
100
101
110
111
1000
These numbers correspond to zero to eight in
the decimal system.
3
A sequence of 0’s and 1’s represent an integer
in the binary system.
(bn bn-1 bn-2…b1 b0)2=(bn×2n + bn-1×2n-1 +…+ b1×2 + b0)10
Example of converting from binary to decimal
(101100101)2=(x)10
Number 1 0 1 1 0 0 1 0 1
× × × × × × × × × +=
Weights 256 128 64 32 16 8 4 2 1
= 256 + 64 + 32 + 4 + 1 = (357)10
Rule: To find the decimal equivalent add the
weights where the bit is one.
4
Example of converting from decimal to binary
357
178
89
44
22
11
5
2
1
0
1
0
1
0 remainders of progressive
0 divisions by 2
1
1
0
1
quotient of division by 2
(357)10 = (101100101)2
Rule: Progressively divide by 2, recording the
quotient and remainder. When a quotient of 0 is
reached – you are finished. The remainder read
upward is the binary equivalent of the decimal
number.
5
General number system
base r numbers:
digits used: {0, 1, 2,…,r-1}
(dndn-1...d0.d-1d-2...d-m)r =
Integer part
Fractional part
dn×rn + dn-1×rn-1 +...+ d1×r1 + d0×r0 + d-1×r-1 +
d-2×r-2 +...+ d-m×r-m
Example
1. r=10
523.61 = 5×102+2×101+3×100+6×10-1+1×10-2
2. r=2
1011.11 = 23+21+20+2-1+2-2= (11.75)10
6
3. r=4
31.2 = 3×41+1×40+2×4-1 = (13.5)10
4. r=8, octal
65.3 = 6×81+5×80+3×8-1 = 53 3/8 = (53.375)10
Conversion from base 10 to base r:
(531.375)10 = (x)8
 Treat the integer part and the fraction part
separately.
531
66
8
1
0
3
2
0
1
remainder of
division by 8
x=1023.3
.375
3.000 3
integer part of
multiplying by 8
7
Example:
r=3
(48.5)10=(x)3
0
1
2
1
.5
1.5 1
1.5 1
1.5 1
…
48
16
5
1
0
\ x=1210.1111…=1210.1
Example:
r=5
(76.85)10=(x)5
.85
4.25 4
1.25 1
1.25 1
…
76 1
15 0
3 3
0
x=301.411…=301.41
8
Example:
r=16, hexadecimal system
digits used:
{0, 1, 2,…, 9, A, B, C, D, E, F}
(F3)16 = (x)10
x=F×161 + 3×160 = 15×16 + 3 = 243
(A92.1E)16 = (x)10
x=A×162 + 9×161 + 2×160 + 1×16-1 + E×16-2
30
=10×256+9×16+2+ 116 + 14 256 =2706 256 =2706.1171875
(102.5)10 = (x)16
102 6
6 6
0
.5
8.0 8
0
x=66.8
9
Conversion to and from binary, octal and
hexadecimal
8=23, 3-group size
(i) binary to octal
(1010111101100011)2 = (x)8
added to make
a full group
001 010 111 101 100 011
1
2
7
5
4
3
x=127543
4
(ii) binary to hexadecimal 16=2 , 4-group size
(1010111101100011)2 = (x)16
1010 1111 0110 0011
A
F
x=AF63
6
3
10
(iii) Conversion from octal to binary
(7615)8=(x)2
group size-3
7 6 1 5
111
110
001
101
x=111110001101
(iv) hexadecimal to binary
(7615)16=(x)2
group size-4
7 6 1 5
0111 0110 0001 0101
x=0111011000010101
delete leading zeroes.
11
Decimal representation
The Binary-Coded-Decimal numbers (BCD):
Decimal Number
0
BCD number
0000
1
2
3
4
5
0001
0010
0011
0100
0101
6
7
8
9
0110
0111
1000
1001
 Note, that (99)10 converted to binary yields
1100011, but when represented in BCD code it
becomes 1001 1001, namely each decimal digit is
separately encoded.
12
ASCII code for characters
character
A
B
C
ASCII code
100 0001
100 0010
100 0011
⋮
⋮
O
P
Q
100 1111
101 0000
101 0001
⋮
⋮
Z
0
1
101 1010
011 0000
011 0001
⋮
⋮
9
blank
(
011 1001
010 0000
010 1000
⋮
⋮
=
011 1101
13
Fixed point representation
 Need a sign, magnitude and a radix point
 To represent the sign:
0
positive
1
negative
1st bit =
 The decimal (or binary) point is usually either at
the extreme left of the register, or at the extreme
right of the register.
 The radix point (decimal or binary) is usually
implicit
14
 Before we show the fixed point representation we
have to define the complement of a number:
(i) (r-1)’s complement
 The (r-1)’s complement of a number in radix
r is obtained by subtracting each digit of the
number from r-1.
Example:
(a) r=10. The 9’s complement of 671 is 328.
(b) r=2.
00101.
The one’s complement of 11010 is
15
(ii) The r’s complement
 Obtained by adding 1 to the low order digit of
its (r-1)’s complement.
Example:
(a) r=10. The 9’s complement of 671 is 328.
The 10’s complement of 671 is 329.
(b) r=2.
The 1’s complement of 11010 is
00101. The 2’s complement of 11010 is:
one's complement
00101
+
1
00110
16
 The 2’s complement can be formed also by
leaving all least significant 0’s and the first 1
unchanged, and then complementing the
remaining digits:
Let N=11010
The 2’s complement of N is
00110
complemented unchanged
Example: The 2’s complement of
101101110001110100
is 010010001110001100
17
 To represent a positive number attach a 0 to
its magnitude.
 To represent a negative number there are 3
methods:
1. Signed magnitude representation.
2. Signed 1’s complement representation.
3. Signed 2’s complement representation.
Signed magnitude
 The magnitude of the number is inserted after a
negative sign (1).
Let N=6 stored in a 7-bit register
N
0 0 0 0 1 1 0
Sign bit
18
then –N is represented as
−N
1 0 0 0 1 1 0
Sign bit
Signed One’s complement
 The negative number is represented by the 1’s
complement of its positive number.
Example: Same as before N=0000110,
then –N=1111001
Signed Two’s complement
 The negative number is represented by the 2’s
complement of its positive number.
19
Example: Same as before N=0000110,
then –N=1111010
Arithmetic addition
 With signed magnitude:
A+B=?
- If sign (A) = sign (B), add magnitudes and
attach signs.
- If sign (A) ≠ sign (B), subtract small magnitude
from large magnitude, and attach sign of large
magnitude.
 This procedure is slow for a computer.
20
With 2’s complement:
 Add the two numbers, including their sign bit,
and discard any carry out of the leftmost bit.
+6
+9
+15
0 000110
+
0 001001
0 001111
−6
+9
+3
carries
1 111010
+
0 001001
10 000011
discarded
carries
+6
−9
−3
0 000110
+
1 110111
1 111101
−6
−9
−15
carries
1 111010
+
1 110111
11 110001
discarded
21
With 1’s complement:
 Add the two numbers, including their sign bit. If
there is a carry out of the most significant (sign)
bit, the result is incremented by 1 and the carry
discarded.
+6
−9
−3
0 000110
+
1 110110
1 111100
−6
+9
+3
1 111001
+
0 001001
10 000010
+
1
0 000011
Called end-around carry.
22
 Advantage of 2’s complement: unique
representation of 0:
Signed magnitude
+0
0 0…0
−0
1 0…0
1’s complement
0 0…0
1 1…1
2’s complement
0 0…0
None
 Range of numbers with a register of k+1 bits is
±(2k−1), where k bits are reserved for the number and
one bit for the sign. 2’s complement system is
asymmetric – it has one more negative then positives.
Arithmetic subtraction
A−B=A+(−B)
 In 2’s complement A−B=A+(2’s complement of
B)
23
Example: Let
A=(3)10=000011
B=(5)10=000101
to perform A−B, we first complement B:
2’s complement of B:
111011
Then, we add A to it:
000011
+
111011
111110
2's complement representation
of (−2)10
24
Floating point representation
 Has two parts: mantissa, and exponent
 Mantissa, m, represents a signed fixed point
number. Usually the binary point is at the
leftmost position of the number.
 Exponent, e, designates the position of the actual
binary point.
 The value of the floating point number, with
mantissa, m, and exponent, e, is
m×re
where r, is an implicit radix.
r differs from computer to computer.
Typically r=2, 8, 16.
25
Example: Consider a 24 bit register:
0
±
1
16 17 18
23
±
●
m
e
0
-
plus
1
-
minus
Sign:
r=2
What is the value of the floating point number:
011001000000000000010100
sign
m
e
sign
3
1
25
m=+.11001=2-1+2-2+2-5= 4 + 32 = 32 =.78125
e=+010100=24+22=16+4=20
N=.78125×220=819200
26
 A mantissa is called normalized if it has no
leading zeroes. In this case it contains the
maximum number of significant digits.
± 1
±
1st digit ”1”.
Digital logic circuits
 Manipulation of binary information is done by
logic circuits, called gates.
 Each gate has a distinct graphical symbol and its
operation can be described by either an algebraic
function or a truth table.
27
 AND gate:
A
B
x
Truth table
A
0
0
1
1
x  AB
or
x  AB
B x
0 0
1 0
0 0
1 1
 OR gate:
A
B
x
Truth table
A
0
0
1
1
x  AB
B x
0 0
1 1
0 1
1 1
Note – this is not the arithmetic plus.
 Inverter:
A
x
x  A
or
xA
Truth table
A x
0 1
1 0
28
 NAND gate:
NAND=NOT AND
A
B
x
Truth table
A
0
0
1
1
x  ( AB )
or
x  AB
B x
0 1
1 1
0 1
1 0
 NOR gate:
NOR=NOT OR
A
B
x
x  ( A  B )
or
x  AB
Truth table
A
0
0
1
1
B x
0 1
1 0
0 0
1 0
 Exclusive-OR gate:
A
B
x
x  AB
Truth table
A
0
0
1
1
B x
0 0
1 1
0 1
1 0
29
 Equivalence gate (exclusive nor):
A
B
x
x  ( A  B )
or
x  AB
Truth table
A
0
0
1
1
B x
0 1
1 0
0 0
1 1
Note that equivalence and exclusive-or are
complements of one another.
Gates with more than two inputs:
 AND gate
xn
y
...
x1
x2
y  x1 x2
xn
Truth table
x1 x2 ... xn y
0 0 ... 0 0
0 0 ... 1 0
...
...
1 1 ... 0 0
1 1 ... 1 1
Output is “1” iff all inputs are “1”.
y  Min  x1 , x2 , , xn 
30
 NOR gate:
Truth table
y
...
x1
x2
xn
x1 x2 ... xn y
0 0 ... 0 1
0 0 ... 1 0
...
...
or
1 1 ... 0 0
1 1 ... 1 0
NOR=NOT OR
 OR gate:
xn
...
x1
x2
Truth table
y
y  x1  x2 
 xn
x1 x2 ... xn y
0 0 ... 0 0
0 0 ... 1 1
...
...
1 1 ... 0 1
1 1 ... 1 1
Output is “0” iff all inputs are “0”.
y  Max  x1 , x2 , , xn 
31
 NAND gate:
xn
Truth table
y
...
x1
x2
y  ( x1 x2
x1 x2 ... xn y
0 0 ... 0 1
0 0 ... 1 1
xn )
xn
...
y  x1 x2
...
Or,
1 1 ... 0 1
1 1 ... 1 0
The output is “0” iff all inputs are “1”.
NAND=NOT AND
 Exclusive-OR gate (parity function):
xn
...
x1
x2
Truth table
y
y  x1  x2 
 xn
x1 x2 ... xn y
0 0 ... 0 0
0 0 ... 1 1
...
...
y=1 iff odd # of inputs equal “1”.
32
Example: 3-way Exclusive-OR
x1
x2
x3
Truth table
y
x1 x2 x3 y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
 Equivalence gate:
y  ( x1  x2 
 xn )
Or,
y  ( x1  x2 
...
 xn )
x1 x2 ... xn y
0 0 ... 0 1
0 0 ... 1 0
...
xn
Truth table
y
...
x1
x2
y=1 iff even # of inputs are “1”.
Note that exclusive or and equivalence are
complements of one another.
33
Boolean algebra
 Basic relations:
1.
x0 x
2.
x0  0
3.
x  1 1
4.
x 1  x
5.
xxx
6. x  x  x
7.
x  x 1
8.
xx 0
9.
xy yx
10. xy  yx
commutative law
commutative law
11. x  (y  z)  ( x  y )  z  x  y  z associative law
12. x(yz)  ( xy )z  xyz
associative law
13. x(y  z)  xy  xz
14. x  yz  ( x  y )( x  z)
15. x  y  x y
16. xy  x  y
17. x  x
distributive law
distributive law
De Morgan’s law
De Morgan’s law
34
Examples:
1. Simplify
F  ( x1  x2 )x2
F  x1 x 2  x 2 x 2  x1 x 2  x1  x 2  x1  x 2
0
x1
original
x2
function
F
x1
x2
F
simplified
function
35
2. Simplify
F  ( x1  x2 )( x1  x2 )  x3
According to the distributive law
x  yz  ( x  y )( x  z)
Therefore,
F  x1  x2 x2  x3  x1  0  x3  x1  x3
0
x1  x2
x1
x2
( x1  x2 )( x1  x2 )
x1  x2
x3
x1
x3
F
simplified
function
original
function
F
36
 A measure to the complexity of a function is the
number of literals in it.
 A literal is an appearance of a variable, or its
complement, in the function.
Example: In the previous example we have found
that
( x1  x2 )( x1  x2 )  x3  x1  x3
5 literals
2 literals
 All the Boolean algebra relations may be proved
by using truth tables.
37
Example: Proof of De Morgan’s law
15. x  y  x y
x
0
0
1
1
y xy xy
1
1
0
0
0
1
0
0
0
0
0
1
two identical
columns
Example: Proof of distributive law
x  yz  ( x  y )( x  z)
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z x  yz ( x  y )( x  z )
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
two identical
columns
38
Map simplification:
 Is a graphical way of simplifying functions.
 The simplification will be done by a Karnaugh
map.
 A combination of variables for which the output
is one is called a minterm.
 A combination of variables for which the output
is zero is called a maxterm.
 Every function can be implemented with ANDs,
ORs and INVERTs.
39
Example: Implement the following function
decimal
equivalent
0
1
2
3
4
5
6
7
x1
0
0
0
0
1
1
1
1
x2 x3
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
F
0
1
0
1
0
1
1
1
x1
x2
x3
Minterms:
001,011,101,110,111
Maxterms:
000,010,100 
?
 Instead of describing the function by a truth
table, it is possible to specify it by listing its
minterms
F  1, 3, 5, 6, 7 called standard sum
or, by its maxterms
F  0, 2, 4 called standard product
F
40
 Implementation of standard sum components:
0  x1x2 x3 , 1  x1x2 x3 ,
2  x1x2 x3 , 3  x1x2 x3 ,
4  x1x2 x3 , 5  x1x2 x3 ,
6  x1x2 x3 , 7  x1x2 x3
can be implemented by AND gate and Inverters,
like:
x1
x2
x3
 4 
 Implementation of standard product components:
0  x1  x2  x3 , 1  x1  x2  x3 ,
2  x1  x2  x3 , 3  x1  x2  x3 ,
4  x1  x2  x3 , 5  x1  x2  x3 ,
6  x1  x2  x3 , 7  x1  x2  x3 ,
41
can be implemented by OR gate and Inverters, like:
x1
x2
x3
 4 
 Note that
  i1 , i2 ,
, in     i1     i2  
   in 
and,
  i1 , i2 ,
, in     i1    i2 
  in 
Going back to the example:
F   1, 3, 5, 6, 7    1   3    5    6    7  
 x1x 2 x 3  x1x 2 x 3  x1x 2 x 3  x1x 2 x 3  x1x 2 x 3
called standard sum of products
42
x1
x2
x3
F
Sum of product implementation
cost = 15
43
 The function could have been implemented by a
product of sums:
F   0, 2, 4    0   2  4  
 ( x1  x 2  x 3 )( x1  x 2  x 3 )( x1  x 2  x 3 )
x1
x2
x3
F
Product of sums implementation
cost = 9
44
Karnaugh maps
x2
x1
0
0 0
1
2
1 1
3
x3
x1x2
00 01 11 10
0 0 2 6 4
1 1
two variable
map
3
7
5
three variable
map
x3 x4
x1x2
00 01 11 10
00 0 4 12 8
01 1
5 13 9
11 3
7 15 11
10 2
6 14 10
four variable
map
45
Going back to the previous example:
F  1,3,5, 6,7
We draw the 3-variable map and indicate the
minterms
x3
minterm 6
x1x2
00 01 11 10
0 0 0 1 0
1 1
minterm
1
1
minterm
3
1
1
minterm
5
minterm
7
 In order to come up with an economical
implementation, we group the minterms into
cubes.
46
 The size of the cubes must be a power of 2.
Like 1, 2, 4, 8, 16.
 Cells (minterms) in the cube must be “adjacent”.
 The bigger the cube, the smaller is its cost.
 A minterm may be covered by more than one
cube.
Example of cubes
x3
x1x2
00 01 11 10
0 0 1 1 0
1 1
1
1
x2 x3
1
x3
x1x2
00 01 11 10
0
0 0
1 1
1
1
x1 x2 x3
1
47
x3
x1x2
00 01 11 10
0 0 1 1 0
1 1
1
1
x3
1
x1x2
00 01 11 10
0 0 1 1 1
1 1
1
x1x2
00 01 11 10
0 1 1 1 1
1 1
1
1
x3
1
x1x2
00 01 11 10
0 1 1 1 1
1 1
1
x3
x3
00 01 11 10
1
0 0
1
1
not a cube
1
1
x2
x1x2
1 1
1
x1
x2 x3
x3
1
1
x3
x1x2
00 01 11 10
1 0
0 0
1 1
1
1
1
not a cube
The rule: If a variable has two different values within a
cube – this variable will not be present in the product.
Otherwise
0 – implies an inverted variable
1 – implies an uninverted variable
48
Going back to the previous example:
F  1,3,5, 6,7
x3
x1x2
00 01 11 10
0 0 0 1 0
1 1
1
1
1
F  x1x2  x3
cost = 3
implementation:
x1
x2
x3
F
 Compare this with the previous implementations
which had costs of 9 or 15.
49
Principles of achieving minimum sum of products
 A prime implicant is a cube that cannot be
included within a bigger cube
x3 x4
x1x2
00 01 11 10
00
1* 1
prime implicant
(also essential)
01
1
not a prime
implicant
11
1
1
10 1* 1
1
prime implicant
(not essential)
essential prime
implicant
 An essential prime implicant is a prime implicant
which includes a minterm that cannot be covered
by any other prime implicant.
50
The procedure:
 Draw the Karnaugh map
 Find all the essential prime implicants
 Use other prime implicants to cover the minterms
not already covered by the essential prime
implicants.
Example: Minimize the previous function
x3 x4
x1x2
00 01 11 10
00
1* 1*
01
1 1 1*
11
1
10 1* 1
F  x1x3  x1 x2 x4  x1 x3 x4
cost = 8
51
Examples:
(i) Sum of products implementation of Exclusive
OR (XOR)
x2
x1
0
1
1
0
x1  x2  x1x2  x1 x2
1 1
F  0, 2,3,5,7,8,10,12,13 
x1x2
x1x2
x3 x4 00 01 11 10
x3 x4 00 01 11 10
(ii) Simplify
00 0
4 12 8
00 1
01 1
5 13 9
01
1
11 3
7 15 11
11 1
1
10 2
6 14 10
10 1
1
1
1
1*
F
x3 x4
x1x2
00 01 11 10
00 1
1 1
01
1
11 1
1
10 1
F  x2 x4  x1x2 x3  x2 x3 x4  x1 x3 x4
or,
1
F  x2 x4  x1x2 x3  x1 x2 x4  x1 x2 x3
1*
Both implementations will have a cost of 11.
52
 The minimum sum of products is not unique!
Principles of achieving minimum product of sums.
Follow a similar procedure to the one described
before (sum of products), except that you will work
with the zeroes rather than with the ones.
Example: Simplify F  0, 2,3,5,7,8,10,12,13
We start from F  1, 4, 6,9,11,14,15
x3 x4
x1x2
00 01 11 10
00 0 4 12 8
x3 x4
x1x2
00 01 11 10
00
0*
x1  x2  x 4
x 2  x3  x 4
01 1
5 13 9
01 0*
11 3
7 15 11
11
10 2
6 14 10
10
0
0
0
0
0
x1  x3  x4
x1  x2  x3
F  ( x1  x2  x4 )( x2  x3  x4 )( x1  x3  x4 )( x1  x2  x3 )
cost = 12
53
Combinational Circuits
 Circuits whose output depends on the value of
the present inputs (not on the history of the
values assigned to the inputs).
 All gates are combinational.
 A connection of gates constitutes a combinational
circuit, if there is no feedback connection from
an output of a gate to an input of a gate.
54
Example:
feedback
sequential
combinational
Analysis of combinational circuits
 Given a design → find the Boolean function it
implements.
Example:
x1
x2
x1x2
F
x3
x4
F  x1x2  x3 x4  x1  x2  x3 x4
x3 x4
55
Design of combinational circuit
 Given a verbal description of the problem →
design a circuit that implements it.
 In order to accomplish this it is necessary to find
a simplified Boolean description before the
circuit implementation.
Half adder
 A circuit that adds two bits and produces a “sum”
and a “carry”
x
y
HA
S
C
56
 The truth table:
N
0
1
2
3
x
0
0
1
1
y
0
1
0
1
C
0
0
0
1
S
0
1
1
0
 Boolean functions
C  3  xy , S  1, 2  1  2
S  xy  xy  x  y
 Implementation:
x y
C
HA
S
57
Parallel adder
y0
x0
FA
S-1
S0
y1
x1
C1
C
FA
xn-1 yn-1
C2
...
Cn-1
S1
1st number
= x0x1x2…xn
2nd number
= y0y1y2…yn
The sum
= S-1S0S1…Sn
C
FA
Sn-1
yn
xn
Cn
C
HA
Sn
Full adder
 Adds the two incoming bits, the carry from the
previous stage and produces the sum bit, and the
carry to the next stage.
58
Example: We show how 111 is added to 110 in
each stage:
1
1
FA
1
1
1
1
C
FA
1
0
C
HA
0
 Truth table of a full-adder
N
0
1
2
3
4
5
6
7
xn yn Cn+1 Cn
0 0 0
0
0 0 1
0
0 1 0
0
0 1 1
1
1 0 0
0
1 0 1
1
1 1 0
1
1 1 1
1
Cn  3, 5, 6, 7
0
1
Sn
0
1
1
0
1
0
0
1
Sn  1, 2, 4, 7
1
59
 Karnaugh maps of Cn and Sn:
xn y n
Cn 1 00 01 11 10
0 0
2
6
4
1 1
3
7
5
xn y n
xn y n
Cn 1 00 01 11 10
1*
0
1* 1 1*
1
Cn 1 00 01 11 10
Cn
 3, 5, 6, 7
Sn
  1, 2, 4, 7 
1
0
1 1
1
1
 Boolean functions
Cn  x n y n  Cn 1 x n  Cn 1y n
 x n y n  Cn 1 ( x n  y n ) , called majority
function.
Sn  xn y nCn 1  xn y nCn 1  xn y nCn 1  xn y nCn 1
it is possible to prove that
Sn  xn  y n  Cn1
60
 Implementation
xn yn
Cn
Cn+1
FA
Sn
Decoders
 A decoder is a circuit that decodes binary
information from one code to another.
61
 Has n inputs and 2n outputs
 When an input combination is applied, one
output becomes “1”, while the others stay at “0”.
Example: 2x4 Decoder
x1
Z0  x1x2
Z1  x1x2
x2
Z2  x1x2
Z3  x1x2
Zi=1 iff x1x2 in binary represent the decimal i.
62
Example: 3×8 decoder with an enable input
enable = 0  no decoding.
enable = 1  xyz decoded to the corresponding D.
63
Demultiplexer
 Receives information on one line, and transmits it
to one out of 2n possible output lines.
 Implemented by a decoder with enable input.
However the enable input is the data.
Example: A two-input, one data line, 4 output
demultiplexer.
S0
S1
Z0
Z1
Z2
Z3
D
64
Multiplexer
 Receives information on 2n lines and transmits it
on one output line. The input being selected is
determined by n select lines.
 Is the reverse of the demultiplexer
Example: 4x1 multiplexer
I0
I2
Z
I1
I3
S0
S1
65
Sequential circuits
 Circuits whose output depends on the history of
the inputs.
 Sometimes, we say that sequential circuits have
memory.
 Sequential circuits are classified as either
synchronous or asynchronous.
 In synchronous circuits the outputs change only
when the clock is on.
 In asynchronous circuits the outputs change when
the inputs change.
66
 The basic building block of sequential circuits is
the flip-flop.
 A flip-flop is capable of storing a bit, until it is
directed to change states, by a proper input.
The basic latch
S
R
S – "Set" input
R – "Reset" input
Q – output
Q – inverted output
Q
Q
67
0→1→0→0
S
Q 1→0→0→1
Q 0→1→1→0
R
0→0→0→1
Characteristic table:
S
R
Q(t+1)
Comments
0
0
Q(t)
No change
0
1
0
clear
1
0
1
set
1
1
0
not allowed
 If S  R  1 the outputs not complementary,
therefore not allowed.
 Q t  1 is the complement of Q t  1
 Q is called the state of the latch.
 Q t  is present state, Q t  1 is next state.
68
RS flip-flop
 Is a latch with a clock enable
S
Q
C
Q
R
basic latch
 When C=0 no transition is possible.
 When C=1 transition is performed as instructed
by the values of R and S.
 Block diagram of RS flip-flop:
Q
S
C
R
Q
69
D flip-flop
Q
Q
D
Q(t+1)
Comments
0
0
clear
1
1
set
D
C
 The output Q follows the input D when the clock
is on.
JK flip-flop
Q
Q
K
J
C
J
K
Q(t+1)
Comments
0
0
Q(t)
NC
0
1
0
clear
1
0
1
set
1
1
Q t 
complement
70
T flip-flop
Q
Q
T
0
1
C
Q(t+1) Comments
Q(t)
NC
Q (t )
complement
T
 Performs the same as the JK flip-flop, when both
inputs J and K tied together.
Binary counters
A1
A0
T
T
T
T
"1"
C A3 A2 A1 A0
0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
C
…
A2
15 1 1 1 1
16 0 0 0 0
…
A3
Sequence count
71
Binary down-counter
A3
A2
A1
A0
T
T
T
T
"1"
C
…
C A3 A2 A1 A0
1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
…
15 0 0 0 0
16 1 1 1 1
sequence count
72
Register with parallel loads
x3
x2
x1
LOAD
Q3 D3
Q2 D2
Q1 D1
C
CLEAR
 If C=1, and LOAD=1, then the values on x1 x2 x3
are loaded into the D-flip flops.
 If LOAD=0 then the state of the flip flops does
not change.
 When CLEAR=1, the register is set to
Q1=Q2=Q3=0
73
Shift registers
(i) Shift left
Q3 D3
Q2 D2
Q1 D1
Q0 D0
Din
C
 If Din=1, and if Q3=Q2=Q1=Q0=0, when the clock
becomes 1, the new state becomes Q3=Q2=Q1=0,
Q0=1.
 When the second clock pulse becomes 1, the
state of Q0 is shifted left into Q1; and the value on
Din enters Q0. For example if Din=0, the next state
becomes Q3=0, Q2=0, Q1=1, Q0=0.
 If Din is fixed at 0, each time a clock becomes 1,
the number stored in the register is multiplied by
2.
74
Example:
Suppose Q3=0, Q2=1, Q1=1, Q0=0. Then if Din=0,
and C=1, the new state is Q3=1, Q2=1, Q1=0, Q0=0.
Thus the corresponding decimal values of the states
are:
0110 − 6
1100 − 12
(before the clock)
(after the clock)
(ii) Shift right
Q3 D3
Din
Q2 D2
Q1 D1
Q0 D0
C
75
 Din is connected to the leftmost flip-flop.
 The state is shifted one place to the right with
each clock pulse.
 The rightmost bit is lost with each clock pulse.
Example:
present state
Q3 Q2 Q1 Q0
Din
next state
Q3 Q2 Q1 Q0
0
1 1 0
1
1
0 1 1
1
0 1 1
0
0
1 0 1
0
1 0 1
1
1
0 1 0
1
0 1 0
1
1
1 0 1
 Note, that if Din=0, a right shift corresponds to
dividing by 2. For example if
Q3Q2Q1Q0=1010 (10), then after the shift
Q3Q2Q1Q0=0101 (5).
76
Shift left control
SHL
Din
Q2 D2
Q1 D1
Q0 D0
C
 If SHL=0 then the state of the register does not
change.
 If SHL=1, the shift-left operation is performed on
the register.
Shift register symbol
x
LOAD
SHL
SHR
C
Din
CLR
Q
77
Bus oriented computer
 A bus is a group of wires used as a common data
path between registers.
RA
C
LB
EB
LA
EA
LOAD
Enable
CLEARA
RB
CLEARB C
bus
 To load the contents of RA into RB, the controls
should be LB=EB=1, EA=LA=0, CLRA=CLRB=0
(the clock C is common to both registers).
78
Simplified drawing
LA
C
CLRA
EA
LB
C
CLRB
EB
RA
RB
BUS
RC
LC
C
CLRC
EC
RD
LD
C
CLRD
ED
79
Memories
(i) Random access memories (RAM)
 A memory unit is a collection of words.
 Each word is a collection of flip-flops.
 Each word is addressable.
 In a RAM it is possible to read the contents of a
0
1
2
⋮
word, and write information into a word.
⋮
j
word
address
Schematic diagram
of a RAM
memory word
memory cell
80
 A collection of 8 bits is called a byte.
 The contents of a memory word (0’s and 1’s)
may represent a number, an instruction, a letter
of the alphabet, etc.
 The size of the RAM is the number of words in
it.
1K = 210 words = 1024 words
4K = 4096 words
64K = 216 words
 Communication between the RAM and the
environment is achieved through control lines,
address selection lines, and data input and
output lines.
 The READ/WRITE control specifies the
direction of information transfer.
81
 The address specify the particular word
selected.
 The input lines provide the information to be
stored in the selected word.
 The output lines supply the information coming
out of the selected memory word.
n data input
lines
k address
lines
2k=m
RAM
m words
n bits/word
n data output
lines
READ/WRITE
control
82
 When the READ/WRITE = 1 (Read operation)
the contents of the word selected by the address
lines is outputted.
 When the READ/WRITE = 0 (Write operation)
the information supplied by the data input lines
is stored in the word selected by the address
lines.
 The memory cell:
SELECT
logic diagram
R
S
INPUT
Q
READ/WRITE
1/0
block diagram
Input
Select
BC
READ/WRITE
Output
OUTPUT
83
 When SELECT = 0, the contents of the
memory cell does not change.
 When SELECT = 1, and READ/WRITE = 1,
the contents of the cell appears at the output.
 When SELECT = 1, and READ/WRITE = 0,
the input is stored in the cell:
if input = 1, the cell is set (=1)
if input = 0, the cell is reset (=0)
84
Example: 4 by 2 RAM
DATA INPUTS
D0
word 0
BC
2×4
D
D1
E
Address C
O
D
Selection E
R D2
word 1
BC
BC
word 2
BC
D3
BC
BC
word 3
BC
BC
Memory
Enable
READ/WRITE
DATA OUTPUTS
 When Memory Enable = 0 no word is being
selected and the contents of memory stays
unchanged.
85
Memory (RAM) operation
 Two external registers are associated with the
RAM.
 Address lines to the RAM are supplied by the
Memory address register (MAR).
 The information transfer to and from memory
is done via a Memory buffer register (MBR)
(also called Memory data register, MDR)
 The block diagram:
MAR
RAM
Address in
MBR
Data in/out
READ/WRITE
86
 When the WRITE control is activated, the
contents of MBR is written into the word selected
by MAR.
 When the READ control is activated, the contents
of the selected word are placed in the MBR. The
content of the selected memory word does not
change (non-destructive READ).
Sequence of events
Sequence of events
for READ:
for WRITE:
1. Put address bits
in MAR.
2. Activate READ.
1. Put address bits
in MAR.
2. Put data bits
in MBR.
3. Activate WRITE.
87
(ii) Read only memories (ROM)
 A memory unit that performs the read operation
only.
 The stored information is made permanent during
production according to the customer’s request.
 After production the contents of the ROM is
usually unerasable (unlike RAMs).
 An m×n ROM:
k address lines
m words
m×n
ROM
m=2
k
n output lines
88
Example: 4×3 ROM
D0
X0
D1
X1
D2
Address
Selection
D3
- broken links
2×4
Decoder
A1
truth table:
Address
X0 X 1
0
0
0
1
1
0
1
1
Outputs
A1 A2 A3
0
1
0
0
0
1
1
0
1
1
1
0
A2
A3
data outputs
89
 The ROM is fabricated first with outputs all
being 1.
 The particular pattern (personalization) is
obtained by breaking the links where 0’s are
required.
 The personalization is done by the manufacturer
according to a table supplied by the customer.
 ROMs are useful for conversion of codes, lookup tables, microcode sequencing etc.
90
Positive logic:
high voltage = 1
low voltage = 0
Negative logic:
high voltage = 0
low voltage = 1
Choice of logic level assignment affects the
resulting gate type:
Let a device have the following function table:
A
L
L
H
H
B x
L L
H H
L H
H H

Positive Logic
A B x
0 0 0
0 1 1
OR gate
1 0 1
1 1 1
Negative Logic
A B x
1 1 1
1 0 0
AND gate
0 1 0
0 0 0
91
Assertion Level: The logic level that activates the
device
Don’t care conditions: In some cases specific input
combinations do not appear in normal operation. In
these cases you may assign any logic value to the
device (for these specific input combinations).
These assignments are called “don’t care”
combinations (denoted  or ). The actual
assignment is then chosen to minimize the
implementation cost.
Example: Design a conversion circuit from BCD
code to Gray code.
BCD – binary coded decimal
Gray – Special unit-distance code
92
Solution:
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BCD
b4 b 3 b2 b1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Gray
g4 g3 g2 g1
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
























93
Standard sums:
g 4   8, 9     10,11,12,13,14,15 
g 3   4, 5, 6, 7, 8, 9     10  15 
g 2   2, 3, 4, 5     10  15 
g1   1, 2, 5, 6, 9     10  15 
K-Maps
b4b3
b2b1 00 01 11 10
b4b3
b2b1 00 01 11 10
00 0
0

1
5 13 9
01 0
0

1
11 3
7 15 11
11 0
0


10 2
6 14 10
10 0
0


00 0
4 12 8
01 1
Template
g4=b4
b4b3
b2b1 00 01 11 10
b4b3
b2b1 00 01 11 10
00 0
1

1
00 0
1

0
01 0
1

1
01 0
1

0
11 0
1


11 1
0


10 0
1


10 1
0


g3=b3+b4
g 2  b3 b 2  b3 b 2  b 2  b3
94
b4b3
b2b1 00 01 11 10
00 0
0

0
01 1
1

1
11 0
0


10 1
1


g 1  b 2 b1  b 2 b1  ( b1  b 2 )
Implementation:
b3
g4
g3
b2
g2
b1
g1
b4
95
Further reduction by factoring
Assume a minimal sum of products has been
derived: F  AB  CB
Straight implementation (2-level):
A
B
F
C
After factoring B :
F  ( A  C )B
A
C
B
F
96
Quine-McCluskey algorithm
Is a function minimization that can handle large
number of variables. It is suitable for computer
programming.
Example: Find a minimal sum for
F  0, 2, 4, 6,7,8,10,11,12,13,14,16,18,19, 29,30
Step 1: Determine all prime implicants
Step 1ʹ:
 Group all minterms according to the # of 1s in
their binary representation. For example
decimal
8
7
binary
01000
00111
# of 1s
1
3
belong to
different
groups
97
(0)
(2)
(4)
(8)
(16)
(6)
(10)
(12)
(18)
(7)
(11)
(13)
(14)
(19)
(29)
(30)
v
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
w x
0 0
0 0
0 1
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1 1
0 0
1 1
1 1
y
0
1
0
0
0
1
1
0
1
1
1
0
1
1
0
1
z
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
98
Step 2ʹ: Create adjacent pairs
(0,2)
(0,4)
(0,8)
(0,16)
(2,6)
(2,10)
(2,18)
(4,6)
(4,12)
(8,10)
(8,12)
(16,18)
(6,7)
(6,14)
(10,11)
(10,14)
(12,13)
(12,14)
(18,19)
(13,29)
(14,30)
v
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
-
w x
0 0
0 - 0
0 0
0 - 0
0 0
0 1
- 1
1 0
1 0 0
0 1
- 1
1 0
1 1 1
1 1
0 0
1 1
1 1
y
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
99
Step 3ʹ: Create quads by combining adjacent
pairs
(0,2,4,6)
(0,2,8,10)
(0,2,16,18)
(0,4,8,12)
(2,6,10,14)
(4,6,12,14)
(8,10,12,14)
v
0
0
0
0
0
0
w x
0 - 0
0 0
- - - 1
1 -
y
0
1
-
z
0
0
0
0
0
0
0
ü
ü
ü
ü
ü
ü
Step 4ʹ: Create 8-cubes
(0,2,4,6,8,10,12,14)
v w x y z
0 - - - 0
List of prime implicants: all unchecked cubes
100
prime implicant
product term
A
bit configuration
v w x y z
0 0 1 1 -
B
0 1 0 1 -
v wx y
C
0 1 1 0 -
v wxy
D
1 0 0 1 -
vw x z
E
- 1 1 0 1
wxyz
F
- 1 1 1 0
wxyz
G
- 0 0 - 0
w xz
H
0 - - - 0
vz
v w xy
Step 2: Create a minimal cover of all minterms
using the just computed list of prime implicants.
Step 1ʺ: Create the prime implicant table. Rows
= prime implicant. Columns = minterms. Place
an “x” if a minterm is included in a PI.
101
PI table:
minterms
ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü
PI
0 2 4 8 16 6 10 12 18 7 11 13 14 19 29 30
A*
x
B*
x
x
C
x
x
D*
x
x
E*
x
x
F*
x
x
G*
x x
H*
x x x x
x
x
x
x x
x
x
essential row (PI): A PI that includes a distinguished
column denoted by *
distinguished column: A minterm that is covered by a
single PI. Denoted by
102
F  A BDEFGH
 v z  w x z  wxy z  wxyz  vw x y  vwxy  v wxy
Is the minimal sum. Note that in this case all PIs
that were selected were essential. This, however, is
not always the case in general.
Definitions:
 Two rows I and J of a prime implicant table which
have x’s in exactly the same columns are said to be
equal (I=J).
 A row K of a PI table is said to dominate another row
L of the same table if row K has x’s in all columns in
which row L has x’s and if, in addition, row K has at
least one x in a column in which row L does not have
an x. (Notation: K  L )
 Two columns I and J of a PI table which have x’s in
exactly the same rows are said to be equal (I=J)
103
 A column I of a PI table is said to dominate another
column J of the same table (written I  J ) if column I
has x’s in all the rows in which column J has x’s and
if, in addition, column I has at least one x in a row in
which column J does not have an x.
Theorems:
 A row I of a PI table can be removed and at least one
minimal sum can still be obtained from the reduced
table (with row I missing) if (1) there is another row J
of the table which is equal to row I and does not have
a higher cost than row I or (2) there is another row K
which dominates row I and which does not have a
higher cost
 A column I of a PI table can be removed without
affecting the minimal sum sought if (1) there is
another column J of the table which is equal to
column I, or (2) there is another column H of the table
which is dominated by column I.
104
Note: You remove dominated rows and dominating
columns.
Step 3: If the minimal sum includes non-essential
PIs you continue the process by eliminating
dominated rows and dominating columns.
105
Example: Minimize the following PI table
A*
B*
C*
D
E
F
G
H
I
J*
K
L
M
N
O
P
Q
ü üüü ü ü ü ü
x
x
x
x
x
x
ü
x
x
x
x
ü ü ü ü
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ü
x
x
x
x
x
x
x
x
x
1 4 8 5 9 18 20 24 7 11 13 14 19 21 25 26 28 15 23 27 29 30
x
x
x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
106
After removal of essential rows and distinguished
columns we get:
D
E
F
G
H
I
K
M
N
O
P
Q
7 11 14 28 15 23 29 30
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Since F=I and K=M we remove I and M (same
cost).
After the removal we get the following reduced
table
107
D
E
F
G
H
K
N
O
P
Q
7 11 14 28 15 23 29 30
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Now we can remove the dominated rows:
K F
GH
remove F, H, Q
EQ
We, then, get the new table
108
ü ü
ü ü ü ü
7 11 14 28 15 23 29 30
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D
** E
** G
** K
N
O
P
** = secondary essential rows
Removal of secondary essential rows and
corresponding columns results in:
14
D
N
O
P
30
x
x
x
x
Since N  P , O  P , we can remove N and O, in
which case P becomes a new essential (secondary)
row.
109
Thus:
F  A B C JE GK P
 v yz  wxy  wxy  vxy  wxz
 vwz  vxy  w xy z
is a minimal sum of products.
Hazards
Hazards are glitches that occur while variables are
changing state. These glitches are due to spurious
delays in the network. How can we avoid them?
110
Static hazards
Definitions:
 A static 1 hazard is a transition between a pair of
adjacent input states which both produce a 1 output,
during which transition it is possible for a momentary
0 output to occur.
 A static 0 hazard is a transition between a pair of
adjacent input states which both produce a 0 output,
during which transition it is possible for a momentary
1 output to occur.
Example of static 1 hazard:
A
C
M
F  AC  BC
B
N
111
Let A=B=1, and let C change from C=1 to C=0.
Timing diagram:
A
B
1
1
t
C
t
M
t
N
1
t
F
1
t
t
The occurrence of the glitch depends on circuit
delays.
112
Example of a static 0 hazard:
A
B
M
F  ( A  B )(C  B )
C
N
Let A=C=0, and B changing from B=0 to B=1
A
C
t
B
t
M
t
N
t
F
t
t
113
Analysis of hazards in CL
For static hazards:
Step 1: Compute the sum of products while
keeping all x i  x i terms and x i  x i terms.
The function will look like:
F  Ax i  B xi  C( xi  xi )  D
For static 1 hazard solve:
A=B=1, D=0
For static 0 hazard solve:
D=A=B=0, C=1
114
Example:
Find all the static hazards in the circuit:
w
x
y
wxy
F
wz
z
w z wy
wy
Step 1:
F  wxy w z wy  wxy  w z wy
 wxy  (w  z )(w  y )
 wxy  ww  wy  w z  yz
Candidates: w and y
115
Step 2:
(i) Detection of static 0 hazard on w:
F  w( xy  y )  wz  ww  yz
Need to solve:
xy  y  0  ( x  y )( y  y )  0  x  y  0
z0
yz  0
Solution:
x  0, y  1, z  0 (w changing )
(ii) Detection of static 1 hazard on w:
F  w( xy  y )  wz  yz
116
xy  y  1  x  y  1  x  1
z 1
yz  0  y  1
Solution: x  1, y  z  1 (w changing )
(iii) Static 1 hazard on y:
F  wxy  (w  z)y  wz
wx  1
w z 1
wz  0
w  x 1
z   (don ' t care )
We have discovered two input combinations:
w  x  1, z  0
( y changing )
w  x  1, z  1
( y changing )
117
Fixing static hazards:
Fixing can be done by either fixing the sum of
products, or the products of sums representation.
The procedure calls for:
For each pair of adjacent input states that both
produce a 1 output (0 output), there is at least one
PI that includes both input states of the pair.
Thus the procedure of choosing PIs to include in
the expression must be modified as follows:
A sufficient number of PIs must be picked so that
each pair of adjacent input states, which both
produce 1 outputs (0 outputs), is included in a
single PI.
118
Example: Fix the static hazards in the previous
example.
Solution: The function was
F  wxy  ww  wy  w z  yz
 wxy  wy  w z  yz
wx
00 01 11 10
00
1 1
wy
01 1
1
1
yz
11 1
1
1
yz
wz
10
1
original
design
1
wxy
wx
00 01 11 10
00
1 1
yz
wz
01 1
1
1
11 1
1
1
10
1
Redundant
term
1
redesign
Redundant
119
The hazard-free function is:
F  w z  wx  wy  xz  yz
the minimal sum
redundant terms
to avoid hazards
Implementation:
F  w z  (w  z )y  x(w  z)
 w z  (w  z )y  (w  z )x  w z  (w  z )( x  y )
We will seek a NAND implementation:
120
F  wz  (w  z)( x  y )
Bubbles added
w
z
F
x
y
Bubbles added
w
z
F
x
y
w
z
F
x
y
121
The conversion:
w
Add even #
of inverters
z
F
y
x
After De Morgan substitution:
w
z
F
y
x
Note that this is a NAND implementation since
≡
122
Since
w
w
w

w
we get:
w
z
F
x
y
123
Dynamic hazards
Definition: A dynamic hazard is a transition
between a pair of adjacent input states, one of
which produces a 0 output and the other of which
produces a 1 output, during which transition it is
possible for a momentary 0 output and a
momentary 1 output to occur.
Intended transition:
Transition subject
to dynamic hazard:
124
Theorem: The hazard-fixing procedure described
earlier for static hazards eliminates all dynamic
hazards as well.
Variable-Entered Maps (VEMs)
May be used to plot an n-variable problem on an
n-1 variable map.
Consider the case of minimizing
F  1, 5, 8,10,11,13
The minterms are
A
0
0
1
1
1
1
B
0
1
0
0
0
1
C
0
0
0
1
1
0
D
1
1
0
0
1
1
F
1
1
1
1
1
1
125
We can rewrite the table in terms of a Map Entered
Variable (MEV) D:
A
0
0
1
1
1
B
0
1
0
0
1
C F
0 D
0 D
0 D
1 D D
0 D
The corresponding map
AB
C
00 01 11 10
0 D
1
D
D
D
cover of D
D D
PIs are selected based on “similar” terms.
Since D  D  1:
F  A CD  B CD  A B D  A B C
126
Realizing functions with MSI logic
MUXes
The MUX realizes logic functions by setting up a
one-to-one correspondence between input line
number and minterm number of a logic expression.
Example:
A
B
0
0 0
1
1
1 1
1
F  (1, 2, 3)
MUX
B
A
1
S0
S1
0
1
2
3
EN
Control
block
F
Example: Realizing an n-variable function
with 2(n-1):1 MUX.
Consider the function
X  A B C  A B C  AB
127
We will create the VEM in reference to MEV=C.
MUX
A
0
0
1
1
B
0
1
0
1
X
0
1
B
A

C
1
C
C
S0
S1
0
1
2
3
EN
X
Example: In some cases we can implement an
n-variable function using 2n-2:1 MUX. Consider
the function:
X  A B C D E  ABC D E  A B C D E  A B CDE
 AB C D E  AB CD E  ABCDE  21, 24, 20, 3, 8,10, 31
The VEM:
AB
AB
C
00
01
11
0
DE
D E D E
DE
1
0
0
DE
C
00
01
11

D ED E
0 DE
E
DE
10
0
1
0
DE
D
10
0
0
128
Implementation using 8:1 MUX:
MUX
D
E
C
B
A
S0
S1
S2
0
1
2
3
4
5
6
7
EN
X
Expanding an MSI function
Because of pin limitations relatively small
functions can be implemented in MSI. It is
possible, however, to extend the function across
several chips. The following is an expansion using
16:1 MUXes to a 64:1 MUX.
129
A 64:1 multiplexing circuit.
MUX4
63
62
⋮
49
48
EN
15
14
⋮
1
0
Out
MSB LSB
C D E F
MUX3
47
46
⋮
33
32
EN
15
14
⋮
1
0
Out
MSB LSB
C D E F
MUX2
31
30
⋮
17
16
EN
15
14
⋮
1
0
C D E F
MUX1
15
14
⋮
1
0
3
2
1
0
Out
MSB LSB
A
Out
MSB LSB
EN
15
14
⋮
1
0
MUX5
EN
Out
MSB LSB
C D E F
B
Circut
output
130
Decoders
Let the output lines be numbered in accordance
with the decimal equivalence of the input binary
code. Each output corresponds to the
corresponding minterm. Addition (OR function) of
all the minterms of the function is a decoder-based
implementation.
Example: Consider the function X  4,8,9,10,13 .
Implementation with a 4x16 decoder, and
Enable asserted low,
Outputs asserted low:
D
C
B
A
0
1
2
3
EN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
X
131
Example: 74LS138, a 3-line to 8-line decoder chip.
There are 2n(=8) NAND gates each having n+1
inputs (n select inputs, and 1 enable input)
132
Example: Use a decoder to convert a binary code to
a Gray code
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Binary
A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Gray
w x y z
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
w  8,9,10,11, 12,13,14,1 5 
x  4,5,6,7,8, 9,10,11
y  2,3,4,5,10 ,11,12,13 
z  1,2,5,6,9, 10,13,14 
133
Implementation of the code conversion:
Assume that the outputs are asserted low. The ORs
with inverted inputs are equivalent to NAND gates.
134
6:64 Expanded decoder made out of 4:16 and 2:4
decoders.
A, B selects a decoder
C, D, E, F selects an output
135
A more practical implementation of a 6:64 decoder
that saves on the 2:4 decoder.
136
Example: The 2-input enable allows implementation of
a 3:8 decoder from a 2:4 decoders
A=0 activates decoder 1, and
A=1 activates decoder 2.
Input ABC=011 activates
output 3;
Input ABC=111 activates
output 7.
Example: X  0,2,4,5,13,14 
137
Example:
MUX implementation of:
F1    3,5, 6, 7,9,12,15 
F2    0,1,8,11,14,15 
F3    0,1, 4,5, 6,8,10,11,14 
F4    5, 7,9,10,12 
Verify at home using MEV=D
138
Encoder realizations
An encoder has 2n inputs and n outputs. It normally
implements a conversion of a numbered input line
to its corresponding binary code.
A priority encoder is an extension of the binary
encoder. It allows several input lines to be asserted
simultaneously while the output presents the binary
code of the highest-numbered asserted input line.
For example, if input lines 3, 5 and 8 are asserted,
the output is 1000. Priority encoder was designed
to be used in conjunction with priority interrupt
system.
Example: 74148 is an 8-input, 5-output priority
encoder with low assertion input and output
signals.
139
0 1 2 3 4 5 6 7 EI
EO
EI
H
L
L
L
L
L
L
L
L
L
A 0 A1 A 2 GS
0 1 2 3 4 5 6 7
GS A 0 A1 A 2 EO
H H H H H H H H
       L
      L H
     L H H
    L H H H
   L H H H H
  L H H H H H
 L H H H H H H
L H H H H H H H
H H H H H
H H H H L
L L L L H
L H L L H
L L H L H
L H H L H
L L L H H
L H L H H
L L H H H
L H H H H
       
EI enables the outputs when asserted low.
EO = output enable; GS = group signal
140
As long as the chip is enabled and EO is high, the
output binary code will indicate the number of the
highest numbered line asserted. Output GS is
asserted low when any input line is active.
The additional outputs GS and EO allow the 74148
to be used to create larger encoders.
141
The Comparator
Compares 2 numbers, A and B, and determines
whether A<B, A=B, or A>B. This is done by
checking the corresponding bits from the MSB
down.
The key block:
Ai Bi
Ai>Bi
Ai=1
Bi=0
Ai=Bi
Ai=Bi=0
or
Ai=Bi=1
Ai<Bi
Ai=0
Bi=1
142
Example:
Example: A 4-bit comparator slice
Outputs from a comparison
of 4 bits of lesser significance
143
Creation of an 8-bit comparator from 2 4-bit
comparators:
+5v
x0 x1 x2 x3 y0 y1 y2 y3
x4 x5 x6 x7 y4 y5 y6 y7
A0A1A2A3 B0B1B2B3
A0A1A2A3 B0B1B2B3
A<B
A=B
A>B
A<B
A=B
A>B
7485 #1
A>B A=B A<B
7485 #2
A>B A=B A<B
x>y x=y x<y
IC#1 compares the four MSB. IC#2 compares the
four LSB. The MSB chip has extension inputs so
that they do not interfere with the comparison.
Therefore: inputs A<B and A>B are tied low and
input A=B is tied high.
144
Two-chip propagation delay in comparing two
24-bit numbers.
145
Constructing a T-FF from a D-FF:
T
Out
Q
D
Q
CK
Constructing a JK-FF from an SR-FF:
J
CK
K
S
Q
R
Q
The problem with this circuit: unless the clock
pulse is very narrow the circuit will change state
multiple times under the input conditions J=K=1.
What is then needed:
J
CK
K
Pulse
narrowing
circuit
S
Q
R
Q
146
Pulse narrowing circuit:
odd #
…
Edge Triggered FF:
A flip flop that changes state at the edge of the
clock: either at the rising edge, or the trailing edge.
 Still another way of avoiding multiple transitions
when the clock is high, is to use a master-slave
flip-flop (JK).
Master
J
Slave
Q
CK
K
Q
147
During the rise of the clock the information is
latched into the master; during the fall of the clock
the information is transferred into the slave. The
master slave FF uses, therefore, level signals.
Master is
latched
Slave is
latched
No multiple transitions are possible with either an
edge-triggered FF or a master-slave FF.
148
Example: FF1: Edge-Triggered JK-FF
FF2: Master-Slave JK-FF
Let the output change at the trailing edge of the JK,
edge triggered FF. Let the output in the master latch
when the clock is high, and the output latch in the slave
when the clock is low.
Jin
Q
J
ETout
FF1
Kin
K
Q
J
MSout
FF2
Q
K
Q
ck
M S M S M S M S M S M S M S
ck
Jin
Kin
ETout
MSout
149
Generation of a delayed clock
D
oscillator
ock
ock
D
Q
DC
Q
DC
Q
C
Q
C
ock
ock
C
DC
 In many microprocessor applications there is a
need for a 2-phase clock.
150
Example circuit that generates a 2-phased clock.
Even # of inverters
ckd
J
Q
K
Q
ck
1
2
"1"
The inverters act as “delay element.”
The FF is edge triggered at the leading edge.
ck
ckd
Q
Q
1
 ckd  Q
2
 ckd  Q
151
Sequential Machine Design
Mealy machine structure:
Inputs
Input
Forming
Logic
(comb.)
Memory
Output
Forming Outputs
Logic
(comb.)
Moore machine structure:
Inputs
IFL
OFL
Outputs
Memory
152
Excitation Tables
For DFF:
Let Qn be the state (Q-value) at time n (also called
present state)
Let Qn+1 be the state at time n+1 (also called next
state)
The excitation table describes the input value
needed to the FF in order to change its state.
Qn Qn+1 D
0 0
0
0 1
1
1 0
0
1 1
1
153
For SRFF:
Qn Qn+1
0 0
0 1
1 0
1 1
S
0
1
0
R
J
0
1
K


0
1
0
For JKFF:
Qn Qn+1
0 0
0 1
1 0
1 1




1
0
Notice that for SRFF, S and R are not allowed to
be on at the same time. This restriction does not
hold for the JKFF.
154
For TFF:
Qn Qn+1
0 0
0 1
1 0
1 1
T
0
1
1
0
Sequential machines are divided into two kinds:
synchronous and asynchronous.
synchronous – driven by clocks
asynchronous – driven by input changes
Till otherwise stated, we will be dealing with
sequential machines which are synchronous.
155
Analyzing sequential machines
Circuit Comb. ckt.
Diagram Analysis
Excitation
function
Excitation
table
Example: Given the circuit:
x
DA
A
y
A
ck
DB
B
B
Excitation and output function:
D A  xB
DB  A
y  AB
Out
State
Table
156
Excitation table:
x
A
0
0
1
1
B
0
1
0
1
0
01
01
00
00
1
01
11
00
10
The entries are the values
of DADB based on the
excitation equations.
D A DB
Output table:
x
A
0
0
1
1
B
0
1
0
1
0
0
0
0
1
y
1
0
0
0
1
The entries are elements
of y.
157
Transition (Next State) and Output table:
Present State
A
0
0
1
1
B
0
1
0
1
x=0
0 1,0
0 1,0
0 0,0
0 0,1
x=1
0 1,0
1 1,0
0 0,0
1 0,1
Entries are elements
of NS,O values.
Next State,Output
State Table:
x
State 0
α β,0
β β,0
γ α,0
δ α,1
1
β,0
δ,0
α,0
γ,1
AB
00
01
10
11
State
α
β
γ
δ
Entries are
elements of
NS,O.
158
Timing diagram
Assume inputs change at the leading clock edge,
and states change at the trailing clock edge
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
ck
x
A
B
yout
00
α
01
β
11
δ
00
α
01
β
01
β
01
β
State
In the timing diagram we assume an initial state
of α (00).
159
State diagram
The state diagram describes the state table in a
pictorial way.
0,0
α
-,0
β
0,1
-,0
γ
1,1
1,0
δ
Every arc is
displayed with
the input, output
value.
If in state α: any input will move the machine to
state β and produce an output of 0. If in state β, an
input of 0 will leave the machine in state β and
produce an output of 0; an input of 1 will move the
machine to state δ and produce an output of 0, etc.
160
Synchronous machine design
We follow the opposite route: from word
description of the problem we create state diagram,
state table, excitation table, excitation function, and
finally the circuit.
Example: Design a counter of clock pulses that
outputs the sequence:
000, 011, 101, 111, 100, 000 …
The circuit has no inputs other than the clock.
State diagram:
000
a
100
e
b 011
d
c
111
101
161
Transition table: Let the FF outputs be Q1, Q2, Q3.
Let the Flip-Flops be JK.
PS
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
NS
Q1 Q2 Q3
0 1 1
  
  
1 0
0 0
1 1
1
0
1
1 0
0
  
Excitation table:
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
J1 K1 J2 K2 J3 K3
0  1  1 
  
  
1  
 1 0
 0 1
  
 0 
  
  
1  0
 0 
  0
  
1  1
162
Q1Q2
Q1Q2
Q3
00
01
11
10
Q3
00
01
00
11
10
   
1 
1 1 
0
Q3
01
J3
Excitation functions:
K1  Q3
J 2  Q1  Q3 , K 2  1
J3  Q1 ,
11
10
  0
1 
  
1
K2
J1  Q3 ,
11
10
11
10
  0
1 
  1
1
0
Q1Q2
00
0
01
J2
Q1Q2
01
Q3
K1
Q1Q2
00
10
0
J1
Q3
11
   1
1 
 0 0
  
1 
1  
0
0
Q1Q2
K 3  Q1Q2
Q3
00
01
   
1 
0 1 0
0
K3
163
The design:
"1"
J1
Q1
K1
Q1
J2
Q2
K2
Q2
J3
Q3
K3
Q3
Output
ck
Number of FFs
Let the # of states be S. The # of FFs, n, need to
satisfy 2n ≥ S
Example: For S=18 we need n=5.
164
Example: In a manufacturing line the signal x
provides information on various processes that go
on. The signal x provides serial information at
predetermined intervals controlled by a master
clock. In particular, a sequence of 110011 signifies
a completion of a special manufacturing phase.
Design a synchronous digital circuit that will
output a “1” whenever a sequence of 110011 has
been observed on line x. Thus the following output
z should be generated as a result of the following x:
x:
z:
0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1...
0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0...
Use SR FFs in your design.
165
Solution:
Before we create the state diagram we determine
the different states the circuit will need:
A = Initial state
B = The signal “1” has been observed
C = The signal “11” has been observed
D = The signal “110” has been observed
E = The signal “1100” has been observed
F = The signal “11001” has been observed
Notice that there is no need to remember the
“110011” state. We only need to output a “1” when
this sequence is detected.
166
State diagram:
B
1/0
0/0
Init
1/0
1/0
"1"
C
0/0
1/0
A
"11"
0/0
1/1
0/0
0/0
D
F
"110"
"11001"
1/0
E
"1100"
# of FFs needed = 3
0/0
167
State table:
PS
A
B
C
D
E
F
NS,O
x=0 x=1
A,0 B,0
A,0 C,0
D,0 C,0
E,0 B,0
A,0 F,0
A,0 C,1
State encoding (assignment)
State
A
B
C
D
E
F
Q1 Q2 Q3 Two states are unused:
0 0 0 010, 101.
0 0 1 Selection is relatively
0 1 1 arbitrary. State assignment
1 1 0 influences complexity of
1 0 0 hardware.
1 1 1
168
Transition table:
PS
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
NS,O
x=0
x=1
000,0
001,0
000,0
011,0
,
,
110,0
000,0
011,0
111,0
100,0
000,0
001,0
011,1
,
,
169
Output function:
Q1Q2
Q3x
00 01 11 10
00 0  0 0
 0 0
11 0 0 1 
10 0 0 0 
01
0
Z=Q1Q3X
Z
Excitation table for FF#1:
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x=0
0
0
S
x=1
0
0


0
0

10
01

0
01
01
01
R
S1R1
170
Excitation functions for FF#1:
Q1Q2
Q3x
00 01 11 10
00 0   0
Q1Q2
Q3x
00 01 11 10
00   0 1
 0 
11 0 0 0 
10 0 1 0 
  1 0
11   1 
10  0 1 
01
0
01
S1
R1
 Q1 Q2 x
 Q2 x  Q2 x  Q1 Q3
Excitation table for FF#2:
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x=0
0
0

0
0

01
01
x=1
0
10

0
10

01
0
S2R2
171
Excitation functions for FF#2:
Q1Q2
Q3x
00 01 11 10
00 0  0 0
Q1Q2
Q3x
00 01 11 10
00   1 
 0 1
11 1   
10 0  0 
  1 0
11 0 0 0 
10  0 1 
01
0
01
S2
R2
 Q1 Q2 x  Q3 x
 Q2 Q3  Q1 x
 (Q1Q2  Q3 )x
Excitation table for FF#3:
Q1 Q2 Q3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x=0
0
01

01
0

0
01
x=1
10
0

0
10

10
0
S3R3
172
Excitation functions for FF#3:
Q1Q2
Q3x
00 01 11 10
00 0  0 0
Q1Q2
Q3x
00 01 11 10
00    
 1 1
11    
10 0 0 0 
 0 0
11 0 0 0 
10 1 1 1 
01
1
S3  x
01
0
R3  x
Note that different state assignments would
have led to different realization. The best
state assignment is still an open problem.
173
The design:
x
S1
Q1
R1
Q1
Z
ck
S2
Q2
R2
Q2
S3
Q3
R3
Q3
174
State equivalence and machine minimization
 It is possible for a given machine to have
redundant states.
k-equivalence
 Two states, Si and Sj, of machine M are
distinguishable if, and only if, there exists at least
one finite input sequence which, when applied to
M, causes different output sequences, depending
on whether Si or Sj is the initial state.
 The sequence which distinguishes these states is
called a distinguishing sequence of the pair
(Si,Sj).
 If there exists for pair (Si,Sj) a distinguishing
sequence of length k, the states (Si,Sj) are said to
be k-distinguishable.
175
Example: Consider machine M1:
PS
A
B
C
D
E
F
NS,z
x=0
x=1
E,0
D,1
F,0
D,0
E,0
B,1
F,0
B,0
C,0
F,1
B,0
C,0
The pair (A,B) is
1-distinguishable.
The pair (A,E) is
3-distinguishable.
 States that are not k-distinguishable are said to be
k-equivalent.
In the above example, (A,E) are 2-equivalent.
 States that are k-equivalent are also r-equivalent
for all r<k.
 States Si and Sj of machine M are said to be
equivalent iff, for every possible input sequence,
the same output sequence will be produced
regardless of whether Si or Sj is the initial state.
176
The minimization procedure
We seek to partition the states of M such that two
states are in the same block iff they are equivalent.
 We start with partition P0 that corresponds to
0-distinguishability.
 We then compute P1 by placing those states having
the same outputs, under all inputs, in the same block.
 To create P2 (set of states that are 2-equivalent) we
observe that two states are 2-equivalent iff they are
1-equivalent, and all their successors are 1-equivalent.
 Procedure continues in this same manner, computing
P2, P3, …, Pm
 If for some k, Pk+1 = Pk the process terminates, and
defines the states that are equivalent as the states
contained in the same block of Pk.
177
Example: Consider again: (M1)
PS
A
B
C
D
E
F
NS,z
x=0
x=1
E,0
D,1
F,0
D,0
E,0
B,1
F,0
B,0
C,0
F,1
B,0
C,0
P0=(ABCDEF)
P1=(ACE)(BDF)
P2=(ACE)(BD)(F)
P3=(AC)(E)(BD)(F)
P4=(AC)(E)(BD)(F)
Defining α = (AC); β = E; γ = (BD); δ = F, we get
the minimal machine M1*:
PS
α
β
γ
δ
NS,z
x=0
x=1
β,0
γ,1
α,0
δ,1
δ,0
γ,0
γ,0
α,0
 To every machine M there corresponds a
minimal machine M* which is equivalent to M
and is unique up to isomorphism.
178
Asynchronous Machines
 Has no clock;
 State changes as a result of input changes;
 Uses feedback to produce the memory function;
 Uses gates rather than Flip-Flops;
 Simple example:
X
Z
Y
A change in either X or Y may cause a change in
Z, which after a delay may cause Z to change
again.
179
 The feedback variable along with system inputs
determine the values of these same feedback
variables.
 A fundamental-mode model has been used to
reflect this behavior. We consider the gates to
have 0 delay, while the delay element has a delay
of Δt.
Model for the previous circuit:
Feedback
variable z
Δt
X
Excitation variable
Ƶ
Y
Excitation function: Ƶ=Xz+XY
180
Excitation map:
XY
z
00 01 11 10
0
0
0
1
0
1
0
0
1
1
Ƶ
 Note that the value Ƶ takes on will also be the
value assumed by z after a delay of Δt.
 Information in the above map is, therefore,
dynamic.
 Assume X=Y=1, z=1  Ƶ=1 and this is a
stable state. (Ƶ=z)!
If X changes to 0, the output Ƶ will change to 0.
181
 According to the excitation map an unstable
situation of X=0, Y=1, z=1 will exist for a period
of Δt, after which the new stable state is entered:
X=0, Y=1, z=0
(Ƶ=z=0)
XY
z
The stable
state finally
reached.
00 01 11 10
0
0
0
1
0
1
0
0
1
1
The unstable state
that lasts for Δt.
 Stable states are identified on the map by a circle:
XY
z
00 01 11 10
0
0
0
1
0
1
0
0
1
1
Ƶ
Stable states
are those for
which Ƶ=z
182
 As seen before, system input changes force a
direct horizontal movement in the map.
 A horizontal movement may cause an indirect
vertical movement after Δt in order to reach a
stable state
 A primitive state diagram containing a number of
states equal to the number of cells can be drawn
from the map. The format lists
gate inputs/feedback variable.
 In the primitive state diagram:
1.Only in a stable state can system inputs be
changed. All transient states have the same
value of system inputs entering and exiting
from the state.
183
2.In order to leave a stable state, a system
input must change.
3.In order to cause a feedback variable
change, the system must pass through a
transient state.
4.Only one input can be changed in moving
from one stable state to another.
184
Example: Develop the excitation map and find the
stable states for:
We have:
C=0
AB
d
D  dB  AB  A C d
C=1
AB
d
00 01 11 10
00 01 11 10
0
1
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
1
1
0
D
 Map of D is split for C=0 and C=1.
 Stable states are those for which D=d.
185
Problems in asynchronous circuits
1. Oscillation:
AB
z
00 01 11 10
0
0
1
0
1
1
1
0
0
1
Ƶ
If the system is in state A=B=z=0 and B changes
from B=0 to B=1, a transient state is entered
(A=0, B=1, z=0). Since Ƶ changes to Ƶ=1, the new
state is A=0, B=1, z=1, which is again transient.
The system will oscillate between (A=0, B=1, z=0)
and (A=0, B=1, z=1).
2. Hazards:
This problem was discussed before. A hazard may
cause entering unwanted states.
186
3. Critical races:
Assume the state is e, and B changes from B=1 to
B=0. The next state should be x=y=11. But since
x=y=0 before the input change, two feedback
variables need to change.
Since they cannot change simultaneously, the
system will end up in either state b or d, depending
on which variable changes faster. This is a
critical race. Notice that when in state e, a change
from A=0 to A=1 creates a non-critical race (always
ends up in the same state x=y=1).
187
Example: Determine oscillations and critical races
in the following map.
Solution: A change from ABxy=1000 to
ABxy=1100 creates an oscillation between
ABxy=1100 and ABxy=1110.
A critical race exists while changing from
ABxy=0010 to ABxy=1010. Due to the double
change in feedback variables, the system may
either land in ABxy=1000 or ABxy=1011.
188
Basic design principles
 Normally there are several different circuits that
can satisfy the specs.
 We generally can define only the stable states.
 We need to add transient states to cause the
system to sequence through the proper states
without introducing any critical races.
Example: An input G gates the oscillator, Osc. If
Osc is high when G is on, the output does not go
high until the beginning of the next Osc cycle. If G
is deasserted (turned off) when Osc is high, the
output Y remains until Osc drops low.
189
The states are defined by (G,Osc/Y) values. In state
“a” G=Osc=Y=0. If Osc changes to high, no output
is generated, and the system moves to state “b”. If
G goes high at this time, again Y=0, and we move
to state “c” (time t1, Fig 10.12). Output is “1” when
moving into states “e” or “f”. The state diagram is
a vehicle to create the primitive excitation map.
190
There is one stable state for each row of the
excitation table. Transient states are added to cause
the proper movement between stable states. The
requirement that inputs must not be changed
simultaneously leads to “don’t care” conditions:
GOsc
00 01 11 10
Y
a
0
 d
a b c 
 b c d
a  e d
 f e d
a f e 
b
0
0
0
1
1
The primitive excitation table can be reduced
by merging states.
191
In the reduction process the “don’t care” conditions
can be taken to be anything. We, therefore, define
them in such a way that # of states will be
minimized; as we merge rows, we will not merge
similar rows when output differs:
 d
a b c 
 b c d
a  e d
 f e d
a f e 
a
b
 a
b
 a
 e d

a
f
c
e
d
d
192
The new excitation table (minimized)
GOsc
00 01 11 10
Y
a
b
d
0
a
 e d
0
a
f
1
c
e
d
We, therefore, need 2 state variables. The
assignment of state variable is done arbitrarily,
even though it affects the final circuit
implementation:
x
z
row 1
0
0
row 2
0
1
row 3
1
1
1
0
unused
We now choose the ‘s so that implementation will
be minimized.
193
 &  both mean don’t care.
xz
GOsc
00
01
11
10
00
0
0
0
0
01
0
0
0
0
11
1
1
1
1
10




Out=X
Based on the excitation equations there is no xfeedback! So, there is practically only one
feedback variable.
194
Example: Redesign the following circuit to be more reliable.
The modification:
195
The redesigned circuit:
Design of a pulse synchronizer
Circuit is similar to the gated clock circuit, except
that a maximum of 1 clock pulse can appear at the
output, even if the input remains on for several
clock periods.
196
If the control signal, W, is asserted when the clock
signal, C, is low and remains on when C goes high,
the output, Out, is coincident with the positive
half-period of C.
If C is high when W goes high and W remains
asserted until C goes low and returns high for a
second time, Out, is coincident with the second
assertion of C.
If C is high when W goes high, but W returns low
before the second assertion of C, Out=0. We also
assume that successive assertions of W will be
separated by at least one-half clock period.
197
State diagram includes all combination of
(C, W, Out).
The state diagram follows the word description of
the problem. From the state diagram we create the
primitive excitation map, where there is one stable
state per row.
198
The primitive excitation table is not minimized.
After merging states we get 4 distinct rows.
For example, the first three rows can be merged to
a
b
c
d
199
We analyze two assignments.
Assignment (a) has problems. Assignment (b) is
received by switching rows 3 and 4.
This
assignment
has
problems.
The circuit implementation appears in
p.198 (notes)
This
assignment
is ok.
200
Programmable Logic Devices (PLDs)
Hardwired system: a digital system where components
are connected with wires.
On the other hand, a PLD is an IC chip that includes
arrays of logic elements and allows the user to specify
the connections among the elements.
 The user does not have direct access to every
connection on the chip.
 Some connections may be fixed while others may be
programmable.
 There are several kinds of PLDs:
o Combinational PLDs: Read-Only Memories (ROM),
Programmable Logic Arrays (PLA), Programmable
Array Logic (PAL)
o Sequential PLDs: Programmable Logic Sequencer
(PLS), Field Programmable Gate Array (FPGA),
Registered PLA, Registered PAL.
201
 PLDs are part of a larger group of Application
Specific Integrated Circuits (ASIC)
 Advantage of use of PLDs is quick turn-around design
time.
 Disadvantage of use of PLDs is performance lower
compared to custom made.
 PLDs come in two different flavors: user-specified
and field programmable.
o User-specified: user tells the manufacturer how to
interconnect the elements.
o Field-programmable: user makes the connections
himself.
 Circuits in a PLD can either be un-connected, or
over-connected.
o If unconnected – programming means specifying
which connections to make.
o If overly-connected – programming means which
connections to break
202
 A connection is normally made by placing a
transistor switch between components.
 A connection is removed (normally a fusable link)
by passing large current through the link.
 Removal of fusable links is normally irreversible.
 A “programmer” is an equipment used to
program the PLD.
 The Xilinx FPGA is a reconfigurable PLD.
 Other reconfigurable PLDs: erasable ROM
(EPROM), and electrically erasable ROM
(EEROM).
203
ROM organization
 ROM can be visualized in terms of a decoder
followed by a set of OR gates.
 For n input lines there are 2n AND gates in the
minterm decoder.
 For an m-bit output word, there are m OR gates
that can be programmed to “pick-up” selected
minterms.
 Consider implementing the following ROM:
Input
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Output
x 0 x1 x2 x3
0 0 1 0
1 0 1 1
0 1 0 1
1 0 0 1
1 1 0 1
0 1 1 0
1 0 0 0
0 1 1 0
204
The implementation:
205
PLAs
 Can be viewed as a ROM that has had a large
percentage of its minterms (AND gates) deleted.
 In a ROM only the OR gates connections are
programmable. In a PLA both, the AND, and the
OR gates connections are programmable.
 A 16×96×8 PLA is a PLA with 16 inputs, 96
minterms (product terms), and 8 outputs.
 Primary application of PLA is function
realization.
 PLAs are less expensive than ROMs.
206
Simplified schematic representation:
N×M×K
Field Programmable
Logic Array.
The EXOR gates pass
true value if the other
input is connected to
ground.
If no connection (fuse
blown) (like in O2) it
passes the complement
(since 1 x  x )
207
Things to notice:
 If there are more product terms than necessary to
realize a function – minimization is not
important.
 If we are constrained and there are not enough
product terms – minimization is important.
 The ability to invert the outputs of any OR gate
allows the possibility of realizing the
complement of a desired function and then
inverting it.
 What should be minimized in PLA design? # of
inputs to each AND gate is fixed! # of OR gates
is fixed!
The only remaining variable to control is the
number of AND gates!
208
Example: Design the following functions using a
PLA. (Use smallest # of AND gates)
F1A,B, C, D  1, 3, 12, 13, 14, 15 
F2 A,B, C, D  5, 10, 11, 12, 13, 15 
F3 A,B, C, D  0, 3, 4, 7, 8, 10, 11
Solution:
AB
CD 00 01 11 10
00 0 0 1 0
AB
CD 00 01 11 10
00 0 0 1 0
AB
CD 00 01 11 10
00 1 1 0 1
01
1
0
1
0
01
0
1
1
0
01
0
0
0
0
11
1
0
1
0
11
0
0
1
1
11
1
1
0
1
10
0
0
1
0
10
0
0
0
1
10
0
0
0
1
F1
F2
We next compute all minimal expressions of
F1, F1, F2 , F2 , F3 , F3
F3
209
AB
CD 00 01 11 10
00 0 0 1 0
AB
CD 00 01 11 10
00 1 1 0 1
01
1
0
1
0
01
0
1
0
1
11
1
0
1
0
11
0
1
0
1
10
0
0
1
0
10
1
1
0
1
F1
One choice for F1:
F1  AB  A B D
F1
AB
CD 00 01 11 10
00 1 1 0 1
Two choices for F1:
01
0
1
0
1
F1  AB  A B  A D
11
0
1
0
1
F1  AB  A B  B D
10
1
1
0
1
F1
We continue to do the same for F2, F2, F3 , F3 :
F2  ABC  B C D  ACD  A B C
F2  ABC  B C D  ABD  A B C
F2  A D  AC  B C  BCD
210
F3  A C D  A B C  ACD  B C D
F3  A C D  A B C  ACD  A B D
F3  A C D  A B C  ACD  B C D
F3  A C D  A B D  ACD  B CD
F3  AB  C D  AC D
 In determining whether F or F should be used, we
consider not only the functions that have fewest # of
terms, but also product terms that can be used to share
between function. For example, F1 requires 2 product
terms, while F1 requires three.
Furthermore, the AB term of F1 is common to F3 ,
thus F3 can be implemented with only two additional
gates. For this example either F2 or F2 could be used.
In the next foil we implement F1 , F2 and F3 .
211
Implementation of F1 , F2 , F3 uses 8 AND gates.
PALs
 Trademark owned by American Micro Devices
(AMD).
 OR gates make fixed connections to certain AND
gates outputs
 PAL is less flexible than PLA, but also less
expensive and easier to program
212
Example: A PAL with 4 inputs, 4 AND gates, and
4 OR gates. Input connections to the AND gates
are programmable. OR gate connections are fixed.
The PAL implements:
Ο1  Ι ΒΙ D  Ι Α Ι Β Ι D
Ο 2  Ι A Ι Β ΙC  Ι Α Ι Β Ι D
Ο3  Ι Β Ι D  Ι Α Ι Β Ι C
Ο 4  Ι A Ι Β ΙC  Ι A Ι ΒΙC Ι D
213
 AMD’s PAL 16L8 is a combinational PAL
having 16 inputs and 8 outputs.
 The L specifies combinational. R denotes
registered (sequential)
 Schematic of 16L8 is show on page 216.
 Each AND is 32-input (16+16 for
uninverted/inverted positions)
 Upper AND gate of each group does not drive an
AND gate, but drives the enable of a tri-state
inverting buffer:
E
I
O
I
0
1
E
0
1
1
O
High Ƶ
1
0
High Ƶ means
floating
214
 If all the 32 fusible links connected to this AND
gate are blown, the tri-state buffer will be
enabled. In this case each blown input floats, and
is considered at a value “1”.
 There are 10 dedicated input pins: I0 to I9. The
normal and inverted value being connected to a
vertical line.
 The six other lines I/O2 through I/O7 can be used
for either input of output lines. When used for
input lines, the three-state buffer should be
disabled (E=0).
 The 32 vertical lines can be driven by up to 16
inputs (10 normal + 6 I/O).
 The other seven AND gates of a group are ORed
to form a logic expression.
215
 Often only a few of these gates will be involved
in the implementation. The unused AND gates
need to be deactivated.
Since normally all inputs are connected by
leaving all these connections intact the
corresponding AND gate is deasserted. ( x  x  0 !)
 We, as an example, show the realization using
16L8 PAL of two 4 variable functions:
Y  A B C D  BCD
Z  AB CD
 Notice that we use the Y and Z expressions,
since the buffer will invert them to Y and Z .
 We use inputs I0, I1, I3 and I/O5
216
217
 The following is the personalization of the 16L8 to
implement Y and Ƶ.
 The unshaded gates represent circuits that have been
programmed.
 The presence of a fuse or connecting link is
represented by an x while no mark indicates a blown
fuse.
 The shaded AND gates represent circuits that have
had no fuses blown (were deactivated, x  x  0 )
 The tri-state buffers of Y and Z are enabled by
blowing all fuses to the AND gates that drive these
two buffers.
218
 Variable D is applied on I/O5 and the tri-state
buffer driving this pin is disabled. This is done by
leaving all fuses that drive the corresponding
AND gate intact.
 Pins I2 and I4 are tied to ground. The enabling
AND gate (to I/O5) will have some inputs
connected to ground and will never enable the
tri-state buffer.
 Same thing is true of all shaded AND gates, ie.
the outputs of all these gates will remain “0”, and
not influence Y or Z .
 The following fuse map presents the PAL
personalization.
219
 Variable A is connected to vertical line 0, while A is connected
to line 1. Similarly, B is connected to line 2, B to line 3. C is
connected to line 8, C to line 9. D to line 14, D to line 15.
 Notice that the tri-state drivers invert Y and Z to form Y and Z:
Y  Y, Z  Z
220
Combinational PLD-based state machines
 A state machine may be designed using ROM:
Inputs
ROM
A
D
D
R
E
S
S
O
U
T
P
U
T
Outputs
FFs
 Machine is personalized by the ROM contents.
 Next state & outputs are completely determined
by the present state and the inputs.
 ROM uses the system inputs and present state as
input addresses.
221
 ROM is programmed to produce the correct next
state conditions and output responses.
 Note that:
# of inputs + # state FFs = # of required ROM
address bits
# of outputs + # state FFs = ROM word size.
Example: Given a 5-input, 4-output system with
3DFFs, what size ROM is needed?
Solution: # Address bits = 5+3 = 8.
Therefore the ROM will need 28 = 256 words of
width 4 + 3 = 7 bits each. The minimum size ROM
is therefore 256 × 7.
222
Example of state machine design:
(a) and (b) are ROM personalization of different
circuits.
223
Signetics programmable logic sequencer (PLS)
Typical PLS chip:
PLS155 is a 16×45×12 device. It has 16 inputs (4
dedicated + 12 programmable I/O pins that can be
made either input or output), 45 product terms (and
4 edge triggered FFs), and 12 output lines.
224
Example:
225
Implementation: