Handbook of Silicon Based MEMS
Materials and Technologies
Micro & Nano Technologies
Series Editor: Jeremy Ramsden
Professor of Nanotechnology
Microsystems and Nanotechnology Centre, Department of Materials
Cranfield University, United Kingdom
The aim of this book series is to disseminate the latest developments in small scale technologies with a particular
emphasis on accessible and practical content. These books will appeal to engineers from industry, academic and
government sectors.
9780815515944
Veikko Lindroos, Markku Tilli, Ari Lehto and Teruaki Motooka, Handbook of Silicon Based
MEMS Materials and Technologies (2010)
9780815515838
Waqar Ahmed and M.J. Jackson, Emerging Nanotechnologies for Manufacturing (2009)
9780080964546
Richard Leach, Fundamental Principles of Engineering Nanometrology (2009)
9780815520238
Jeremy Ramsden, Applied Nanotechnology (2009)
9780815515869
Matthew Hull and Diana Bowman, Risk Governance of Nanotechnology (2009)
9780815515432
Nam-Trung Nguyen, Micromixers (2008)
9780815515449
Jean Berthier, Microdrops and Digital Microfluidics (2008)
9780815515777
Behraad Bahreyni, Fabrication and Design of Resonant Microdevices (2008)
9780815515739
Francois Leonard, The Physics of Carbon Nanotube Devices (2009)
9780815515784
Mamadou Diallo, Jeremiah Duncan, Nora Savage, Anita Street and Richard Sustich,
Nanotechnology Applications for Clean Water (2009)
9780815515876
Rolf Wüthrich, Micromachining Using Electrochemical Discharge Phenomenon (2009)
9780815515791
Matthias Worgull, Hot Embossing (2009)
Handbook of Silicon
Based MEMS Materials
and Technologies
Veikko Lindroos,
Markku Tilli,
Ari Lehto and
Teruaki Motooka
William
Andrew
Applied Science Publishers
William Andrew is an imprint of Elsevier
The Boulevard, Langford Lane, Oxford OX5 1GB, UK
30 Corporate Road, Burlington, MA 01803
First edition 2010
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Notices
Knowledge and best practice in this field are constantly changing. As new research and experience broaden our
understanding, changes in research methods, professional practices, or medical treatment may become necessary.
Practitioners and researchers must always rely on this own experience and knowledge in evaluating and using any
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Preface
In summer 2006 we were approached by William
Andrew Publishing about producing a MEMS related
handbook. As the general guideline from the publisher
was to keep in mind that they are particularly seek­
ing book content geared towards practical applications
rather than theory.
During the summer of 2006 we matured our under­
standing of the state-of-art as well as the further devel­
opment and needs of MEMS materials and technologies.
As a result of such a maturation process, we understood
that there are currently many handbooks and textbooks
covering MEMS components, but their focus is more
in the device physics and design rather than in mate­
rials and manufacturing processes. Also, it has been
experienced in practice, that there is a need for a book
covering starting materials as well as the most impor­
tant process steps in bulk micromachining fulfilling the
needs of a device design engineer as well as process or
development engineer working in manufacturing proc­
esses. Although many comprehensive textbooks cover,
for instance, silicon from many aspects, they are not
worn out in the hands of MEMS engineers, as they are
too specialized. That is why a special emphasis was put
on silicon, the most important starting material used in
MEMS devices, different varieties of silicon wafer types
used in MEMS process, material properties and meas­
urement techniques as well as analytical methods used
in the silicon materials characterization. The aim is not
to go too deep into the scientific details but, instead,
to give a broader overview tailored for the needs of the
MEMS industry. Also, in a similar manner, important
selected process steps in MEMS manufacturing are
treated to give an overview of the most recent progress.
The MEMS industry is now at a turning point;
MEMS industry has been so far mainly driven by auto­
motive and industrial applications—now the industry
driver will be consumer electronics, more precisely
portable electronics: mobile phones, MP3 players,
digital cameras, camcorders, etc. The growth of the
MEMS industry is forecast to be close to 20% annu­
ally, and there will be new entrants in the industry, who
need to get basic understanding of the MEMS materi­
als and processes. Consumer electronics applications
are also very cost sensitive. Therefore, it is essentially
important to minimize the overall device costs and to
understand the whole supply chain. By applying proper
material selection it makes possible to influence on the
MEMS device processing costs. In order to fully under­
stand the present state-of-the-art and, in particular,
the future trends of MEMS technology and industry,
the Editors appreciate this opportunity to include the
invited introductory overview contribution “Impact of
Silicon MEMS – 30 Years After” by Dr. Tapani Ryhänen
from Nokia Nanoscience Centre at the University of
Cambridge.
Based on the above motivation of the present state as
well as the further development and needs, we have pre­
pared the present “Handbook of Silicon Based MEMS
Materials and Technologies”. The book consists of five
parts:
Part I Silicon as MEMS material
Part II Modeling in MEMS
Part III Measuring MEMS
Part IV Micromachining technologies in MEMS
Part V Encapsulation of MEMS components
These five parts are consisting of altogether 42 chap­
ters written by 73 world class MEMS contributors from
12 countries from Europe, North America and Asia. In
addition to the general Editors of the book there were
also invited and nominated additional Part Editors
for each part of the book; i.e., Markku Tilli for Part I,
Teruaki Motooka and Risto Nieminen for Part II, VeliMatti Airaksinen for Part III, Helmut Seidel for Part IV
and Ari Lehto and Heikki Kuisma for Part V.
During the actual course of the writing process of the
book, there were arranged, in addition to the regular edi­
torial meetings, also “MEMS book author meetings,” once
or twice annually, in order to maintain the common scope
and objective for a uniform compilation of the book.
Finally, the Editors would like to express their great
appreciation to all of their fellow contributors for this
unique window of opportunity to work with them,
resulting in a comprehensive MEMS handbook, which
illustrates a global cutting edge knowledge and exper­
tise within the most vigorously growing industry today.
Furthermore, the Editors are grateful for the appropriate
and constructive co-operation with the publishers, i.e.
William Andrew (WA) and Elsevier, since its acquisition
ix
Preface
of WA in January 2009. Our particular thanks go to
Dr. Nigel Hollingworth of WA as well as to Matthew
Deans, Melanie Benson and Renata Corbani of Elsevier
for their valuable co-operation during the course of the
work. Finally, the Editors are grateful to the Helsinki
x
University of Technology, which will be a member of
the new Aalto University to be established at the begin­
ning of the year 2010, for providing various premises,
such as secretarial and computational services, for the
needs of the editorial work.
List of Contributors
Timo Aalto
VTT Technical Research Centre of Finland, P.O. Box
1000, FI-02044 VTT, Finland
Veli-Matti Airaksinen
Helsinki University of Technology, P.O. Box 3500, FI­
02015 TKK, Finland
Marco Amiotti
SAES Getters S.p.A., Viale Italia 77, 20010 Lainate
(Milan), Italy
Olli Anttila
Silfex Incorporated - A Division of Lam Research
Corporation, 950 South Franklin Street, Eaton, Ohio
45320, USA
Paul A. Anzalone
FEI Company, P.O. Box 332, Merrimack, NH 03054, USA
Abhinav Bhushan
University of California, Department of Mechanical and
Aeronautical Engineering - College of Engineering - Bainer
Hall - One Shields Avenue-Davis, CA 95616, USA
Antonio Bonucci
SAES Getters S.p.A., Viale Italia 77, 20010 Lainate
(Milan), Italy
Cristina Davis
University of California, Department of Mechanical
and Aeronautical Engineering - College of Engineering Bainer Hall - One Shields Avenue - Davis, CA 95616,
USA
Viorel Dragoi
EV Group, E. Thallner GmbH, DI Erich Thallner
Strasse 1, A-4782 St. Florian/Inn, Austria
Simo Eränen
VTT Technical Research Centre of Finland, P.O. Box
1000, FI-02044 VTT, Finland
Sami Franssila
Helsinki University of Technology, P.O. Box 3500,
FI-02015 TKK, Finland
Alois Friedberger
EADS Innovation Works, IW-SI, 81663 Munich,
Germany
Maria Ganchenkova
Helsinki University of Technology, P.O. Box 1100,
FI-02015 TKK, Finland
Lucille Giannuzzi
FEI Company, Hillsboro, OR 97124, USA
Jakub Bruzdzinski
The Nordic Hysitron Laboratory, Helsinki University of
Technology, P.O. Box 6200, 02015 TKK, Finland
Miguel Gosálvez
Dept. Micro Nanosystems Engineering,
University, 464-8603 Nagoya, Japan
Robert Candler
UCLA Department of Electrical Engineering,
Department of Electrical Engineering, 6731-H Boelter
Hall, Los Angeles, CA, 90095, USA
Jakub Gronicz
The Nordic Hysitron Laboratory, Helsinki University of
Technology, P.O. Box 6200, FI-02015 TKK, Finland
Kuo-Shen Chen
National Cheng-Kung University, Tainan, Department of
Mechanical Engineering, National Cheng-Kung University,
1 University Rd., Taiwan, 70101, R.O.C.
Andrea Conte
SAES Getters S.p.A., Viale Italia 77, 20010 Lainate
(Milan), Italy
Nagoya
Atte Haapalinna
Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland
Eero Haimi
Helsinki University of Technology, P.O. Box 6200,
FI-02015 TKK, Finland
Kimmo Henttinen
Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland
xi
List of Contributors
David Horsley
University of California, Davis, Department of
Mechanical and Aeronautical Engineering, University of
California, Davis, One Shields Ave., Davis, CA 95616,
USA
Akihisa Inoue
Tohoku University, Institute for Materials Research,
2-1-1 Katahira Aoba-ku, Sendai 980-8577, Japan
Brandon Van Leer
FEI Company, Hillsboro, OR 97124, USA
Ari Lehto
Helsinki University of Technology, P.O. Box 6200,
FI-02015 TKK, Finland
Christina Leinenbach
Robert Bosch GmbH, P.O.Box 10 60 50, 70049
Stuttgart, Germany
Henrik Jakobsen
Institute for Microsystem Technnology, Faculty of
Technology and Engineering, Vestfold University
College, P.O. Box 2243, N-3103 Tønsberg
Paul Lindner
EV Group, E. Thallner GmbH, DI Erich Thallner
Strasse 1, A-4782 St.Florian am Inn, Austria
Kerstin Jonsson
NanoSpace AB, Uppsala Science Park, SE-751 83,
Uppsala, SWEDEN
Veikko Lindroos
Helsinki University of Technology, P.O. Box 6200,
FI-02015 TKK, Finland
Dirk Kähler
Advanced Electronic Packaging, Fraunhofer Institut
für Siliziumtechnologie, Fraunhofer Str. 1, D-25524,
Itzehoe, Germany
Giorgio Longoni
SAES Getters S.p.A., Viale Italia 77, 20010 Lainate
(Milan), Italy
Hannu Kattelus
VTT Technical Research Centre of Finland, P.O. Box
1000, 02044 VTT, Finland
Jari Mäkinen
Okmetic Oyj
P.O. Box 44, FI-01301 Vantaa, Finland
Roy Knechtel
X-FAB Semiconductor Foundries AG, Haarbergstraße
67, D-99097 Erfurt, Germany
Peter Merz
MEMS
Department,
Fraunhofer
Institut
für
Siliziumtechnologie, Fraunhoferstrasse 1, D-25524,
Itzehoe, Germany
Kathrin Knese
Robert Bosch GmbH, Automotive Electronics (AE/
EST2), Postfach 13 42, 72703 Reutlingen, Germany
Douglas J. Meyer
AZonic Solar, Mesa, AZ, USA
2753 East El Moro Ave, Mesa, AZ 85204, USA
Kai Kolari
VTT Technical Research Centre of Finland, P.O. Box
1000, FI-02044 VTT, Finland
Marco Moraja
SAES Getters S.p.A., Viale Italia 77, 20010 Lainate
(Milan), Italy
Mika Koskenvuori
Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland
Teruaki Motooka
Dept. of Materials Science & Engineering Kyushu
University, Motooka 744, Fukuoka 819-0395, Japan
Heikki Kuisma
VTI Technologies Oy, P.O. Box 27, FI-01621 Vantaa,
Finland
Adriana Lapadatu
SensoNor Technologies AS, P.O. Box 196, N-3192
Horten, Norway
Franz Laermer
Robert Bosch GmbH, Corporate Sector Research and
Advance Engineering, Microsystems (CR/PJ-TOP54),
Postfach 10 60 50 , 70049 Stuttgart, Germany
xii
Gerhard Müller
EADS Innovation Works, IW-SI Sensors, Electronics &
Systems Integration, 81663 Munich, Germany
Shijo Nagao
The Nordic Hysitron Laboratory, Helsinki University of
Technology, P.O. Box 6200, FI-02015 TKK, Finland
Risto Nieminen
Helsinki University of Technology, P.O. Box 1100,
FI-02015 TKK, Finland
List of Contributors
Roman Nowak
The Nordic Hysitron Laboratory, Helsinki University of
Technology, P.O. Box 6200,FI- 02015 TKK, Finland
Scott Sullivan
Disco Hi-Tec America, Inc., 3269 Scott Blvd. Santa
Clara, CA 95054-3011, U.S.A.
Juuso Olkkonen
VTT Technical Research Centre of Finland, P.O.Box
1000, FI-02044 VTT, Finland
Tommi Suni
VTT Technical Research Centre of Finland, P.O. Box
1000, FI-02044 VTT, Finland
Kuang-Shun Ou
Department of Mechanical Engineering, National
Cheng-Kung University, 1 University Rd., Taiwan,
70101, R.O.C.
Tuomo Suntola
Picosun Oy, Tietotie 3, FI-02150 Espoo, Finland
Jari Paloheimo
Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland
Riikka Puurunen
VTT Technical Research Centre of Finland, Tietotie 3,
Espoo, Finland
Wolfgang Reinert
Advanced Electronic Packaging, Fraunhofer Institut
für Siliziumtechnologie, Fraunhofer Str. 1, D-25524,
Itzehoe, Germany
Steve Reyntjens
FEI Company, PO Box 80066, 5600 KA Eindhoven,
The Netherlands
Markku Tilli
Okmetic Oyj, P.O. Box 44, FI-01301 Vantaa, Finland
Ilkka Tittonen
Helsinki University of Technology, P.O. Box 3500,
FI-02015 TKK, Finland
Santeri Tuomikoski
VTI Technologies Oy, P.O. Box 27, 01621 Vantaa,
Finland
Örjan Vallin
Uppsala University, The Ångström Laboratory, Solid
State Electronics, Box 534, SE 75121 Uppsala, Sweden
Timo Veijola
Helsinki University of Technology, P.O. Box 3000,
FI-02015 TKK, Finland
Tapani Ryhänen
Nokia Research Centre, Eurolab, c/o Nanoscience
Centre, University of Cambridge, 11 J J Thomson
Avenue, Madingley Road, Cambridge, CB3 0FF, UK
Eeva Viinikka
Culminatum Innovation, Tekniikantie 12, FI-02150
Espoo, Finland
Lauri Sainiemi
Helsinki University of Technology, P.O. Box 3500,
FI-02015 TKK, Finland
Oliver Wilhelmi
FEI Company, PO Box 80066, 5600 KA Eindhoven,
The Netherlands
Hele Savin
Helsinki University of Technology, Espoo, P.O. Box
3500, FI-02015 TKK, Finland
Piotr Zachariasz
The Nordic Hysitron Laboratory, Helsinki University of
Technology, P.O. Box 6200, FI-02015 TKK, Finland
Helmut Seidel
Universität
des
Saarlandes,
Lehrstuhl
für
Mikromechanik, Mikrofluidik/Mikroaktorik, Postfach
15 11 50, D-66041 Saarbrücken, Germany
Irena Zubel
Faculty of Microsystem Electronics and Photonics,
Wroclaw University of Technology, Janiszewskiego
11/17, 50-372 Wroclaw, Poland
Parmanand Sharma
Tohoku University, Institute for Materials Research,
2-1-1 Katahira Aoba-ku, Sendai 980-8577, Japan
xiii
Overview
Impact of Silicon MEMS—30
Years After
Tapani Ryhänen
Nokia Research Centre, Cambridge, UK
Introduction
Silicon deforms elastically and is a very robust mechanical
material. Silicon has small thermal expansion, high speed of
sound and very low intrinsic mechanical losses. There exist
various methods for both isotropic and anisotropic etching of silicon. The well controlled anisotropic etching of
silicon especially has enabled the fabrication of microscale
mechanical structures and devices. When these mechanical characteristics and the micromachining are combined
with the mass scale manufacturing solutions from the IC
industry, we have a platform for producing micromechanical sensors and actuators in huge volumes at low cost.
First mechanical characterization and experiments in
chemical wet etching of silicon were already carried out
in the 1950s; and the industrial scale MEMS was born
in the late 1970s.
Today the various devices and even smaller objects of
our physical world are becoming extensively connected
to the digital information networks. We can say that the
physical and digital worlds are merging. Smaller and
smaller physical objects can be indexed by RF ID tags
and other electrical labels. Small processors and communication capabilities can be integrated into a variety
of small physical objects. The microelectromechanical
components and systems (MEMS) developed over the
past 30 years form the technology platform that enables
sensing and even actuation in these small devices.
Here the development of MEMS technologies is presented from the perspective of the mobile communication industry—from the rise of automotive applications
of MEMS sensors to the expansion of MEMS components into consumer products. We have seen the first
expressions of new user interface concepts based on
capabilities to sense, compute and create an action in
real time. However, this pervasive capability of sensing,
computing and communication means a complete new
era of mobile devices and related digital services.
This book is a demonstration of the maturity of the
silicon MEMS technologies. The silicon micromechanics,
measurement electronics and the packaging technologies
have all been developed to a level where very large volume manufacturing is possible. We are ready to take the
next leap towards the future devices and digital services.
Towards Mass Volumes of MEMS
Devices
Early Visions
When Kurt E. Petersen wrote his famous review [1] of silicon micromechanics in 1982, there existed already eight
companies working in the field. He covered nearly two
hundred essential references in his paper. Above all the
vision of the applications and opportunities was already
well understood. Petersen discussed a very broad set of
potential applications with commercial significance, such
as, accelerometers, pressure transducers, torsional mirrors, resonant gate transistors, light modulators, resonating
beam arrays, inkjet printer heads, and microelectromechanical switches. The research community was already
formed: for example, the IEEE Transducers conference was organized already in 1969, and the Sensors and
Actuators journal was established in 1980. The first large
volume application of MEMS was only some years away.
xv
Overview
Fig 1 l Resonant gate transistor published in 1968 by William E. Newell and his coworkers [8].
Most of the concepts of micromechanical devices and
fabrication technologies go back in time to the 1960s and
the early 1970s. The mechanical characteristics of single crystalline silicon, the anisotropic etching of silicon
by potassium hydroxide (KOH) and several concepts of
micromechanical devices were studied [2–6]. An interesting example of early device concepts is shown in Fig. 1.
W.E. Newell and his coworkers [7, 8] published a resonant gate transistor based on a micromechanical resonator made of electroplated gold in 1967.
Integration of micromechanical structures, such as
resonators, was a natural continuum from the pre-silicon
electronics to the early concepts of silicon integrated
devices. The first commercial application by Hewlett
Packard used a MEMS cantilever based frequency
detector in frequency synthesizers in 1980 [9]. In spite
of these early concepts, the development of practical
commercial applications based on MEMS resonators has
taken nearly 30 years, even today very few commercial
devices exist besides the scientific instruments, such as,
the resonating cantilevers of the atomic force microscopes [10, 11] and the biosensors [12].
The capability to create large arrays of similar components with precise dimensions enabled new device
concepts. Furthermore, the possibility to benefit from
the fabrication capabilities that were scaling up in the
IC industry created the starting point towards the commercial applications of MEMS.
Ink Jet Printer Nozzles Create the
Industry
This capability to manufacture precise components
and arrays of micromachined structures practically
enabled the ink jet printers during the 1980s. IBM
xvi
demonstrated [13, 14] the value of silicon micromachining to achieve the necessary printing precision with
the integrated methods to control and manage the inks
in the same micromachined device. The first mass volume application of silicon MEMS was created, and the
ink jet printers became the main stream of printing in
the growing information technology market.
The electrostatic control of ink jets [15] for printing purposes was studied in the beginning of the 1970s.
The capability to etch the ink jet nozzles into the silicon
wafer using anisotropic KOH wet etching and to integrate the control electrodes into the same device using
thin film and semiconductor processes enabled the sufficient miniaturization to improve the quality of ink jet
printing to the level where the commercial solutions
were possible.
Still today the ink jet printer application forms one
third of the total MEMS market. Today the printing
is expanding as a paradigm to electronics manufacturing [16]. Reel-to-reel manufacturing solutions based on
either inorganic or organic inks will be one of the future
solutions for manufacturing low cost electronics.
Automotive Applications Drive the
Reliability and the Quality
The automotive applications of pressure and motion
sensors practically created the MEMS industry. The
manifold air pressure (MAP) sensor introduced by Ford
in the mid seventies was the first micromechanical sensor in mass volumes. The accelerometers [17–19] were
introduced to replace mechanical switches in airbag
launchers, and later they enabled sophisticated chassis
control systems.
Overview
The automotive industry already in the 1980s was
characterized by advanced project management and
quality control that included all the module manufacturers and subcontractors. The duration of product
development projects was long and required a commitment for several years. The MEMS developers soon
learned to apply these strict rules of project and quality
management. The high requirements for reliability created long development projects with careful testing and
verification phases.
The automotive applications also created the requirements for the sensor electronics, such as voltage levels and system interfaces, and for the sensor module
packaging. Robust system-on-package solutions were
created. Operating temperatures and shock tolerance
were extremely demanding. In addition, the frequency
dependence of the sensors in chassis control and airbag
launchers required very careful control of intrinsic gas
damping and structural parameters.
The motion sensors in automotive applications were
soon divided into two categories: the high performance
3–5 g sensors for measurement of the motion of the
chassis of the vehicle and the low cost 50–200 g sensors
for the airbag launchers. This created the distinct paths
for the development of the manufacturing solutions.
Leaps Towards a Generic
Manufacturing Platform
The two paradigms of micromachining develop almost
in parallel. In the beginning the anisotropic etching of
bulk silicon to form microstructures into the silicon
wafer was a more efficient strategy [20]. The bulk
micromachining benefits from the optimal mechanical
characteristics of the single crystalline silicon. The doping of the silicon wafers and the optimization of their
characteristics for chemical etching required specific
development by the wafer manufacturers.
Even the simplest MEMS devices require insulating layers. The successful practical method [18, 20]
was to use a sandwich of silicon and borosilicate glass
wafers. The wafers were bonded together by a so called
anodic bonding process. However, the difference in the
thermal expansion of the glass and silicon wafers was a
problem causing strong temperature dependence and
even warping or buckling of the micromechanical structures. The solution was to use only very thin insulating
glass layers between silicon wafers [19] . Later the glass
manufacturers, such as, Corning and Hoya, introduced
glass wafers with thermal expansion characteristics that
matched the silicon.
Bulk micromachining enabled several different products [20]: pressure sensors, accelerometers, lab-on-chip
devices, etc. As the bulk micromachining provided an
inherent wafer level packaging of the micromechanical
structures, the very accurate control of the gas damping
of accelerometers or the reference pressure of the absolute pressure sensors was feasible.
The other paradigm was to grow a polysilicon thin
film on top of a sacrificial silicon dioxide layer [21, 22].
The polysilicon film was anchored to the underlying silicon wafer and patterned to form the particular mechanical structure, e.g., the proof mass and the capacitor
structures of an accelerometer. When the sacrificial silicon oxide layer was removed, the mechanical structure
was released to move.
The promise of the polysilicon surface micromachining was in the integration of mechanical structures with
CMOS electronics. The approach was very successful in
the development of accelerometers for the airbag application that was not as demanding on the acceleration
resolution. The thickness of the polysilicon layer determines the proof mass of the accelerometer, and the
intrinsic acceleration resolution is inversely proportional
to the square root of the proof mass. Thus the smaller
mass of the polysilicon structures became a limiting factor for the application that required high acceleration
resolution.
The control of the intrinsic stress of the polysilicon
membranes was challenging and made the release of the
micromechanical structures difficult. The deposition of
a thick polysilicon layer was eventually developed [22].
After solving the challenge of wafer level encapsulation,
the polysilicon surface micromachining provided smaller
dimensions at lower cost, possibility for monolithic integration with CMOS devices and allowed more complex
mechanical structures.
In the mid 1990s two disruptive technologies
appeared. The deep reactive ion etching (DRIE) of
silicon using an inductively coupled plasma source, the
Bosch process [23], made it possible to etch deep high
aspect ratio trenches into silicon. Secondly, the development of silicon on insulator (SOI) wafers enabled high
quality relatively thick monocrystalline silicon layers for
micromechanical structures [24]. These technologies
brought together the advantages of the bulk and surface
micromachining. Through these innovative processes
the MEMS technologies are becoming a true generic
technology and manufacturing platform.
The CMOS electronics integration with MEMS
devices has been an intensive topic of research and
development (see Review in [25]). Both pre- and postCMOS integration have been used. The key challenge
has been the different pace in the development of
MEMS and CMOS processes. In addition, the cost of
the area on a CMOS wafer is getting increasingly more
expensive; the CMOS components get smaller but the
miniaturization of the MEMS devices is constrained by
the sensor resolution and the necessary physical size.
xvii
Overview
Most of the manufacturers have adopted a system-inpackage strategy to overcome the integration challenge.
Silicon on insulator (SOI) wafers has also opened a
path towards embedding mechanical structures during the wafer manufacturing [26]. This can be a major
change in the value chain of the MEMS manufacturing. The primary mechanical structures can be embedded into the SOI wafer by the wafer manufacturer. The
device manufacturer can integrate the CMOS circuits
on the wafer and finally release the mechanical structures by the DRIE process.
The capabilities for large scale manufacturing and
foundries capable of producing components in scalable
volumes exist today.
Towards Every Pocket
New Trends
At the end of the 1990s the micromechanical pressure
sensors and accelerometers existed in relatively large
volumes for the automotive industry. The sensor elements, signal conditioning electronics and the packaging
were developed according to the automotive system and
environmental requirements. When consumer electronics and mobile phone manufacturers became interested
in sensors and other MEMS devices suitable for their
products, immediately they faced some challenges:
The interface electronics with sufficiently low power
consumption and low supply voltage level did not exist.
Even though a large variety of packaging standards
existed, the miniaturization had not addressed the
critical requirement of thinness.
n
n
Strict requirements for sensor performance and reliability increased the cost, and the testing and verification during both product development and production
were very expensive procedures.
Manufacturing volumes were not yet sufficient for
consumer applications, and the lack of long-term
commitment from the consumer industry did not
support the investments to scale up the production
capabilities.
Industry dynamics of consumer products and mobile
phones were disruptive to the operations of the sensor
manufacturers: emphasizing faster ramp-ups, shorter
commitments, speed of innovation, and extreme cost
consciousness.
Figure 2 illustrates the major shifts in the MEMS
industry. The consumer products created a demand of
lower cost MEMS devices with more relaxed requirements on performance. Especially, measurement electronics and packaging required rethinking. Figure 3
illustrates an example of the miniaturization of accelerometer modules for consumer products, for the game
controllers and the mobile phones [37, 38]. In the early
2000s the ground was very fruitful for new innovation,
and the global MEMS industry was very optimistic
about these new application areas.
Figure 4 shows a recent estimate of the growth of the
MEMS component volumes [39]. Even the total unit volume of MEMS components is expected to nearly triple
during the coming five years, the total annual growth of
the revenue is clearly smaller with roughly 14% CAGR.
Most of the growth is expected to come from the consumer applications of inertial sensors, silicon microphones
and RF MEMS. In addition, the significant growth of
microfluidics systems in medical applications, such as,
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Fig 2 l MEMS devices are moving towards consumer products and will enable the embedding of intelligence into human environments,
i.e., the ambient intelligence.
xviii
Overview
Fig 3 l Miniaturization of packaged MEMS accelerometers by ST Microelectronics [38].
Fig 4 l The estimated MEMS market trend by the Yole Développement [39].
xix
Overview
the drug delivery, may happen during the coming five
years. The price erosion of the MEMS components can
actually be even more dramatic due to the extreme cost
competition in consumer products and mobile phones.
Eventually, the new cost structure of MEMS devices will
affect the automotive sensor market as well.
What are these consumer applications that motivate
the annual implementation of half a billion accelerometers, over one billion RF MEMS components and nearly
two billion silicon microphones?
Consumer Products
From Wristwatch to Wearable Electronics
As the wristwatch is one of the miracles of miniaturization in the early 20th century, it is not surprising that
sensors measuring the motional and physiological state
of a person and the environmental conditions became a
part of the wearable wrist devices. These wrist top computers became a driver for the integration of MEMS
devices into consumer applications, such as sports, outdoors and wellness. The heart rate monitor, altimeter
and the electrical compass with integrated accelerometer to compensate the inclination create benefits to
any active persons exercising, skiing or trekking in the
wilderness. Even this consumer segment is relatively
limited, the applications defined the requirements of
battery powered wearable devices: small package and
very power efficient operation.
The wrist devices created a starting point for wearable electronics applications [40, 41] where the sensors,
processors and the user interface are embedded into
wearable devices or clothes. The concepts can be used
for following the daily activity of a person, measuring
physiological parameters, detecting the physical context
and location of a person or for observing the environmental conditions.
Wearable electronics creates a new platform for digital services when the measured information is connected
via Internet to communities of people that benefit from
sharing their own data with other members [42]. The
measured data from the individuals can be aggregated
into meaningful shared information and knowledge. For
example, sharing of sports, fitness or wellness data with
a reference group enables a person to compare their own
performance with the reference group.
The measurement of human scale motion by accelerometers and angular rate sensors can be used to extract
and recognize relatively complex patterns of human
scale motion, such as, walking, running, climbing stairs.
Figure 1.5 shows an example of a wearable pilot device
developed by Nokia in 2003. The device was capable
of detecting motion patterns and recording the daily
xx
Fig 5 l Nokia Fitness Monitor pilot product that measures and
recognizes various motion patterns.
activity of a person. Even more complex motion patterns, e.g., playing golf or exercising yoga, can be recognized, recorded and used to help the person to learn,
repeat and to correct these complex motion patterns.
Professional training methods thus become possible
for any serious amateur sportsman, and eventually, the
sports and gaming will merge into various interesting
combinations of physical and virtual realities.
Cameras and Projectors
The data projectors and projection displays became a
new driver of MEMS development after the invention
of micromirror devices at the end of the 1980s. The
DLP technology by Texas Instruments was ahead of
its time in complexity when it was first introduced in
1993 [43, 44]. Based on digitally controllable aluminum
micromirrors, the DLP chip enabled the miniaturization of video projectors when the personal computers
became the primary tool for creating presentations.
The miniaturization of data projectors has made them
portable. The further miniaturization depends primarily
on the power consumption and efficiency of the light
source and the thermal management of the device. In
addition to LED projectors also the laser sources, even
RGB laser sources [45], are appearing. The micromirror
based reflection devices will, however, meet a lot of competition from other technologies, such as, holographic
displays that can be much more power efficient [46].
Image stabilization became an essential feature of
SLR cameras and their optics. Miniaturized Quartz
gyroscopes are used to measure the camera movement
in order to control the mechanical actuators compensating the movement. The silicon angular rate sensors
Overview
are becoming an alternative for piezoelectric devices
in image stabilization. Digital photography may open
new applications for sensors. Automatic rotation of the
image requires a mechanical sensor. Advanced image
stabilization and more complex algorithms to improve
the quality of still and video images are beneficial also
for people who are not especially experienced in photography. However, many of these operations can be
performed by pure image processing.
The automatic generation of metadata for digital
images [47, 48] will be primarily based on date, time
and location. However, additional sensor information
can be used for more complete sets of metadata; light
condition, barometric pressure, humidity, temperature,
direction, inclination are valuable information in the
metadata for the further use and processing of images.
Based on the metadata the sharing and searching of the
images will become possible in a global scale in various
Internet services [49].
Gaming
The future of user interface and human machine interaction may already be visible in computer games and
game controllers. Ideas for using sensors and haptics in
the user interfaces of gaming devices has been developed by several research groups during the last ten
years [50].
Figure 6 presents this kind of prototype device developed and published by Nokia Research Center in 2004.
The detection of movements and gestures can be used to
create an immersive gaming experience; a combination of
a near-eye display, advanced audio functionality, gesture
and body movement detection and a haptic feedback
interface are ways to create virtual reality games or to
augment the physical reality by virtual features [51].
Nintendo created a commercial breakthrough with
their Bluetooth game control Wii Remote that extensively
introduced the motion and gesture control to computer
games. The game controller uses a 3D accelerometer for
tracking the motion patterns. Game controllers together
with an excellent set of games and a very good marketing
campaign made the product a real success story in 2007.
Nintendo Wii is a viable demonstration of multimodal
user interface for augmented or virtual reality concepts
and eventually also for remote communication.
Medical Applications of MEMS Devices
The health care services are globally challenged by
the increasing population in the developing countries
and the ageing population in the developed countries,
including China [52, 53]. Other global phenomena,
such as, obesity, require new solutions and rethinking
Fig 6 l 3D accelerometer and 2D angular rate sensor-based
game controllers created by Nokia Research Center in 2004.
of the preventive health care strategy. Furthermore,
the Internet connectivity enables the access to personal
health information and remote services.
The health care services are moving closer to the consumers. Networked professionals are capable of providing more demanding treatments. The health data of an
individual can be managed more efficiently and accessed
by an authorized institution or a health care professional. The personal health data can be managed in a
distributed manner but also accessed by the individual
anywhere, anytime. Based on this more easily accessible
health data, the health care services can be tailored to
fit to the medical history of the patient.
Furthermore, the medical treatments can be moved
to more convenient and less costly settings. A smaller
point-of-care can be responsible for diagnostics and
treatments that require an extremely sophisticated
environment today. In practice, this means remote
health care services in developed countries; for example, capabilities to provide a service for chronic patients
or elderly persons at home. In the developing countries,
the improvement of health care in the rural areas can be
based on similar solutions. Nurses and doctors in rural,
remote locations can benefit from the connectivity to
large hospitals and their information and diagnostics
capabilities.
The key driver for this kind of change is the need
to find very low cost solutions for health care using
new diagnostic tools, remote connectivity and capabilities to efficiently manage the personal health data.
Miniaturized diagnostics based on MEMS devices will
potentially influence both the future diagnostics and the
treatments.
Today the most important MEMS devices in medical applications are the microfluidics systems, pressure
xxi
Overview
sensors for blood pressure monitoring and the accelerometers for cardiac pacemakers. The largest potential
for new applications and business growth is related to
microfluidics used in diagnostics and drug delivery.
The micromachined structures have made it possible
to handle very small samples of liquids in a reliable way.
Furthermore, the MEMS miniaturization creates a possibility to use simultaneous parallel measurements in the
same system. These highly integrated lab-on-chip solutions [54, 55] change the nature of the in vitro diagnostic devices. Multichannel integrated biosensors, advanced
sample handling and new sensitive transducers will enable point-of-care devices that are capable of, e.g., cancer
diagnostics or any other analysis of the genomes [56].
The continuous monitoring of physiological parameters of a patient opens opportunities for more precise
diagnostics. In addition to monitoring of heart rate,
ECG and blood figures the possibility to monitor and
register the daily activity and context of the patient
during these measurements gives more information that
may have a correlation to the physiological data and that
can help in the diagnostics. The continuous monitoring
and the possible remote connectivity will open a new
segment of wearable health care products.
The MEMS devices are already used in the in vivo
devices: the cardiac pacemakers use accelerometers to
detect the activity of the patient in controlling the pacemaker rhythm [57, 58]. This application is a marvelous
example of the reliability of the MEMS sensors. The
next very potential application will be the implantable
MEMS drug delivery systems [59]. The possibilities to
integrate timing, sensors and microfluidics actuators
into an implantable device will revolutionize the treatment of several chronic diseases, such as, diabetes.
Mobile Phones and Mobile
Multimedia Computers
The mobile phones have converted to smart phones or
mobile multimedia computers. These mobile devices
are continuously gaining more dominance. These mobile
multimedia devices outnumber personal computers by
a factor of five. In some growth markets, such as China
and India, the ratio is even higher-close to 10:1. This
means concretely over three billion mobile subscribers
and over one billion wireless broadband subscribers. By
2010 it is expected that up to 90% of the global population will have mobile coverage. This creates an immense
platform to build digital services that are based on
remote connectivity.
The mobile phones have become digital cameras, music
players, internet browsers, mobile TVs in addition to
being communication devices that people carry with them
always and everywhere. The mobile phones integrate a
lot of functionality from consumer appliances and personal computers into a small integrated device. Figure 7
presents potential new arising trends in the mobile communication industry. Currently, the industry is shifting
towards Internet-based mobile services. This is a clear
consequence of new Internet-based business models
and the ongoing convergence of mobile communication,
information technologies and consumer electronics.
The studies and trials of MEMS components in mobile
devices started at the end of the 1990s in the laboratories
of both the mobile devices and MEMS component manufacturers. The MEMS provided possible solutions for RF
integration, local oscillators, sensors, microphones, displays,
power solutions, etc. The most potential applications of
Fig 7 l Mobile industry in shift towards services and ambient intelligence.
xxii
Overview
MEMS in mobile devices are related to the RF implementation, sensors and the audio functionality. On the
other hand, practically all the consumer electronics
functionalities can be integrated into mobile multimedia
computers or at least used in their accessories.
The rapidly growing volumes of mobile phones created expectations of large volumes of MEMS devices.
However, after roughly ten years of development the
impact is still rather modest. Why?
RF MEMS
The radio and the antenna implementations in mobile
devices are continuously getting more complex. The
number of supported radio standards has increased, making the design of the radio chip sets and the antenna solutions more challenging. The promise of MEMS devices
has been related to tunable RF components that reduce
the number of discrete elements in the radio front end.
MEMS RF switches, tunable MEMS capacitors and
MEMS resonator-based devices, such as, delay lines and
filters, have been the focus of extensive development
both in the university and industry laboratories [27–30].
The development of reliable RF MEMS devices
has, however, taken much longer than expected in the
beginning. There are some fundamental dimensional
constraints that make the integration of RF MEMS
components to mobile devices challenging:
The conductivity of even highly doped bulk silicon or
polysilicon is not sufficient for a high enough quality
factor for capacitors, inductors or switches in the frequency range of 1–5 GHz.Thus the use of metal film
based micromechanical structures is required, leading
to several other challenges.
The temperature dependence in devices that consist of
multiple materials is very difficult to control and reduce.
Even practical solutions have been found [35,36].
Low cost system-in-package integration of RF ICs, passive components and MEMS devices is challenging.
Voltage levels required to actuate RF MEMS devices
are typically much higher than the supply voltage levels of modern ICs.
Oscillators based on MEMS resonators at 10 MHz
frequency range with low losses (Q~200000) and
very good phase noise (−155dBm/ Hz ) have been
developed [31, 32]. However, the thermal stability of
the devices is still a challenge.
MEMS resonators are limited to roughly 10 MHz frequency. At higher frequencies, e.g., in 1–5 GHz range,
the fabrication tolerance of narrow electrode gaps,
very high control voltages and the lower Q values of
resonators limit the development of practical devices.
Recently, the development of piezoelectric actuators
for MEMS resonators has improved the efficiency of
electrical coupling [33,34].
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The complexity of the value chain has also made the
development slower: the MEMS devices, RF ICs and RF
modules have been manufactured in many cases by different manufacturers, according to the specifications of the
system integrators. Both technical and commercial challenges in creating integrated solutions have existed. Recent
development is clearly bringing the technologies together.
The radio communication is gradually developing
towards concepts that are generally known as the cognitive radio [60, 61]. The concept is based on the capability
of the radio system to sense the available radio resources
and the context of the user, assess the situation, dynamically plan and take the actions to allocate radio resources,
and finally learn about them. The requirements for the
radio front-end implementation are very demanding: the
radio spectrum analysis over a broad frequency range and
the fast adaptation to the optimal radio band. The power
efficient tunable antennas, filters and impedance matching circuits are the fundamental enablers of the future
intelligent radios. The technology for the cognitive radio
does not exist today; the RF MEMS components may
enable some of these required capabilities.
Sensors and Actuators
The sensor functionality is clearly becoming a part of
consumer products. However, there still exists a challenge in integrating new functionality in devices that are
sold in huge volumes. The products are extremely cost
sensitive, and the functionality needs to be meaningful
for most of the end users. What are these new functions
enabled by MEMS sensors?
Furthermore, the mobile phone market is driven
globally by mobile network operators. What are the
benefits and the revenue opportunities for the telecommunication operators of the sensor functionality? So
far applications that would motivate a very large scale
integration of sensors into mobile devices have simply
not existed. The additional cost related to the sensors
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Fig 8 l Tunable metal film capacitor design by Nokia Research
Center and fabricated by Philips Research.
xxiii
Overview
and their application software has slowed down the
development.
The number of possible sensor applications in mobile
devices is huge. Table 1 summarizes some possible mobile
device applications and their requirements for the sensor
system. Even if it is possible to list a large number of use
cases and applications, the key challenge is how to make
the functionality so generic that it enables this multitude
of applications for various consumers.
Recently, Nokia has introduced three axis accelerometers in the high end mobile multimedia computers, such
as, the models N82 and N95. The application programming interface (API) to the sensors has been published
for third parties. Nokia has also produced a multitude of
beta applications for fitness and sports [62]. The three
axis accelerometer-based motion detection and the GPS
based location have been the key data sources. Apple
iPhone, LG, Nokia, and Samsung have also used accelerometers for controlling the user interface. Recently,
Apple’s novel Appstore business model has enabled
development of various accelerometer applications for
mobile devices by the software development community.
The three axis accelerometer is the key sensor for
mobile devices. It enables several possible functions: hard
disk protection, gesture recognition, user interface control,
activity monitoring, etc. The functionality is generic, and
the motion data can create a basis for several applications.
The awareness of the context means to be able to recognise the status of the environment, the user, the device
itself and of the network. The context awareness is the
generic functionality that enables the future intelligent
sensing, computing and communication devices. The
context awareness is based on merging information and
measurements from several different sources. From the
embedded sensors it is possible to get, e.g., the activity, the
location, the physiological state of the user and the environmental conditions, such as, temperature, illumination
and humidity. Based on this primary sensor data the higher
level abstraction of the context of the user can be created.
Based on the context information it is possible to
build the applications for sports, gaming, gesture-based
device control, user interface control and adaptation,
automatic generation of image metadata, more sophisticated imaging algorithms, etc. Various sensor applications can be created using a generic software library that
consists of routines to compute the various abstraction
levels of context.
Silicon Microphone
Even the introduction of silicon MEMS microphones
[63, 64] into mobile devices has happened much slower
than anticipated, the silicon MEMS microphones have
clear benefits in comparison to, e.g., electret condenser
microphones. The silicon microphones are smaller. They
are surface mountable through a standard reflow assembly process. It is easier to protect them against EM and
RF interferences. They own better linearity and smaller
device-to-device variances in their design parameters.
Furthermore, their dependence on temperature and
humidity is lower.
These benefits are clear in the mobile device applications. However, replacement of an existing technology
always takes a long time. The existing technologies have
their cost advantages, operational supplier chains, the
assembly of existing components has been verified in large
volumes, and typically their characteristics fulfill most of
the application requirements. In order to be successful any
new technology needs to bring some unique advantage that
makes a difference to the end user of the product.
Table 1 Sensors and sensor applications in mobile devices
Sensor
Sports
Gaming
Gestures
UI
Metadata
Imaging
Accelerometer (3 axis)
M
M
M
M
I
N
Angular rate sensor
I
N
I
I
Magnetometer
M
N
N
GPS
I
N
M
Barometric pressure
M
Temperature
I
Humidity
N
(M  Must. I  Important. N  Nice to have.)
xxiv
M
N
N
I
N
N
Overview
In the case of silicon MEMS microphones the added
value became primarily not from the tangible added value to
the end user in the first place. The benefits were related to
the manufacturing solutions, and the possibility to use
the reflow process
simpler testing procedures in production
easier implementation into device mechanics
The capability to integrate the silicon MEMS microphone more easily with the CMOS electronics makes
a real difference. A compact digital microphone module and even a single chip implementation are recently
shown to be feasible by Akustica and other manufacturers. Even the cost of such a highly integrated device can
be a challenge in consumer electronics, the integrated
digital microphones enable multimicrophone arrays that
can be used for spacial filtering and directional control.
The active noise cancellation algorithms are based on
multiple microphones. The digital microphones can be
freely placed far from each other, owing to the digital
output signals that are resistant to interferences.
As the natural language is becoming a more important
way to interact with digital devices, applications and
services, these novel features and intelligences in the
overall audio system are drivers for high quality MEMS
microphones with integrated mixed signal electronics.
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Towards Modular Architectures in Consumer
Products
The requirements for the MEMS-based technologies in the
consumer electronics can be contradictory. There is a clear
tendency towards modularity; the new functionality should
be easy to implement in the devices. On the other hand,
the large volumes create severe cost constraints. MEMS
products with different levels of integration and complexity are needed, e.g., sensors varying from simple indicators
to integrated complex intelligent wireless sensors.
Figure 9a presents a possible configuration of an intelligent sensor module for a consumer product. The typical
features of such an implementation [65] are that the sensors and their primary signal conditioning circuitry are integrated into the same module. However, the system of Fig. 9
has several other interesting features. An integrated low
power DSP core and a specific hardware accelerator are
used for sensor signal processing. The feedback to the actuators controlled by the sensor signals is computed locally to
minimise the control loop delay. The efficient power management circuitry is used to control the various sleep and
active states of the device. The regulation of MEMS control voltages and the system clock are integrated into the
system. Optionally, a general purpose signal processor can
be added for more complex computational tasks, such as,
the asynchronous communication with the host processor.
The driver for such a high level of integration is the
autonomous, energy efficient sensing and signal processing. In many cases, continuous measurements are needed.
The modular implementation and careful design of the
internal power management of the sensor module are
essential. Various wake-up mechanisms, e.g., based on
a defined signal threshold or an interrupt from the host
processor, can be used. Only the minimal necessary functionality of the system is powered at any time.
Fig 9 l Architecture of an autonomous smart sensor module. (a) Sensor module that can be integrated via asynchronous digital
communication interface. (b) Wireless autonomous device with its own energy sources and storage.
xxv
Overview
The high signal abstraction level in the system interface of the module enables easier integration to the end
product. The processing and recording of sensor signals
and the recognition of the motion patterns or the context can be performed by the energy optimized sensor
module. These high abstraction states or their recorded
time sequences can be requested by the host processor
applications. In general, this kind of service oriented
architectures (SOAs) are becoming more common in
the distributed information technologies [66] but can
also be applied to embedded devices [67].
The modular implementation opens a new opportunity for MEMS devices. The low cost and miniaturized
integration of a system clock into the module, as illustrated in Fig. 9, is a challenge using a separate Quartz
crystal. The MEMS reference oscillators based on silicon resonators are a very potential solution. Currently,
the quality of the MEMS-based reference oscillators in
the 10 MHz range are becoming feasible.
The same type of modular architecture can be applied
to other electronics modules: mass storage, projection
display, radio modem, etc. The modular implementation will open new possibilities for adding functionality
to consumer products. There are several initiatives to
define the low power scalable digital interfaces, such as,
the USB and the MIPI consortia [68, 69].
Ubiquitous Sensing, Computing
and Communication
Merged Physical and Digital Worlds
The capability to add an index and a digital identity to
smaller physical items, such as sales packages and consumer goods, will enable more efficient logistics and
quality control from manufacturers to retailers. These
commercial solutions will create an information platform
that also enables the consumers to get deeper knowledge
of their purchased goods. We are talking about the first
steps towards the Internet of Things that is a concept of
connecting different physical objects to the information
networks [70]. These concepts extend towards possibilities to have an Internet address or an URL embedded in
the physical objects and thus a possibility to link them
into the information networks.
The next possible phase of this development has
many names [71–74]: Ambient Intelligence, Pervasive
Computing, Ubiquitous Computing (see Fig. 7). The
net­worked devices embedded in our physical environment provide sensing, computing and communication
services that can be accessed locally. When this localized information is connected to the global information
xxvi
networks that are capable of data aggregation, we will
live in a responsive environment that knows our preference and adapts to serve our particular needs. The
microsystems of sensors, processors and radios are
essential enablers of these intelligent environments.
The safety and comfort have been the key drivers of
automotive sensor applications. The adaptive and intelligent user interface is the driver of consumer applications. The key drivers for the Internet of Things and
the Ambient Intelligence will be related to the next big
challenges of human societies. The challenge of energy
production, the scarce natural resources and the ageing global population are creating a need to optimize
the human economical processes. The increasing urban
population creates more severe issues with the security
and safety of persons and their properties. The environmental challenges of pollution and changes in natural
ecosystems will require increasing human care.
Wireless Sensing and Sensor Networks
The wireless sensor networks [75–78] are enablers for
the Internet of Things and the future ambient intelligence. The sensor networks can be used for optimizing
the logistics and transport; the possibilities to localize
and to measure the condition of transported goods can
be used to optimize logistics cost and energy consumption. The safety and security can be increased by more
efficient sensor networks.
The wireless sensor networks will enable more precise
measurements and denser grids for monitoring of our
chemical environment and the atmospheric, hydrological
and seismic processes. The building automation and the
monitoring of the structural integrity will improve the
energy efficiency, the safety of the urban infrastructures
and the comfort of living. The solutions for assisted living
of elderly or handicapped people can be based on sensor
networks embedded in their home environment.
The intelligence and computing in a wireless sensor
network can be distributed in various ways [78, 79].
In an optimised wireless sensor network, some level of
data aggregation is typically calculated in each node in
order to reduce the energy consumption related to the
communication. In addition, the distance of the sensor
nodes is optimized with respect to the necessary transmission power. The very lower power operation of a
sensor network requires some complexity in the communication protocols and thus signal processing capabilities. A multitude of possible wireless protocols have
been developed for sensors and sensor networks.
Table 2 summarizes the key figures of merit of the
most important initiatives of wireless sensor radios, the
Bluetooth, Zigbee and the Near Field Communication
Overview
Table 2 Comparison of the most important existing sensor radios
Figure of merit
Bluetooth [82]
Bluetooth LE [83]
Zigbee [84]
NFC (RFID) [85]
Range
10 m
10 m
50 m
5 cm
Power
Ref index  1
0.1-0.5
0.6
4 reader/0 tag
Data rate
1 Mbps
1 Mbps
0.25 Mbps
0.4 Mbps
Pairing speed
Slow
Fast
Fast
Inherent
Security
Authentication
Access approval
n/a
n/a
Silicon size
Medium
Tiny
Small
Very small
Typ use case
Accessories
Sensors
Automation
Identification
(NFC) standards. These standards have not been developed and optimized for actual multi-hop sensor network
applications. The basic concept of these radios is related
to connecting various sensors into a host device, such as,
a mobile phone, that can be a gateway into the information networks [80, 81].
A wireless sensor consists typically of a radio, a microprocessor, a small memory, and an energy source in one
single robust package. Figure 1.9b presents a possible architecture of wireless sensor that has specific requirements
related to the radio communication and autonomous
operation: extremely low power consumption enabling
energy autonomy, capability to wake-up the system by an
external sensor signal or an external radio (i.e., a wake-up
radio [86]), and an efficient control of the measurement
and signal processing duty cycles. Furthermore, the wireless sensor nodes need to be easy to deploy, self-configuring, extremely robust and fault tolerant.
The challenges in developing the energy solutions
for the ambient intelligent systems requires new thinking and new technologies. Today business models are
still missing, and various societal issues, such as, privacy
and security in these novel networks, need to be solved
before any broad deployment.
Mobile Phone as a Sensor
As discussed before, soon 90% of the global human population will have mobile coverage. In some years these
devices have become also sensors and computers that
are inherently connected to the global information network. The mobile devices can have several roles in the
context of ambient intelligence and sensor networks.
The mobile device is already today a user interface
towards the global Internet based services and digital
content, and the user interfaces of the mobile devices
will have improved capabilities for this multimodal
information. Secondly, based on the efficient radio solutions (see Table 2) the mobile devices are also becoming
a user interface to access the sensors and other devices
in the local environments. Figure 10 presents the paradigm of a mobile device as a trusted personal user interface towards the local and global information.
However, the most important new capability is to
use the mobile device as a gateway between the local
networked environment and the global information
networks. The mobile devices all over the world can
simultaneously collect information and feed it into computing services that can aggregate the information into
meaningful form for the end users. Powerful data mining and search algorithms [87] can be used to extract
local information, local history and predictions. Possible
examples are pollution and traffic monitoring where the
information of individual devices can be aggregated into
maps and future projections that are meaningful for
the people joining to these services. The mobile solutions for remote health care and continuous monitoring of patients are another clear example of this kind
of application. The privacy of the individuals connected
to these services is an essential feature of the network
operation and the infrastructure.
The mobile device itself can be a sensor node of a
sensor network. The multiple integrated sensors and
their context and location awareness create as such the
information that is meaningful to be aggregated into
knowledge. The information that can be retrieved from
the behavior and the preferences of the consumers is
always valuable for service providers. The questions
are, with whom the consumers are willing to share their
preferences and what do they win by doing so? And
what will be the future business models?
xxvii
Overview
Fig 10 l Mobile phone as a gateway between local intelligent environment and global digital services and content.
Future of MEMS Technologies
Is Silicon Enough?
Silicon is a nearly perfect mechanical material and enables the micromachining of very precise structures. There
are also some limitations related to the cost and the ultimate material properties. In microfluidics and optical
applications, e.g., in diffractive optics, the use of polymer
substrates and structures is much more inexpensive in
large volumes. The sophisticated technologies for replicating the microstructures into polymer surfaces have
been developed [88–91]. The basic idea of the process
is to fabricate the primary mechanical structure into the
surface of the silicon wafer, deposit a metal film on top of
the silicon structure and electroplate a thick metal layer
(for example, a nickel layer). When the thick metal layer
is removed from the surface of the silicon wafer, we have
a mold to replicate the structure on a polymer surface,
for example, using injection molding or hot embossing.
In RF applications the conductivity of even the very
highly doped silicon or polysilicon is not sufficient for
a high enough quality factor for tunable RF capacitors,
switches or inductors. The use of metal films has been
a way to increase performance of the micromechanical
components. The use of free standing metal thin films
for tunable or switchable structures is shown to be
possible. The behavior of metal thin films differs from
bulk metals; for example, inelastic deformations are
smaller [92, 93].
The novel nanomaterials will create a possible impact
in the future MEMS. The use of carbon nanotubes as
piezoelectric transducers has been demonstrated with
good results [94–99]. The use of bottom up grown sili-
xxviii
con nanowires for resonators has been studied [100102]. Nanotechnologies will create new material
solutions for MEMS, and possibly some new nanoscale
mechanical structures, so called NEMS structures, will
become commercially feasible some day.
Figure 11 illustrates a concept of a future consumer
device based on polymer electronics [103], stretchable
electronics [104] and new functional surface materials
[105, 106]. The key attributes of such a future device
are transformability, compliancy in terms of controllable flexibility and stretchability, extreme thinness and
transparency. The integration of functionality will be
based on reel-to-real assembly [107] and printing of
interconnects [16] together with many active and passive printed components [108, 109]. This kind of device
is still very far in the future but the first steps towards
the novel integration solutions will be taken within the
coming years based on printed electronics. What are the
implications to the MEMS module packaging?
Platform for Nanoscience
and Nanotechnologies
The MEMS has also created capabilities for the probing
and manipulation of matter in the nanoscale. The atomic
force microscopy based on micromechanical cantilevers
and tips is one of the key methods for scanning, imaging
and measuring nanoscale objects. The micromechanical probes can be used for accessing nanoscale systems
and their dynamical properties. The micromechanical
systems will play a significant role in developing the
nanoscale electronics, functional nanomaterials and surface structures.
Overview
Conclusions
Fig 11 l A transformable and wearable device, based on
stretchable electronics. Industrial design by Jaakko Saunamäki,
Nokia [113].
The explosion of digital content in terms of images,
music and videos creates an increasing need for high
density, low power and intelligent mass storage systems.
The magnetic hard disks will not scale to the memory
densities that would fulfill these requirements.
The micromechanical cantilever array has already been
developed for nanoscale mass storage concept. Several
companies, such as, IBM, HP, ST Microelectronics and
Seagate, have been working for a concept called probe
storage [110, 111]. The concept is based on reading,
writing and erasing information on the surface of a polymer film, metal film or a magnetic film using a microelectromechanical cantilever and a micromachined tip.
The IBM Millipede [112] has a capability to read,
write and erase dots on the surface of the polymer film
with the pit resolution of 20 nm. The micromachined
system is relatively complex with the array of cantilevers and the actuators to move the plate hosting the polymer film. However, the manufacturing of the MEMS
system is feasible today; the challenge of the probe
memory technologies is the stability of the nanostructures used for the memory.
After over 30 years of development the silicon micromechanics has become a major established industry of
its own. The applications in ink jet printer nozzles and
automotive sensors had the sufficient momentum to
develop technologies that are now applicable to consumer products in large volumes. The requirements of
the consumer products have pushed the manufacturers to invent solutions for extreme miniaturization of
MEMS devices and their packages. Very low power and
low voltage sensor electronics exist as well.
The driver for automotive sensors was the safety and
comfort of the vehicles. The consumer electronics created
sensor applications related to the more sophisticated interaction between the human and the different intelligent
devices. The replacement of existing technologies with
purely technical arguments never creates an immediate
market pull. The integration of new functionality in cost
optimized consumer products depends on the real value
and novelty to the end user. Understanding of the complete
business case and the added value related to all the stakeholders is essential for MEMS component manufacturers.
The business models of the consumer electronics are
changing as the strong bundling of devices with services
and content is becoming a necessity. The new business
models will require increasingly fast response time to bring
new products to the market. Modular solutions to implement new functionality, such as, tunable RF components
for the cognitive radio, low cost integrated reference oscillators for modular electronics, three axis accelerometers
for motion pattern recognition and digital silicon microphones for advanced audio systems, are surely needed.
The ramping up and down of the production will need to
happen very fast because the volumes of particular end
products are going to be very difficult to estimate.
The global challenges–scarce energy and other natural resources, environmental and heath care challenges,
growing urban population–will require more efficient
sustainable economics and new ways to guarantee the
safety, security and well being of people globally. Sensor
networks and ambient intelligence will be enablers of our
future sustainable way of living, and the microelectromechanical systems together with arising nanotechnologies are important to make this global implementation of
sensing, computing and communication possible.
Acknowledgements
We would like to acknowledge the numerous colleagues at Nokia Research Center, especially, Vladimir
Ermolov, Kari Hjelt, Antti Lappeteläinen, Jukka
Salminen and Henry Tirri, with whom I have worked
xxix
Overview
towards microsystems, sensors and their applications in
the mobile industry. In addition, I want to express my
gratitude to Heikki Kuisma, Markku Tilli and Benedetto
Vigna for sharing their deep insights of the MEMS
industry.
This chapter is not meant to be a thorough review.
We are aware of the very extensive research in various
MEMS technologies and their applications. Here we
are referring only to some of the key breakthroughs in
the field.
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Chapter One
1
Properties of Silicon
Markku Tilli and Atte Haapalinna
Okmetic Oyj, Vantaa, Finland
1.1 Properties of Silicon
Silicon is an abundant element found in the Earth’s
crust in various compounds. Semiconductor and MEMS
applications use more than 20000 tons/year (2008)
of high-purity silicon. Today most of the silicon used
is either N- or P-type, doped with antimony, arsenic,
phosphorus (N-type) or boron (P-type); the dopant
concentration ranges between 1013 and 1020 dopant
atoms/cm3 Si. Intrinsic (no intentional doping) or very
slightly doped high resistivity silicon above 1kΩcm is
used in small amounts. Statistics pertaining to silicon
can be found, for example, in the US Geological Survey
2006 Minerals Yearbook [1].
Quartz, or silicon dioxide, is the most common start­
ing raw material for purified silicon for semiconductor
and sensor applications, and the Siemens process is the
most commonly used in semiconductor-grade silicon pro­
duction. In the classical Siemens process, metallurgicalgrade silicon, made first in an electric arc furnace by
reducing quartz with coke, is turned to silicon-hydrogen­
chloride compounds in fluidized bed reactors and those
compounds are converted to TCS (trichlorosilane, or
SiHCl3). TCS is purified by distillation, during which
concentrations of impurity compounds having either
a lower or higher temperature of volatility than TCS
(38.4°C) are reduced. Purified TCS is fed together with
hydrogen into a reactor. In the reactor TCS is decom­
posing onto hot silicon filaments forming a pure polysilicon rod. This rod is then used as a raw material for
crystal growth, either in rod form or in crushed pieces.
There are alternative, newer techniques for purifying
silicon; one variant is similar to the Siemens process
but uses silane (SiH4) as a precursor. In some processes,
heated silicon filaments are replaced by silicon particles
floating in fluidized bed reactors; these processes yield
granular polysilicon.
The result of the purification process is high-purity
silicon containing very small amounts of foreign dis­
solved atoms. If the single crystals are manufactured by
a Czochralski (CZ) technique, which is most commonly
used (�� 90% of the crystals), the impurity level
increases, as the growth is made from a quartz cruci­
ble having some impurities. The result is, however, still
acceptable. Typically, most of the contamination of the
silicon takes place during actual device manufacturing.
Of impurities, metals are generally harmful, with rare
exceptions, and their concentration should be as low as
possible, typically �� 1012 at/cm3 Si. Oxygen coming
from the CZ-crystal growth step as an impurity has a
dual role: it has beneficial effects (strengthening of the
silicon lattice at high temperatures, gettering effect in
semiconductor use) but also has detrimental effects
(donor formation, defect generation). Nitrogen is a sec­
ond example of an impurity, and it can be used in small
quantities to enhance silicon properties, especially in IC
applications.
The current high demand for low-cost solar-grade sili­
con encourages the exploitation of alternative sources
and new purification techniques. Currently these meth­
ods are not able to produce semiconductor-grade silicon
pure enough for MEMS applications, although in solar
applications these new methods already show prom­
ising results. Woditsh and Koch [2] and Istratov et al.
[3] list some of the available solar silicon purification
techniques.
3
PA R T I
Silicon as MEMS Material
Silicon is an ideal material for various MEMS appli­
cations. Silicon is a semiconductor whose resistivity
can be adjusted by doping from sub-mΩcm to several
kΩcm; it is quite inert in a normal environment, hard,
transparent in an infrared regime, and elastic at room
temperature with no plastic deformation and with high
fracture strength. Finally, a protective stable silicon
dioxide can be grown. Silicon crystal has anisotropic
properties—mechanical, chemical and electrical—which
can be exploited in MEMS component designs. Very
large silicon single crystals in various crystal orientations
can be made with relative ease. These unique combina­
tions of properties have placed silicon as the number
1 material in MEMS manufacturing, although it took
almost 30 years after the invention of the silicon tran­
sistor until the potential of silicon as a micromechanical
material was widely realized; see Petersen [4]. Table 1.1
Table 1.1 Basic parameters of silicon
Atomic number of Si
14
Atomic mass of Si
28 (92.23%) 29 (4.67%), 30
(3.1%)
Crystal structure
diamond
Lattice constant
0.5431
nm
Si atoms
5*1022
atoms*cm�3
Melting point
1687
K
Specific density
2.329
g*cm�3 at 298 K
Specific density (liquid)
2.57
g*cm�3
Thermal conductivity
149
W*m�1K�1
Coefficient of thermal expansion 2.56*10�6
m�1K�1 (at 298K)
Specific heat capacity
19.79
0.705
J*mol�1K�1
J*g�1K�1
Young’s modulus
150
GPa
Speed of sound
8433
m*s�1
Hardness
7
Mohs
Hardness
850
kg*mm�2 (Knoop
hardness)
Volumetric compression
coefficient
1.02*10�8
kPa�1
Index of refraction (varies with
temperature and λ)
3.54
λ 1.1 μm, RT
3.48
4
λ 2 μm, RT
lists some basic parameters of silicon. Some of the para­
meters depend on doping level as well as temperature
and have an effect on MEMS device function.
A more comprehensive treatise on basic silicon
properties can be found, for instance, in a handbook
edited by Hull [5] or in Landolt-Börnstein Group III:
Condensed Matter volumes [6].
1.1.1 Crystallography of Silicon
Silicon crystallizes into a diamond cubic crystal struc­
ture (Figure 1.1) in which the atoms are covalently
bonded. Other elements, like germanium, in periodic
table group IV typically have the same structure. The
unit cell contains 8 atoms, and the atoms follow a face
centered cubic (fcc) Bravais lattice. In each fcc lattice
point there are 2 atoms (motif): one in the lattice point
and the second displaced by ¼ of the unit cell length
towards the [111] direction. The unit cell length at
room temperature is 0.5431 nm. Actually, this value is
one of the most precisely known among elements, since
silicon crystal can be grown almost perfectly, and the
lattice parameter can be measured precisely accord­
ing to Martin et al. [7] with an uncertainty of about
3…6*10�8. Thus, silicon is a good candidate for vari­
ous references, for instance, in determining Avogadro’s
constant. The density of packing of silicon in this lattice
is 34%. The packing density is quite loose compared
with that of fcc lattices (some metals, like copper, have
this structure), whose packing density is 74%, and that
of a body centered cubic structure (for instance, pure
iron at room temperature), whose packing density is
68%. The largest empty place in the diamond cubic lat­
tice is the octahedral hole, which can occupy an atom
Fig 1.1 ● The silicon lattice unit cell. Gray silicon atoms in the
lattice are in the fcc position, and light color atoms are shifted
from fcc positions toward the [111] direction by ¼ unit cell length.
Properties of Silicon
41% of the size of the host atom. Atoms dissolved in
the lattice in empty places are called interstitial atoms;
the solubility is called interstitial solubility. The most
typical interstitially dissolved (impurity) atom is oxy­
gen. The maximum oxygen equilibrium content at crys­
tal growing in the interstitial state can in practice be
almost up to 20 ppm, which corresponds to up to 1018
atoms/cm3 Si. Carbon is the second most common
interstitial impurity in silicon; in practice the concen­
tration is �0.3 ppm in semiconductor-grade material.
Dopant atoms, of which boron, antimony, arsenic, and
phosphorus are commonly used, are in substitutional
lattice sites (i.e., replacing silicon atoms), with the
exception of very high doping levels (meaning high con­
centrations above 1018 atoms/cm3 Si), at which a small
fraction of the doping elements are electrically inactive
and in interstitial places. The maximum substitutional
solubility depends on the atom size and some other fac­
tors; typically it is �1021 atoms/cm3. Germanium is an
exception; it is completely miscible.
1.1.1.1 Miller Index (hkl) System
A convenient way to describe atomic planes and direc­
tions in the crystal lattice is to use Miller indexes. When
the lattice has maximum symmetry, or is cubic (as the
silicon lattice is)—that is, the lattice axes are orthogo­
nal and the lattice parameters in all directions x,y,z
CHAPTER 1
are identical—the Miller notation is easy to use and is
described later.
Let us consider an orthogonal coordinate system,
with axes x, y, and z, with equal unit vector size, a
(Figure 1.2). In Figure 1.2a the plane intercepts the
x-axis at a distance a from the origin and is parallel to
the y- and z-axes, or intercepts them at �. The inter­
cept points in each axis are thus a,�,�. Miller indexes
(hkl) are constructed in such a way that reciprocals
of the intersect points are taken. Thus, in the case of
Figure 1.2a, the Miller indexes (hkl) are a/a, a/�,a/� or
(100). If the plane intercept points would be ½ a,�,�,
Miller indexes of that plane would be (200). A plane
intersecting axis y at a and the x and z axes at �, respec­
tively, is (010). If the plane would intersect axis y at –a,
and the x and z axes at �, it is (0-10) or ( 0 l0 ) in Miller
notation, where the negative sign is above the index
number.
A plane(110) means that plane intersect points
are a,0,0, 0,a,0, and 0,0,�; with (111), plane inter­
sect points are, in a similar way, a,0,0, 0,a,0 and 0,0,a.
Correspondingly, the (321) plane is a plane with inter­
sects at points a/3,0,0, 0,a/2,0 and 0,0,a (Figure 1.2f).
The convention is that when the plane is marked as
(hkl), it means that the plane is only that. If the mark­
ing is {hkl}, all planes in the same family are included,
and in a cubic lattice it means that {khl} includes all
8 identical planes (hkl), ( hkl ), ( hkl ), ( hk l ), ( hkl ),
Fig 1.2 ● Miller indexes.
5
PA R T I
Silicon as MEMS Material
( hk l ), ( hk l) and ( hk l ). Indexes for directions are
expressed in square brackets as [hkl]. The direction is
perpendicular to the plane. Finally the family of direc­
tions is expressed as hkl, and again in cubic lattice it
includes all identical 8 directions hkl, hkl , hkl ,
hk l , hkl , hk l , hk l and hk l . Those who would
like to have a comprehensive picture of Miller indexes
should consult, for instance, Cullity and Stock [8].
1.1.1.2 Stereographic Projection
Stereographic projection in crystallography is a helpful
and illustrative tool when investigating atomic planes or
directions and visualizing various orientation dependent
phenomena. In stereographic projection crystal direc­
tions are projected onto a plane. Construction of stereo­
graphic projection is made as follows: The crystal lattice
is placed in the center point of the sphere and crystal­
lographic directions are projected onto the sphere’s sur­
face. A plane touching the sphere in point S is drawn.
A line connecting points N and the projection point of
the crystallographic direction on the sphere P* is drawn.
This line intersects the plane in point P. When all crys­
tallographic low index directions intersecting the sphere
in the southern hemisphere are drawn and projected to
plane, a stereographic projection is constructed. This
kind of projection preserves angles (but not areas), so it
is possible to measure angles between crystallographic
directions. This can be done manually using a Wulff ’s
net. Silicon based MEMS technology uses commonly
(100) oriented silicon wafers; that is, the (100) crystal­
lographic plane is the surface of the wafer. Less often,
wafers with (111) or (110) are used. Some special appli­
cations may use off-oriented wafers, for instance, where
the angle between (111) plane and water surface is 45°.
Below are stereographic projections of cubic crystals in
(100), (111) and (110) orientations constructed in such
a way that the wafer orientation mark (a flat or notch) is
facing downward and is of 01 l type.
There is useful commercial and free software for con­
struction of stereographic projections and calculation of
angles between directions and planes [9, 10]. A com­
prehensive presentation about stereographic projections
and their use can be found, for example, in Cullity and
Stock [8] (Figures 1.3–1.7)
1.1.2 Defects in Silicon Lattice
Although single crystalline silicon is almost perfect to
a degree where it can be used as a standard to define
Avogadro’s constant, in reality single crystals made
either with CZ or float zone (FZ) growing methods
contain defects, some of which are characteristic to
the particular growing method. Furthermore, defects
6
are formed intentionally or unintentionally during the
processing of silicon wafers to final components. These
defects can be classified as (1) point defects (or their
agglomerates), (2) linear defects, (3) planar defects or
(4) volume defects.
Silicon crystals are grown from the melt. Because
of the low diffusivity of the point defects—vacancies
and self-interstitials—many of the defects thermody­
namically at equilibrium concentration at the freezing
point are “frozen in” the crystal during cooling phase.
Depending on the temperature gradient close to the
freezing interface and the time at high temperatures,
point defect agglomerates can be formed, too. In IC tech­
nology COPs (crystal originated particles, or large vacancy
agglomerates) have a great impact on thin gate oxide integ­
rity, for instance. Crystals grown with the CZ method also
contain foreign atoms, like oxygen and carbon. Initially
they are like point defects or clusters of a few atoms in
the crystal at equilibrium in freezing temperature, and at
normal device processing temperatures they are supersatu­
rated, eventually generating volume defects (precipitates)
and/or secondary linear or planar defects. A growing oxide
precipitate can nucleate stacking fault or dislocation loops
around the precipitate. Oxygen can also form electrically
or optically active defects, donors, which are discussed
later in Section 3.6. Therefore, it is essential to control
these defects not only in device manufacturing but also in
the crystal growing step. As the relationship of the growth
in defects in the crystals and defects in finished devices is
complex and depends on the thermal processing steps, it
is beneficial for the crystal grower to know, in as detailed
a manner as possible the device manufacturing steps to
optimize the behavior of the silicon. Reviews of Falster et
al. [11, 12] give an overview of intrinsic point defects in
CZ silicon.
Linear defects are called dislocations (see Section 11.2).
In silicon single crystals grown by CZ or Float Zone
methods, or in wafers cut from these crystals, the dislo­
cation density is practically zero. During the processing
of the silicon wafer at higher temperatures, the applied
stress may generate dislocations. The origin of these
N
S
P*
P
Fig 1.3 ● Construction of a stereographic projection.
Properties of Silicon
–
013
–
012
–
023
–
011
–
032
–
021
CHAPTER 1
–
031
–
133
–
132
–
010
–
122
–
–
001
–
131
113
–
–
112
– 121
– 233
232
223
–
–
–
–
111
130
103
213
231
–
–
––
–
332
031
323
–
120
013
102
–
–
221 –
–
212
322
230
–
203
331
––
313 –
––
–
–
131
113
021
–
012
211 321
312
110
101
––
231
–
–
–– 213 ––
320
311
––
121
302 –
331
032
023
313
–– 112
201 –
210
132
––
221
123
––
––
212
232
223 ––
301
321
310
332
312
323
––
–– –– ––
–– –– –– ––
100
011
011
133 122 233 111 322 211 311
311 211 322 111 233 122 133
–
123
––
––
323
––
–
312
223
301
232 332–– 321
310
221
212
123
–
201
––
––
210
313
331
–
112
–
121
302
––
311
320
213
231
–
–
–
101
–
110
––
321 211
312
113
131
–
–
–
203
–
230
313
331 –
322
–
–
221 –
102
120
– 212 –
–
332
–
323
231
–
213
103
130
111
–
–
223 –
– 232
–
112
– 121
–
233
131
113
––
–
010
–
–
122
001
132
123
–
133
–
–
013
–
031
–
012
–
–
021
023
–
032
011
––
132
––
032
––
021
––
031
023
012
013
Fig 1.4 ● Stereographic projection of (100)-oriented crystal.
stresses can be thermal gradients during temperature
transients in heat treatment steps, or mismatch stresses
caused by thin films or heavily doped areas in combi­
nation by high temperatures. Movement of dislocations
through the crystal lattice causes permanent deforma­
tion. Dislocations in silicon move on {111} planes along
110 directions. This deformation can be seen visu­
ally as slip lines. If the deformation is heavy, the wafer
warpage may increase. In general dislocations in silicon
wafers have adverse effects on device performance, and
in the worst case dislocations may even prevent the
device from functioning. Dislocations attract impuri­
ties, and the result can be that moving dislocations leave
precipitate colonies behind. Dislocations can also match
together two parts of silicon lattices having slightly dif­
ferent lattice constants. This happens when an epitax­
ial layer is grown on a substrate and their doping levels
differ substantially (see Figure 6.11). These dislocations
are called misfit dislocations, and normally they are
confined in the interface. In MEMS applications where
silicon is etched, areas containing dislocations generally
have a non-uniform etch result because of the stress
field around the dislocation core. A further consequence
of the presence of dislocations is a reduction of yield
strength at higher temperatures. The yield strength of
zero dislocation silicon is higher than silicon having dis­
locations in temperatures where plastic deformation can
occur. This means that once slip has occurred, silicon
wafers are more susceptible to additional slip in follow­
ing thermal treatments. However, dislocation locking
by impurity atoms diffusing to the dislocation core or
strained area increases resistance to additional slip.
Planar defects are called stacking faults. In silicon
stacking, faults are along (111) atomic planes and they
are surrounded by partial dislocation. A silicon lattice
may contain an extra atomic place; this stacking fault is
called extrinsic. If an atomic plane is missing, the stack­
ing fault is intrinsic. Most stacking faults in silicon are of
the extrinsic type. Extrinsic stacking faults are formed
by excess silicon interstitials; oxidation induced stacking
7
Silicon as MEMS Material
PA R T I
–
011
–
123
–
112
–
213
–
223
–
– –
313 212 323
–
111
–
123
–
122
–
–
132
233
–
232
– –
132
– –
121
–
032
–
021
– –
131
– –
231
–
031
–
121
–
131
–
–
–
–
–
– 332
110
130 120 230
–
322
–
231
–
010
221
312
–
–
211
130
– 331
–
321
302
230
120
–
–
–
–
231
331
110
131
–
311
031
201
131
–
–
320
231
221
–
121
021
331
210
301
121
–
–
–
221
232
332
310
032
132
321 332 232 132
–
–
–
– –
––
322
311 211 322 111 233 122 133 011 133 122 233 111
100
311
–
101
––
312
––
211
–
321
–
211
323 223
–
123
–
–
023
123
223 323
212
112
–
––
–
313
–
012
321
112
312
213 113
212
–
–
–
013
210
–
–
101
113
311
313
213
203
–
–
320
102
– 312 –
103
313
211
–
–
001
321
–
212
–
–
–
–
213
322
103 –
–
–
102 203
110
101
323
–
– –
–
113
–
331 221 –
–
112
332 111 223
–
013
–
––
–
123
–
113
–
233
–
232
231
––
012
–
213
122
–
–
–
023
133
121
––
112
–
132
––
–
123
011
–
310
301
201
302
312
Fig 1.5 ● Stereographic projection of a (111)-oriented crystal.
faults (OISFs) or stacking faults around growing oxide
precipitates are typical examples. A large oxygen pre­
cipitate may generate stacking fault(s) to reduce misfit
stresses. Wet oxidation of silicon wafer also may induce
stacking faults. Intrinsic stacking faults can be found,
for instance, in epitaxial layers. Although the largest
stacking faults in wafers can extend over several hun­
dred μm’s, typically the diameter is less than 100 μm.
Volume defects in silicon are precipitates. They can
be coherent (the lattice of the precipitate is aligned with
the host silicon lattice), or non-coherent, when there is
a mismatch in lattice alignment. Small precipitates are
often coherent, and when they grow, they turn first semicoherent, and then non-coherent. Precipitates are nor­
mally compounds of silicon:silicates or silicon dioxide.
Czochralski-grown silicon contains dissolved oxy­
gen, which is supersaturated at wafer processing tem­
peratures, unless a special low oxygen content material
is used. Extended thermal treatments grow oxygen
precipitates. Also, there can be a redistribution of
8
precipitates, in which large precipitates are grown at the
expense of small ones. This phenomenon is called an
Ostwald ripening process. At a given temperature there
is a critical size of precipitate; larger precipitates are
grown, provided that there is enough supersaturation at
that temperature, and smaller precipitates are dissolved.
Using this phenomenon, it is possible to tune both the
distribution and size of precipitation, first designing
a proper lower temperature nucleation step to adjust
the size distribution and density of nuclei, and then, at
higher temperatures, growing precipitates which exceed
the critical size at that temperature. At the same time
it is also possible to form a precipitate-free zone below
the wafer surface. The precipitate nucleation process
depends especially on the properties and thermal his­
tory of the grown crystal; therefore, silicon wafers from
different sources behave differently. However, if, fol­
lowing thermal cycles, the crystal grower knows what
silicon wafers are seeing in the manufacturing steps that
follow, it is also possible to adjust the crystal growth
Properties of Silicon
CHAPTER 1
–
110
–
331 –
– –
221 –
– – 331
332
– – 221
332
–
–
– –
–
230
111
231
– –
231
111
–
– –
–
232
232
–
120
– –
–
223
–
–
–
– –
121
121
233
233
–
223
– –
–
130
–
– –
–
131
131
–
112
– –
122
122
– –
132
132
112
–
–
–
–
– –
133
133
123
123
–
–
113
010
– –
031 021
– 021– 031
113
032
– 032
011
011
–
023
– 023
–
012
130
012
131 132
– 131
–
–
133
133 132 –
013
013
120
–
121
–
121
–
122 123
123 122 –
– 231
230 231 232 233
233 232
–
–
–
–
– – –
–
113 112 223 111 332 221 331 110 331221 332 111 223 112 113
001
001
–
103
––
113
–
213
–
102
––
213
––
112
––
223
–
203
–
–
–
323 322 321
–
–
212
211
–
–
–
313 312
311
–
101
––
313
––
212
––
323
–
302 201–
––
312
––
322
–
301
––
311
––
211
––
111
––
332 ––
221
320
210
310
100
–
310
–
210
––
321
––
331
–
320
–
110
Fig 1.7 ● Wulff net used in measurement of angles in
stereographic projection.
322 323
212 213
211
103
313
311 312
102
203
101
302
301 201
–
113
–
–
213
313
–
–
312
–
–
212
112
311
–
–
323
–
211
–
223
322
–
321
–
111
321
–
331
–
– 332
221
Fig 1.6 ● Stereographic
projection of a (110)-oriented
crystal.
process and crystal properties in such a way that desired
results are obtained. If wafers are used in IC manufac­
turing, the objective normally is to have precipitation on
the bulk; the surface area remains defect free, to get the
maximum effect out of internal gettering (see Figure
4.7). On the other hand, some MEMS manufacturing
processes yield optimum results only if the bulk of the
wafer remains essentially precipitate free.
COP, a cluster of vacancies, is also a volume defect.
The size and density of this defect depend on the crys­
tal growth process; the average size can be from tens of
nm to less than 200 nm. COP has mostly an effect-gate
oxide quality in CMOS devices. Because the COP origi­
nates from crystal growth process involving melt, epi­
taxial layers are free from COPs (Figure 1.8).
“Defect Engineering” can be used successfully in sili­
con technology to maximize device yield; however, it
should be remembered that conventional approaches
used in IC manufacturing are not necessary successful
in MEMS technology. Reviews by Borghesi et al. [13]
on oxygen precipitation in silicon; Bergholz and Gilles
9
PA R T I
Silicon as MEMS Material
τ
τuy
τly
ε
Fig 1.9 ● Schematics of stress–strain behavior of dislocation-free
silicon single crystal at elevated temperatures. τuy � upper yield
strength, τly � lower yield strength, � � strain.
Fig 1.8 ● Defects in primitive cubic lattice. (a) vacancy, (b)
interstitial atom, (c) interstitial atom (can be foreign atom or selfinterstitial), (d) dislocation (edge), (e) intrinsic stacking fault, (f)
extrinsic stacking fault, (g) non-coherent precipitate.
–1
1000/T (K )
0.5
1
1.5
2
10000
[14] on defects in general in silicon; and Sinno et al. on
defect engineering in CZ silicon [15] give a good over­
view of how defects affect IC manufacturing.
1.1.3 Mechanical Properties of Silicon
Silicon is a hard, brittle material, and at room tempera­
ture under stress silicon single crystal elongates elasti­
cally until fracture stress appears without significant
plastic deformation. Therefore, defects (scratches,
dents, mechanical damage, etc.) on the surface or
periphery of the silicon wafer can cause premature
cracking under stress because of the notch effect.
Silicon wafers having a rough surface or residual dam­
age left on the wafer surface (cut wafer, lapped wafer,
or ground wafer without stress relief) are more prone
to break compared with polished wafers. The ideal,
“strong” wafer is double side polished, and the wafer
edge is polished and round, also. Samuels and Roberts
[16] used pre-cracked bar-shaped single crystal speci­
mens in four point bending tests and found a brittleductile transition temperature of 545°C at ambient
pressure. At room temperature they measured a frac­
ture stress of 270 MPa. Under 1.5-GPa confining pres­
sure, the brittle ductile transition temperature can be
lowered to 275°C, after Rabier and Dement [17]. For
a comparison, Vedde [18] gives, for median fracture
strength (at 50% probability level) when using a doublering bending test method, 1.18 GPa for polished CZ
wafer and 1.01–1.12 GPa for FZ wafer (different
growth processes), compared with an as-cut state from
180 to 220 MPa or 270 to 330 MPa in an as-lapped state.
However, these values are here only as indicators,
since, in practice testing conditions, the starting mate­
rial quality, wafer manufacturing processes, and possible
10
τ (MPa)
1000
100
10
1
0.1
Fig 1.10 ● Lower yield strength of silicon vs. deformation
temperature. Reprinted from Physica Status Solidi B, Copyright
2000 John Wiley.
post-treatments of the wafers have an influence on the
fracture tendency.
At elevated temperatures silicon starts to show plastic
deformation. Once the upper yield strength (also called
upper yield point) is achieved, dislocations start to gener­
ate, multiply, and move on slip planes, the stress lowers
to the lower yield strength (point), and plastic deforma­
tion proceeds. When the dislocation density is increasing,
dislocations reach each other, slip is prevented, the lat­
tice hardens, and stress required for further deformation
is increased, until fracture occurs. Silicon single crystals
made with CZ or FZ techniques have similarly shaped
stress–strain curves, provided that the crystals are ini­
tially dislocation free [19, 20] (Figure 1.9).
The value of lower yield strength varies with the
temperature, according to Figure 1.10 [17]. At 900°C,
the critical shear stress on the (111) plane required to
move dislocations is about 8 MPa.
Oxygen containing CZ silicon has, in practice, a
higher tolerance against slip compared with oxygen-free
FZ silicon. The difference is that when the deformation
stops, in oxygen containing CZ, silicon dislocations are
locked rapidly by diffusing oxygen to dislocations, while
in oxygen-free FZ silicon, this locking does not take
Properties of Silicon
3
2
O-treated FZ-Si
(O)~ 1017 cm–3
τeff
O-treated FZ-Si
FZ-Si
CZ-Si
FZ-Si
1 × 106
5
CZ- Si
(O) ~ 8×1017cm–3
1
N0(cm–2)
2 × 105
6
T = 900°C , ε̇ ~1.1× 10–4 s–1
N0~106cm–2
τuy , 107N/m2
Resolved shear stress,107 N/m2
4
CHAPTER 1
4
T = 800°C
3
2
0
T = 900°C
10
20
30
40
50
1
Shear strain, %
Fig 1.11 ● Actual result of stress–strain behavior of silicon single
crystals having initial dislocation density of 106/cm�2 deformed
at 900°C. Oxygen-free FZ-silicon does not have an upper yield
point. FZ with added oxygen, as well as standard CZ-silicon, has
an upper yield point. Reprinted with permission from Japanese
Journal of Applied Physics, Copyright 1980, Japan Society of
Applied Physics [20].
place and dislocations can move easily. Once deformed,
CZ material shows again an upper yield point consider­
ably higher compared with the stress required to move
dislocations, while FZ silicon starts to deform at a stress
level required to move dislocations in constant deforma­
tion (Figure 1.11) [20]. FZ silicon can be “hardened” by
adding oxygen or nitrogen, but, in general, FZ is more
prone to slip, which has to be taken into account when
designing thermal treatment steps.
Oxygen concentration in dislocated silicon crystals
has a significant effect on upper yield strength. Figure
1.12 shows an upper yield strength dependence on
oxygen concentration at 800°C and 900°C, with two
different initial dislocation densities [21]. When the
initial dislocation density increases, the effect of oxy­
gen diminishes and the upper yield strength falls. Thus,
slipped wafers in thermal treatments (and especially
in the cooling phase, where radial stresses in wafers
are highest) are more susceptible to further slip with
increasing initial dislocation content.
It should be noted that silicon wafers in the
as-received state typically do not have dislocations;
exceptions are some epi wafer types with thick epitax­
ial layers. In these epi wafers, specifications allow some
maximum amount of slip.
The oxygen-related bulk microdefect density has to
be minimized in some MEMS processes; this is done by
minimizing the initial oxygen content in silicon wafers.
The adverse effect is that when such wafers are used,
more attention has to be paid to controlling stresses
in wafers during thermal processes at temperatures at
which silicon is still plastic.
0
0
5
10
Co , 1017cm–3
Fig 1.12 ● Upper yield strength vs. oxygen content of dislocated
CZ-silicon at 800°C and 900°C. Silicon crystal with a higher
dislocation content has lower strength (τ is the effective stress on
the (111) slip plane). Reprinted with permission from Journal of
Applied Physics, Copyright 1984, American Institute of Physics.
1.1.4 Electrical Properties
Silicon is a group IV element in the periodic table and is
a semiconductor with a bandgap of 1.12 eV, which means
that pure silicon at room temperature is almost an insu­
lator. By doping with group III or group V elements, the
resistivity of silicon can be varied over a wide range.
1.1.4.1 Introduction—Dopants and Impurities
in Silicon
Semiconductors are solid materials that have electrical
conductivities in between those of conductors and those
of insulators. The physical reason causing a material to
behave as a conductor, semiconductor, or insulator lies
in the availability, or lack thereof, of free current carriers
in the material. Semiconductors are characterized by the
narrow bandgap between the valence bands, occupied by
electrons, and the conduction band, in which electrons
move freely according to applied electrical fields. Intrinsic
(i.e., pure) semiconductors act as insulators at room
temperatures, but their behavior changes dramatically
with temperature, and, more to the point, with small
impurities present in the crystal. Very small amounts of
electrically active impurities can totally alter the electri­
cal properties of semiconductors such as silicon. This is
because the electrically active impurities either easily
donate valence electrons (donors) or accept them, creat­
ing holes (acceptors). These electrons or holes are free
(i.e., not bound to individual atoms). Their movement due
11
PA R T I
Silicon as MEMS Material
to applied electrical fields carries electrical currents, giv­
ing rise to the term charge carriers used to denote them.
The electrical properties of semiconductor materi­
als such as single-crystal silicon are thus defined by the
impurity concentrations present in the silicon lattice.
Impurities are introduced into the starting materials dur­
ing crystal growth and modified during device processing
by additional doping of the silicon material with electri­
cally active impurities. In intentional doping of silicon,
impurity atoms from group III (acceptors) and group V
(donors) are used. The dopants used in crystal pulling,
and the conductivities reached with specific impurity
concentrations, are described in more detail in Sections
3.1 and 3.3, Dopants and impurities in silicon crystals.
Manipulation of the electrical properties in the struc­
tures created during MEMS device manufacturing follows
practices established in semiconductor device manufactur­
ing. Techniques used include both very traditional meth­
ods, such as deep diffusions of dopants, which have been
abandoned in mainstream semiconductor processes, and
current standard techniques such as ion implantation and
epitaxial deposition. While semiconductor-grade starting
materials are largely free of other electrically active impu­
rities, the incorporation of unintentional contamination
into silicon during processing can have significant effects
on the electrical properties of the manufactured devices.
Unintentional doping of silicon includes the intro­
duction of unwanted donors or acceptors to the crystal
lattice from the processing environment. These impuri­
ties can be either group III/V-type atoms misplaced, or
other contaminants, such as some transition metals.
The generation of electrically active donors also takes
place within the single-crystal CZ silicon itself, with­
out the introduction of additional impurities. CZ silicon
always includes a few ppma of interstitial oxygen atoms,
originating from the quartz crucible used to hold the
melt during crystal pulling (see also Chapter 3). At cer­
tain temperatures, ranging from 400°C to 550°C, these
interstitial atoms create conglomerates of several oxygen
atoms within the lattice. Such silicon–oxygen microclus­
ters are known as thermal donors (TD), as they donate
free electrons to the conduction band, influencing the
electrical properties accordingly [22, 23]. The concentra­
tion is, however, usually below 1E15/cm3, and thus has
only very marginal effects on other than high-resistivity
silicon. These donors are not stable at temperatures above
600°C, and even for applications requiring high-resistivity
silicon, their effect can be suppressed by quick cool­
ing down over the generation temperature range. This
method is called thermal donor anneal (TDA), and while
it is effective, it does not prevent the generation of new
TD if temperatures in the critical range are used later in
the device processing. For further details, see Section 3.6.
The use of semiconductors is based on the fact that
the charge carrier concentrations are also influenced by
12
any electric fields that are present. This can take place
intentionally, as, for example, in transistors, but also
due to electric fields generated by surface effects such
as charging. These effects are more pronounced in highresistivity silicon, but they bear consideration in general.
In the vast majority of cases, the electronics required
for the realization of a MEMS-based sensor consist of
the basic building blocks of semiconductor electronics
used since the birth of the silicon-based semiconduc­
tor industry and described in the basic handbooks of
the industry, such as Sze [24]. In MEMS applications
requiring very high resistivity, in fields such as RF and
optical, special considerations apply. The very high resis­
tivity materials used are obviously strongly affected by
even the smallest concentrations of unintended charge
carriers. These unintended charge carriers can be intro­
duced into the material by methods such as TD genera­
tion (described earlier), oxidation, and contamination
of the surface if the donors/acceptors are not subse­
quently evaporated. In very high resistivity silicon, these
effects can be severe, in some cases even leading to type
reversal.
1.1.4.2 Piezoresistive Effect in Silicon
General Piezoresistive Effect
The change in the resistance of metal devices due to an
applied mechanical load was first discovered by Lord
Kelvin in 1857. With the large-scale use of single-crystal
silicon in the making of semiconductor circuits, a much
stronger piezoresistive effect was discovered in silicon
[25]. This discovery forms the basis for practically all
piezoresistive MEMS applications.
Strain
When a sample is subjected to physical force, the force
yields a change in length, dL, that follows the well
known Hooke’s law F � kΔL, where k is a material
constant. The stress is defined as the applied force per
unit area. Stress (σ) is thus given by
σ � F/A � kΔL/A � k L ΔL/AL or k εL L/A
(1.1)
where �L denotes the differential deformation, ΔL/L,
known as strain. Most solids exhibit elastic behavior for
small stress loads. In elastic deformation the strain is
proportional to the applied stress and the material fol­
lows Hooke’s law, which, in the simple case of uniaxial
stress, can be written as
σ � Y εL
(1.2)
where the scalar Y stands for the modulus of elasticity,
also known as Young’s modulus. This material parameter
for crystalline materials such as silicon is not omnidirec­
tional, but varies according to crystal planes.
Properties of Silicon
For strains above certain thresholds, Hooke’s law is
no longer valid. This is caused by non-elastic, or irreversible (i.e., plastic) deformation.
The piezoresistive effect is quantified using the gauge
factor G, describing the relationship between the applied
strain and the change in resistivity. The piezoresistive
effect, and thus also the gauge factor of semiconductor
materials, is several magnitudes larger than the geometri­
cal effect observed in metals. The effect is observed in
several semiconductor materials, such as germanium,
polycrystalline silicon, and single-crystal silicon.
The large piezoresistive effect in silicon is due to the
fact that, instead of a stress-dependent change in geo­
metry, the effect is first and foremost due to the stress­
dependent resistivity of the material. The strain applied
to the lattice causes the anisotropic band structure to
deform, giving rise to anisotropic change in the mobility
of the current carriers.
Stress in Anisotropic Materials
The elastic behavior of isotropic materials can be
defined with just two elastic constants, commonly used
parameters being the Young’s modulus Y and Poisson’s
ratio ν, but modified constants known as bulk modulus
K and shear modulus G are also sometimes used. In the
general anisotropic case, the stress state of the mate­
rial, is defined by a matrix known as the stress tensor, a
3 � 3 matrix in three dimensions.
Crystallographic symmetry allows the reduction of
stress tensors in silicon to 6-vector notation. In static
equilibrium, the situation is further simplified to just 6
independent variables, and the stress tensor can be writ­
ten as [26]:
⎡σ xx
⎢
⎢
σ � ⎢σ xy
⎢
⎢ σ xz
⎣
σ xz ⎤⎥
⎥
σ yz ⎥
⎥
σ zz ⎥⎦
σ xy
σ yy
σ yz
(1.3)
Typically, the geometries used in MEMS applications
reduce the situation, as in the case of a piezoresistive
sensing layer created on a relatively thick silicon substrate. For such a layer, the vertical (z) stresses can be
equated to zero, and the stress is reduced to
⎡σ xx
⎢
σlayer � ⎢⎢σ xy
⎢
⎢⎣ 0
σ xy
σ yy
0
0⎤
⎥
0⎥⎥
⎥
0⎥⎦
(1.4)
This expression can be further simplified if we limit
our discussion to stresses parallel, and stresses perpen­
dicular, to the direction of current. For practical sensor
systems, this limitation can easily be applied.
Thus, the forces can be denoted as σl (parallel stress)
and σt (perpendicular or transverse stress).
CHAPTER 1
Strain Effect on Resistivity
In metals the conduction/valence bands are partially
filled with charge carriers, and small changes in band
shape do not affect most of the carriers. In semiconduc­
tors the shape and dimension of the bandgap has a much
larger effect, and shifts in energy bands due to applied
stress affect the mobility of charge carriers. The result
is resistivity change due to applied stress and gauge fac­
tors up to two magnitudes larger than those observed in
metals. Because the relative change in resistivity is proportional to strain, it can be written as
Δρ
� Y πL εL
ρ
(1.5)
For strained anisotropic material, the resistivity is thus
no longer scalar and is described through tensor math­
ematics, similar to the mathematics described earlier for
stresses in anisotropic material. Thus, the dependence of
the current density J on the electric field E is denoted
⎡
⎡E ⎤
⎢ρxx
⎢ x⎥
⎢
⎢E ⎥ � ρ
⎢ xy
⎢ y⎥
⎢
⎢ ⎥
⎢ ρxz
⎢⎣ Ez ⎥⎦
⎣
ρxy
ρ yy
ρzy
ρxz ⎤⎥ ⎡ J x ⎤
⎢ ⎥
⎥
ρ yz ⎥ ⎢⎢ J y ⎥⎥
⎥⎢ ⎥
ρzz ⎥⎦ ⎢⎣ J z ⎥⎦
(1.6)
Details of the tensor mathematics explaining the
anisotropic resistivity are described in, for example,
Thomsen [26].
In typical applications the MEMS devices are con­
structed in such a way that the current in the piezore­
sistors is either parallel or perpendicular to the direction
of the stress. Also, the vast majority of applications
are made on (100) silicon wafer substrates, with the
substrate oriented in such a way that the resistors are
aligned on the [110] direction on p-type and the [100]
direction in n-type, as depicted in Figure 1.13. These
directions yield the maximum positive and negative
piezo coefficients (i.e., the maximum relative resistivity
change for a given applied force).
For a system in which the coordinates are chosen to
coincide with the crystallographic axes, the relationship
between the stress tensor and the anisotropic change in
resistivity simplifies due to crystallographic symmetries
of silicon, and can be defined as
⎡ ∂ρ11 ⎤
⎡ Π11 Π12
Π12
1
⎢
⎥
⎢
⎢∂ρ22 ⎥
⎢ Π12 Π11 Π12
⎢
⎥
⎢
⎢Π
Π12 Π11
1 ⎢⎢∂ρ33 ⎥⎥
�⎢
� ⎢⎢ 12
⎥
∂
ρ
0
0
0
ρ ⎢ 23 ⎥
⎢
⎢ 0
⎢∂ρ ⎥
0
0
⎢ 13 ⎥
⎢
⎢
⎥
⎢
0
0
⎢⎣∂ρ12 ⎥⎦
⎢⎣ 0
0
0
0
0
0
Π44
0
0
0
0
Π44
0
0 ⎤ ⎡ ∂σ11 ⎤
⎥
⎥⎢
0 ⎥ ⎢∂σ22 ⎥
⎥
⎥⎢
0 ⎥⎥ ⎢⎢∂σ33 ⎥⎥
0 ⎥⎥ ⎢⎢∂σ23 ⎥⎥
0 ⎥⎥ ⎢⎢∂σ13 ⎥⎥
⎥
⎥⎢
Π44 ⎥⎦ ⎢⎣∂σ12 ⎥⎦
(1.7)
13
PA R T I
Silicon as MEMS Material
Table 1.2 Independent piezo coefficients for crystalline bulk
silicon [25, 27]
10�11 1/Pa
n-Si ND � p-Si NA p-Si NA
2e15[25] 1e18[27]
4e1425
Π11
�102
�6,6
Π12
�53
�1,1
Π44
�14
�138
�103
1
[π11 � π12 � π44 ]
2
�81
(1.8)
(1.9)
The corresponding transversal piezo coefficient then
becomes
πt �
1
[π11 � π12 � π44 ]
2
(1.10)
For piezoresistors in the �100� plane of an n-silicon
substrate, the maximum piezo coefficient is found along
the (100) crystal axis, and the piezo coefficients are
reduced to
πl � π11
(1.11)
and
have contributed to the dominance of bridge circuits in
piezoresistive sensing based on silicon.
The alignment of piezoresistors to be constructed
is governed by the piezoresistive coefficients listed in
Table 1.2. Almost universally, the optimal solution is to
align the sensing resistors according to maximum pie­
zoresistive effect, as described by the examples depicted
in Figure 1.13. The choices of resistor direction, dicing
direction, and anisotropic etching are determined by
the crystal orientations. In addition, the specification of
the crystallographic location of the substrate wafer flat
is based on the chosen crystal alignment. The primary
flat has historically been located at the �110� direc­
tion, and dicing along and perpendicular to the primary
flat is depicted in Figure 1.13a, c.
Linearity
In comparison to many other physical phenomena, the
piezoresistive effect is a fairly linear effect. To be exact,
the linear equations for piezo coefficients should, how­
ever, be replaced with higher order polynomials. For
resistors aligned on the �110� crystal axis, for maxi­
mum piezoresistive effect in p-type silicon, a quadratic
correction to the transversal piezoresistive coefficient is
sufficient for a wide range of doping concentrations and
applied stresses. The quadratic correction for p-type sil­
icon along the �110� crystal axis is of the form [28]
∂ρ
� πl σl � πt σt [1 � 6.66 � 1010 σt 1/pa]
ρ
(1.13)
yielding a quadratic correction of less than 1% for
stresses up to 10 Mpa.
Effect of Temperature and Doping
πt � π12
(1.12)
It is immediately observed that for both n- and ptype piezoresistors, uniaxially stressed at respective
optimum locations for sensitivity, the longitudinal and
transverse piezo coefficients have opposite signs. The
advantages offered by this fact in a Wheatstone bridge
14
(c)
N-type silicon,
Dicing along <100>
Fig 1.13 ● Typical piezoresistor alignments used on MEMSstandard (100) silicon wafers, aligned to utilize maximum piezo
coefficients for rectangular membranes of the type used in
pressure sensors.
where the common notions of longitudinal piezo coeffi­
cient πl and transversal piezo coefficient πt are used. As
an example of a common situation, let us consider the
case of a p-type piezoresistor constructed to utilize the
maximum piezo sensitivity as described in Figure 1.13a.
For such a resistor, which is uniaxially stressed and lying
in the (110) direction, the shear strain is zero and the
longitudinal piezo coefficient is simplified to
πl �
(b)
P-type silicon,
Dicing along <100>
p-Si NA
1e19[27]
where Π11, Π12 and Π44 represent three independent
piezo coefficients, listed in Table 1.2.
In most applications the change in resistivity is
limited to stresses parallel and perpendicular to the
resistive path. In such cases, the situation is greatly sim­
plified [28]. The tensor element becomes a scalar equa­
tion, and can be written as
∂ρ
� πl σ l � πt σ t
ρ
(a)
P-type silicon,
Dicing along <110>
In addition to the piezoresistive effect, the silicon resis­
tors exhibit strong temperature dependence. For pie­
zoresistors with low to moderate doping, the resistivity
changes can reach one magnitude for every 100°C.
Change in offset is caused by leakage currents, which
are strongly dependent on temperature according to
Laermer [29]. While in some cases the temperature
Properties of Silicon
dependence can be utilized or ignored, in the vast major­
ity of cases this must be compensated for. Combined
with the effect of doping on the piezoresistive effect,
the temperature effect can be corrected with the pie­
zoresistance correction factor P(N,T). Generally, a
higher dopant concentration in silicon reduces the tem­
perature effect, whereas the higher the temperature,
the lower is the effect of doping level. Thus, designing
of the resistor requires a trade-off between sensitivity
and temperature stability (Figure 1.14).
The modern IC technology can provide a mathemati­
cal solution to the compensation of the piezoresistors,
by introducing signal conditioning of the linearity and
temperature effect to the sensing setup. This approach
provides additional accuracy and flexibility at the cost
of some cost and complexity. While the approach is
commonly used to improve nonidealities in surface
micromachined sensors, the performance of sensing ele­
ments manufactured from bulk, single-crystal silicon
is usually close to ideal when temperature effects are
accounted for.
Basic solutions for correcting for temperature varia­
tions include the use of a reference (i.e., a non-strained
resistor which is at the same temperature). The differ­
ence of signal between the strained and non-strained
sensors provides the desired signal due to strain only.
The other basic technique is to utilize a temperatureindependent circuit—in practice, a bridge circuit.
In a Wheatstone bridge circuit application, the four
resistors are doped to the silicon and arranged in such a
way on the sensing membrane that they react to strain in
pairs. In addition to having the advantages in sensitivity,
discussed earlier, the bridge circuit can be used to com­
pensate for temperature effects. The standard setup of
a Wheatstone bridge in (100) silicon substrate consists
of one pair of resistors aligned to give maximum positive
change in resistivity (longitudinally stressed if p-type,
Piezo correction factor P(N,T)
1.6
T = –73 °C
n-Si
1.4
1.2
T = –25 °C
1.0
T = 25 °C
0.8
T = 75 °C
T = 125 °C
T = 175 °C
0.6
0.4
0.2
1E16
1E17
1E18
ND1/cm3
1E19
1E20
Fig 1.14 ● Piezo correction factor P(N,T) in n-Si as a function of
doping level, for various temperatures. Redrawn and modified
from Kanda [30].
CHAPTER 1
transversely stressed if n-type), while the other pair
yields the maximum negative change (a perpendicular
alignment with respect to the first pair of resistors).
This bridge circuit provides an output signal which is
independent of temperature, assuming that the whole
membrane is subjected to equal temperature changes.
The circuit output is thus, to a first-degree approxi­
mation, directly proportional to the change in resistiv­
ity due to the applied stress. The main disadvantage of
piezoresistive gauging using bridge circuits lies in the
current requirements in the milliampere range, which
cause limitations in the use of these circuits in powersensitive applications.
Example of a Piezoresistive Sensor Design
Pressure sensing has utilized piezoresistive sensing based
on MEMS technology for years and is the first widely
adopted application of the technology. This is due to
the fact that thin micromachined silicon membranes
with a piezoresistor bridge implemented on top of them
provide a rather ideal solution to the common prob­
lem of sensing pressure over a known, rather limited
range of pressures, over long periods of time and count­
less cycles of pressure changes, for low cost and no
maintenance.
A very basic sensing setup is as follows:
Starting point:
Silicon substrate, N-type, (100) orientation, device
dicing along �110� direction.
Membrane defined by etching, using an alkali etchant from the backside of the wafer. The long etching is
carried out in concentrated KOH or TMAH, requiring
a thick protective layer of oxide, or nitride. The tradi­
tional bulk micromachining has utilized backside pat­
terning for these cavity-etching processes.
Cavity sealed through wafer bonding. The sealing
options range from glues and glass frits to fusion bond­
ing of silicon wafers.
Piezoresistors are boron implanted on top of the wafer,
at the edges of the membrane, where the stress maxims
are located when the cavity pressure differs from the
outside pressure. Boron implantation of the ohmic con­
tacts can usually also be performed at this stage.
The basic device is finished with one or two layers of
metals.
The dopant profile of a simple implanted and dif­
fused piezoresistor of the type described is illustrated in
Figure 1.15. The denuded zone responsible for the elec­
trical isolation is shown without bias; with reverse bias,
it can be extended to meet the requirements.
The basic device outlined earlier follows the geom­
etry outlined in Figure 1.16. This device has the pie­
zoresistors located at the stress maximums of the
rectangular membrane and along the crystal axis yield­
ing greatest change in resistivity for a given stress. Also,
15
PA R T I
Silicon as MEMS Material
(a)
(b)
V output
V input
Fig 1.16 ● Basic MEMS-based sensor application using
piezoresistors in �100� silicon. (a) Side view (cross-section
along the �110� plane. (b) Top view, with the piezoresistors
located in a Wheatstone bridge, along the (110) direction on the
top of the silicon membrane.
Fig 1.15 ● Basic diffused piezoresistor dopant depth profile.
The wafer surface is to the left, and the piezoresistor is hatched.
The transition zone under the piezoresistor acts as the electrical
isolation. The hatched line (� · · �) on the left denotes free hole
concentration, and the hatched line (— · —) on the right side
of the transition denotes free electron density, approaching the
starting material ND density in the depth of the wafer. The graph
is calculated using IC-simulation software ICECREM 4.3 for
WINDOWS™ by Fraunhofer Gesellschaft for Integrated Systems
and Device Technology (IISB), Erlangen, Germany[31], and the
carrier concentrations refer to zero bias.
the shear stresses of the membrane are minimized, the­
oretically to zero, at the locations of the resistors.
Surface Effects
In many cases, the carrier concentration depth profile
of the piezoresistor can be very important. Especially
in accelerometers, the piezoresistive MEMS-sensor is
often loaded so as to cause compressive strain on one
side of the membrane and tensile strain on the other.
In such a case the effective piezo coefficient, and thus
the sensitivity, is very strongly influenced by the ratio
of carrier concentrations between the membrane sur­
faces. Also, those piezoresistors whose stress is purely
compressive or tensile are affected by the vertical car­
rier profiles, as the greatest strains are located at the
very surfaces of the membrane. On the other hand,
the carrier concentrations tend to change more rap­
idly the closer they are to the surface. Because the car­
rier concentrations near the device surfaces can also
be affected by charging of the dielectric layers used to
isolate and seal the micromachined structures, a care­
ful consideration of the design principles used in ana­
log transistor design is necessary to ensure the reliable
operation of the piezoresistive element.
References
1. 2006 Minerals Yearbook, Silicon,
published by US Geological Survey,
March 2008 (http://minerals.usgs.
gov/minerals/pubs/commodity/silicon/
myb1-2006-simet.pdf)
2. P. Woditsch, W. Koch, Solar grade
silicon feedstock supply for PV
industry, Sol. Energ. Mate. Sol. Cells
72 (2002) 11–26.
3. A.A. Istratov, T. Buonassini, M.
D. Pickett, M. Heuer, E.R. Weber,
Control of metal impurities in
“dirty” multicrystalline silicon for
solar cells, Mat. Sci. Eng. B 134
(2006) 282–286.
4. K. Petersen, Silicon as a mechanical
material, P. IEEE 70 (1982) 420–457.
5. R. Hull (Ed.), Properties of Crystalline
Silicon, Inspec, London, 1999.
16
6. Landolt-Börnstein Group III,
Condensed Matter volume series,
Springer Verlag
7. J. Martin, U. Kuetgens, J. Stümpel, P.
Becker, The silicon lattice parameter—
an invariant quantity of nature?
Metrologia 35 (1998) 811–817.
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X-ray Diffraction, third ed., Prentice
Hall, 2001.
9. �http://www.jmtilli.iki.fi/~juhis/
stereographic/� a free software
10. �http://www.jcrystal.com/products/
winwulff/index.htm� a commercial
software
11. R. Falster, V.V. Voronkov, F. Quast, On
the properties of the intrinsic point
defects in Silicon: a perspective from
crystal growth and wafer processing,
Phys. Status Solidi B 222 (2000)
219–244.
12. R. Falster, V.V. Voronkov, The
engineering of intrinsic point defects in
silicon wafers and crystals, Mater. Sci.
Eng. B73 (2000) 87–94.
13. A. Borghesi, B. Pivac, A. Sassela, A.
Stella, Oxygen precipitation in
silicon, J. Appl. Phys. 77 (1995)
4169–4244.
14. W. Bergholz, D. Gilles, Impact of
research on defects in silicon on the
microelectronics industry, Phys. Status
Solidi B 222 (2000) 5–23.
15. T. Sinno, E. Dornberger, W. von
Ammon, R.A. Brown, F. Dupret,
Defect engineering of Czochralski
single-crystal silicon, Mater. Sci. Eng.
28 (2000) 149–198.
Properties of Silicon
16. J. Samuels, S.G. Roberts, The
brittle-ductile transition in silicon. I.
Experiments, P. Roy. Soc. Lond. A421
(1989) 1–23.
17. J. Rabier, J.J. Demenet, Low
temperature, high stress plastic
deformation of semiconductors: the
silicon case, Phys. Status Solidi B 222
(2000) 63–74.
18. J. Vedde, P. Gravesen, The fracture
strength of nitrogen doped silicon
wafers, Mater. Sci. Eng. B36 (1996)
246–250.
19. K. Sumino, H. Harada, I. Yonenaga,
The origin of the difference in the
mechanical strengths of Czochralski­
grown silicon and float-zone-grown
silicon, Jpn. J. Appl. Phys. 19 (1980)
L49–L52.
20. K. Sumino, I. Yonenaga, A. Yuasa,
Mechanical strength of oxygen doped
float-zone silicon crystals, Jpn. J. Appl.
Phys. 19 (1980) L763–L766.
21. I. Yonenaga, K. Sumino, K. Hoshi,
Mechanical strength of silicon
crystals as a function of the oxygen
concentration, J. Appl. Phys. 56
(1984) 2346–2350.
22. H. Takeno, K. Aihara, Y. Hayamizu,
T. Masui, Influence of rapid
thermal annealing on thermal donor
formation and oxygen precipitation
in Czochralski silicon, in: T. Abe,
W.M. Bullis, S. Kobayashi, W. Lin,
P. Wagner (Eds.), Defects in Silicon
III, Proceeding Volume 99-1, The
Electrochemical Society, USA, 1999,
150–161.
23. G.S. Oehrlein, T.Y. Tan,
R.L. Kleinhenz, J.L. Lindstrom, On
the question of oxygen diffusion
during oxygen related thermal donor
formation in silicon, in: M. Wittmer,
J. Stimmell, M. Strathman (Eds.),
Materials Issues in Silicon Integrated
Circuit Processing, Mater. Res. Soc.
Symp. Proc., 71 (1986) 65–67.
24. S.M. Sze, Physics of Semiconductor
Devices, Wiley, New York, 1981.
25. C.S. Smith, Piezoresistance effect in
germanium and silicon, Phys. Rev. 94
(1954) 42–49.
26. E.V. Thomsen, J. Richter, Piezo
Resistive MEMS Devices: Theory and
Applications, Technical University of
Denmark, Copenhagen, 2005.
CHAPTER 1
27. J. Richter, O. Hansen, A. Nylandsted
Larsen, J. Lundsgaard Hansen, G.F.
Eriksen, E.V. Thomsen, Piezoresistance
of silicon and strained Si0.9Ge0.1,
Sensor Actuat. A 123–124C (2005)
388–396.
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piezoresistive Siliziumsensoren auf
der basis halbleitertechnologischer
standardprozesse, Doctoral thesis,
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31. Fraunhofer Gesellschaft for Integrated
Systems and Device Technology
(IISB), Erlangen, Germany.
17
2
Chapter Two
Czochralski Growth of Silicon
Crystals
Olli Anttila
Silfex Incorporated—A Division of Lam Research
Corporation, Eaton, OH, USA
Czochralski (CZ) growth of silicon has been named
after the Polish scientist Jan Czochralski, who in 1918
published his report on the growth of single-crystal
metal filaments from melt [1]. The present method is
largely attributable to Teal and Little and dates back
to the early 1950s when it was not yet clear whether
single-crystal semiconductor material would have any
significant advantage over polycrystalline materials and
the material of choice was germanium more often than
silicon [2–4]. The differences in the method devel­
oped by Teal and Little were so large compared with
the original method by Czochralski that it would prob­
ably be more just to call it the Teal–Little method [4].
The existence of another method, zone refining, that
was originally used to purify germanium polycrystal­
line material for semiconductor applications and from
which the float-zone (FZ) method was developed, may
have had an influence on the choice of the name of the
method: The abbreviations form now a nice match.
In this chapter, only CZ crystal growth is discussed.
This is because CZ material dominates the industry by
a large margin, crystal availability is good, modern tech­
niques also allow growth of high-resistivity silicon, and
all commercial crystal sizes can be made with CZ tech­
nique. Only if very high-resistivity silicon (2–3 kΩcm)
or silicon without dissolved oxygen is needed, FZ
material should be used. Still today, the availability of
the highest-purity FZ crystals in 200 mm diameter is
limited. Those interested in learning more about the
FZ technique should consult, for example, reviews of
Dietze [5], Zulehner [6], or Mühlbauer [7].
In late 1950s, Dash significantly improved the
method of growing silicon crystals by adding a neck­
ing step to avoid dislocations [8]. This improvement is
routinely used for both CZ and FZ crystals. The role
of this step is explained later in more detail. The CZ
growth method has remained fundamentally unchanged
since, and it is the workhorse that produces the vast
majority of single-crystal silicon used even today, almost
50 years after its introduction. Major evolutionary steps
have been made; for example, maximum crystal weights
are several hundreds of kilograms, magnetic fields are
applied for better control of the melt behavior, all imag­
inable quality requirements have been reviewed several
times, and the productivity has experienced enormous
improvements.
2.1 The CZ Crystal-Growing
Furnace
The CZ furnace is a vacuum furnace that consists of
the following subassemblies: crucible lifting and rotat­
ing system, growth chamber that houses the hot zone
(HZ), vacuum interlock, receiving chamber for the
grown crystal, and crystal rotating and lifting sys­
tem. For more details, see Ref. [9], Figure 81 a and b.
Modern CZ systems are able to grow crystals up to
450 mm in diameter, with charge sizes close to 500 kg.
In MEMS applications, however, the maximum size of
the crystal is 200 mm in diameter, and charge size may
exceed 100 kg.
2.1.1 Crucible
An essential part of CZ growth is that the single semi­
conductor crystal is pulled out of melt that is contained
19
PA R T I
Silicon as MEMS Material
in a refractory crucible. No solvent is used; that is, the
melt consists of the same elements as the growing crys­
tal. In the case of silicon, the melt is almost pure ele­
mental silicon, at about 1420°C. The crucible and the
crystal are both rotated, and the crystal is slowly pulled
upwards in such a manner that a cylindrical body of
desired diameter is achieved.
Molten silicon reacts with all known materials to the
extent that there are very few potential materials for
a crucible [9]. The only available crucible material for
high-quality crystals is silicon dioxide in its amorphous
state, silica. A glimpse at the periodic table of the ele­
ments and the knowledge of the deleterious impact that
most elements have on silicon material quality, even in
very minute quantities, lead to only a few candidates.
Almost all metals are excluded because the allowed
concentrations are only in parts-per-trillion atomic
(ppta) range. Group III and group V elements are elec­
trically active dopants that often may be tolerated to
much higher levels, typically to parts-per-billion atomic
(ppba) range, but this concentration is also far too low
to allow crucibles to be made with compounds of these
elements. Ceramic materials are excluded as well,
either because they contain one of the aforementioned
elements or because they contain other elements whose
concentrations likewise must be held very low. Nitrogen
(e.g., from silicon nitride crucible) is poorly soluble to
the crystals, and the growing crystal tends to strongly
reject it. The same applies to carbon. Concentrations of
these elements in the melt are then highest very near
the freezing interface, and as solubility is approached
in the melt, there will be small particles nucleated that
destroy the single-crystalline structure of the growing
crystal. Furthermore, neither nitrogen nor even less so
carbon is allowed in the crystal in levels even close to
their solubilities, though nitrogen is sometimes inten­
tionally introduced into the material, especially for FZ
crystals. However, this topic will not be pursued any
further here.
The situation with oxygen is, fortunately, different.
Oxygen is allowed in the crystal in a fairly large concen­
tration, typically in 10 parts-per-million atomic (ppma)
range; and in most applications for silicon wafers, oxy­
gen is a desired element, in controlled quantities, with
clear beneficial effects. Furthermore, oxygen does not
tend to be rejected by the crystal; that is, its segregation
coefficient is close to unity [10], and there is no risk of
oxide particles being created near the freezing interface.
In addition to this, silicon has a volatile oxide, contrary
to its carbides and nitrides: At high temperatures, in an
oxygen-lean environment, silicon tends to form silicon
monoxide rather than silicon dioxide. This monoxide is
easily volatilizable, with vapor pressure of about 12 mbar
at silicon melting temperature [6]. In practice, the vast
majority (98–99%) of oxygen that is being dissolved
20
from the silica crucible wall by the highly reactive sili­
con melt will be evaporated into the grower atmosphere
and purged away by the inert gas flow that is mandatory
for successful growth. Only 1–2% of the dissolved oxy­
gen ends up in the growing crystal itself.
The introduction of the reactive silicon monoxide to
the otherwise inert gas flow is a major factor that causes
unwanted reactions on the hot surfaces around the cru­
cible and melt. The gas flow patterns inside the grower
must be designed to take the potentially harmful effects of
monoxide into account, especially as the quantity of oxy­
gen released into the gas flow over one growth may be in
the range of hundreds of grams in today’s large furnaces.
2.1.2 Hot-Zone Materials
The basic building material for a HZ for silicon CZ crys­
tal growth is high-purity graphite. The term “hot zone” is
used in this book to define the structural and insulating
parts inside of the vacuum compatible chamber of a crys­
tal grower, which parts are essential in creating a proper
temperature distribution around the semiconductor melt
and the growing crystal. Furthermore, HZ design largely
defines purge gas flow patterns inside the grower.
Graphite is the material of choice because of its good
availability as large blocks, its machinability, as well as its
high temperature characteristics. Carbon in the form of
diamond or graphite has the highest melting point of any
element or almost any chemical compound. The mate­
rial is reasonably strong, especially at high temperatures.
It is also a fairly good conductor of electricity and heat.
Its electrical conductivity makes it suitable as heater
material, and its thermal conductivity is often desirable,
as heat needs to be transported from the heater(s) to the
crucible and elsewhere inside the HZ. However, radia­
tion is typically the dominant mode of heat transfer at
these high temperatures, especially over long distances.
The most commonly used insulator material is graph­
ite felt, in different forms. The felt is made out of thin
fibers, which act as insulation as they block thermal
radiation many times over a short distance. Soft felt is
woven into a relatively thin sheet of material, which may
then be cut into desired shapes and bent over reasonably
tight radii. Rigid felt is made of originally similar fiber
material, but a carbon-containing binder is used to tie
the separate fibers to a more solid, self-supporting body.
Instead of a binder, chemical vapor deposition (CVD) of
carbon may also be used to enhance the mechanical per­
formance of the material. Oftentimes, the outer surfaces
of rigid felt insulation are coated with a more continu­
ous layer of graphite paint or foil, to reduce erosion and
wear as well as particulate contamination. Other types of
carbon-based insulation also exist, such as carbon foam.
Generally, graphitized materials are clearly preferred,
Czochralski Growth of Silicon Crystals
as graphitization reduces drastically the surface area of
the fibers. Therefore, it is much less time consuming to
pump a grower into a proper vacuum, as outgassing from
these high-surface-area materials is significantly reduced.
The graphite parts are manufactured initially from
fine carboneous particles that are mixed with a carbo­
neous binder to form a mass that can be molded either
by extrusion or in an isostatic press. Higher-quality parts
are typically isostatically pressed. The molded blocks are
first carbonized and finally graphitized at very high tem­
perature, close to 3000°C. The parts that are machined
out of these blocks are typically purified in a halogencontaining atmosphere at an elevated temperature to
remove metallic contamination in order to comply with
requirements by the semiconductor industry. However,
even after proper purification, the metal contamina­
tion levels are several orders of magnitude higher than
what is allowed for silicon single-crystal material. Care
must therefore be taken in the hot-zone design to pre­
vent contamination from these parts from accessing the
melt or the crystal surface. The graphite material is also
slightly porous, which makes it possible for the remain­
ing metals deep inside to reach the surfaces fairly eas­
ily. Furthermore, silicon monoxide that is present in the
purge gas around the graphite surfaces is able to pene­
trate deep into the bulk of material and react there.
Many other materials are used to create HZs.
Carbon-fiber-reinforced graphite (CFC) is mechanically
much stronger; but it is also more expensive and poses
more limitations to the design. Silicon carbide (SiC) is in
many respects a better-performing material than graph­
ite; but it has significantly higher cost, and large-sized
components’ availability is poor. However, SiC is often
used as a CVD coating to enhance the lifetime of graph­
ite parts that are exposed to corrosive silicon monoxide,
or to reduce contamination from graphite. The dense
CVD coating effectively blocks contaminants inside of
the slightly porous graphite material from getting to the
surface. Another possibility is CVD carbon, which also
forms a very dense layer on top of a graphite part. Other
high-temperature refractory materials, such as molybde­
num or ceramic materials that are compatible with the
environment, may be used in locations where there is no
risk of contamination to the melt. Molybdenum is often
used because of its moderately high cost, as well as its low
diffusivity into silicon crystal and its very low segregation
coefficient of about 5*10-8 [11], which allows substantial
molybdenum contamination in the melt before damaging
concentration may enter into the crystal.
2.1.3 Hot-Zone Structure
A traditional HZ, as shown in Figure 2.1, contains a
graphite susceptor around the silica crucible (which is
CHAPTER 2
Neck
Graphite heater
Crystal
Silica crucible
Meniscus
Melt
Graphite susceptor
Heat shield
Spill tray
Fig 2.1 ● Basic HZ structure. The melt is contained in a silica
crucible, out of which the crystal is slowly pulled. Around the
heater there are insulating elements to reduce heat losses, and a
spill tray is located below the melt to collect the melt in case the
crucible were to break. Modern HZs may be considerably more
complex.
often called quartz crucible), a cylindrical heater, and a
heat shield around and below the heater. The susceptor
is required because the high temperature causes the
crucible to soften, and a proper mechanical support
is therefore needed. The susceptor also helps distrib­
ute heat around the silica crucible a little bit more
uniformly.
The heater is usually connected to two or four elec­
trodes at its lower edge, typically by some kind of sup­
porting elements also made of graphite. The electrodes
deliver the required power, which is at least tens of
kWs, but often well exceeds 100 kW. The heater is nor­
mally of picket type, which means that it has vertical
slits cut into it in a manner that forces the electric cur­
rent flow up and down, in opposite directions in neigh­
boring pickets (see Figure 2.4). The voltage is quite low
and amperage is high, mainly because of the high elec­
trical conductance of the heater, but also because of the
poor electrical insulation properties of the inert gas at
the low pressure and high temperature normally used in
silicon CZ growth.
A heater would radiate approximately 400 kW per
square meter, at silicon melting point with no insula­
tion around the HZ. The heat shield drastically reduces
the power consumption, and it also helps create a more
proper temperature distribution around the susceptor.
The insulation itself is usually supported and shielded
by structural graphite parts, but these graphite parts
have much less impact on the temperature distribution.
Typically, only a small fraction of the total power fed to
the heater is lost through the insulation. Careful design
is needed to control heat losses through such struc­
tural parts that extend through the insulation, such as
the heater supports, as well as at all openings that are
needed, including the additional open spaces around
21
PA R T I
Silicon as MEMS Material
the heater supports and any openings for gas flows.
Structural parts stretching through the insulation may
easily lead to several, or even more than ten kW’s, of
additional power losses per such part, and more poorly
controlled temperature distribution usually will result.
Under the heater there is a so-called spill tray whose
function is damage containment in the unfortunate
event that the crucible should break while there is melt
inside. This is a rare, but risky, situation, as the molten
silicon is capable of making its way through the walls
of the water-cooled vacuum chamber. Should this
happen, there is a significant risk of dangerous steam
explosion. The role of the spill tray is to collect all mol­
ten silicon and stop it before it makes contact with the
stainless surfaces of the chamber or damages the expen­
sive mechanisms lower in the grower that are respons­
ible for crucible rotation and lift.
2.1.4 Gas Flow
Silicon CZ growth takes place under a continuous flow
of inert gas. A schematic picture of the gas flow pattern
is shown in Figure 2.2. Considering the high tempera­
ture and the reactivity of silicon melt, noble gases are the
only ones allowed. Argon is the gas of choice because of
its much lower cost than that of other noble gases. Argon
has also the advantage of poor thermal conductivity
low pressure
argon gas
silica
crucible
Si
crystal
SiO
Si
melt
O from
crucible
graphite
heater
graphite
support
Fig 2.2 ● Schematic picture of inert purge gas flow. Oxygen is
dissolved from the crucible, and the purge gas removes volatile
silicon monoxide from the vicinity of the melt and the crystal. Only
a small fraction of total dissolved oxygen ends up in the growing
crystal.
22
compared with, for example, helium, and this feature
facilitates the effort to insulate hot areas around the melt
from the water-cooled vacuum-chamber walls. However,
helium remains an option in situations where more effi­
cient cooling is desirable, for example, to enhance cool­
ing of the grower after the power has been shut off.
Typical gas pressure is in the15–50 mbar range,
and gas flow is in the tens to more than 100 standardliters-per-minute (slpm) range. Lowered pressure is
used to reduce gas consumption relative to atmos­
pheric growth. As an example, if the process is running
at 60 slpm/25mbar and the receiving chamber of the
grower has an inner diameter of 12 inches, the result­
ing gas velocity in that part of the grower would be
0.5–0.6 m/s, which is enough to ensure clean laminar
flow. However, larger pressure would require also a
larger mass flow of purge gas, to maintain a flow pattern
that would not be overly influenced by temperature dif­
ferences in the gas and to avoid undesired thermal con­
vection. Furthermore, the oxygen containing gas that
evaporates from the melt must be transported away in
a controlled manner, which requires sufficient volume
flow and gas velocity. The reduced pressure also helps
with the insulation to a certain degree. The practi­
cal lower limit is close to 12 mbar, which is the vapor
pressure of silicon monoxide in equilibrium with silicon
melt at melting point [9]. The monoxide concentration
of the melt is close to saturation near the silica crucible
wall, where the temperature is also typically a few tens
of degrees higher than the melting point. If the pressure
is lowered too much, the melt starts to “boil,” as the
gas pressure is no longer sufficient to prevent monoxide
from escaping in a manner not unlike boiling water.
In a traditional HZ, there is a large open space
above the melt, which space is limited from above by
the water-cooled chamber walls. This large continuous
space allows uncontrolled convection to take place as
the gas experiences heating from below, and the hot­
ter and lighter gas wants to travel upwards, against the
incoming gas flow. Silicon monoxide from the melt,
traveling with this convection and meeting with the
chamber wall, condenses on the cool surface. There are
also other surfaces above the melt that are not quite
that cold, but cool enough for monoxide to deposit.
These layers threaten to cause macroscopic particles to
fall back into the melt, with a high risk of destroying
the single crystalline structure of the growing crystal.
Such poorly controlled gas flows also tend to bring in
other contamination, such as carbon, from the exposed
surfaces of the HZ.
There is also a more subtle mechanism through
which the evaporating silicon monoxide risks killing
the crystal. The saturation vapor pressure of the mon­
oxide is strongly dependent on the gas temperature. As
the monoxide containing gas travels upwards, it cools
Czochralski Growth of Silicon Crystals
down, and tiny monoxide particles are formed. (It is
not clear whether these particles are really made of sili­
con monoxide or whether the composition is rather a
very-fine-grained mixture of silicon dioxide and elemen­
tal silicon.) The poor control of gas flow allows a part
of this cloud of tiny particles to go back down towards
the melt, and some of them may survive the hotter con­
ditions until they make contact with the melt surface
very close to the freezing interface. Marangoni convec­
tion (see Section 2.6.4) then takes the particles directly
to the crystal, again with a chance of loss of structure.
2.2 Stages of Growth Process
The first step of a growth run is to charge the silicon
into the crucible. Silicon is normally stored in clean
double bags, about 5 kg in a bag, though larger contain­
ers may also be used. Double bags also make it possible
to remove the outer bag separately before bringing the
bags into the charging area, to reduce any contamination
that could be transported into the crucible. The cruci­
ble may be charged as it already sits inside the grower.
In order to save time at the grower and also to avoid
contamination, the charge may be prepared in a sepa­
rate area, after which the full crucible, with or without
the graphite susceptor, is transported to the grower and
lifted into place. Handling of a full crucible is challeng­
ing, as its weight varies from tens to hundreds of kgs,
depending on hot-zone size; the material is hard and
brittle, allowing no shocks or scratching; and contami­
nation is an eternal foe.
The way in which different sizes of silicon pieces
are stacked into the crucible is an art of its own kind.
During the time that the temperature is raised, the
charge experiences significant thermal expansion.
However, dimensions of the silica crucible remain
almost unchanged. There is a clear risk that the
expanding charge will chip or even crack the crucible
if large chunks are stacked without sufficient caution.
Furthermore, the charge takes a considerably larger
space before than after it has molten. Normally, the
charge extends well above the rim of the crucible, but
after melting the crucible is less than two-thirds full.
There may be some “hangers” on the walls: chunks
that remain attached to the walls; and some of them
may interfere with the growth or may chip the cruci­
ble before falling down. These hangers remain cooler
than the crucible, as they are free to radiate heat to the
empty space above. Very high power, which could cause
the crucible wall to soften and sag, would be required to
make them lose contact. Careful stacking of the charge
reduces the risk of problematic hanger formation. The
batch melts starting from the edges, and a high col­
umn of silicon chunks, which are fused together, often
CHAPTER 2
forms. This column may create a considerable splash as
it falls down. Furthermore, problems in stacking and
how the melting is performed may result in a bridge
in which the batch is molten from below in such a way
that a layer of fused chunks remains connected to the
walls, high above the melt level. As this bridge plunges,
a severe splash may result.
A crack in the crucible is always a serious situa­
tion, and its consequences must be taken into account
in the design of the HZ as well as in the process con­
siderations. Silicon melt is very fluid and wets various
surfaces, and that is why it is capable of penetrating
through narrow holes and gaps. Therefore, even though
a hole or a crack in the crucible is a rare or very rare
occasion, most HZs are designed to take the full silicon
or almost full silicon charge into the spill tray.
The HZ and silicon melt are both sensitive to any
oxidizing components in the surrounding gas, and that
is why the growth takes place in inert gas ambient, and
at reduced pressure. The growth chamber must there­
fore be highly vacuum proof, and it must be properly
evacuated and purged before the temperature may be
raised. Oftentimes a leak test is performed at this stage:
The purge gas flow is shut down, the chamber is evacu­
ated further, vacuum valves are closed, and the pressure
in the chamber is monitored. The process is allowed to
continue only if the leak rate is under a predetermined
level. This is done to ensure that there are no leaks in
the system that could introduce air, and thus contami­
nation, into the melt and the surroundings during the
long process hours. Another policy is to perform a leak
test after the growth. This kind of test may use tighter
acceptance values, as there are no fresh materials that
could outgas in the chamber. Therefore, this kind of leak
test better ensures the overall vacuum compatibility of
the system; and furthermore, the overall cycle time is
somewhat shortened. As there is seldom the need to
open more than a couple of vacuum seals to remove the
grown crystal, clean the furnace, and charge it again,
this approach is quite valid, as those seals are carefully
cleaned before the furnace is closed for a new run.
2.2.1 Melting
The next step, melting, takes a few hours, during which
the temperature inside of the HZ is first brought to
close to 1500°C, and then maintained there to bring
enough heat to fully melt the batch. The temperature
margin is not very wide, as the silica crucible is already
quite soft at those temperatures, and excessive heat
is avoided in order to prevent the crucible walls from
sagging. Furthermore, the hottest area of the crucible,
typically the low corner area, will start to wear as soon
as it is in contact with the melt. Excessive heat would
enhance the wear and shorten the useful time available
23
PA R T I
Silicon as MEMS Material
before the material is so worn that difficulties are cre­
ated in maintaining the dislocation-free (DF) structure
of the crystal, later in the process.
After the whole batch is molten the crucible is lifted
to the desired starting position, which is typically higher
up than during the meltdown. The temperature is then
stabilized to close to the preferred temperature, based
on experience about previous growths, and the seed
crystal is ready to be dipped. The stabilization of the
temperature is customarily controlled by a two-color
pyrometer that senses the surface temperature close to
where the seed will be dipped.
2.2.2 Neck
At the right temperature, the end of the seed will melt
away and a meniscus (see Section 2.3.1) will form. As
the seed is slowly pulled upwards, new material will be
crystallized in the end of the seed, obeying the original
crystal structure. The seed is usually not DF at this point,
as the temperature shock caused by the contact to the
melt tends to create dislocations even if the original seed
was free of them. That is why a necking step normally
follows (see Figure 2.3), and the same seed may be used
over and over again without excessive concerns about
whether the DF structure is maintained or not.
The basic idea in the necking step, originally intro­
duced by Dash in the late 1950s [8], is that disloca­
tions have limited mobility in silicon, and if the crystal
is grown rapidly and thin enough, the dislocations will
grow out from the sides of the neck and eventually be
frozen and excluded from the material. There are a few
requirements for this to happen. The dislocations in sili­
con have a preferred axis in a 110 direction. Should
one try to grow a neck of uniform thickness to this crys­
tal orientation, some of the dislocations would have no
difficulty in staying within the neck; they would simply
Fig 2.3 ● Neck, crown, and beginning of the body of a crystal.
Around the crystal a bright ring, or meniscus, is visible. It is used
to control the diameter of the crystal.
24
grow in length together with the neck. The more the
growth axis deviates from the nearest 110 direc­
tion, the easier it will be to get rid of dislocations.
That is why other common crystal orientations, (100)
and (111), are relatively easy to grow DF, but growth
of DF (110) material is much more challenging. The
other requirements are that thermal stresses are low,
pull speed is high, and to sum up, that the rate of climb
of dislocations in the direction of the neck axis remains
smaller than the pull rate. A thin neck combined with
low thermal gradient reduces stress.
The climb, which is essentially silicon interstitials (or
vacancies) attaching to the edge of the additional atomic
plane, which edge forms the dislocation line proper, is a
much slower process than slip. Slip often occurs when
silicon wafers are processed, or in the crystal if the
DF structure is lost, and also in the end of the tailing
step (see Section 2.2.5) as the crystal is detached from
the melt. High pull speed also favors silicon vacancies,
which slows down the climb towards the melt interface.
Pull speed of the order of 3 mm/min is usually ade­
quate, the thickness seldom much exceeds 4 mm, and a
few cm’s in the proper speed/diameter range suffices.
The crystals used for today’s bulk MEMS applications
are still lightweight enough that a regular Dash neck
is applicable to orientations other than (110). However,
crystals used for IC applications may be so heavy that
a standard neck would no longer be able to carry the
weight of the crystal. Several approaches have been
used to address this issue, such as enabling the use of a
thicker neck, constructing an additional means to sup­
port the weight, or developing ways to grow DF crystals
without any necking procedure at all. However, these
approaches are beyond the scope of this book.
There exists some confusion about the density of
dislocations in CZ silicon crystals. Because of histori­
cal reasons, specifications often allow nonzero disloca­
tion density, for example, less than 100 count/cm2;
however, today it is much easier to grow large crystals
that contain zero dislocations than it is to grow crystals
that contain a small but nonzero number of them. The
neck is an effective means of eliminating all linear dis­
locations from the material, and it is more difficult to
create the first dislocation into DF material than for an
existing one to multiply to a large number.
Oftentimes, the neck is grown longer than would
actually be required for DF structure. This adds a cer­
tain safeguard to the quality of material in the end of
the neck, but the primary reason for doing this is related
to the often slow thermal response of the system: It is
desirable that the melt temperature in the beginning of
the next step, the crown, is correct to about 1°C. The
thin neck acts as a very reproducible temperature sen­
sor, better than the pyrometers used in the instrumen­
tation. As soon as the neck diameter and average growth
Czochralski Growth of Silicon Crystals
rate have reached the desired window for a sufficient
time, the temperature is also correct.
2.2.3 Crown
When the proper length of the neck as well as the right
temperature have been reached, the crown is started.
Pull speed and temperature are lowered, crystal and
crucible rotation speeds may be changed, and melt level
may also be adjusted gradually. The purpose is to create
suitable conditions in which the crystal acquires diam­
eter at a proper pace: Too slow results in an unnecessar­
ily long process time as well as increased probability of
structure loss, as the melt is also warmer and therefore
less stable than is optimal; on the other hand, too large
a growth rate results in structure loss, as the too-cool
melt causes an uncontrollable growth rate in some crys­
tal orientations.
The larger the diameter of the crown, the cooler
must the melt also be, and that is why there is a con­
tinual decrease in the heater power/temperature. The
typical temperature difference between the end of the
necking step and the beginning of the full diameter
body is several tens of degrees Centigrade, and most of
that is needed during the crown.
On the melt surface, diameter increase may be
observed (see Figure 2.3), but there are also things tak­
ing place under the surface, which we cannot see. The
freezing interface usually becomes increasingly con­
vex towards the melt, and that shape has a significant
impact on the chances of success of the crown and sub­
sequent steps. A very slow pull speed in crown results
in a flat crown shape that is economical when it comes
to the usage of original silicon material in the charge.
However, the freezing interface then tends to be highly
convex, and as it tends to be fairly straight or even con­
cave in the body, the shape of the freezing interface
needs to experience a very significant change towards
the end of the crown and the beginning of the body.
The actual speeds of crystallization near the center axis
of the crystal and near the edge will then be very dif­
ferent, and the loss of structure will be more probable
than if those speeds are close to each other. Especially
in the case of material doped heavily with antimony or
other volatile n-type dopants (which is, in general, more
difficult to grow than lightly doped or heavily borondoped material), this change of interface shape may
easily be fatal for the crystal. Why this should be so is,
however, beyond the scope of this book. On the other
hand, if the diameter growth rate is kept small and
the pull speed relatively high, the crown shape will be
more conical and the freezing interface will experience
a smaller change towards the body. This will make it
easier to make the transition to the body, but at the cost
CHAPTER 2
of more time spent and poorer silicon material usage.
That is why a suitable tradeoff is chosen, with a high
probability of success for the crown and early phases of
the body, but with as little time and material spent as
feasible.
2.2.4 Body
The cylindrical part of the crystal, out of which the
actual wafers will be fabricated, is called the body.
Between this section and the crown there is a transitory
period that is sometimes called transition and some­
times shoulder. The shoulder is started a little before
the desired diameter for the body is reached, and the
pull speed is raised significantly. This cuts the growth in
the diameter over a relatively short distance, and ideally
the growth turns vertical at the same diameter as is cho­
sen for the body. At that point, the pull speed is low­
ered again, to match that of the early body. If the pull
speed of the transition is maintained high for too long,
the diameter of the crystal will start to diminish again.
After completion of the shoulder, the body is started.
At this point, some further temperature drop is usually
needed, but after a while, the temperature changes will
be slow. Diameter is controlled through instantaneous
pull speed, most often by using a PID (proportional­
integrating-derivative) control loop that needs to be
tuned properly, and average pull speed is maintained by
adjusting the heater power, or temperature. If there is a
bottom heater or other additional heaters, their power
may be changed in a predetermined manner; or there
may be instrumentation to measure the temperature,
and a predetermined profile may be followed. Gas flow,
pressure, as well as crucible and crystal rotation rates
are among the controllable parameters along the body
length, and there may be more, such as strength and
shape of a magnetic field, melt level, etc.
2.2.5 Tail
In the end of the body, a significant portion of the melt
is still remaining, typically at least 10% of the original
charge, though in some applications this portion may be
smaller. A part of this remaining melt is used to form
a so-called tail. This section of the crystal is needed
for two purposes: First, there will be thermal shock
that will almost inevitably introduce slip dislocations
as the crystal is detached from the melt. This slip will
proceed a shorter distance upwards than if the growth
would have been disrupted at full diameter. In addition,
a smaller volume of melt is consumed to produce a tail
than to produce a corresponding length of full diameter.
Altogether, a longer DF body can be produced from the
same amount of melt. Secondly, there may be a desire
25
PA R T I
Silicon as MEMS Material
to achieve a more uniform thermal history to the end
of the body, more comparable to the other parts of the
body. Should the crystal be detached at full diameter,
the end portion would cool down much more rapidly
than if a long tail is grown.
2.2.6 Shut-Off
After the tail is complete, power to the heater(s) may
be shut off and the crystal pulled into the receiving
chamber to cool down. However, the lower end of the
crystal may be left to stay for a while inside the HZ,
while the power is ramped down slowly, according to a
suitable profile followed in order to produce a desired
thermal history of the crystal, especially to the last few
tens of cms of the body.
After the crystal has cooled down sufficiently, it is
removed from the receiving chamber. This normally
happens before the HZ is cold enough that it may be
opened for cleaning and recharging, and for a new crys­
tal to be grown. Cooling of the HZ may be enhanced to
save process time, for example, by moving parts inside
of the chamber to allow for a more effective escape of
heat; by purging the system with a suitable high-volume
gas flow; or by adding, for instance, helium into the
chamber. The cleaning involves removal of the used
crucible and the frozen residual melt (also called pot
scrap), vacuuming any silicon-monoxide-containing dust
from the surfaces, potential replacement of worn parts,
and checking of overall condition of the HZ parts.
2.3 Issues of Crystal Growth
In the following sections, diameter control, doping, and
HZ lifetime are discussed.
2.3.1 Diameter Control
There is a clear-cut balance between the growth rate
of the crystal and thermal gradients on both sides of
the freezing interface. The growing crystal needs to be
cooled, mainly through radiation, and to some extent
also by the purge gas flow. Near the freezing interface,
the heat flux density can be taken to be equal to the
magnitude of thermal gradient times thermal conductiv­
ity, on both sides of the interface. However, the solidifi­
cation process releases heat at a rate that is equal to the
speed of crystallization times latent heat. In a balanced
situation, the external pull speed of the crystal is equal
to the rate of solidification, and the thermal flux density
on the crystal side is larger than that on the melt side by
the amount released in the crystallization process. The
crystal then tends to grow, maintaining its diameter, at
26
least averaged over time. The time-dependent processes
in the melt make temperature gradients at the melt side
vary over time, which creates striations to the crystal
(see Figure 2.5), but as long as the balance is maintained
averaged over time, no major difficulties should occur in
the diameter control.
The crystal diameter is almost always measured opti­
cally. The melting point of silicon is high enough to give
ample intensity for optical measurements, and in prac­
tice, most of the available light and infrared radiation
are filtered out. A traditional way was to observe the
bright ring, known as the meniscus, around the crystal
with a pyrometer that was focused on a small spot in
such a manner that an increase in diameter resulted in
a larger signal, as the more radiant meniscus and the
lower end of the crystal were taking a larger portion
of the spot. More modern measurements rely on video
feed that is processed to give either the chord length,
obtained by measuring the locations of two points at
the meniscus, or several point locations that are iden­
tified and a best-fit calculation performed to get the
diameter of the meniscus. The luminousness of the
meniscus (Figure 2.3) is caused by the reflection of light
from the melt surface at locations where the surface is
curved upwards in such a way that the hotter crucible
wall is reflected to the eye of an observer. The bound­
ary between solid and molten material is very difficult
to distinguish. The diameter is then measured at some
suitable location in that meniscus, a few mms outside of
the crystal edge.
The physical properties of elemental silicon define
what is known as wetting angle, whose magnitude is 11°:
This is the angle between the edge of the growing (verti­
cal) silicon crystal and the melt, very close to the triple
point (edge of the crystal at the solid–melt interface).
As the crystal edge is vertical, the melt also turns almost
vertically upwards to meet the solid, since the melt has
quite a large affinity to the solid. The edge of the freez­
ing interface is located as much as about 7 mm above
the melt level, as measured a couple of cms outside the
crystal. The balance between the surface tension of the
melt and gravity dictates the shape of the interface near
the crystal, that is, the shape of the meniscus.
Should there be a need to adjust the diameter, the
most commonly used approach is to change the exter­
nal pull speed. For instance, if the diameter is too large,
an increase in the pull speed will begin to change the
diameter within a few tens of seconds to a few minutes.
However, the increased pull speed does not immedi­
ately change the speed of crystallization, as it is dictated
by thermal balance. In order for the crystal-melt system
to adapt to the new situation, three alternatives are pos­
sible: (1) Heat transfer at the crystal side of the inter­
face could be enhanced. However, if no changes take
place there, this does not happen by itself. (2) Heat
Czochralski Growth of Silicon Crystals
transfer at the melt side could be lowered, but again, no
intentional changes are made there. (3) The production
of latent heat may be brought back to the original value.
As the heat produced at the interface equals the speed
of solidification times latent heat times the surface
area of the freezing interface, the increased pull speed
results in decreased diameter.
Should the average pull speed, after proper control of
the diameter has been established, be off from the tar­
get, slower means of control are used. The target speed
is typically in the 1 mm/min range, depending on the
crystal diameter (larger crystals grow more slowly), HZ
design (cooler environment experienced by the crys­
tal allows larger growth rate), and quality issues. Some
crystals are grown slowly to establish a suitable balance
between growth rate and thermal gradients, which bal­
ance has an impact on very small vacancy-related defects,
known as COPs, in dense IC circuits [12]. A crystal
grows more rapidly from a cool melt, and this is again
caused by the requirement of thermal balance: Colder
melt delivers less heat to the freezing interface, and more
heat may then be produced by the crystallization process.
Change of the melt temperature has therefore an impact
to the average growth rate, the average taken over sev­
eral tens of minutes. There is a pyrometer watching the
heater temperature(s), and a change in that temperature
also changes the melt temperature after a significant
delay. Another possibility is to change the heater power.
There are a couple of other possibilities that have a
speedier influence on the thermal balance, to control
either diameter or the average pull speed, but these
approaches are more seldom used. Thermal radiation
at the crystal side may be changed by adding a heater,
halogen, or IR lamps [13]; by other means of introduc­
ing energy to the crystal; or by changing its thermal
environment in a more passive way. At the melt side,
transport of heat from crucible wall towards the freez­
ing interface may be changed, for instance, through
small changes in crucible rotation rate or magnetic field.
These measures are faster than control through heater
power or temperature, but also more complicated, as
these other possible control parameters must also be
kept close to their desired average values.
2.3.2 Doping
Most material used for MEMS applications is lightly
doped with boron or phosphorus, up to a few tens of
Ωcm. This corresponds to 1015–1016 dopant atoms/cm3,
which translates to only mgs of elemental dopant to
a charge of tens of kgs or more. A small quantity like
this is very difficult to allot in a consistent manner, and
therefore the dopant is usually introduced as-diluted to
a larger amount of silicon. A suitable amount of dopant
CHAPTER 2
element may be melted together with silicon to make an
alloy in which the dopant concentration is in the 0.01–
0.1% range. If this alloy is prepared carefully so that
the concentration is uniform, a very convenient amount
of alloy may be mixed with the silicon charge to result
in a reproducible concentration in the melt. There is a
further advantage in using silicon alloy to introduce the
dopant: Very little of the dopant will be able to vaporize
during the melting of the charge.
In mass production of silicon crystals, this alloy is
usually prepared in a very simple manner: A very heav­
ily doped single crystal is grown, its resistivity profile is
measured, and wafers cut from this crystal are used to
introduce dopant into hundreds of lightly doped crystals.
Low resistivity crystals are usually doped using ele­
mental dopants. Boron is essentially nonvolatile, and it
may be introduced into the charge at the same time as
the silicon chunks are laid into the crucible. However,
the common n-type dopants antimony, arsenic, and
phosphorus are highly volatile, and they are prefer­
ably put in only after the charge is molten. Antimony
is relatively simple to pour into the melt, as it is readily
available in granular form; that is, it flows easily from
and through various cups and channels, and its density
is high enough to take it into the bottom of the melt,
with little evaporation or splashing. Arsenic and phos­
phorus, on the other hand, tend to volatilize at or above
the melt, and a significant portion may be lost into the
purge gas flow. This adds costs, as more dopant will be
needed; there will be more dirt in the system, adding
to chances of particles and yield losses; and the repro­
ducibility of the amount of the dopant in the melt will
be poorer. Furthermore, there will be added hazards to
the cleaning of the equipment because of the additional
burden posed by the superfluous dopant in the vacuum
lines and on other cool surfaces. Various approaches
have been developed to introduce these dopants into
the melt in a more efficient and cleaner manner.
The volatile n-type dopants normally reduce oxy­
gen concentration in the grown crystals, as oxygen in
the melt is depleted more efficiently near the gas–melt
interface. Volatile oxides of the dopant are carried away
by the purge gas just as oxygen is carried as silicon mon­
oxide, adding to loss of oxygen. The faster evaporation
rate of oxygen tends to increase the wear rate of the
crucible, and extra care must be taken not to exceed
the useful lifetime of the crucible. These dopants have
also some effect on surface tension and therefore to the
melt flows near the melt surface (see Section 2.6.4).
2.3.3 HZ Lifetime
HZ materials have only a limited lifetime, partly
because of high temperatures and partly because of the
27
PA R T I
Silicon as MEMS Material
Fig 2.4 ● Worn heater after tens or a few hundreds of crystal
growth cycles. Silicon monoxide evaporating from the silicon melt
reacts with carbon in the heater, attacking the hottest parts first.
corrosive action of silicon monoxide. The heater and
the susceptor are those parts that typically suffer most
rapidly.
The heater is sensitized because it runs at a higher
temperature than other parts of the HZ, and that is why
the reactions with monoxide have the largest impact on
it. Furthermore, its picket structure allows gas to attack
it from several directions simultaneously, whereas, for
example, the cylindrical heat shield made of graphite
(sometimes called the heat-shield liner if the insulat­
ing part is called the heat shield) is attacked only from
the inside. The resistivity distribution of the heater is
also of major importance. The erosion is normally not
uniform, and the power distribution of the heater then
changes with its age (Figure 2.4), causing quality and
yield problems. In a traditional HZ design, the purge
gas, which contains also the corrosive silicon monoxide,
is sucked down around the crucible and through and
around the heater. Further downstream, the reactivity
of the gas has already been reduced. The lifetime of a
heater may be as short as just twenty crystals, but with
more sophisticated designs, it may be hundreds of crys­
tals or more.
The susceptor is also enclosed in the hottest part of
the furnace. Even though its temperature is not quite as
hot as that of the heater, the susceptor is mechanically
more strained. The main stress is experienced during
cooling at the end of the cycle, as the susceptor mate­
rial starts shrinking when the temperature goes down.
However, the coefficient of the thermal expansion of
the silica crucible is extremely small, only about onetenth of that of the susceptor material. During the time
the temperature was close to the silicon melting point,
the crucible was soft enough to have accommodated
28
the shape of the susceptor. During the early part of the
cooling, the crucible hardened again, but the susceptor
tended to shrink a further couple of mms. This cycle
exposes the susceptor to tremendous stress. In order to
alleviate the problem, the susceptor is normally cut to
several (usually, three) sections. The cuts allow separate
sections to move independently. However, in addition
to reduced mechanical strength, there is also a further
price to pay for this.
The intimate contact between the silica crucible and
the graphite susceptor, together with the high tempera­
ture, makes graphite and silica react to form carbon and
silicon monoxides, which are both volatile. This reac­
tion wears the material in locations where there are easy
escape paths for the gases and the temperature is the
highest. Typically, the wear is the fastest in the vicin­
ity of the cuts performed to allow susceptor sections to
move relative to each other. Furthermore, the result­
ant production of carbon monoxide creates a significant
risk of carbon contamination, as the source is close to
the melt.
2.4 Improved Thermal and Gas
Flow Designs
The CZ process has to be designed in such a way that
energy consumption is minimized, HZ lifetime is maxi­
mized, and the crystal quality is good and repeatable.
Modeling methods are indispensable in achieving these
goals.
Modern HZs utilize such structures above the melt
that cut direct visibility between the hot crucible wall
and the growing crystal, except for the first few cms
of the crystal above the melt [18]. This allows for bet­
ter control of the temperature distribution in the crys­
tal. Temperature gradients over the freezing interface
experience smaller variations. Furthermore, growth
rate in the body can be made essentially independent
of the location in the crystal, contrary to traditional
HZs, where achievable growth rates decline towards
the end of the body, as the hot crucible rises gradu­
ally. All this gives a better and more reproducible qual­
ity. Furthermore, the freezing interface can be made
straighter, and thermal stresses in the growing body are
smaller, resulting in better growth yields.
At the same time, there is a significant reduction in
power consumption as the earlier intense heat loss from
the surface of the melt and the upper parts of the HZ
is reduced. The improved thermal insulation results in
enhanced lifetimes of the HZ parts, as maximum tem­
peratures inside the HZ are lowered and the wear of
different parts becomes slower and more uniform. The
stability of the whole process is further enhanced by the
Czochralski Growth of Silicon Crystals
fact that improved insulation results in a situation where
the temperature distribution becomes less dependent
on where in the heater the heat is actually produced.
In addition to thermal design, any structure above
the melt must also be optimized for gas flows. The three
main goals for better gas flow configuration, in addi­
tion to contributing to control of oxygen in the growing
crystal, are to reduce the risk of particle formation in
such locations, from where a particle may end up in the
melt; to protect the melt from gaseous contamination;
and to protect the most critical HZ parts from the cor­
rosive action of the purge gas, after the gas has passed
the melt surface.
Aforementioned structures that help optimize the
temperature distribution around the crystal may also
serve to create more laminar gas-flow patterns near the
crystal and melt surfaces. However, as it is advantageous
to go fairly close to the melt with such structures that
help modify temperature distribution, a rule of thumb
being that one should go to about one-quarter diame­
ter of the growing crystal from the melt or even signifi­
cantly closer, this may be somewhat too close to allow
proper gas-flow control near the melt surface. Various
schemes have been envisioned to give more independ­
ence between gas flows near the melt surface and ther­
mal design in the same area.
After the gas has passed by the melt surface and
exited the crucible, it will unavoidably hit some hot
surfaces and react there (unless some very expensive
materials are being used). The resulting carbon monox­
ide will not get back into the melt if the gas flow is kept
laminar after leaving the crucible. However, in order to
extend the lifetimes of the heater, the susceptor, and
other expensive hot-zone parts, it is preferable that the
contact of the gas with these part be kept to a mini­
mum. Various approaches are available, which, however,
all add to the complexity of the hot-zone design.
2.5 Heat Transfer
There are three significant modes of heat transfer that
operate during silicon crystal growth: conduction, con­
vection, and radiation.
Radiation is of major significance between sur­
faces that are separated from each other by a physical
gap, but between which there is direct visibility. Most
materials that are being utilized absorb heat so effi­
ciently that heat transferred by reflected radiation is
less significant; but, especially over the melt, it cannot
be neglected. The importance of thermal radiation is
enhanced by its strong dependence on temperature: the
Stefan–Boltzmann law tells us that the radiant power
density is proportional to the fourth power of the tem­
perature. That is why, especially over longer distances,
CHAPTER 2
where the role of conduction is reduced, radiation plays
an important and often dominant role.
Conduction is the normal mode of heat transfer
through a material, solid or fluid. Structural graphite
materials are excellent conductors of heat at high tem­
peratures, much better than, say, stainless steels. On
the other hand, insulators are designed in such a man­
ner that conduction is made difficult. For example,
the graphite fibers conduct only along the fibers, and
as there is limited contact between fibers, it is difficult
for the heat to be conducted through the thickness of
an insulating layer. At the same time, the fibrous struc­
ture cuts the radiation repeatedly over a short distance,
making radiation a much less effective means of heat
transfer than transfer over free space. Furthermore,
insulating material makes it difficult for the inert gas to
flow through, cutting or seriously impeding convective
heat transfer, too.
A silica crucible has quite low thermal conductivity,
but it also transfers heat through radiation. The cruci­
ble is manufactured in a process in which high-purity
quartz sand is fused, using, say, an electric arc, into a
dense, solid material. However, the outer edge of the
crucible contains a large density of small bubbles, which
makes radiation less effective. The inside, on the other
hand, is fused to be essentially bubble free (why this is
made will be explained in Section 2.8), and radiation
may pass freely. Sometimes, the bubble structure of the
crucible has a significant impact on its temperature dis­
tribution, as the wall may act almost as an optical guide
for thermal radiation.
In the melt, heat is transferred by conduction and
convection. The melt is metallic in nature, its thermal
conductivity is at par with graphite, and the conduc­
tion must be considered as a substantial contributor to
overall heat transfer. However, a simple analysis tends
to show that convection should play the dominant role.
This will be discussed a little later.
The crystal also has these two components to the
heat transfer, which must be included in analysis. This
may sound slightly surprising, since the growth rate of
the crystal is small, in 1 mm/min range only. The melt
flows, driven by buoyant forces, have 2 to 3 orders of
magnitude greater speeds than the typical pull rate.
The purge gas flow has two components to the heat
transfer, neither of which is usually very large; however,
they cannot be ignored, especially where the impact
is most significant. Even though the furnace pressure is
low in the silicon CZ process and argon is a poor ther­
mal conductor, the presence of the gas has nevertheless a
significant negative impact on the insulating properties of
the used fibrous materials. Another mode of heat loss by
the gas flow is created by the need to heat up the incom­
ing gas itself. Typically, the gas flow is in tens of slpm,
and during the passage through the HZ, the temperature
29
PA R T I
Silicon as MEMS Material
rises by well more than 1000°C. In most cases, a few, but
no more than about 5, additional kW escape from the
HZ because of the conduction, convection, and heating
up of the purge gas, which is relatively little compared
with the power of 40 to well beyond 100 kW that the
HZs consume. However, the action of the cool incoming
purge gas may be quite local on the crystal as well as in
the areas close to the melt surface, and then this effect
may not be ignored, even if the magnitude of this addi­
tional, but local, heat loss is only in 1 kW range. The total
upward directed heat transfer rates in, say, 150–200 mm
crystals seldom exceed 2–3 kW in today’s HZs, though
this number may be increased to a very significantly
larger value.
2.6 Melt Convection
The largest CZ crystals grown today weigh several hun­
dreds of kgs, and the size of the crucible corresponds to
that of a small bathtub. The freezing interface is located
at the top surface of the melt, and that is why the surface
areas are colder than those deep in the melt. As the melt
expands with the temperature, warmer melt close to the
bottom is less dense, and it tends to rise up towards the
surface. The viscosity of molten silicon is somewhat less
than that of water; that is, there is very little that the vis­
cosity does to slow down melt movements. That, com­
bined with the large volume of the melt, makes it very
difficult to control the melt behavior properly. The crys­
tal sizes grown for MEMS applications are, fortunately,
slightly smaller (the present charge sizes seldom exceed
100 kg), but even so, it is a major challenge to create such
growth conditions that the instability of the melt does
not cause serious impediments to the yield of the growth
or to the quality of the growing crystal.
The two major approaches to stabilizing the melt, in
addition to creating a favorable temperature distribution,
Growth axis
30
are crucible rotation and magnetic fields. The use of
magnetic fields is very common for large melts and
crystals, where crucible rotation tends to be insuf­
ficient to bring in adequate stabilization. For smaller
melts, such as those used for MEMS crystals, magnetic
fields are useful in extending crystal properties beyond
what is straightforward to achieve without them, for
example, in broadening the available range of oxygen
concentration.
2.6.1 Free Convection
CZ-grown silicon material shows oxygen and resistivity
striations (Figure 2.5) because the melt is heated from
below and from the sides, and this kind of temperature
distribution is seldom stable. The hotter, less dense
melt tends to move upwards, bringing heat with it; and
at other locations in the melt the cooler and denser
melt goes down.
There are two dimensionless numbers that are com­
monly used to characterize the behavior of a volume of
fluid as it comes to free, or natural, convection. The
first one is the so-called Grashof number (Gr) that tells
the ratio between buoyant forces and viscous forces. The
buoyancy of the hotter melt closer to the bottom of the
crucible is greater for deeper melt, larger temperature
differences, and higher value for thermal expansion.
Evidently, we do not consider the magnitude of gravity
here (in microgravity, it would be much easier to achieve
striation-free crystals). The viscous forces are directly
related to the viscosity of the melt, which is, as men­
tioned earlier, quite low. As the Gr surpasses about 107,
the flow ceases to be laminar and becomes turbulent. For
large silicon melts, Gr is typically around 1010, that is,
well above this turbulence limit [14]. However, the value
is still so low that the turbulence is not very strong, and
the turbulent vortices created by natural convection are
relatively large, the smallest ones being in the 1 mm range.
Sample cut
Fig 2.5 ● LPS (Lateral Photovoltage
Scanning) [20] map of a lightly doped
150 mm N100 crystal. The sample
has been cut out of a 50 mm thick
section of the crystal, as shown
on right, and then etched. The
freezing interface shape may be
readily extracted from the map, and
information about the amplitude
spectrum of axial resistivity striations
may also be obtained.
Czochralski Growth of Silicon Crystals
The second dimensionless number is known as
the Rayleigh number (Ra), and it describes the ratio
between the convection of heat to the conduction of
heat. This number may be easily calculated from Gr, as
it is the Gr multiplied by the ratio of kinematic viscos­
ity to thermal diffusivity. As the melt has low viscosity,
but high thermal conductivity, this ratio is small, on the
order of 0.01. However, as Gr is so large, Ra is also quite
large, and based on its value, the convective transport of
heat should clearly dominate over conduction.
Free convection tends to form distinctly separate
areas in the melt, both where hot melt goes up and in
other areas where cooler melt goes down. The locations,
sizes, and shapes of these areas change continuously;
some of these vortices disappear and new ones are
formed; and an accurate prediction of the melt flows is
extremely difficult, as is often the case with turbulent
flows. The growing crystal feels these volumes of differ­
ent temperatures, and over cold spots the growth rate is
greater than over hot spots, where the crystal may actu­
ally be even melting for a short period. The variations
in growth rate have also an impact on the momentary
dopant concentration that will be embedded into the
growing crystal. These will then be visible as resistivity
striations (Figure 2.5). As the crystal is rotated during
growth, there is typically some component to the stri­
ations that is related to the rotation rate. In addition,
there are longer-term variations that are related to the
time that it takes a new larger hot spot to arrive under
the crystal, after the previous one has gone. The tem­
perature disturbances may also result in the loss of the
single crystalline structure; unstable melt behavior typi­
cally results in poorer yields.
In addition to resistivity striations, oxygen striations
may be found in a crystal after growth. They have some
correlation to resistivity striations, as oxygen originates
from the crucible wall and so does heat. However, oxy­
gen has much lower diffusivity in the melt than heat.
Oxygen variations in the melt tend to be more sharply
defined; and especially for fine vortices, the correlation
between temperature and oxygen may be poor. That is
why the time-dependent variations in oxygen concen­
tration in the crystal do not follow too closely the resis­
tivity striations.
It was mentioned earlier that conduction significantly
contributes to heat transfer in the melt, too, even
though the Ra would suggest otherwise. The main rea­
son for this discrepancy is forced convection by crucible
and crystal rotations and the optional use of magnetic
fields, or other potential means of stabilizing the melt
against uncontrolled natural convection. If free convec­
tion is not the dominant convection mechanism, the
inferences derived from these dimensionless numbers
(Gr, Ra) may be grossly misleading.
CHAPTER 2
2.6.2 Crucible Rotation
In a typical CZ growth process, the melt as a whole
rotates approximately with the crucible. Because of
low viscosity, it may take a long time for the melt to
adjust its rotation rate to that of the crucible, but this
time is short anyway compared with the total proc­
ess time. Under the crystal, which is normally rotated
in the opposite direction, the rotation rate of the melt
is slower, just because the crystal opposes the rotation
with the crucible. There are, however, exceptions to
this general rule; for instance, magnetic forces may be
used to make the melt rotate more slowly or faster than
the crucible, or the crucible may be rotated in such a
manner that its rotation rate changes quite quickly over
time. The best known case in which the melt rotates at
a rate that is clearly different from that of the crucible
is if one uses a transverse magnetic field. A static trans­
verse field exerts a strong decelerating force to a rotat­
ing body of electrically conducting fluid, and the melt
will be almost nonrotational, independent of the cruci­
ble rotation rate. However, this case will be discussed in
a little more detail in Section 2.7.1, and other cases will
not be touched here at all.
Let us assume that the hottest spot in the melt is
somewhere near the crucible radius, that is, far from
the centerline. This is most often reality, too. The melt
there would like to start going upwards, and it is push­
ing the melt on top sideways, towards the cooler crys­
tal. The coldest spot is just under the crystal, where
the temperature is very close to the melting point. That
melt would like to go down, kind of completing the
circle with the upward directed flow near the crucible
edge. However, the situation is far more complex.
First of all, the viscosity is too low to prevent the
upward-going flow from turning down just a couple of
cms inwards from the crucible wall. And correspond­
ingly, the downward-going flow somewhere under the
crystal would take up a much smaller area than that of
the whole (large) crystal, and there would be upwardoriented channels of flow under and close to the crystal,
too. This would be the effect of free convection and a
large Gr.
Secondly, the fairly large velocity component along
the circumference of the crucible, the azimuthal velo­
city, would pose a serious challenge for any fluid volume
that would try to make its way too close to the crystal.
The fluid would tend to keep its linear velocity when
moving radially inwards. However, as the distance from
the crucible centerline becomes smaller, the angu­
lar velocity would increase correspondingly. The same
behavior may be seen in the case of tornadoes and hurri­
canes, where the wind approaching the eye of the storm
rotates ever more rapidly. This phenomenon has a major
31
PA R T I
Silicon as MEMS Material
impact on the centrifugal force that this fluid volume
experiences, whereas the rest of the melt that is rotat­
ing approximately with the crucible is unaffected. The
higher the crucible rotation is, the shorter the distance
will be that the fluid volume is able to make towards
the center, before the increase in rotation rate will stop
it from going any further.
An idea of the magnitude of the phenomenon may
be gained if we consider a simple numerical example.
Let us assume that the crucible rotates at 10 rpm, and
we observe a volume of fluid that is at 200 mm radius.
Should this fluid try to move inwards, say, to a radius
of 180 mm, its rotation rate would tend to go up to
11 rpm. This volume of fluid that rotates at 11 rpm
would experience about 100 N/m3 larger centrifugal
force than fluid rotating at the original 10 rpm. This
so-called body force may not sound very large (gravity
makes melt experience a force of about 25000 N/m3),
but in practice this difference in centrifugal force is
very significant. Gravity itself does not cause free con­
vection, but differences in fluid density do, together
with gravity. As a comparison, a vertical column of melt
that is 5 K hotter than the surrounding melt, a signifi­
cant temperature difference, would experience buoyant
force that is 20 N/m3, that is, a considerably lesser force
than that caused by relatively short radial travel.
That is why, for relatively high crucible rotation rates,
the melt flow patterns tend to form vortices that are
elongated in the vertical direction, and more so if the
rotation rate is increased (Figure 2.6). On the other hand,
narrow vortices may more easily exchange heat between
the warm, upward-directed regions of flow and those
colder regions that are going down. This exchange of heat
reduces temperature differences between neighboring
parts of vortices, and it also reduces the role of convec­
tion in the heat transfer. In principle, it would be possible
to rotate the crucible so rapidly that the rotation alone
would result in such small structures that the conductive
heat transfer would effectively eliminate temperature
differences between upward- and downward-directed
portions of the vortices. At the same time, this balanc­
ing of temperatures would eliminate the driving force
0
32
0.01
0.02
for free convection, and free convection would no longer
play a role in heat transfer. However, several tens of rev­
olutions per minute would be required, and in practice
this would be very challenging to realize. Use of a suitable
magnetic field to support the stabilizing effect of melt
rotation would seem to make this approach to stabilizing
melt behavior somewhat more realizable [15].
2.6.3 Crystal Rotation
The most evident reason for the rotation of the grow­
ing crystal is to keep its shape essentially round. The
semiconductor industry is geared to using round wafers,
and there is an abundance of good reasons for the prac­
tice of using that shape, which the wafer manufacturers
must then also follow. However, the crystal rotation has
also a significant impact on melt flows under the crystal.
The classical approximation for the flow under the
crystal is that of a rotating disc over stagnant fluid. This
case has been widely studied, and it is one of the few
situations where a three-dimensional fluid flow may be
solved analytically [16]. The resulting flow pattern con­
tains an upward-directed component that is independ­
ent of the distance from the centerline of the crystal.
There is also a radially outward-directed component
that is zero at the freezing interface and very far from it,
and it has a maximum value quite close to the interface.
In a thin layer, of the order of less than 1 mm thick, the
flow is directed radially outwards in a spiral pattern. If
the crystal rotation rate is increased, the thickness is
reduced proportionally to the square root of the rota­
tion rate, but at the same time, the velocity of the flow
is increased linearly. This adds up to an increase in the
mass flow that is directed outwards, which is also pro­
portional to the square root of the rotation rate.
The driving force for this outward-bound flow is the
rotational movement that the crystal causes. The melt
under the crystal experiences centrifugal force that is
strongest at the interface. However, the melt closest to
the interface cannot effectively move outward, as the
solid surface located just above slows down that portion
of the melt. The same viscous forces that make the melt
0.03
0.04
0.05
Fig 2.6 ● Momentary but representative
velocity profiles for various crucible
rotation rates; left at 5 rpm and right at
15 rpm [19]. The results are calculated
from two-dimensional simulations; full
three-dimensional results would be
more complicated. The perpendicular
velocity component to the direction of
rotation is shown, only. The velocity
scale is in meters per second.
Czochralski Growth of Silicon Crystals
rotate in the first place prevent it from moving relative
to the crystal. Far from the interface, the rotation rate
is essentially zero and, therefore, so are the centrifugal
force and radial velocity. The viscosity of the silicon
melt is so low that only a thin layer under the crystal
actually rotates with the crystal, and it is in this layer
where the maximum radial velocity can be found.
The outward-directed flow is quite important in dis­
tributing dopants and oxygen more uniformly into the
crystal. Typically, the easiest solution for excessively high
radial dopant or oxygen gradients is just to increase the
crystal rotation rate. However, the solution may some­
times prove to be more complicated than that. The cool
melt from under the crystal tends to reduce thermal
gradients outside of the meniscus. Any disturbance out
of the cylindrical shape has a better chance of surviving
and growing into a significant disturbance if the tem­
perature outside of the crystal increases only gradually.
There are always such disturbances because of random
fluctuations and because of the anisotropy of the grow­
ing single crystal. The most prominent anisotropic fea­
ture is the existence of four vertical growth nodes along
the crystal, at 90° intervals, in case of (100) material.
The nodes are caused by closed packed {111} planes
that try to grow a little longer along the meniscus than
other parts of the crystal. If the thermal gradients are
made too small, uncontrolled growth over the meniscus
and the loss of a single crystalline structure may result.
Before that, if the crucible and crystal rotation rates are
fairly large, three-dimensional flow patterns will develop
near the periphery of the crystal, again at four-fold sym­
metry, that cause the relatively narrow growth nodes
to widen and flatten, and finally the crystal changes its
shape to become somewhat star-shaped.
This simple and well-organized flow pattern by crys­
tal rotation, as approximated by a rotating disc, is only a
very partial truth. If we would only rotate the melt and
the crystal would be still, the melt immediately under
the crystal would rotate more slowly than the rest of
the melt and rotation rates would again create a sim­
ple flow. In this case, the pattern would be identical to
what was described previously, but the direction of the
flow would be inversed [16]. This kind of configuration
would create very large oxygen gradients over the radial
dimension of the crystal, as well as a high dopant gradi­
ent in the case of a volatile dopant, such as antimony in
low-resistivity material.
As counter-rotation is the industry standard, where
both the crucible and the crystal are being rotated, no
easy analytical solution for the melt flow exists (even if
we would not consider other components of flow, such
as free convection). Normally, the crystal is rotated at a
clearly faster pace than the crucible. However, because
of the much larger surface area in contact with the cru­
cible, most of the melt, also under the crystal, rotates
CHAPTER 2
in the same direction as the crucible; under the crys­
tal, at a lower rate than outside of the crystal radius.
The melt immediately under the crystal rotates with
it, but already, a few mms below, the direction of the
rotation is normally the opposite. In between, there is a
narrow layer where the actual rotation is close to zero.
Above and below, the melt tends to flow outward, again
because of centrifugal force, but in between there is a
sheath of melt that flows inward. This flow is extremely
important for the control and uniformity of oxygen in
the growing crystal: The melt under this flow layer is
quite oxygen rich, bringing oxygen from the bottom of
the crucible; but this layer is more oxygen lean, as it
flows in under the crystal after spending some time near
the melt-gas interface, where oxygen has been removed
from the melt. However, three-dimensional turbulent
effects complicate the flow patterns further.
2.6.4 Marangoni Convection and Gas
Shear
On the melt surface, there is a force that causes the melt
flow towards the crystal in such a way that any small par­
ticle that would fall onto the surface of the melt would
have high chances of hitting the crystal, thereby causing
it to lose its DF structure. This force and flow is called
Marangoni force and flow, and its origin is in the tem­
perature dependence of surface tension at the melt–gas
interface. Surface tension is the phenomenon that causes
small water droplets to try to take spherical shape:
A volume of liquid wants to minimize its surface area.
But it is the temperature dependence of surface tension
that creates the Marangoni force, not surface tension
itself. Farther away from the crystal, the surface tem­
perature of the melt is higher, and that is why surface
tension there is lower. Marangoni force, whose unit is
force per area (N/m2), is therefore directed towards the
cooler area, that is, towards the crystal, and its magni­
tude is larger for a larger temperature gradient. As the
melt viscosity is low, this flow has limited impact on the
melt behavior deeper down, but the flow velocity right
at the surface cannot be ignored.
There is another surface force that is opposing the
Marangoni flow, in HZs where the purge gas flow or a sig­
nificant part of it is directed close to the melt. At low pres­
sure, hot purge gas may have a velocity in the 10 m/s range
very near to the melt surface, and this creates a shear that
is directed outwards. The magnitude of this shear is often
in the same range as the Marangoni force. Especially if low
oxygen material is desired, the efficient sweeping of oxy­
gen containing gases is needed in the vicinity of the meltgas interface, and this translates to high gas velocity.
Oftentimes, if melt behavior during CZ growth is
simulated computationally, oxygen is considered as
33
PA R T I
Silicon as MEMS Material
not having an influence on melt flows. This makes the
optimization of the growth process substantially easier,
as the melt flows may be modeled on thermal con­
siderations and forced convections, only. After hav­
ing modeled the melt flow patterns, one may calculate
oxygen distribution in the melt with varying purge gas
flows. Proper simulation of the melt flow is a much
more laborious exercise than that of gas flow or oxygen
distribution.
However, if the gas flow is high enough to cause sig­
nificant shear to the melt interface, or if the cooling
effect of the gas flow changes the temperature distribu­
tion in the crystal and around the crucible by a consid­
erable amount, this approach is no longer valid. Then
the melt flows should be recalculated, adding very sig­
nificantly to the computational effort, for every major
change in the gas flow.
2.7 Magnetic Fields
There are two different kinds of static magnetic fields
in widespread use to produce CZ silicon crystals, trans­
verse and cusp fields. Almost pure axial fields are poorly
suited, as they tend to prevent transport of oxygen
and dopant from under the crystal; and, therefore, the
resulting oxygen concentration is high and variation of
oxygen and dopant in the radial direction (radial gradi­
ents) is often large.
Magnets weigh usually several tons, and the power
may be well beyond 100 kW. However, more powerhungry magnets have been increasingly replaced with
superconducting magnets. Sometimes, especially older
growers have been modified to take more lightweight
magnets, despite the cost of higher electric current den­
sity and larger power loss, as the space around the vac­
uum chamber has been in short supply and the grower
frame has not allowed for significant excess weight.
Furthermore, if low field is considered sufficient, mod­
ern permanent magnet materials together with iron
yokes may be applicable.
The movement of an electrically conducting fluid in a
magnetic field causes an electromotive force that is per­
pendicular to both the field and the direction of move­
ment. This electromotive force tends to create electric
currents that, in interaction with the external magnetic
field, oppose the fluid motion. The field strengths typi­
cal for magnetic CZ (MCZ) processes are sufficient to
slow down various flow patterns very significantly. This
has implications to various crystal properties such as
oxygen and dopant distributions; but they also tend to
reduce crucible wear, thus extending the lifetime of the
crucible, and reduce thermal fluctuations in the melt,
which, together with reduced crucible wear, results in
better DF growth yields.
34
2.7.1 Transverse Field
A transverse magnetic field is created from conventional
copper or superconducting coils that are located in the
vertical position. Heavy iron yokes are used to shorten
the magnetic path and to reduce the important stray
fields. This type of field has the unpleasant character­
istic of breaking the otherwise almost perfect cylindri­
cal symmetry of the growth geometry. However, as
the field impacts on melt behavior only, and the melt
flows in the case of large crystals deviate from cylindri­
cal symmetry in a significant manner anyway, this loss of
symmetry is not as serious a breach as it may first seem.
The crucible (and melt) rotation is normally rela­
tively fast in growth, with no magnetic field to stabilize
the fluid, but this is not the case for the transverse field.
The lateral field, together with melt rotation, would cre­
ate electric potential differences between the bottom
and near-surface regions of the melt. These differences
would be of varying magnitudes, depending on the angle
between the direction of the field and the fluid velocity;
and large electric currents opposing the rotation would
flow. That is why, under any transverse magnetic field,
the melt rotation rate would be close to zero, essentially
independent of the crucible rotation rate.
2.7.2 Cusp Field
Cusp magnetic field is essentially a field created by two
round horizontal coils, with a distance between them,
connected in such a way that their magnetic dipoles
oppose each other. That is why there is a region of
almost zero field that is usually close to the freezing
interface [17]. The cylindrical symmetry is maintained.
A typical shape of cusp field is shown in Figure 2.7.
This type of field also creates electromotive forces as
the melt is rotated, but contrary to the transverse field,
there is little force created that would try to stop the
rotation. That is why an MCZ process utilizing the cusp
field may be very similar to a normal CZ process. Far
from the freezing interface, the magnetic field is strong­
est and its impact on reducing melt flows is also great­
est. In a way, it may be considered that the cusp MCZ
purports to grow the crystal from a melt that has been
reduced in effective volume by creating circumstances
in which the melt close to the freezing interface and
below the crystal sees little effect of the field, and out­
side of the crystal radius the melt convection is largely
suppressed.
Oxygen concentration in an MCZ process is often con­
sidered to be substantially lower than in an otherwise sim­
ilar process but with no magnetic field. This is not always
true. It is proper to say that a magnetic field reduces the
rate of dissolution of the crucible; that is, introduction
Czochralski Growth of Silicon Crystals
0
0.2
0.4
of oxygen into the melt is diminished. However, it also
has an impact on melt flows near the melt–gas interface,
reducing flows there. It is essentially the balance between
the dissolution and evaporation of oxygen that dictates
the oxygen concentration in the melt.
As the magnetic field stabilizes the melt behavior,
a more effective means, for instance, in gas flows may
be utilized to remove oxygen from the melt, and that
is why the use of a magnetic field does allow the reach­
ing of lower oxygen levels. However, a lower oxygen
level in the melt does not guarantee low oxygen in the
crystal in a straightforward manner. Growth processes
are possible in which flow patterns under the crystal
are such that if that region is oxygen rich, the crystal
also becomes oxygen rich even if the melt outside of
the crystal radius has relatively low oxygen contents.
Such processes are normally not applied, as it would be
quite difficult to control the radial uniformity of oxygen
concentration.
2.7.3 Time-Dependent Fields
Much more complex magnetic fields may be devised
for better control of melt behavior, and the fields may
also be time dependent. However, these possibilities are
beyond the scope of this book.
2.8 Hot Recharging
The CZ crystal growth process that has been described
earlier depicts a standard batch process, in which one
crystal is pulled from the melt. Occasionally, for various
reasons, two small crystals may be pulled from a single
melt. However, this is a rarer occasion than so-called
hot recharging, in which a relatively large residual melt
is left in the crucible and new silicon material is added
into the melt. The easiest way of doing this is to use
0.6
0.8
1
CHAPTER 2
Fig 2.7 ● Shape of a typical cusp
magnetic field within the melt volume
and lower portion of the crystal.
Maximum field strength (white color
at scale value 1.0) is attained at the
crucible corner. Near freezing interface,
there is almost no field. Solid lines
depict the magnetic lines of force.
granular polysilicon, small spheres in the 1–4 mm diam­
eter range that flow easily, even through small-diameter
tubes or other structures, to make the feed. However,
because of the limited availability of this material and
additional concerns, other types of materials may also
be used: Small-sized chunks may be fed in a manner
similar to granular material, using larger-sized chan­
nels. Or a vertical tube-like structure filled with small
chunks may be lifted into the receiving chamber, after
removal of the crystal, and a valve in the lower end of
the tube opened to allow the charge to be replenished.
Furthermore, large rods of material may be put hang­
ing into the end of the seed cable/shaft and fed into
the melt in a well-controlled manner. Or adding to the
complexity in a significant manner, new silicon may be
added as molten from outside of the crucible proper.
In all of these cases, the main goal is to reduce cost
and save time compared with growing a single crystal
from the melt. The cost of the relatively expensive cru­
cible, which will break during cooling down, will then
be shared with a larger number of crystals. The residual
melt will also be shared with several crystals, however,
with the further expense of somewhat more contamina­
tion in the end of the last crystal than there would have
been at the same position if only one crystal would have
been pulled. However, today’s high purity processes
typically allow for that. There will usually be some time
savings, too, to the cycle time per produced kg of crys­
tals, as there will be less time needed to heat up and
cool down the HZ, again per crystal pulled.
A major impediment to the use of hot recharging has
been, in addition to the limited availability of granular
poly material, the strain that the very long total hot
time exposes the crucible to. There is a continual wear
in the crucible wall. The possibility that the advancing
wear will release small silica particles into the melt and
thus cause a structure loss increases as the wear pro­
ceeds. The way the crucible wall has been fused makes
35
PA R T I
Silicon as MEMS Material
the near inner surface of better quality than the deep
bulk of the material. Over the years, various alterna­
tives have been pursued to extend the lifetime, either
through modifications to the way the crucible behaves
when exposed to reactive silicon melt, or through
changes made to hot-zone design and the growth proc­
ess, in order to reduce the wear at the crucible walls.
Some approaches used within the industry today are
modifications to the silica material itself, including the
use of high-purity sand for an inside layer, sand that
has been manufactured starting from high-purity gases,
or fusing this inner layer to contain fewer bubbles and
other imperfections that would initiate nonuniform
wear that may result in the release of small silica/quartz
particles into the melt. Further possibilities are the
application of small quantities of various elements
whose role is to enhance the so-called devitrification of
silica, in order to ensure that the wear takes place more
uniformly than in the absence of this uniform devitri­
fied layer, and at the same time the crystal rejects those
added elements so powerfully that the concentration
in the crystal remains insignificant. It is recommend
to enhance the thermal design of the HZ in such a
way as to reduce the crucible inner wall temperatures
and thus to diminish wear through the lowered solu­
bility and reduced intensity of the melt flow patterns,
as well as to use various magnetic fields to stabilize
the melt.
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13. U. Ekhult, T. Carlberg, M. Tilli, Infra­
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A. Juel, T. Mullin, D.S. Riley, Free
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Further reading
G. Müller, J. Métois, P. Rudolph (Eds.),
Crystal Growth—From Fundamentals
to Technology, Elsevier, 2004.
36
H. Scheel, T. Fukuda (Eds.), Crystal
Growth Technology, John Wiley & Sons,
2003.
17. R.W. Series, Effect of shaped
magnetic field on Czochralski
silicon growth, J. Cryst. Growth 97
(1989) 92.
18. O.J. Anttila, M.V. Tilli, V.K.
Lindroos, Computer modelling of
the temperature distribution in the
silicon single crystals during growth
and the thermal history of the crystal,
in: J.C. Mikkelsen, Jr., S.J. Pearton,
J.W. Corbett, S.J. Pennycook,
(Eds.), Oxygen, Carbon, Hydrogen
and Nitrogen in Crystalline Silicon,
vol. 59, Materials Research Society
Proceedings Series, 1985, Vol. 59,
p. 323.
19. O. Anttila, M. Laakso, J. Paloheimo, J.
Heikonen, J. Ruokolainen,
V. Savolainen, T. Zwinger, Simulation
of silicon Cz growth: where we are
now, in: C.L. Claeys, M. Watanabe,
P. Rai-Choudhury, P. Stallhofer (Eds.),
High Purity Silicon VII, vol. 200220,
ECS Symposium Proceedings Series,
Vol. 2002–20, p. 65.
20. A. Lüdge, H. Riemann, Doping
inhomogeneities in silicon crystals
detected by the lateral photovoltage
scanning (LPS) method, in: J.
Donecker, I. Rechenberg (Eds.),
Defect Recognition and Image
Processing in Semiconductors 1997,
CRC Press, 1997, p. 145.
3
Chapter Three
Properties of Silicon Crystals
Jari Paloheimo
Okmetic Oyj, Vantaa, Finland
Many properties of Czochralski (CZ) silicon wafers origi­
nate partially or totally from the crystal growth used to
produce the single-crystalline silicon. For example, the
diameter and orientation of the as-grown crystal are
already close to those of the final wafers. Furthermore,
the conductivity type (p or n), selection of the dopant
element and its concentration (which induces certain
electrical resistivity), oxygen concentration and amount
of carbon, and the homogeneity of these concentrations
in the microscopic and macroscopic scales all originate
from the growth process. Also, other important qualities
(e.g., the amount of harmful transition-metal impurities
and many of the typical defects encountered in silicon
processing) are contributed by the initial crystal mate­
rial. In the optimal case, the most important quality fac­
tors of the crystal, considering the planned use of the
wafers, are properly identified beforehand; the allowed
range of properties is specified; the quality is controlled
by the crystal-growing process; and the resulting qual­
ity becomes ascertained from the crystal and/or wafers.
Such procedures, if handled properly, give a good starting
point for the subsequent device processing on the wafers.
Furthermore, feedback about the yield and quality prob­
lems encountered in wafer and device processing gives
useful information for further improvements in the crys­
tal quality. In the worst case, the crystal may contain too
many impurities or defects, or have a tendency toward
later defect formation because of insufficient initial infor­
mation or knowledge, compromises in the crystal qual­
ity or cost, inherent limitations of the growth process,
or some other more accidental reason. The insufficient
quality could lead to rejection of the crystal material or
wafers or, if unfit wafers are delivered to customers, to
negative influence on the yield or quality of their product,
which can be an integrated circuit, discrete device, sensor
structure, solar cell, or some other type of application.
In this chapter, the typical properties of CZ silicon
crystals are reviewed, covering impurities and defects,
their effects, control, and incidence. We concentrate on
the properties of as-grown crystal, while the contribu­
tions by wafer processing are only mentioned briefly.
Specifically, the quality factors that have proven to be of
the greatest practical importance in the crystal-growing
industry for 4–8 in. nominal crystal diameters, which is
also the range used in microelectromechanical systems
(MEMS), are covered. The connections of impuri­
ties and defects to the success or failure of later device
fabrication on the wafers are indicated where possible;
although, due to the extent of the subject, only major
items can be covered. More detailed information can be
found in the references of this chapter and in the other
chapters of this book.
3.1 Dopants and Impurities
The CZ silicon crystals contain small amounts of impuri­
ties of which some are essential, in controlled amounts,
for the quality of the crystal and wafers, while other
impurities are harmful if their concentration is too high
and, thus, the latter elements must be avoided. The
acceptor or donor impurities and oxygen, in suitable
amounts, are among the former, useful elements. The
acceptor and donor dopants are usually elements from
groups III and V of the periodic table of elements, the
most used ones being boron (acceptor, for p-type crys­
tals) and phosphorus, antimony, and arsenic (donors, for
n-type crystals) (see Table 3.1). These typical dopants
37
PA R T I
Silicon as MEMS Material
Table 3.1 Table of elements indicating substitutional dopant
impurities of silicon
Period
Group III
IV
V
2
B(A)
3
Al
Si
P(D)
4
Ga
As(D)
5
In
Sb(D)
The elements most used, in practice, as acceptors and donors in CZ crystals are
indicated by (A) and (D), respectively.
are substitutional impurities (i.e., they replace silicon
atoms in the lattice) and donate one hole or electron per
each acceptor or donor atom to the valence or conduc­
tion band of silicon, respectively [1, 2]. The acceptors
and donors are used to control the charge carrier con­
centration (and resulting resistivity) and type of charge
carriers of the crystal. These parameters are essential
considering the operation of the semiconductor devices
processed on the wafers [1]. Instead of boron, some
other elements from group III could also be used as
acceptors in CZ crystals but have certain limitations and
are not common in practice. For example, gallium dop­
ing has been suggested for solar cell applications in order
to avoid the initial degradation of the efficiency observed
in solar cells made of boron-doped CZ silicon [3]. The
three donors—phosphorus, antimony, and arsenic—are
not replaceable by each other, at least self-evidently,
because they have different properties. For example, the
different dopant elements have different limits for the
lowest resistivity achievable and the amount of axial var­
iation of resistivity within crystal depends on the dopant.
Furthermore, the diffusion and redistribution behavior
of the dopants in the wafer during device processing also
varies [1]. For some dopants, certain safety issues exist
in crystal growing or later processing and may require
precautions. In practice, the users of the wafers already
specify, for each wafer product, the dopant element to
be used in the crystal. Boron and phosphorus are typi­
cal in lightly doped crystals while all four elements (i.e.,
boron, phosphorus, arsenic, and antimony) are used in
the highly doped case.
Oxygen originating from the silica crucible is one of
the most characteristic impurities in CZ silicon in con­
trast to float-zone (FZ) silicon, which contains practi­
cally no oxygen. A suitable oxygen concentration is
considered to be among the main quality factors to be
controlled in the crystal-growing process. Oxygen in
interstitials gives the wafers mechanical strength against
thermal, gravitational, or mechanical stress during heat
38
treatments, decreasing the risk of slip dislocation for­
mation and wafer warping [4, 5]. Furthermore, oxy­
gen forms precipitates [6–8], which are often used for
impurity gettering in device processing where gettering
is a method to remove harmful metal impurities from
the device region of the wafer [9]. Also too high an
oxygen concentration can be harmful if it induces too
strong precipitation of oxygen and formation of defects.
Nitrogen can be intentionally added to crystals in
concentrations around 1015 cm�3 to control the microdefect formation [10], mainly to enhance oxygen pre­
cipitation or to reduce the size of vacancy-originated
defects, and/or to strengthen the crystal [11]. Nitrogen
has the potential for commercial applications in largediameter wafers but is not used in standard smallerdiameter CZ silicon wafers and is also not expected to
offer benefits in typical MEMS.
Only one acceptor or donor dopant element is used in
one growth, the other acceptor or donor dopants being
avoided because their coexistence could cause a shift
of resistivity or other, possibly unpredictable, effects.
However, unintentional dopants have several potential
sources and cannot be totally avoided, although their
concentration can be kept at an acceptably low level.
For example, small amounts of aluminum and boron
dopants originate to the melt and crystal from standard
silica crucibles made of natural quartz containing these
impurities. Aluminum is an acceptor and, if present
at high concentrations on the wafer surface, has been
found to influence the growth and quality of oxide lay­
ers grown on wafers [12]. Fortunately, the concentra­
tions originating from crystal growing, typically 1013
Al atoms/cm3, do not yet cause surface-quality prob­
lems, although aluminum may already have some effect
on the resistivity of the wafers if these have very high
resistivities. Dopants from earlier runs may also reside
inside the furnace chamber and in the hot zone, or even
in the seed crystal, and could end up in the next crys­
tals if this risk is not properly taken into account in the
crystal-growing procedures.
The harmful impurities in CZ silicon crystals include
carbon, transition-metal impurities (e.g., Fe, Cu, and
Ni) [13–16], and alkali and alkali earth metals (e.g.,
Na). These impurities, as well as accidental dopants,
may originate from the starting materials (polysili­
con, recycled silicon, if used, and dopants), silica cru­
cible, and materials and contamination of the furnace
and the hot zone (see Chapter 2 and, e.g., Ref. [17]).
Contamination may also be caused by procedures or
mistakes by the operators or malfunction of the crystalgrowing furnace. Carbon is electrically inactive in
silicon, while transition-metal impurities may form
deep impurity levels within the band gap between the
conduction and valence bands, behave as recombina­
tion centers or as unwanted acceptors and/or donors, or
Properties of Silicon Crystals
form complexes with dopants under certain conditions.
Transition metals are also relatively fast diffusers in sili­
con at temperatures above room temperature; copper,
especially, remains quite mobile even at room tempera­
ture. The transition metals, or their precipitates, may
decrease the recombination or generation lifetimes and
the minority carrier diffusion lengths, and cause leakage
currents in the junctions of the devices, lower efficiency
of solar cells, quality problems with gate oxides in
metal-oxide-semiconductor structures, or even a shift of
the resistivity [13, 14, 16, 18]. The exact effect of the
metal impurities depends considerably on the metal, its
concentration and state, defects formed, and the type
and resistivity of the silicon wafer. For example, iron
can be very effective in decreasing the recombination
lifetime, especially in p-type silicon, while copper is
considered to have a greater impact on the lifetime of
n-type wafers than on p-type wafers [16].
3.2 Typical Impurity Concentrations
The typical concentrations of a few characteristic impu­
rities in CZ crystals are listed below in Table 3.2. The
concentration of the specified dopant (or, actually, the
resistivity value), as well as the oxygen, carbon, and
iron concentrations, are routinely measured. The val­
ues indicated are valid for semiconductor-grade crys­
tals, where contamination levels are typically low, and
are applicable, especially, for nominal crystal diam­
eters of 4 in., 5 in., 6 in., and 8 in., covering the diam­
eters used in present and near-future MEMS. In most
cases, these carbon and metal concentrations of the asgrown crystal are not the limiting factors, considering
the success of device processing, and can be tolerated.
However, considerably larger contamination concentra­
tions of the crystal are possible in some cases (e.g., in
solar-grade crystals) if lower-quality production materi­
als are used for cost reduction, especially if the residual
silicon remaining in the crucible after previous growth
(so-called “pot scrap”) is recycled into the next charge
to replace pristine polysilicon.
The solubilities of various elements in silicon crystal
at high temperatures can be found in [19] and refer­
ences therein, and are among the limitations and mech­
anisms to be taken into account in crystal growth. The
actual concentration of the dopant and other impuri­
ties in CZ growth are typically much below their solu­
bility at the melting point of silicon, Tm1412°C. The
solubility in the melt and crystal in the vicinity of Tm
may be approached only in the following anomalous
cases: (1) The melt, by mistake or by furnace malfunc­
tions, becomes highly contaminated by carbon or some
other impurity. (2) Very large amounts of acceptor or
CHAPTER 3
Table 3.2 Typical range of concentration of impurities in
semiconductor-grade CZ silicon crystals, grown with or without a
magnetic field
Impurity
Typical concentrations in crystals
Specified acceptor
or donor dopant*
0.1 ppba…
1000 ppma
5 � 1012…5 � 1019 cm�3
Other acceptors or
donors
�1 ppba
�5 � 1013 cm�3
Oxygen*
5–18 ppma
2.5 � 1017…9 � 1017 cm�3
Carbon
�0.5 ppma
�2.5 � 1016 cm�3
Iron
�1 ppta
�5 � 1010 cm�3
The concentrations of the impurities denoted by the asterisk (*) are
controlled to their optimized and/or specified values, while other
impurities are considered to be contamination. Notice that 1.0 ppma
corresponds to 5.0 � 1016 atoms/cm3. The interstitial oxygen
concentrations are given in “new ASTM units” (ASTM F 121-83 [24])
and carbon concentrations are given in ASTM F 123-86 units [21].
donor dopants are added to the melt to reach resis­
tivities below standard levels. If the solubility limit is
reached, particles start to form in the melt, especially at
the solid–melt interface, probably causing dislocations
in the crystal and making the growing of single crystals
impossible [20]. For example, according to our experi­
ments on carbon-contaminated crystals, dislocations
start to appear in the CZ crystal and its single crystalline
structure is lost if the carbon concentration of the crys­
tal reaches 11–13 ppma (concentration is expressed in
units of ASTM F 123-86 [21], in reasonable agreement
with the values for the solubility of carbon reported in
the literature, suggesting that silicon carbide particles
are responsible for the effect. Still, the standard carbon
concentrations in commercial crystals are considerably
below the solubility limit. Even if the concentrations of
impurities in the crystal are below the solubility at Tm,
the solubilities start to decrease with decreasing tem­
perature, often leading to supersaturation of impurities
in the crystal and wafers at lower temperatures. In fact,
this supersaturation becomes the driving force for the
later formation and growth of impurity precipitates of
oxygen and transition metals, for example, if these pre­
cipitates are first able to nucleate.
The interstitial oxygen concentration of the crystal
Oi can be varied over a relatively wide range by chang­
ing the process parameters (e.g., the rotation rate of the
crucible, the argon gas mass flow, the pressure inside the
furnace, the shape and intensity of the magnetic field,
the hot zone structure, and/or the melt height position)
as has been discussed in greater detail in Chapter 2
and in [20, 22, 23], and references therein. Oxygen
39
PA R T I
Silicon as MEMS Material
and carbon concentrations are typically measured by
using infrared absorption techniques (for more details,
see Chapters 5 and 21). The calibration factors used to
calculate the concentration from the measured absorp­
tion coefficient are not unique. Several different factors
have been defined and used, and, thus, the measured or
specified values of interstitial oxygen and substitutional
carbon should preferably include a reference to one of
the standards to make the values exactly defined. In this
chapter, we have systematically used the “new ASTM
units” (also called ASTM F 121-83 [24], or DIN) for
oxygen and ASTM F 123-86 [21] for carbon. The infra­
red absorption measurement of oxygen or carbon is
accurate and practical in lightly doped p- and n-type
crystals, and the Oi of these crystals is routinely meas­
ured from samples sliced from every crystal; however,
the infrared measurement becomes inaccurate or even
impossible in highly doped p� and n� crystals because
of their strong free-carrier absorption. Therefore, other
methods, such as gas fusion analysis (GFA) or secondary
ion mass spectroscopy (SIMS), have to be used in such
cases (e.g., Ref. [25]).
Typical carbon concentrations of 0.1 ppma and
almost always �0.5 ppma in crystals largely originate
from polysilicon charge and from the carbon of the graph­
ite parts of the hot zone (for more details on the contam­
ination mechanisms, see Chapter 2). Fortunately, such
amounts of carbon have only a relatively minor impact
on crystal and wafer quality and can be tolerated, while
much higher concentrations could already enhance oxy­
gen precipitation in later heat treatments and be harmful
[2, 8, 26–28]. In some cases, even the concentration of
0.5ppma could enhance the oxygen precipitation [28],
while for considerably higher concentrations of �2 ppma,
the effect becomes quite clear [26, 27]; however, the lat­
ter values are not common in semiconductor-grade CZ
crystals.
Metal impurities are tolerated in even much lower
concentrations than carbon in the crystal and may be
detrimental in the ppta levels in some cases. For exam­
ple, the carrier lifetimes that are important parameters
in a variety of device structures [1] can be very sensitive
to the iron concentration [18]. In lightly boron-doped,
p-type silicon, assuming that iron is in iron-boron pairs,
the recombination lifetime of the minority carriers
(electrons) is limited to the value
τ(μs) ≈ 1.5 � 1013 /NFeB (cm�3 )
(3.1)
where NFeB is the concentration of the FeB pairs (see
Ref. [15] and references therein). Also, other impuri­
ties, defects, and/or high dopant concentrations (low
resistivity) [29] may decrease the lifetime. For more
information about the detection and identification of
various metals by using minority carrier recombination
40
lifetime measurements, we refer to [16, 18, 30], and
for other metal detection methods, we refer to [14]
and references therein.
The target for the iron concentration appears quite
challenging at first glance. Fortunately, the crystal
strongly rejects typical harmful metal impurities during
growing, as discussed in Section 3.3, leading to much
purer crystal when compared with the melt, allowing
the crystal to reach the low impurity concentrations
needed. For example, a typical iron concentration in the
order of 1010 cm�3 in crystal (see Table 3.2), according
to Eq. 3.1, would allow the recombination lifetime to
have a sufficiently high value of about 1000 μs in p-type
silicon. However, it is important to note that the values
indicated above are for the as-grown crystal, while the
connection between the initial metal concentration of
the crystal and the lifetime in the final device structure
is not simple to analyze because of the additional metal
contamination and diffusion, precipitation, and/or get­
tering of metals during wafer and device processing. In
fact, the exposure of wafer surfaces to metals in later
processing after crystal growing in most cases dominates
the metal contamination and should be controlled to tol­
erable levels, possibly by applying gettering methods [9]
to remove the metals from the active surface region.
3.3 Concentration of Dopants
and Impurities in Axial Direction
The concentration of the dopant, carbon, and metal
impurities increases along the crystal body. Thus, wafers
fabricated using silicon material from different parts
of the crystal may behave differently. Much about the
axial concentration profile can already be gleaned by
closely looking at the normal freezing equation, which
expresses the impurity concentration variation as a
function of the solidified mass fraction of the melt (g):
cs (g) � k 0 c0 (1 � g)k 0 �1
(3.2)
Here, c0 is the initial concentration in the melt and
k0 is the equilibrium distribution (segregation) coeffi­
cient, which has a characteristic value for each impurity
in silicon [31] (see Note 1 [32]). In a relatively typi­
cal case, the value of g is quite small—a few percent at
most—in the beginning of the body, while g 0.9 in the
end of the body of the crystal, although the exact values
depend on the process details. Table 3.3 below gives the
distribution coefficients, k0, of some of the most impor­
tant impurities in silicon. Oxygen has the highest value
of k0 of all elements, k01 [39], while the dopants
and especially the transition metals have lower values
of k0 and are rejected by the growing crystal. In prac­
tice, to reach exact agreement between the theoretical
Properties of Silicon Crystals
Table 3.3 Equilibrium distribution coefficient k0 of typical impurities
in silicon (see [19] and [31] and references therein, and [39] for
oxygen)
Element
k0
O
1
B
0.8
P
0.35
As
0.3
C
0.07
Sb
0.023
Ga
8 � 10�3
Al
2 � 10�3
Na
1.7 � 10�3
N
7 � 10�4
Cu
4 � 10�4
Ni
1 � 10�5…1 � 10�4
Fe
8 � 10�6
segregation behavior and experiments, an effective
value keff of the distribution coefficient, slightly dif­
ferent from k0, should be used instead of k0 in Eq. 3.2
(see Note 2 [33]). According to Eq. 3.2, the concentra­
tion cs increases (decreases) with increasing g for k0 �1
(k0 � 1), while cs � c0 if k0 � 1. Theoretical concen­
tration curves for a few typical impurities are shown in
Figure 3.1. For impurities that have k0 ��1 (e.g., tran­
sition metals), the shapes of the curve become almost
independent of k0 (i.e., cs(g)k0c0(1 � g)�1, where k0
is a prefactor only), further indicating that the ratio cs/
c0 of the body (g0.0–0.9) varies in the range of k0…
10 � k0. Thus, in principle, CZ growing is an effective
method to purify silicon of impurities with k0 ��1.
Equation 3.2 predicts the axial concentration profiles
correctly only if the impurity does not evaporate from
the melt surface and additional impurity is not sup­
plied into the melt during pulling. Considering various
dopant elements, boron in p and p� crystals and phos­
phorus in lightly doped, n-type crystals obey Eq. 3.2
with reasonable accuracy. On the other hand, the nor­
mal freezing equation is not useful with oxygen which
evaporates from the melt surface and is supplied to the
melt from the dissolving silica crucible during pulling
[22, 34]. The equation should also be used with care
with carbon and metal impurities, which are, to some
CHAPTER 3
extent, supplied to the melt during pulling, or with
highly doped n� crystals with large concentrations of
phosphorus, antimony, or arsenic, which noticeably
evaporate from the melt.
The oxygen concentration of a crystal preferably should
be axially uniform, the values within the given specification,
and suitable for the planned use of the wafers. Knowledge
about the suitable oxygen concentration range is included
in the wafer specification. In lightly doped products, inter­
mediate Oi targets are in the range of 13–15 ppma; how­
ever, significantly different targets are also common. The
concentration is controlled during crystal pulling (see, e.g.,
Refs [20, 22–23, 34], and Chapter 2) by using proper val­
ues for the process parameters for each oxygen target and
measurements of the actual result after growth. Examples
of the measured oxygen concentration curves of two crys­
tals with significantly different oxygen targets are shown in
Figure 3.2. Relatively uniform oxygen concentrations can
be achieved in boron-doped p-type and in phosphorusdoped n-type crystals, the typical variation of axial Oi
(measured at radius r � 0) being within � 1 ppma from
the target value.
The dopant has no effect on crystal’s oxygen concen­
tration in lightly boron- or phosphorus-doped p- or n-type
crystals; however, according to the literature, in highly
boron-doped p� crystals, the oxygen concentration may
be increased by 20% for similar process parameters
[22, 34, 35], but this shift depends on the process condi­
tions and boron concentration and may also be practically
negligible. Moreover, the oxygen concentration is not as
easy to accurately measure in p� or n� crystals, which
also complicates their exact oxygen control. Thus, oxy­
gen control in p� crystals is less accurate than in lightly
doped cases. The precise control of oxygen is even much
more difficult in highly doped n� crystals as the dopant
evaporates, which has as a consequence that the evapora­
tion of dopants and the evaporation of oxygen are inter­
related and cannot be optimized independently by the
process parameters. Furthermore, the oxygen evapora­
tion from n� melt is enhanced, the evaporating oxygencarrying species typically being oxides of the dopant
instead of SiO [36]. Because of these reasons, the oxygen
concentrations in n� crystals are often relatively low and
have a relatively large axial variation [37].
The carbon concentration in the beginning of the crys­
tals is typically low, 0.0 ppma, according to the infra­
red absorption measurements. The carbon concentration
increases with length at a faster rate than the normal
freezing equation (Eq. 3.2) predicts because of the accu­
mulation of carbon contamination from the atmosphere
into the melt during crystal pulling. This additional car­
bon contamination can be kept at reasonable levels by
using suitable hot zone design and growth parameters
and procedures, typically leading to low carbon values
of �0.5 ppma in the end of the body, typically located
41
Silicon as MEMS Material
PA R T I
1.E+01
1.E+00
cs(g)/c0
1.E−01
1.E−02
1.E−03
k0 = 1
k0 = 0.8 (boron)
k0 = 0.35 (phosphorus)
k0 = 0.07 (carbon)
k0 = 0.0017 (sodium)
k0 = 8E-6 (iron)
1.E−04
1.E−05
1.E−06
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Solidified fraction of melt, g
Fig 3.1 ● Concentration of impurities in the crystal vs. solidified fraction of the melt, g, calculated from the normal freezing equation.
The concentration has been scaled by the initial melt concentration, c0.
into the charge before or after melting. It is actually
the resistivity that is defined in the wafer specifica­
tion instead of dopant or charge carrier concentration
because the resistivity can be measured relatively easily
and accurately. The resistivity and carrier concentrations
are connected by the following equations [1]:
16
Oi (ppma) (new ASTM)
15
14
13
12
11
10
9
8
Crystal 1 (high Oi)
Crystal 2 (low Oi)
7
6
0
0.2
0.4
0.6
0.8
Solidified fraction of melt, g
Fig 3.2 ● Experimental oxygen concentrations vs. the solidified
fraction of the melt, g, in two lightly doped crystals that have
different targets for Oi.
at g0.9. In principle, the precipitation of oxygen in the
crystal could be enhanced by intentionally adding small,
controlled amounts of carbon into the initial charge, but
such attempts would lead to relatively unpredictable
or uneven results as the wafers from different parts of
the crystal would inevitably have very different carbon
concentrations. In practice, low carbon concentrations
are preferred in the final use of the wafers and, thus, the
maximum allowed carbon concentration is quite often
given in the wafer specification.
3.4 Resistivity
The resistivity, ρ, and conductivity type (p-type vs.
n-type) of crystals are controlled by adding precise
amounts of the specified acceptor or donor impurities
42
� � (qμ p p)�1
for p-type silicon, and (3.3a)
� � (qμ n n)�1
for n-type silicon
(3.3b)
where q is the elementary charge 1.602 � 10�19 C, μp
(μn) is the mobility of holes (electrons), and p (n) is
the density of holes in the valence band (electrons in
the conduction band). The mobility values of Eqs 3.3a
and 3.3b are not constants, but instead are dependent
on the dopant densities, mainly at high concentrations
of �� 1015 cm�3. The carrier concentration induced by
the doping is approximately equal to the dopant density
for the typical dopant elements and densities. In the
lightly doped region, at concentrations of �1016 cm�3,
the resistivities at 23°C are approximately (based on
SEMI MF723-0307 [38])
ρ (ohm-cm) ≈ 1.3 � 1016 /N A (cm�3 ) (3.4a)
for boron-doped, p-type silicon, and
ρ (ohm-cm) ≈ 4.5 � 1015 /N D (cm�3 ) (3.4b)
for phosphorus-doped, n-type silicon
Here, NA (ND) is the boron (phosphorus) concentra­
tion. The simple Eqs 3.4a and 3.4b are only for the lightly
doped case; they have relatively limited accuracy at higher
concentrations. However, a more general and accurate
correlation between the resistivity and dopant concentra­
tion, valid in lightly and highly doped p-type and n-type
silicon, can be presented by using parameterized functions,
Properties of Silicon Crystals
CHAPTER 3
1.E+04
p-type / boron
1.E+03
n-type / phosphorus
Resistivity (ohm-cm)
1.E+02
1.E+01
1.E+00
1.E+12
1.E+13
1.E+14
1.E+15
1.E+16
1.E+17
1.E+18
1.E+19
1.E+20
1.E−01
1.E−02
1.E−03
1.E−04
Dopant density (cm–3)
Fig 3.3 ● Resistivity vs. dopant density at 23°C, calculated according to SEMI MF723-0307. The two separate curves correspond to
boron-doped (p-type) (upper, solid curve) and phosphorus-doped (n-type) silicon (lower, dashed curve).
ρ(g) ≈ ρ(g � 0) � (1 � g)1�k 0
(3.5)
10
9
Resistivity (ohm-cm)
which can be found in SEMI MF723-0307 [38], together
with the references to the experimental data on which
the fit is based. The resulting accurate curves are shown in
Figure 3.3 and are basically for boron and phosphorus,
although the latter curve is also a relatively good approxi­
mation for antimony and arsenic. The correlation is very
practical as it allows the calculation of the axial resistiv­
ity profile if the axial concentration profile is known (e.g.,
from the normal freezing equation) or, correspondingly,
the axial concentration profile if the axial resistivity varia­
tion is known (e.g., from resistivity measurements).
Figure 3.4 shows typical examples of experimen­
tal resistivity curves of lightly boron- and phosphorus-doped, p- and n-type crystals, indicating a larger
resistivity variation along the crystal for the dopant with
a smaller value of k0 (i.e., phosphorus in this case) (see
Table 3.3). The actual curve shapes can be explained and
analyzed by using the relationship of SEMI MF723-0307
[38] and the normal freezing equation (see Eq. 3.2). The
resulting fitted values of the distribution coefficients,
denoted by k in the figure, are quite close to the values
of k0 in Table 3.3. As a rule of thumb, the concentra­
tion of boron in p- or p� -type (phosphorus in n-type)
crystals will vary by a factor of 1.6 (4.5) within the
typical body length of g0.0 to g0.9 in CZ growth
because of normal freezing behavior. According to Eqs
3.4a and 3.4b, the resistivity will vary along the body by
approximately the same factors as given above for the
dopant concentrations. The resistivity in lightly boronor phosphorus-doped crystals approximately obeys the
following equation:
8
7
6
5
Resistivity p-type (boron)
Resistivity n-type (phosphorus)
Theory for boron (with k = 0.77)
Theory for phosphorus
(with k = 0.34)
4
3
2
0
0.2
0.4
0.6
0.8
Solidified fraction of melt, g
Fig 3.4 ● Experimental axial resistivity variation in typical
p-type (boron-doped) and n-type (phosphorus-doped) crystals
presented as a function of g in the body. The solid and dashed
curves are obtained by fitting the normal freezing equation to
the resistivity curve shape. The fitted values of the distribution
coefficients are given in the figure.
Depending on the dopant element and the resistivity
specification, which defines the upper (ρmax) and lower
(ρmin) limits of the resistivity allowed for the wafers,
either the whole crystal or only part of it is within the
resistivity specification, the latter case giving a lower
commercial crystal yield and higher cost per wafer.
Figure 3.5 shows the fraction of the body within the
resistivity specification as a function of the ratio ρmax/ρmin
of the limits of the resistivity specification. The curves
of Figure 3.5 are approximations calculated by using Eq.
3.5, assuming that the resistivity in the beginning of the
body at g0.0 is accurately adjusted to be equal to ρmax
43
Silicon as MEMS Material
PA R T I
1.2
80
p-type / boron
n-type / phosphorus
60
40
20
0
1
1.5
2
2.5
3
3.5
4
4.5
5
Resistivity/Resistivity at g = 0
Fraction of body within
specification (%)
100
Beginning of
crystal
1
End of
crystal
0.8
0.6
0.4
As (n+) (no evaporation)
As (n+) (with evaporation)
Sb (n+) (no evaporation)
Sb (n+) (with evaporation)
0.2
Resistivity ratio of specification
Fig 3.5 ● Fraction of body within resistivity specification in
boron- or phosphorus-doped crystals. Here, the resistivity ratio is
defined as the ratio ρmax/ρmin between the upper (ρmax) and lower
(ρmin) resistivity limits allowed by the wafer specification.
and the body ends at g0.9. Although the model in
Figure 3.5 is an approximation, it already describes the
main trend. The optimal case, with 100% of the body
in the specification, is only reached for a specification
that is wide enough (see Note 3 [40]). For example,
for a resistivity specification 8.0–14.0 ohm-cm (i.e., for
ρmax/ρmin � 14.0/8.0 � 1.75), Figure 3.5 suggests that
the whole body of a boron-doped p-type crystal can be
adjusted to be within the specification, while only about
60% of the body of a phosphorus-doped n-type crystal
is within the requested range for a similar specification,
while the rest of the crystal would be unfit. The differ­
ent shapes of the curves give a natural explanation for
the fact that relatively wide resistivity specifications are
preferred for phosphorus-doped wafers, while consid­
erably narrower specifications are possible for borondoped wafers. Dopants with k0 ��1 (e.g., gallium,
which is only rarely used), would result in an even
larger resistivity variation compared with that of boron
or phosphorus [3].
In highly doped n� crystals—doped with antimony,
arsenic, or phosphorus—the resistivity curves cannot
be predicted by using Eq. 3.2. This is because the resis­
tivity curves of n� crystals are contributed by dopant
evaporation from the melt, which depends on the
dopant element and the process parameters, such as
argon gas mass flow, the pressure of the chamber during
pulling, the hot zone design, and the dopant concentra­
tion in the melt. Therefore, the enrichment of dopants
in n� crystals is slower and the axial resistivity varia­
tions smaller than the normal freezing equation would
suggest [20, 41], which results in a narrower distribu­
tion of resistivities within a crystal (see Figure 3.6),
which is largely beneficial considering the quality of
the wafers. In extreme cases, the resistivity may even
increase with the body length position in n� crystals if
44
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Solidified fraction of melt, g
Fig 3.6 ● The figure indicates the theoretical result of the normal
freezing equation for antimony- and arsenic-doped crystals and,
schematically, the behavior with evaporation. Note that the latter
curves, which include evaporation, are not unique, but will vary
if any process parameters or conditions affecting evaporation
are changed.
evaporation is very strong [20], but this process region
is typically not used.
Most of the lightly doped CZ crystals have resistivity
targets somewhere between 1 and a few tens of ohmcm in the beginning of the body. The highest and low­
est resistivities achievable in CZ crystals are far beyond
this range in both directions, and depend on the dopant
and process conditions. If the resistivity target is too
low compared with the process capability, it becomes
impossible to grow the crystal without dislocations.
Typically, the lowest resistivity specifications for highly
doped 6 in. crystals are in the order of �3 mohm-cm for
boron and arsenic, �1.5 mohm-cm for phosphorus, and
�17 mohm-cm for antimony. These lowest resistivities
are, as a general rule, used in the fabrication of power
devices, while they are not common in MEMS. The
highest resistivities achievable in CZ crystals are above
1 kohm-cm and are only reached by carefully control­
ling the purity in order to avoid unintentional dopants.
The resistivity ranges covered thus correspond to dopant
densities within a wide range of 1012…1020 cm�3.
3.5 Radial Variation of Impurities
and Resistivity
The measured or specified value of the resistivity or oxy­
gen concentration typically refer to the value at the radius
r � 0 unless otherwise defined, and describes accurately
only a fraction of the wafer area, missing the periphery
area. The dopant and oxygen concentrations typically
Properties of Silicon Crystals
1.25
2
Scaled resistivity
Oxygen gradient (%)
6 in. p<100>
6 in. n<111>
1.20
1.15
1.10
1.05
0
−2
−4
–75 –60
–45 –30
–100
15
30
45
60
75
Radius (mm)
Fig 3.7 ● Resistivity profiles of lightly boron-doped 6 in. p �100�
and lightly phosphorus-doped 6 in. n �111� crystals, scaled by
the resistivity at r � 0. The differences between the two curves
are due to different dopants and orientations.
decrease, and resistivity increases, toward the wafer
edge, the resistivity in most cases showing U- or Wshaped curves along the diameter as shown in Figure 3.7.
This radial dependence of the dopant concentration adds
to the variations of properties of the devices if these are
sensitive to the charge carrier density and resistivity of
the substrate. Large radial variations in oxygen may
result in large variations in oxygen precipitation behavior
and gettering efficiency or a greater risk of slip formation
during thermal cycles. The amount of radial variation of
dopants and oxygen also shows dependence on the body
length position in the crystal due to the corresponding
changes in the process parameters, the amount of the
remaining melt, and the melt flow characteristics. The
radial profiles also vary to some extent from one wafer
to the next because the profiles are contributed by vary­
ing concentration striations, caused by fluctuations in
the melt flow and/or melt temperature and growth rate
of the crystal (see Chapter 2 and Refs [42] and [43]).
Examples of the experimental curves for resistivity and
oxygen are shown in Figures 3.7 and 3.8, respectively.
Relatively high crystal rotation rates and suitable val­
ues for other parameters affecting the mixing of the
melt and its concentration variations are essential for
reaching tolerable radial variation in the crystal, although
a certain amount of radial inhomogeneity still remains.
The radial resistivity variation is affected by the dopant
and orientation, and relatively different radial profiles
are obtained for different products. For example, the
variation is greater in phosphorus-doped (n-type) vs.
boron-doped (p-type) crystal of the same orientation.
In fact, the variation is often greater for the dopants
that have lower k0 values, because a small k0 allows and
gives rise to greater variations in the effective value keff
in the radial direction, while the impurities with k01
8 in. p<100>,
Process A
8 in. p<100>,
Process B
−6
1.00
0.95
–15
0
CHAPTER 3
–75
–50
–25
−8
0
25
50
75
100
Radial position (mm)
Fig 3.8 ● Measured radial variation of oxygen in lightly borondoped 8 in. p �100� crystals grown by using different process
parameters. Here, the oxygen gradient, defined later in Eq. 3.6b,
is expressed as a function of the radius of the measurement
point.
(such as boron with k00.8 or oxygen with k01) could
lead to better radial uniformity. In fact, in boron-doped
p �100� crystals, the radial variation of the resistiv­
ity is only a few percent (see Figure 3.7). On the other
hand, as shown in Figure 3.8, the oxygen concentration
typically decreases with r due to evaporation of oxygencontaining species from the melt, which leads to lower
concentrations at the melt surface and in the melt close
to the crystal edge than in the melt below the crystal
at r0, where the melt is more protected by the crys­
tal from oxygen evaporation. Evaporation may also
contribute to some extent to the radial resistivity vari­
ations for the dopants antimony, arsenic, or phospho­
rus in n� crystals. In n� crystals, the concentration
of antimony, arsenic, or phosphorus will decrease and
resistivity will increase significantly with increasing r
(see Figure 3.9).
Furthermore, �111� -oriented crystals often have
greater radial variation in the resistivity than correspond­
ing �100�-oriented crystals (see Figure 3.9). This dif­
ference is due to the formation of a planar {111} facet
in the center of the growth interface of the �111�
crystal during growing [20, 44, 45], as schematically
presented in Figure 3.10. The {111} facet region has
a larger effective distribution coefficient than the sur­
rounding interface (for impurities with k0 �1) because
of the fast lateral growth of atomic layers in the {111}
facet. This increase in the intake of the dopant leads
to a lower-resistivity region in the center of the crys­
tal and wafers. However, we should point out that the
facet is formed in the center of a �111� crystal only
if the isotherm of the melting point is convex toward
the melt in the center of the growth interface. The
facet, in such cases, is due to the difficult nucleation of
the close-packed {111} plane, which needs a consider­
able amount of undercooling to form [44, 45]. In other
45
Silicon as MEMS Material
PA R T I
0
1.3
Scaled resistivity
1.1
1.0
6 in. n+ (100) (As)
0.9
0.8
–30 –15
0
–75 –60 –45
6 in. n+ (111) (As)
6 in. n+ (111)
rescaled by 0.87
30
45
60
75
Crystal
a
b
Melt
Isotherm Facet
Fig 3.10 ● Formation of a {111} facet in the center of the meltcrystal interface in a �111� -oriented crystal. The facet is only
formed if the isotherm of the melting point (T � Tm) is convex in
the center region and the crystal orientation is �111� (see the
figure on the left). The facet results in a lower-resistivity region
(b) in the core of the crystal and wafers compared with the
surrounding “normal” area (a) as shown in the figure on the right.
cases, such as �111� crystals with a concave interface,
or �100� or �110� crystals with either a convex or a
concave interface, no facet is formed in the center and
the radial resistivity profiles remain practically inde­
pendent of the orientation. Figure 3.9 shows experi­
mental data on a 6 in. n� �111� crystal in which a
{111} facet has decreased the resistivity in the crystal
core due to an increase in the value of keff for arsenic by
a factor of more than 1.1 in the facet. This effect can
lead to considerable radial variation in the resistivity of
n� �111� crystals. Also, the resistivity profile of the
lightly doped 6 in. n �111� crystal in Figure 3.7 has
a contribution from a facet, which, in this case, has a
radius of 20 mm. Contrary to the case of dopants and
resistivity, a �111� facet has practically no effect on
oxygen concentration. Thus, in lightly doped crystals,
the radial oxygen variation is almost independent of the
crystal orientation, whether it is �100�, �111�, or
�110�, and also independent of the dopant.
46
–6
–8
–10
–12
–14
–16
65
70
75
Radial position (mm)
Fig 3.9 ● Resistivity profiles of As-doped 6 in. n� �100� and
�111� crystals, scaled by resistivity at r � 0. The difference
between the orientations is due to the {111} facet in �111�
orientation, more clearly seen after the curve for �111� is
rescaled by a factor of 0.87.
b
–4
–18
15
Radius (mm)
a
Oxygen gradient (%)
–2
1.2
Fig 3.11 ● Relative shift in Oi in the vicinity of the crystal edge
compared with Oi at r � 0. The results are for a 6 in. p � 100�
crystal with a diameter of 157 mm (radius � 78.5 mm) and
Oi(r � 0)13.6 ppma. Note that during further processing of the
crystal into wafers, the radius in excess of 75 mm is removed.
The actual results are indicated by symbols, while the dashed line
is only a guide for the eye.
The radial oxygen or resistivity variations in silicon
wafers are often described or specified by “gradient”
values, which are defined as the relative change in resis­
tivity or Oi from the center (r � 0) to a certain radius
value (r) closer to the edge, that is
Resistivity gradient (%) �
100 � [ρ(r) � ρ(center)]/ρ(center) (3.6a)
Oxygen gradient (%) �
100 � [Oi (r) � Oi (center)]/Oi (center) (3.6b)
For example, for oxygen gradient, the measurement
point r defined in wafer specifications is typically 10 mm
inward from the wafer edge. Thus, r � 65 or 90 mm
in the measurements for a wafer diameter of 150 or
200 mm, respectively (see SEMI MF951-0305 [46]).
The typical absolute value of the measured oxygen gra­
dient in lightly doped �100�, �111�, or �110� crys­
tals is about 5% or less for the standard measurement
position. (In n� crystals, the oxygen gradient values
are often much higher but are not routinely measured.)
In wafer specifications, the absolute values of the gra­
dients in Eqs 3.6a and 3.6b are typically limited to a
certain range. Further variations in resistivity and oxy­
gen take place even up to the crystal surface, as shown
for oxygen in Figure 3.11, where the relative shift in
Oi (i.e., the oxygen gradient) is indicated as a function
of r in Eq. 3.6b. In this particular case, the gradient for
r � 65 mm was 4%, but it increased considerably if
measured closer to the crystal edge. Oi at r 75 mm
was about 14% (or 2 ppma) below Oi at r � 0. The
region very close to the edge has the largest gradient
values but is also more difficult to measure accurately
Properties of Silicon Crystals
1200
Crystal temperature (°C)
and is not routinely studied. Also note that the excess
diameter of the crystal relative to the diameter specified for the wafer (i.e., some of the material with the
highest gradient) is removed by grinding, which slightly
improves the quality.
The radial variations in the resistivity and oxygen
are the ones most accurately controlled and specified
among the impurities. However, other impurity con­
centrations have radial dependence. For example, the
iron concentration may increase and, correspondingly,
the recombination lifetime in p-type crystal (Eq. 3.1)
decreases in the vicinity of the crystal surface, while the
core maintains a higher purity. This increased contamination has been found to originate from the diffusion of
iron from the furnace atmosphere directly into the hot
crystal surface during growth [47]. The surface region
influenced most has a depth in the order of 10 mm in
these cases.
CHAPTER 3
1000
Seed section
800
600
Tail section
400
0
2
4
6
8
10
Time after solidification (h)
3.6 Thermal Donors
Thermal donors (oxygen donors) are a class of sev­
eral species of electrically active oxygen complexes,
consisting of small aggregates of a few oxygen atoms
[48, 49]. Thermal donors are important defects as they
are quite common in CZ silicon and may have a harmful
and unpredictable/unstable effect on the resistivity and
even the conductivity type of lightly doped crystals and
wafers if the thermal donors are not properly taken into
account. The carrier concentration will be decreased
(increased) by the amount of electrons added by the
thermal donors (ΔnTD) in p-type (n-type) crystals,
leading to a corresponding increase (decrease) in the
resistivity. In extreme cases, if ΔnTD exceeds the initial
hole concentration of a p-type material, a change in the
conductivity type from p to n takes place, and the resis­
tivity becomes defined by the remaining electrons.
The most important thermal donors to be considered
in crystal growth are the species formed at relatively low
temperatures, at 300–500°C, especially around 450°C,
while the species formed at higher temperatures are less
important. The concentration of thermal donors depends
on the interstitial oxygen concentration Oi and the time
spent at the critical temperatures during cooling of the
crystal or during subsequent heat treatment of wafers
[48, 49]. The generation rate of thermal donors is highest
at 450°C, while already considerably lower at 400°C or
500°C, and is proportional to Oin where n 4 at 450°C
(i.e., the generation is relatively strongly depending on
the oxygen concentration). In FZ silicon, practically no
thermal donors are formed as Oi 0 ppma, while in CZ
silicon, the Oi level has an important effect on their forma­
tion rate. The donor concentration increases approximately
linearly with the time spent at the formation temperature,
Fig 3.12 ● Measured thermal history of a 6 in. �100� crystal.
Source: The curves are from [7], reproduced by permission of
ECS – The Electrochemical Society. Time of 0 corresponds to
the moment of solidification at the melting point.
although it may finally saturate and even start to decrease
after prolonged treatment [49]. According to Ref. [50],
the formation of thermal donors is enhanced (suppressed)
in heavily doped, p-type (n-type) silicon with a dopant
concentration �1016 cm�3. However, the intentional
dopant concentration in highly doped crystals typically
exceeds the thermal donor concentration considerably
and, thus, thermal donors have no detectable effect on the
resistivity of p� or n� crystals.
The crystal will always experience the 450°C region
during the growth process as the crystal cools from
the melting point of 1412°C toward room tempera­
ture. The temperature vs. time behavior during growth
(i.e., the thermal history) is a property of each particu­
lar CZ growth process. Figure 3.12 shows an example
of thermal history curves [7] where, as usual, the begin­
ning of the body has experienced a longer thermal his­
tory than the end part. According to a simple model, the
thermal donor concentration in the as-grown crystal is
approximately inversely proportional to the cooling rate
at 450°C. The critical temperatures 400–500°C are
also encountered during later processing of the wafer
and/or devices. In practice, the concentration of ther­
mal donors in the crystal after growing is often large
enough to have a detectable effect on the resistivity of
lightly doped p- or n-type wafers. The added electron
concentration ΔnTD may exceed 1015 cm�3 after crystal
growth at relatively high Oi’s, although ΔnTD is much
smaller for low Oi’s. The highest ΔnTD and the greatest
47
PA R T I
Silicon as MEMS Material
effect on the resistivity are typically found in the begin­
ning of the body, which has a longer thermal history
than the end part, although any axial variation in Oi also
contributes [7, 20].
Figure 3.13 shows an example of the resistivity behav­
ior of a p-type crystal in which the boron acceptors are
partially compensated by thermal donors after crys­
tal growth, after letting the crystal cool down to room
temperature. The beginning of the body of the as-grown
crystal, especially, is almost fully compensated and has a
high resistivity. An analysis of the resistivity shift shown
in Figure 3.13 leads to the following values of the added
electrons: ΔnTD2 � 1015 cm�3 in the beginning of
the body and ΔnTD5 � 1014 cm�3 in the end of the
body. The results suggest that for this crystal, the body
region at �600 mm has experienced a much longer
thermal history at the critical formation temperatures
compared with the region at �1200 mm, in agreement
with the expected differences in the thermal history
of the various crystal parts. A comparison of the value
ΔnTD1015 cm�3 and Oi15 ppma � 7.5 � 1017 cm�3
indicates that only a minor fraction of oxygen has
formed thermal donors, as expected.
To prevent the effects of thermal donors, it has been
a common practice to heat-treat lightly doped p- and
n-type wafers at about 650°C for at least some tens of
minutes during wafer fabrication [51]. The treatment at
�600°C will effectively eliminate the thermal donors as
indicated by the resistivity curves in Figure 3.13. Cooling
the wafers relatively quickly from 650°C through the
450°C region to room temperature after the “donorkilling” treatment leaves the thermal donors no time
Resistivity (ohm-cm)
1.E+03
Before donor killing
After donor killing
1.E+02
1.E+01
1.E+00
0
200 400 600 800 1000 1200 1400 1600 1800
Length position (mm)
Fig 3.13 ● Resistivity vs. length position in the body of a borondoped p-type crystal. The resistivity has been measured before
(upper curve) and after (lower curve) thermal treatment (“donor
killing”) of the samples at 650°C, eliminating the thermal
donors. The effect of thermal donors is greatest in the beginning
of the body. The interstitial oxygen concentration of the crystal
is about 15 ppma in new ASTM units. (The lines connecting the
points are only guides for the eye.)
48
to reform, and the subsequent resistivity values and con­
ductivity type will be defined by the “stable”, intentional
dopant element boron or phosphorus only. In principle,
thermal donors may also be formed or eliminated, even
multiple times, during any subsequent wafer or device
processing step at 450°C or �600°C, respectively. In
extreme cases, the thermal donors existing after finish­
ing the processing may cause quality problems or failure
of the devices if the remaining resistivity shift is large
enough to harm the device properties. For example,
the threshold voltage of metal-oxide-semiconductor
field-effect transistors, processed on lightly doped sub­
strates, can shift due to thermal donors [52]. Note also
that Oi in the wafer may decrease from its initial, crys­
tal-originated value during device processing as a result
of oxygen out-diffusion (typically due to denuded zone
formation) or precipitation [51, 53], or Oi may possi­
bly increase because of oxygen in-diffusion [54]. These
changes in Oi have an effect on subsequent thermal
donor formation in the regions of the wafer where Oi
has shifted (i.e., close to the surface for out-diffusion
and in the bulk for precipitation) [51, 53].
3.7 Defects in Silicon Crystals
A large variety of grown-in and process-induced defects
have been identified in CZ silicon crystals and wafers
(see, e.g., Refs [2, 8, 20, 55]). Some of the defects are
directly connected to the success or failure of the crys­
tal growth process or defined by the growth parameters,
while other defects are contributed or dominated by the
following process steps from crystals into wafers and,
finally, into devices. Also the ease of detection of the
defects varies from simple visual inspection of crystals
to more difficult or indirect methods. Crystal defects
can also be classified also according to their dimension­
ality into point defects, line defects, area defects, and
volume defects (see Chapter 1).
We will concentrate on those defects that can have a
direct connection to the crystal growth and its process
parameters, defects that are important considering the
intended use of the wafers, and are, in many cases, also
measured regularly. Such defects include (slip) disloca­
tions, twins, bubble inclusions, vacancies and their aggre­
gates (octahedral microscopic voids that can be detected,
e.g., as crystal-originated particles (COPs), on the wafer
surface), self-interstitials and their aggregates (large dis­
location loops), stacking faults (SFs) formed near the
wafer surface by oxidation treatments (i.e., oxidationinduced stacking faults [OISFs]), oxygen precipitates,
bulk SFs, and dislocation loops. Among these defects,
SFs and dislocation loops are often caused by oxygen
precipitates (see Chapters 4 and 21). Some of the typi­
cal defects found in crystals and wafers have a strong
Properties of Silicon Crystals
Temperature (°C)
correlation to the thermal history of the crystal during
its growth (see Figure 3.14 where the dominating for­
mation temperatures of defects [8, 28, 49, 55–59] are
approximately indicated).
The effect of the defects on the properties and yield
of devices processed on the wafers are characteristic to
each particular process and application, although certain
general trends and risks can be indicated. The defects
may lead to failure or decrease the quality of devices
or, more specifically, to a decrease of carrier lifetimes
(e.g., metal or oxygen precipitates), an increase of leak­
age currents in devices (e.g., metal precipitates, dislo­
cations, or SFs), or quality problems with gate oxides
(e.g., voids or other defects such as metal precipitates
near the wafer surface) [2, 14, 15, 18, 60]. Decoration
of dislocations or SFs by metal impurities may further
increase the detrimental influence of these defects on
the junctions of the devices. Considering MEMS fab­
rication, defects such as oxygen precipitates and SFs
may increase the surface roughness and decrease
the anisotropy in anisotropic wet etching [61, 62].
Therefore, in MEMS wafers, the highest oxygen concen­
trations are avoided to suppress the formation of oxygen
precipitates and associated defects, especially if wet
etching is used to form the structures for the sensors.
Furthermore, considering optimized crystal properties
and the control of defects, special wafers (e.g., siliconon-insulator (SOI) [see Chapter 7]) often have slightly
different requirements and quality risks compared with
the more ordinary wafers.
Short descriptions of the typical defects in CZ silicon
are given from the point of view of crystal growth in
the list below, while we refer to the literature for more
detailed information.
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
Vacancies, self-interstitials, OISF ring radius
(1412°C)
Voids (vacancy clusters) (1000…1150°C)
Dislocation loops (self-interstitial clusters)
(1000°C)
Nuclei for oxygen precipitation
(500…800°C)
Thermal (oxygen) donors
(450°C)
0
1
2
3
4
5
6
7
8
9 10 11 12 13
Time from solidification (h)
Fig 3.14 ● Thermal history of a crystal (the timescale starting
from the moment of crystallization) and the formation
temperatures of various defects during crystal growth. The
formation temperatures indicated are approximate consensus
values collected from the literature. ( The thermal history curve is
only schematic.)
CHAPTER 3
Dislocations and slips: The dislocations are line
defects, which in silicon lie on the {111} slip planes. The
word “slip” is used to denote the formation and propa­
gation mechanism of dislocations, as well as the visually
detectable lines formed on crystal or wafer surfaces by
a large number of dislocations. The CZ single crystals
are grown as dislocation-free, although, sometimes, due
to a disturbance at the melt-crystal interface and/or high
thermal stress in the crystal, dislocations may appear,
multiply, and propagate in the crystal during growth.
The crystal after this point soon becomes multicrystalline
[20, 63]. Dislocations are also spread backwards to the
already-formed crystal within a characteristic distance
of the same order of magnitude as the crystal diameter,
while the even earlier region still remains dislocation-free.
(In some rare, exceptional cases of highly boron-doped
p� crystals, dislocations have been found to propagate
along the body without causing polycrystallization [64],
contrary to the general behavior.) Dislocations in wafers
could have a negative impact on the device yield, and
wafers with dislocations already in the beginning also suf­
fer from further dislocation generation more easily than
dislocation-free wafers. Therefore, the dislocated, as well
as the even worse, multicrystalline parts of the crystal
are rejected from further processing into wafers, which
correspondingly decreases the crystal yield. Fortunately,
most of the crystals are dislocation-free through the
whole body. Furthermore, it is relatively easy to detect
the position where the dislocations first appeared dur­
ing growth as the crystal shape changes, especially as its
characteristic growth lines are cut and disappear starting
from the position where the dislocations appeared [63].
The reason for this external shape change is that the dis­
locations decrease orientation-dependent differences in
the growth at the growth interface [44]. More specifi­
cally, small {111} side facets at the edge of the interface,
responsible for growth-line formation, shrink and, finally,
disappear due to dislocations, which also ends the growth
lines. Visual inspection of the crystal, especially the con­
tinuity of the growth lines and the existence of slip lines
on the surface, is among the basic quality control meth­
ods used for material quality verification.
Although only dislocation-free material is processed
into wafers, which are, thus, initially dislocation-free,
the strength of the wafers against the slip formation and
plastic deformation in later high-temperature process­
ing is increased by interstitial oxygen, while formation
of large oxygen precipitates exposes the wafers to slip
generation [8, 65]. The risk of such plastic deformation
can be reduced by selecting the target of Oi properly
(although other requirements for oxygen also have to be
taken into account) and by keeping the axial and radial
variations of Oi within reasonably tight limits. In addi­
tion to oxygen, dopants at high concentrations have an
impact on dislocation generation. According to Ref. [5],
49
PA R T I
Silicon as MEMS Material
concentration of boron, phosphorus, or arsenic in excess
of 1019 cm�3 (resistivity in the sub 10-mohm-cm region)
increases the critical stress for dislocation generation.
Twins: A twin in silicon crystal corresponds to a
defect where the lattice is changed to its mirror image on
the other side of a {111} plane, called a “twinning plane”
[66]. In �100� and �111� crystals, the vector perpen­
dicular to the twinning plane is inclined with the growth
axis by an angle of about 54.7° or 70.5°, respectively,
while in �110� crystal, the angle is either 35.3° or
90.0°, the latter case corresponding to a twinning plane
parallel to the crystal axis. Twins may be found after the
CZ silicon crystal has lost its single-crystalline structure
and is becoming multicrystalline. They are also some­
times seen even without the loss of structure, although
quite rarely. The twins are not allowed in wafers because
the twin boundary and the shift of the crystal orientation
would probably lead to failure of devices. Thus, the unfit
region, where the twinning plane penetrates the crystal,
is rejected as well as any misoriented material.
Bubble inclusions: Relatively large, approximately
spherical pits, with sizes up to several millimeters, are
occasionally seen on wafer surfaces. These pits originate
from small volumes of gas (e.g., argon) remaining as
bubbles in the melt after melting [2]. Also, gases in sil­
ica crucibles [67] or gases originating from post-melting
doping or silicon feeding procedures [68] can sometimes
contribute to the pocket formation. Some of the bubbles
may remain in the melt, possibly at the melt-crucible
interface, for quite a long time and finally become trans­
ported with the melt flow to the melt-crystal interface
where the silicon solidifies around the bubble, causing
a void. Wafer slicing, lapping, grinding, etching, or pol­
ishing may reveal the in-grown bubbles as air pockets
on the wafer surface or as holes through the wafer, the
latter case being shown in Figure 3.15. Fortunately, the
incidence of bubbles in wafers can be kept at a very low
level by using suitable crystal-growing and wafer-inspec­
tion procedures, and bubble inclusions are typically not
a major quality issue. The rare wafers with large open
pockets of 1 mm are relatively easily detected and
identified by the eye and are rejected in wafer fabrica­
tion, while much smaller pockets may contribute to
the defect count in the final surface inspection [69].
However, hidden voids in the bulk of the wafers pass
the tests and may sometimes cause local yield losses in
device processing, especially if the bubble becomes open
after removal of material from the wafer surface.
Vacancies and self-interstitials and their clusters:
The vacancy- and self-interstitial-related defects have a
strong connection to the process conditions used during
crystal growth [55, 57, 58, 60, 70] and will be discussed
in more detail in Section 3.8 below.
OISFs: The OISFs are generated by silicon self­
interstitials injected into the wafer during oxidation of
50
Fig 3.15 ● Photograph of a 6 in. wafer rejected after slicing due to
a large bubble inclusion.
the wafer surface. An OISF test, either a standard one
(e.g., SEMI MF1727-0304 [71], SEMI MF1810-0304
[72]) or a test representative of the oxidation cycles in
a particular fabrication process, is used to determine a
well-defined value for the OISF concentration of the
sample wafers. The result has correlation with the
tendency of the wafers to form OISFs during oxida­
tion steps during actual device processing. Figure 3.16a
shows an example of OISFs revealed on the surface of
a phosphorus-doped n �100� wafer. The OISFs are
formed as the injected self-interstitials agglomerate into
SFs of an extrinsic type between two adjacent {111}
planes, the defects being bound by Frank partial dis­
location loops [2, 20]. The defects in Figure 3.16 can
be seen in positions where SFs intersect the wafer sur­
face. The lines of the defects on the surface of �100�
wafers have two possible directions, which have an
angle of 90° between each other, while OISFs in other
wafer orientations have their characteristic angles. The
OISFs preferably nucleate at defects such as metal pre­
cipitates, mechanical defects or damage, or oxygen pre­
cipitates if these exist in the wafer [2], and the OISF
density may reflect the quality of the crystal, as well
as the effects of further processing steps prior to the
OISF test.
It is quite common for the users of the wafers to spec­
ify the upper limit for the OISF density of the wafers
(e.g., 100 OISFs per cm2). The actual concentration of
OISFs in boron-doped p �100� wafers is typically on
the order of 1 cm�2 after a standard OISF test, while
slightly higher values are often found in phosphorus-doped
n �100� wafers, especially in those taken from the
region close to the tail of the crystal. On the other hand,
Properties of Silicon Crystals
Fig 3.16 ● (a) Oxidation-induced stacking faults (OISF) on the
surface of a lightly phosphorus-doped n �100� wafer. The
defects were relatively uniformly distributed over the surface.
(b) Example of OISFs in an OISF ring of a highly boron-doped
p� �100� wafer. Here, OISFs were concentrated in the narrow
ring, while the rest of the area was practically free of OISFs. The
figure is taken from the ring region.
the OISF concentrations in n� crystals doped with anti­
mony, arsenic, or phosphorus are low. The reason for the
higher OISF density in lightly phosphorus-doped, n-type
material is still unclear to a certain degree, but the incre­
ment seems to be contributed, for example, by the ther­
mal history of the end part of the crystal. Furthermore,
impurities may play a role here and the addition of
copper into the melt has been found to increase, and
aluminum to decrease, the OISF density in phosphorusdoped, n-type crystals [73]. High OISF concentrations
are sometimes seen in highly boron-doped p� �100�
wafers, resulting from the enhanced oxygen precipitation
in the bulk due to high boron concentration. The strong
precipitation induces and favors SF formation over the
whole thickness of the p� wafer [8, 74], although the
result is expected to be sensitive to the resistivity, oxygen
CHAPTER 3
concentration, length position in the crystal, and the cor­
responding thermal history. Additional heat treatments of
the wafers prior to their oxidation may also increase the
risk of high OISF density if the wafers have a tendency to
form OISFs. In �111� -oriented wafers, the OISF con­
centrations are typically low and lower than in �100�
wafers with the same doping level and dopant.
The OISFs can either be distributed relatively
evenly over the wafer surface or the distribution may,
for example, reflect the location of mechanical defects
or contamination if such exist. Furthermore, in some
cases, a dense “ring” of OISFs is formed, resulting from
a certain distribution of interstitials and vacancies, and
is controlled by the crystal-growing process conditions
[55, 58, 60]. The circular shape and the narrow width
of only a few millimeters of the OISF ring allow the
distinguishing of the OISF ring from OISFs of other
origins. Figure 3.16b shows a microscope picture taken
from the ring region of an OISF ring. The origin of the
ring will be discussed in more detail in Section 3.8.
Oxygen precipitates: The formation and properties
of oxygen precipitates and their useful and harmful influ­
ences [6, 8, 9, 14, 65] are central items, which will be
discussed in more detail in Chapter 4. Oxygen precipi­
tates are typical sources and nucleation sites of SFs and
dislocation loops in the bulk and, sometimes, in the sur­
face region of the wafers; they also have an effect on the
mechanical strength of wafers. The precipitation of oxygen
is enhanced in boron-doped p� wafers and it is retarded
in Sb-doped n� wafers [8, 37, 75, 76], while precipitation
behavior is independent of the dopant type and concen­
tration at lower dopant concentrations of �5 � 1016 cm�3
[75]. The effect of high concentrations of boron or anti­
mony seems to be valid even for samples that have similar
initial oxygen concentrations as the lightly doped refer­
ence wafers have, although the differences in the oxygen
concentrations between these products often contribute
considerably to the precipitation behavior seen in prac­
tice. Also, for n� doped with arsenic or phosphorus, the
precipitation is typically retarded [77]. The precipitation
in p� wafers, although enhanced in principle, has also
been found to have a dependence on resistivity (boron
concentration), among other factors. Ref. [35] suggests a
considerable reduction of oxide precipitate density in p�
for resistivity below a threshold of 7 mohm-cm compared
with resistivities slightly above this threshold. However,
the exact behavior of p� can be quite sensitive to detailed
material and process parameters [78].
3.8 Control of Vacancies,
Interstitials, and the OISF Ring
The growth parameters and conditions of the crys­
tal, especially the growth rate, and doping influence
51
PA R T I
Silicon as MEMS Material
the amount of vacancies, self-interstitials, and related
defects in the resulting crystal [60, 70, 79–81]. A CZ
crystal grown at a high growth rate is known to con­
tain defects called voids, originating from vacancy clus­
tering, revealed as COPs, D defects, or flow-pattern
defects (FPDs), while at low growth rate, silicon self­
interstitials form clusters revealed as (large) dislocation
loops or A defects [60, 80]. An intermediate growth
rate would result in a ring-like OISF region and voids
only inside the ring, while the outside region is practi­
cally void-free, but may contain dislocation loops. The
effect of the voids, dislocation loops, and/or OISF ring
on the quality and yield of devices depends on the
detailed case (exact device structure and its process)
and the properties of the defects (e.g., the size distribu­
tion and density of the voids or dislocation loops). Voids
are known to deteriorate the quality of gate oxides [60,
82], while dislocation loops are a potential risk for the
yield of certain devices (e.g., Refs. [83]).
The theoretical models of the incorporation of vacan­
cies and silicon interstitials into crystals and the formation
of the corresponding defects have been discussed in more
detail in review articles such as [55] and [58], so we will
not go into the details of the theory or modeling of the
defects. Our presentation below is based on the litera­
ture, as well as our own experience, and will focus on the
results that have the greatest importance in practice for
understanding the main connections between the crys­
tal-growing process and crystal quality in order to guaran­
tee the high quality of the crystal and wafers. The focus
is on the CZ crystals, especially on lightly boron-doped
p �100� crystals because these are the standard prod­
uct most frequently discussed in the literature, although
relatively similar defects have also been detected in other
dopant-orientation combinations [84], as well as in the FZ
crystals (see Ref. [60] and references therein).
One of the main conclusions of the models and exper­
iments is that the growth rates (v) of the CZ crystal
and the vertical temperature gradient (G) of the crystal
in the vicinity of the solid-melt interface, or, more spe­
cifically, the ratio v/G, already very accurately predicts
whether the resulting crystal at the corresponding length
position becomes vacancy-rich (for v/G � Ccrit) or self­
interstitial-rich (for v/G � Ccrit) [55, 70]). The critical
v/G ratio, Ccrit, has been suggested to have a value of
about 0.0012–0.0013 cm2/K-min in lightly doped crystals
[58, 81]. While either vacancies or self-interstitials domi­
nate depending on the value of v/G, the concentration
of the other minority species becomes negligible due to
mutual annihilation of vacancies and self-interstitials. The
simple criteria based on the v/G ratio is, according to the
literature, due to the larger equilibrium concentration
of vacancies at the solid-melt interface at the melting
point (compared with that of self-interstitials), favoring
vacancies because of the convection by crystal movement
52
during pulling, while, on the other hand, interstitials have
a higher diffusivity, favoring a flux of interstitials from the
interface into the crystal. The growth rate (which to rea­
sonable approximation equals the pulling rate of the crys­
tal during the particular length position in the body) and
G influence these transport processes and the remaining
concentration of the point defects. Also, the dopants and
impurities influence the balance between vacancies and
self-interstitials [78, 79, 81, 85]. For example, in highly
boron-doped p� crystals, the critical value Ccrit of the
v/G criteria will increase considerably with increasing
boron concentration [81].
The point defect species dominating after the annihi­
lation process becomes increasingly supersaturated as the
crystal temperature decreases, which finally leads to the
formation of larger aggregates—voids in vacancy-rich and
dislocation loops in self-interstitial-rich crystals, respec­
tively. The vacancy-rich crystals are more common of
these two among commercial products [55]. The voids
typically have a small size of 0.1 μm and their concen­
tration in standard vacancy-rich material is in the order
of 1 � 106 cm�3 (e.g., Ref. [86]) and typically about 100
COPs (small pits detected as particles), with sizes above
the detection limit of 0.10 μm are detected on the pol­
ished 6 in. wafer front surface. In interstitial-rich wafers,
however, only a few particles, which are possibly COPs,
are detected on the 6 in. wafer surface. The voids are
formed during crystal growing at around 1150–1000°C
where aggregation of supersaturated vacancies takes
place and void-size distribution is formed [56, 57] (see
Figure 3.14). The dislocation loops in self-interstitial­
rich material are much larger, 1–100 μm, compared
with voids; have a lower concentration, 104 cm�3; and
are formed at 1000°C [56, 79, 80, 87].
In the actual crystal-growing processes, the value
of the axial temperature gradient G is not constant,
but typically increases (and v/G decreases) with r (see
Figure 3.17). In practice, v is controlled by the pull­
ing rate of the crystal, while G(r) is largely defined
by the hot-zone design, although it is also affected to
some extent by various growth parameters, including
the pulling rate. Curve A in Figure 3.17 corresponds
to vacancy-rich and D to interstitial-rich cases, respec­
tively, while curve C is approximately in the boundary
and could basically lead to only relatively few vacancyor self-interstitial-related microdefects [56, 70, 83].
If v/G reaches the critical value at certain r, vacancyrich and self-interstitial-rich regions are formed at
different radial regions (see curve B in Figure 3.17).
However, in the “mixed-quality” crystals, an OISF
ring is typically formed close to the boundary, although
slightly toward the vacancy-rich side, at r, where v/G
is slightly above Ccrit. The combination of experiments
and modeling of G has indicated a critical value of
Ccrit,OISF0.00134 cm2/K-min for this v/G ratio where
Properties of Silicon Crystals
0.0025
A
v/G (cm2/ K min)
0.0020
B
OISF ring
0.0015
C
Critical v/G for OISF ring
0.0010
D
Critical v/G for v-i boundary
v-i boundary
0.0005
0.0000
0
10
20
30
40
50
60
70
80
Radius (mm)
Fig 3.17 ● Simulated v/G vs. r profiles for 6 in. crystals with
various thermal environments and pulling rates (cases denoted
by solid lines A through D). The approximate critical v/G values,
denoted by dashed lines, are from [58] and [81], and can be
used to estimate the radial position of the interface between the
vacancy-rich and self-interstitial-rich regions (v–i boundary) (lower
dashed line) and the OISF ring location (upper dashed line),
respectively. The arrows indicate the radial positions of the v–i
boundary and OISF ring for the growth process of curve B.
CHAPTER 3
wafers have so far not caused significant quality prob­
lems in the majority of cases. On the other hand, largediameter wafers used, for example, for dynamic random
access memory (DRAM) fabrication, can have tighter
requirements with regard to voids [82, 89] and, there­
fore, in these cases, controlling the void distribution
by using an optimized crystal-growing process and/or
additional wafer treatments becomes quite important.
Furthermore, in actual crystal production, other quality
aspects, discussed earlier in this review, as well as crystal
yield and the total production cost of crystal and wafers,
have to be taken into account in addition to vacancies,
self-interstitials, and the OISF ring when optimizing
the process conditions. For example, very low pulling
rates lead to lower productivity of crystal growing and
may also increase the risk of losing the single-crystalline
structure, which are factors that increase the production
cost of lightly doped, interstitial-rich material compared
with that of vacancy-rich silicon.
3.9 Conclusion
the OISF ring appears in lightly doped crystals [81].
The OISF ring shows a highly increased tendency to
form OISFs in densities of 1000 cm�2 in the ring in
�100� wafers, while few OISFs are found elsewhere.
The OISF ring is typically quite narrow, a few millim­
eters at most. For example, the v/G profile denoted by
B in Figure 3.17 is expected to result in wafers with an
OISF ring having a radius of 66 mm. The ring origi­
nates from stable nuclei for oxygen precipitates in the
ring region, formed already during crystal growing. Due
to these defects, the OISF ring region already shows
a reduced recombination lifetime in samples taken
directly from the as-grown crystal, without any oxida­
tion treatments [88]. An example of lifetime deteriora­
tion at the OISF ring position of an as-grown crystal is
shown in Figure 3.18, although this measurement tech­
nique exaggerates the width of the ring.
The OISF ring, voids, and dislocation loops may cause
yield losses of the devices processed on the wafers. It
is possible to totally avoid the formation of the OISF
ring, if necessary or practical, by using suitable proc­
ess parameters in crystal growing [60, 80] to fulfill the
quality requirements defined in the specification and
necessary for the intended use of wafers. The commer­
cial lightly doped CZ crystals have typically been grown
in the vacancy-rich region without an OISF ring, while
there has been more variation in the quality of com­
mercial highly boron-doped p� crystals. Formation and
properties of thermally induced defects in p� wafers
with or without an OISF ring has been studied in more
detail in [74] and [78]. In small-diameter wafers or in
MEMS applications, the voids of vacancy-rich standard
We have covered the major properties of CZ silicon
crystals in this chapter. The focus has been on those
impurities and defects that have the greatest effect on
device performance and/or that have proven to be of
the greatest importance and interest in the industrial
development of the crystal growth process and crys­
tal quality. By understanding the crystal properties and
their connection to the growth process, as well as the
inherent limitations of the CZ silicon crystals, it is pos­
sible to better specify the crystal properties needed and
to improve the growth process, as well as the resulting
material quality. Improved or more suitable material
increases the yield of devices processed on the wafers.
The proper CZ silicon used for wafer fabrication is
always dislocation-free, contains only relatively insignifi­
cant concentrations of harmful impurities such as carbon
and transition metals, has a reasonably controlled or pre­
dictable defect formation behavior, and its resistivity and
oxygen concentrations are suitable for the intended appli­
cation. Typical high-quality CZ material has such a low
carbon concentration that it has almost no effect on oxy­
gen precipitation behavior and, similarly, also the amount
of various harmful transition-metal impurities (e.g., iron)
in the as-grown crystal is typically clearly within accept­
able limits. Furthermore, the radial and axial uniformity
of the properties is important and has been discussed in
this review. The radial variation of oxygen and resistiv­
ity depends on the dopant, resistivity level, and/or crys­
tal orientation, although other process parameters also
influence the result. In practice, various applications can
have quite different requirements for the crystal and
53
PA R T I
Silicon as MEMS Material
Fig 3.18 ● Map of the recombination lifetime of an 8 in. p �100� wafer, measured by using the microwave photoconductance decay (μ­
PCD) method. The wafer has a lower lifetime region at a radius of 40 mm, which corresponds to the radius where an OISF ring would
be formed in an OISF test.
the optimization of certain product-specific properties
may be of major concern and challenge. For example, in
MEMS wafers, the highest oxygen concentrations are typ­
ically avoided to keep the bulk defect-free and to make
sure that the structures, formed by etching, are of high
quality. On the other hand, some other applications may
benefit from relatively high oxygen concentration, mainly
if strong metal impurity gettering by oxygen precipitates
is needed during device processing. Furthermore, the
cost of the material is a relevant issue and should be min­
imized without compromising the quality. For example,
an unnecessarily narrow resistivity specification leads to
a lower commercial crystal yield and, thus, may increase
the cost per wafer unless the rejected material has some
other commercial use.
The customers’ requirements for the impurities and
defects of the crystals and wafers are expected to con­
tinue to develop in the future as the processed device
structures and their complexity, structural dimensions,
and processing methods, as well as targets for device per­
formance, yield, and total cost evolve. The major chal­
lenge for crystal growth is to answer these expectations.
Acknowledgments
Colleagues at Okmetic Oyj, especially the present and
former members of the crystal growth R&D group and
the laboratory staff, are gratefully acknowledged for their
long-term cooperation and contributions to this work.
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57
4
Chapter Four
Oxygen in Silicon
Eero Haimi
Department of Materials Science and Engineering, Helsinki University of Technology,
Espoo, Finland
Single crystal (SC) silicon is one of the chemically purest
technical materials used in large quantities. However, in
spite of the high purity, there are still trace levels of other
elements present in SC silicon. A common additional
element, besides doping elements, is oxygen.
Oxygen is incorporated to SC silicon during crystal
growth. In this respect, there is a fundamental difference
between Czochralski (CZ) and float zone (FZ) crystals.
Oxygen is accumulating to CZ silicon, because molten
silicon dissolves oxygen from silica crucibles used in the
growth process. If it is necessary, reduction of inherent
oxygen concentration is possible by using magnetic CZ
process. FZ silicon appears in lower oxygen concentra­
tion, since crucibles are not needed in FZ process. In FZ
silicon only residual background concentration of oxygen,
due to affinity of oxygen for silicon, is observed.
Oxygen and oxygen-related phenomena affect the
properties of silicon in several ways. From a technologi­
cal viewpoint, oxygen in silicon can be either beneficial
or harmful depending on application. Oxygen can pro­
vide strengthening of wafer against plastic deformation
during processing. Furthermore, oxygen precipitates
can act as traps for fast diffusing metallic contaminants.
Without this “gettering effect,” degradation of IC fabri­
cation yield may take place. On the other hand, oxygen
precipitates and oxygen-related thermal donors (TDs)
may act as defects and may impair processing or device
performance when present at unintended locations.
In the following, basic aspects of oxygen-related
phenomena in silicon, such as oxygen in silicon solid
solution, formation of small oxygen aggregates, oxygen
precipitation, precipitation induced defects as well as
behavior of oxygen in basic heat treatment procedures,
have been overviewed.
4.1 Oxygen in Solid Solution
Oxygen in silicon solid solution is placed interstitially in
the lattice. Equilibrium oxygen solubility has been studied
with various techniques including IR spectroscopy,
gas fusion analysis, secondary mass ion spectroscopy,
charged particle activation analysis, and x-ray diffrac­
tion. Generally results scatter to some extent. A fit of
experimental results gathered from several groups is
given by Mikkelsen [1] in the form of Eq. 4.1:
⎛�1.152eV ⎞⎟
eq
3
Cox
� 9�1022 exp ⎜⎜
⎟⎟ [atoms�cm ] (4.1)
⎜⎝
⎠
kT
Corresponding partial phase diagram of the Si–O
system, which shows boundary between the solid solu­
tion of silicon and the two phase region of silicon and
silica, as a function temperature and oxygen concentra­
tion, is presented in Figure 4.1.
The equilibrium solubility of oxygen in silicon at
room temperature is smaller by several orders of
magnitude than near the melting temperature. In practice,
this means that as-grown CZ silicon is supersaturated
with oxygen after cooling to room temperature due to
slowness of out-diffusion in solid state. Typical oxy­
gen concentration of CZ silicon wafers range from
below 5 � 1017 atoms/cm3 (low) to 5–10 � 1017
atoms/cm3 (medium) to above 1018 atoms/cm3 (high)
(5 � 1016/cm3 � 1 ppma).
Diffusivity of oxygen is dominated by the proc­
ess of jumping from one interstitial site to another.
Experimental oxygen diffusion data in high temperature
range (700–1200°C) is well established. Fitted results
59
PA R T I
Silicon as MEMS Material
n � number of moles
k � Boltzmann constant
T � absolute temperature
Figure 4.1 ● Partial phase diagram of the Si–O system.
of diffusion constant [1] from several experiments can
be expressed as:
⎛ 2.53eV ⎞⎟
2
Dox � 0.13 exp ⎜⎜−
⎟[cm �s]
⎜⎝
kT ⎠⎟
(4.2)
It has been shown that oxygen diffusivity in high
temperature range does not depend much on wafer
orientation, annealing ambient, doping concentrations,
nor pulling technique of crystal [2]. Low temperature
diffusion data are not so well established. The phenom­
enon of enhanced oxygen diffusivity has been observed
frequently and attributed to different causes such as
thermal history, presence of metallic contamination
and interactions with carbon or hydrogen (for details
see Ref. [2]).
4.3 Precipitation of Oxygen
4.2 Formation of Small Oxygen
Aggregates
Supersaturation of oxygen in silicon solid solution
creates a driving force for oxygen aggregation. It can
be shown according to standard thermodynamics (for
derivation, see for example Ref. [3]) that corresponding
chemical driving force, ΔGchem, as a function of oxygen
supersaturation can be approximated as:
eq
�Gchem � nRT In(Cox �Cox
),
where:
Cox � concentration of oxygen
Ceq
ox � equilibrium concentration of oxygen
60
Conceptually, the first stage of oxygen aggregation
is the formation of O2 dimers from essentially isolated
oxygen atoms by diffusion process. The possible role
of such constituents as vacancies or carbon in the free
energy of dimer formation is under scientific discussion.
Aggregation of larger oxygen clusters than dimers is
frequently considered to continue also with atom by
atom process, although some evidence exists that oxygen
dimers may also be mobile.
Formation of small oxygen aggregates has gener­
ally raised interest in two contexts. In its usual inter­
stitial configuration, oxygen is electrically inactive
in silicon lattice. However, annealing of oxygen-rich
silicon (1018 atoms/cm3) in the temperature range
350–500°C, several types of electrically active centers
called thermal donors are formed. Furthermore, for­
mation of so-called new donors has been observed at
higher temperatures. TDs have been attributed to the
growth of small oxygen aggregates as already discussed
in Section 3.6. Another area of interest regarding small
oxygen aggregates is nucleation of precipitates. There
has been discussion about relationship between pre­
cipitate nuclei and especially new donors. However,
much of nucleation studies do not deal with such issues
as detailed structure of the small oxygen aggregate or
exact mechanism of their formation process. Instead,
the emphasis is placed on the later observed precipita­
tion behavior. In the present text the same approach is
followed. Nucleation is discussed further together with
precipitation phenomena in the next chapter.
(4.3)
Precipitation of oxygen in silicon is a diffusion control­
led solid state phase transformation. In the transforma­
tion silicon oxide is formed. Formation of silicon oxide
within silicon lattice requires that oxygen must diffuse
together to form a small volume with correct composi­
tion, and the atoms must rearrange into correct crystal
structure; i.e., both kinetic and thermodynamic require­
ments must be fulfilled.
According to the mass balance, the reaction equation
of oxygen precipitation in silicon reads:
Si + xOi ↔ SiOx
(4.4)
Accurate chemical composition of oxygen precipitates
in silicon has been under scientific debate. It is generally
Oxygen in Silicon
agreed that in SiOx the x is less than 2. The specific
volume of the oxide is about twice as large as that of
silicon. Therefore, the oxide precipitates are originally
strongly strained. It has been proposed that stress accu­
mulation during precipitation is relieved at least par­
tially by ejection of self-interstitials. Consequently, if
conservation of mass and volume in addition to point
defect balance is included, the reaction Eq. 4.4 is modi­
fied to [4]:
aSi + bxOi ↔ bSiO x + (a − b)Sii
ΔG
~4πγ r2
r
r*
(4.5)
In principle, precipitation of a second phase takes
place in three steps: a local fluctuation in chemical
potential (embryo), formation of a stable nucleus, and
precipitate growth. Proposed theories of nucleation of
silicon oxide involve both homogeneous and hetero­
geneous mechanisms and several propositions for the
nuclei structure exist. Regardless of the exact char­
acteristics of the nucleus, some basic thermodynamic
concepts can clarify the nucleation process. The driving
force of the phase transformation is supersaturation of
oxygen, whereas surface energy and strain energy are
setting constraining contributions. Consequently, free
energy change of the phase transformation ΔG can be
expressed as:
ΔG � −V Δg chem + ∑ Ai γ i + V Δg el
(4.6)
ΔG
~ –(4/3)π(Δgchem–Δgel)r3
Figure 4.2 ● Free energy changes expressed as a function of
nucleus radii.
fact a similar type of equation would be obtained for any
nucleus shape as a function of its size. Accordingly, the
important concept of critical size of nucleus is introduced;
if the precipitate is too small it is not thermodynamically
stable. Figure 4.2 illustrates graphically free energy changes
expressed in Eq. 4.7 as a function of nucleus radii.
Critical radius r* of a thermodynamically stable
nucleus is obtained by differentiation of Eq. 4.7, which
yields:
r* =
where:
Δgchem � chemical free energy change per volume
2γ
(�g chem − �g el )
(4.8)
By substituting Eq. 4.8 to Eq. 4.7, the activation energy
barrier against nucleation ΔG* can be expressed as:
Δgel � elastic free energy change per volume
γi � interface surface energy components
V � volume of the precipitate
�G* =
Ai � interface surface area components
In oxygen precipitation, an aggregate of oxygen atoms
constituting a nucleus is formed first. Once formed, the
nuclei can either grow further and form oxide precipi­
tates or dissolve. This can be elaborated on by looking
at the terms in Eq. 4.6 separately. Contributions of sur­
face energy and strain energy oppose the transforma­
tion. However, the separate contributions have different
dependency on the nucleus size. If we ignore the varia­
tion of γ with interface orientation and assume that the
nucleus is spherical with a radius r, Eq. 4.6 becomes
4
�G = − πr 3(�g chem − �g el ) + 4πr 2 γ
3
CHAPTER 4
(4.7)
This is a function of r that first increases up to an acti­
vation energy barrier maximum and then decreases. In
16πγ3
3(�g chem − �g el )2
(4.9)
For critical radius of nuclei in the case of strain free
nucleation (Δgel � 0), manipulation of Eqs 4.8 and 4.3
8.3 yields:
r* =
2γv p
eq
)
kTIn(Cox / Cox
(4.10)
where:
vp � the volume of precipitate per oxygen atom in it.
Importantly, Eq. 4.10 shows that the critical size of
nucleus increases with increasing temperature (because
eq
of temperature dependency of Cox
).
More comprehensive theoretical treatment of critical
radius of nucleus takes into consideration also stressrelieving mechanisms with corresponding crystal defect
61
Silicon as MEMS Material
PA R T I
interactions. Hence, an equation for r* can be written in
the following form [5]:
r* =
r*
2γ
(1 + δ − ε)
ε )3 XkT
eq
In (Cox / Cox
)(C
)(CIeq / CI )ni (C
(CV / CVeq )nv − 6μ
μ m δε
vp
(
)
(4.11)
where:
CI � concentration of self-interstitials
CIeq � equilibrium concentration of self-interstitials
CV � concentration of vacancies
Ceq
V � equilibrium concentration of vacancies
δ � linear misfit between Si and SiOx lattices (for SiO2
δ0.3)
nI � number of self-interstitials emitted
nV � number of vacancies absorbed
X � ratio of oxygen and silicon in precipitate
The compressive strain � in Eq. 4.11 is:
ε=
δ
1 + 4μ m /3Kp
where:
μm � shear modulus of silicon
Kp � bulk compressibility of SiOx
Interaction of oxygen with the other constituents in
association with oxygen aggregation has been observed
experimentally. At sufficiently high temperature, crystal­
line solids contain thermally generated vacancies and self­
interstitials, which are equilibrium point defects in crystals
caused by configuration entropy. In the case of dislocation
free SC silicon, the material is usually supersaturated with
point defects, because lack of other defects acting as point
defect sinks. A fundamental observation regarding intrin­
sic point defects is that silicon crystals can be grown in
either a vacancy or a self-interstitial mode and concentra­
tion of point defects in grown crystals depend on process­
ing conditions. In general, excess vacancies favor oxygen
precipitation, whereas excess self-interstitials suppress
it. It has been found that there is quite a sharp transition
around 5 � 1011 cm�3 vacancy concentration between
enhanced oxygen clustering and “normal” clustering [6].
In addition to crystal growth, changes in point defect con­
centration may take place during wafer processing. Wafer
surfaces act as source or sink of point defects depending
on ambient used. Nitration injects vacancies, whereas
oxidation is introducing self-interstitials into silicon
62
[4, 7, 8]. Also oxygen precipitation is introducing self­
interstitials into silicon. Effect of point defects on oxygen
precipitation depends also on possible point defect reac­
tions. (Interested readers may consult references [6, 9]
and references therein for further details.) Graphite is
used as heating elements in CZ crystal growth furnaces.
In partial vacuum of the growth chamber, there may be
sufficient oxygen that reacts with unprotected graphite
to form carbon monoxide, which dissolves in the silicon
melt. Consequently, carbon can be incorporated in the
silicon crystal during the growth process. When present at
a concentration above 0.5ppm, carbon strongly enhances
oxide precipitate nucleation [10]. In case of heavily boron
doped silicon (p � -type), it is found that precipitation
is enhanced as a function of increasing boron concentra­
tion [11–13]. Moreover, in heavily boron doped silicon,
maximum nucleation rate of oxide precipitates is shifted
toward high temperature regions [14].
According to classical, steady state nucleation theory,
the nucleation rate J is given by the Volmer-Weber­
Becker-Döring nucleation rate equation (for derivation,
see for example Ref. [15])
J = ZC * ω
(4.12)
where C* is the concentration of critical-sized nuclei and
ω is the frequency of attachment of oxygen atoms to the
nucleus. The term Z is the Zeldovich factor, which is a
correction factor corresponding to the fraction of atoms,
which are included in the precipitate nuclei immediately
after nucleation. In practice the Zeldovich factor is a fit­
ting parameter usually in the order of but smaller than 1.
The concentration of critical-sized nuclei C* is given by a
Boltzmann type of equation:
⎛ �G* ⎞⎟
⎟⎟
C* = Cx exp⎜⎜⎜
⎜⎝ kT ⎟⎠
(4.13)
The term Cx is concentration of nucleation sites. In
the homogeneous nucleation models Cx is set equal to
the interstitial oxygen concentration or more properly
interstitial lattice sites in silicon. Heterogeneous nuclea­
tion models assume that Cx is equal to the concentra­
tion of some other constituents such as pre-existing
oxygen aggregates, vacancies or carbon. The attachment
factor ω is given by
ω = 4π(r*)2 Cox
Dox
da
(4.14)
where da is the interatomic jumping distance. The total
number of precipitates per unit volume is calculated from
integrating the nucleation rate with the processing time.
Basically, nucleation rate of oxide precipitates in iso­
thermal heat treatment depends on oxygen concentration
Oxygen in Silicon
in solid solution and processing temperature. Furthermore,
heterogeneous factors may have an effect on nucleation
rate depending on experimental conditions. Nucleation
rate increases with increasing oxygen concentration in
solid solution. When experimental nucleation rate is plot­
ted as a function of temperature, a maximum at a certain
temperature is observed. This can be explained as follows.
When the temperature is very high, the oxygen super­
saturation is small or non-existing, leading to small driv­
ing force and nucleation rate. On the other hand, when
temperature is very low, diffusion becomes slow, leading
to also vanishing nucleation rates.
Nucleation rate is not necessary constant in time.
Nucleation rates slow down and number per volume of
precipitates reach a saturation value in very long anneals.
This has been explained with overlapping of diffusion
zones surrounding each nucleus during long anneals. As
a different type of time dependency, an incubation time
in nucleation rate is observed after processes, where
sudden cooling and concomitant sudden supersaturation
states are developed.
In practice, silicon has already pre-existing nuclei
before many processing situations. Due to possibility
of nuclei dissolution, number per volume of oxygen pre­
cipitates after non-isothermal heat-treatment programs
may differ from pre-existing nuclei density. As discussed
earlier, the size of the nuclei should be larger than the
critical size in order to be stable. Furthermore, the criti­
cal nucleus size increases as a function of rising tem­
perature. Consequently, at high enough heating rate, the
growth rate of a nucleus is slower than the increase of the
critical size of nucleus resulting in dissolution of nuclei.
In Figure 4.3 selection of nuclei capable of growth using
two different two-step heat treatment temperatures
has been illustrated [16]. First, there is a pre-existing
nucleus size distribution. A subsequent anneal selects
nuclei larger than the critical size for further growth. An
alternative low temperature anneal would select larger
proportion of nuclei than respective high temperature
anneal. According to experimental observations, total
Precipitate density
Invisible
As-grown
Visible
Annealing
After annealing
Low temp.
High temp.
rc 10
rc1
100
N(F>rc)
N(r>rc1)
1000
10000
Precipitate size (Å)
Figure 4.3 ● Selection of nuclei capable of growing [16]. Source:
Figure reproduced by permission of the Electrochemical Society.
CHAPTER 4
dissolution of pre-existing nuclei causes long time lag in
subsequent oxygen precipitation [17, 18].
Precipitates are characterized by their size, shape,
crystal structure and number per unit volume. In princi­
ple, the size and the number per unit volume are inter­
related at their upper boundary values, because there
is a finite number of oxygen atoms capable of forming
precipitates. In practice, the typical number per volume
of oxygen precipitates after device processing is between
103 and 1010 cm�3. Diffusion calculations show that for
these densities the diffusion zone of each precipitate
does not have much overlap. As a consequence, the size
of the oxygen precipitates is nearly independent of the
number per unit volume of precipitates (Bergholz, 1994).
Shape of a precipitate depends on their formation tem­
perature as well as oxygen supersaturation and doping
level of the silicon. Three temperature ranges have been
related to the three typical precipitate shapes, i.e., the
needle, the platelet, and the polyhedron in lightly doped
silicon. At low temperatures (~400–650°C) precipitates
grow as needles. In this temperature range the strainenergy contribution to the precipitate total free energy
dominates, since the stress-relieving processes (which
become important at higher temperatures) play a minor
role. At intermediate temperatures (~650–950°C)
platelet-shaped precipitates are typical (although they
can be formed also during short high-temperature
annealing). These precipitates are square formed plate­
lets at {100} habit planes, with edges along the �110�
directions. At high temperatures (above 950°C) strain is
completely released and the precipitates take the shape
with minimum surface energy. Due to the anisotropy of
interface energy, the preferential shape is octahedron
with eight equivalent (111) faces (surface energy of
silicon is minimum in the (111) planes) instead of the
sphere. In the case of heavily doped silicon, precipitate
morphology differs from lightly doped silicon. Plateletshaped precipitates are observed in addition to (100)—
also in (110)—and (111)-type habit planes [19] and
rod-shape precipitates are not formed [11]. According
to Fujimori [20], dependence of precipitate morphol­
ogy on oxygen supersaturation comes from kinetic con­
siderations. Growth rate of a precipitate increases with
increasing supersaturation of oxygen and kinetics of
stress-relaxation processes may become a limiting factor.
Consequently, for higher oxygen supersaturation, there
is a transition zone in boundary temperature between
platelet and polyhedron precipitate formation. The crys­
tal structures of precipitates formed at higher than about
650°C temperatures are amorphous. This is correlated
to precipitate morphology. Only needle-type precipitates
are observed to be crystalline.
At high enough temperatures precipitates do not
nucleate in practice. Only precipitate growth becomes
significant. The kinetics of the precipitation of oxygen
63
PA R T I
Silicon as MEMS Material
in thermal processing can be studied experimentally for
instance by following the diminishing infrared absorption
at 1107cm�1 band, characteristic of interstitially dissolved
oxygen in silicon. Furthermore, transmission electron
microscopy can be utilized in determining size of pre­
cipitates as a function of heat treatment time. It has been
confirmed by many observations, that the time depend­
ence of experimental results are generally in good agree­
ment with the theory of Ham [21] for diffusion limited
precipitation at temperatures above 650°C [22]. Applying
the theory of Ham, Sueoka et al. [23] gives the time (t)
dependence of the dimensions L (edge) and d (thickness)
of platelet precipitates and l (edge size) of octahedral pre­
cipitates. These types of model are called deterministic
growth models:
⎛ C − Cint ⎞⎟0.5
⎜
ox ⎟
L = Λ(Dox t)0.5 with Λ = 2 2 ⎜⎜ ox
⎟
⎜⎝ γπCp ⎠⎟⎟
(4.15a)
0.5
d = δ(Dox t)
⎛ γ(C − Cint )⎞⎟0.5
⎜
ox
ox ⎟
⎜
with δ = 4 ⎜
⎟⎟
⎜⎝
πCp
⎠⎟
(4.15b)
⎛ C − Cint ⎞⎟0.5
⎜
ox ⎟
l = λ(Dox t)0.5 with λ = (8π)1 / 3 ⎜⎜ ox
⎟⎟
⎜⎝
Cp
⎟⎠
(4.15c)
In order to describe the entire precipitation process
from nucleation to precipitate growth, a steady-state
nucleation model and a deterministic growth model
can be combined at the critical size of the nucleus. This
allows simultaneous calculation of oxygen loss, number
of precipitates per unit volume and the average precipi­
tate radius during annealings. Furthermore, precipitate
size-distribution can also be evaluated using coarsening
model together with an iterative numerical calculation
scheme [24]. However, for all nucleus radii smaller than
the critical size, an equilibrium size-distribution has to
be assumed. This assumption is incorrect when rapid
temperature ramping takes place. The most realistic
simulation strategy describes growth and dissolution of
all nuclei and precipitate sizes statistically. This can be
done applying Monte Carlo techniques. The drawback
of the Monte Carlo approach is excessive computational
load. A simulation model using Fokker-Plank equations
can overcome much of the computational problems.
Similarly to the Monte Carlo method, growth and dis­
solution of nuclei and precipitates are described statis­
tically. However, instead of using random numbers for
deciding on growth and dissolution, this is described
64
by a set of chemical rate equations. Furthermore, all
chemical rate equations are approximated with a single
stochastic partial differential equation applying a math­
ematical transformation. The resulting equation is called
a Fokker-Plank equation. For details of Fokker-Planck
modeling see, for example, Ref. [25].
4.4 Precipitate-Induced Defects
As discussed earlier, oxide precipitates in silicon
are originally strongly strained, because the volume
expansion connected with oxide precipitate forma­
tion. Stress relaxation may take place by ejection of
self-interstitials. However, ejected self-interstitials are
not necessarily arranged originally in minimum energy
configuration and stress relaxation is not necessarily
complete. Consequently, precipitate-induced defect
formation may take place.
The ideal case of stress (and strain) fields associated
to a precipitate formation without any stress-relaxation
process can be calculated using standard theory of elas­
ticity. General calculations of this type show the effect
of precipitate shape on elastic energy: lowest elastic
energy is associated to platelet morphology, next low­
est is associated to needle morphology, and the highest
elastic energy is associated to polyhedron morphology.
An experimental technique to study actual local lat­
tice strain around oxygen precipitates is convergent
beam electron diffraction (CBED) mode of transmis­
sion electron microscopy. The local lattice strain can be
measured from higher order Laue zone (HOLZ) pat­
terns. Several of this type of study has been published
[26, 27]. As a result of strain analysis from HOLZ pat­
terns, acquired around a platelet type of precipitate,
the strain along the normal direction to the precipitate
was found to be compressive. Importantly, however,
the strain along the parallel direction to the precipitate
was found to be tensile. Based on FEM simulation, the
strain formation was considered to take place during
cooling of the material [28]. In the case of polyhedron
precipitates, contradictory results have been published.
Otherwise similar behavior to that in the case of platelettype precipitate, but with lower strain levels, has been
reported [28]. On the other hand, results obtained
with high-resolution electron microscope indicating
that polyhedron precipitates exist practically without
strain have been reported [29]. An argument in this dis­
cussion is that amorphous silica cannot support shear
stresses above a glass transition temperature at around
950°C [30]. Apparently, uncertainty concerning stress
and strain fields associated to precipitates comes to
some extent from the fact that the stress formation is
not an equilibrium process, which would depend only
on shape and size of a precipitate. Precipitation process
Oxygen in Silicon
involves the inward diffusion of oxygen, the generation
of stress at the interface and the outward diffusion of
self-interstitials. Consequently, partial stress relaxation
takes place already simultaneously with the stress for­
mation and it is dependent on the process sequence.
Self-interstitials formed in the stress-relaxation proc­
ess associated with oxygen precipitation are likely to be
locally supersaturated. The system can further lower its
free energy by allowing them to agglomerate. Stacking
fault formation is such an agglomeration process. In
general stacking faults can be classified as surface stack­
ing faults and bulk stacking faults. In the case of sur­
face stacking faults, oxidation induced stacking faults
(OISF) are of interest in the present context. They are
usually located as a circular band in the wafer originated
from vacancy reactions during particular crystal growth
processes. Essential factors in formation of OISF are
self-interstitials emitted to silicon due to surface oxi­
dation [31, 32]. Stacking faults in silicon are always
associated with precipitates at their centers providing
that mechanical damage and heavy metal contamina­
tion are excluded as cause of the defects. Transmission
electron microscopy observations of several workers
confirm this [33, 34]. However, only 0.1 to 1% of the
precipitates present in wafers nucleate stacking faults.
In detailed TEM work of Sadamitsu et al. (1995) it was
shown that OISF forms at platelet-type precipitates.
Furthermore, it was observed that one of the �110�
edges of a platelet precipitate always lies exactly on the
(111) OISF plane. As discussed in the previous chap­
ter, platelet precipitates have expansive strain field in
the direction parallel to the precipitate plate. It is well
established in other alloy systems that interstitial atoms,
having a compressive strain field around them, diffuse
toward dilatation-field gradient from the compression
volume to the expansion volume. By analogy Sadamitsu
et al. propose that silicon self-interstitials injected from
Si/SiOx interface are attracted by the expansive strain
field around edge of platelet precipitates and subse­
quently they agglomerate as stacking faults at these
locations. According to Marsden et al. [35] the size of
a disk precipitate must be greater than a certain critical
size in order to act as nucleation center. They defined
the minimum size to be 26 nm. Another work by them
[36] implies that nucleation mechanisms of surface and
bulk stacking faults are similar. Electron microscopy
studies reveal that the stacking faults observed in sili­
con are of extrinsic type and they are bounded by Frank
partial dislocation that has (a/3) � 111� type Burgers
vector [29]. Infrared laser scattering tomography, scan­
ning infrared microscopy and x-ray tomography reveal
directly the true shape of stacking faults, which have
been observed to be predominantly circular [37, 38].
Near the specimen surface the shape may be also oval.
A few hexagonal loops observed occasionally are appar­
CHAPTER 4
ently multiple faults [37]. (The size of a stacking fault
may extend to tens of micrometers in diameter.)
The self-interstitials emission during precipitate
growth does not necessarily relax all the stresses leaving
residual stresses at precipitates. Furthermore, because
the thermal expansion coefficient of silicon is larger
than that of silicon oxide, an additive compressive strain
develops during cooling after precipitate growth [39].
As an additional means of strain relief, prismatic dislo­
cation loops can be punched-out into the silicon matrix.
Normally, this is associated to sufficiently large pre­
cipitates. Punched-out dislocations have been observed
frequently in TEM studies [29, 33, 40, 41]. They have
been determined to be extrinsic types of dislocation
loops that lie in the 110-planes orthogonal to the punch­
ing direction and have 1/2 � 110� type Burgers vector.
Prismatic punching can occur only if the strain energy
is large enough for loop nucleation to occur. Taylor
et al. [39] established a quantitative criterion for such
an event using the theory of Ashby and Johnson [42]
for prismatic loop nucleation.
Occasionally, also other types of precipitation induced
defects, such as dislocation dipoles and irregular dislo­
cation loops, are observed [29]. However, systematic
knowledge of their formation is sparse.
4.5 Behavior of Oxygen in Basic
Heat Treatment Procedures
Heat treatment procedures that silicon wafers expe­
rience during MEMS device manufacturing consists
frequently of several successive anneals in different tem­
peratures and gas ambient. To some extent the effects
of low-temperature steps, high temperature steps, and
ramps between the steps can be treated separately. In
the following, behavior of oxygen in basic heat treat­
ments is discussed.
The first heat treatment CZ silicon experiences is the
in situ annealing after solidification in crystal puller. This
is usually called thermal history. Thermal history var­
ies along the crystal axis and radius. Variation along the
crystal axis is a consequence of the fact that the seedend portion of a crystal spends more time in the puller
furnace than the end portion. The thermal history of
the crystal depends also on the shape of the ingot bot­
tom, the pulling rate, the puller type, the hot-zone con­
figuration, and the time that the ingot remains inside
the puller in the course of growth process. Variations in
thermal history affect oxygen precipitation and the for­
mation of microdefects. It should be emphasized, that
the thermal history effect is always present [2]. Various
heat treatment procedures have been developed to erase
or homogenize the effects of the thermal history. In fact,
65
Silicon as MEMS Material
it has been emphasized [43] that reproducible results
in precipitation treatments cannot be obtained without
proper homogenization treatment of the samples.
A single heat treatment is an elementary step of more
complicated thermal processes in silicon device manufac­
turing. General precipitation behavior in a single treatment
can be characterized as follows. When the temperature of
a heat treatment step is decreased, the supersaturation of
oxygen and driving force for precipitation rises, but the dif­
fusion coefficient falls rapidly. Consequently, in the pres­
ence of adequate numbers of nucleation sites, one predicts
a small number of large precipitates from a high-tempera­
ture anneal, and a large number of small precipitates from
a low temperature anneal [44].
A common two step heat treatment combination is
so called Lo–Hi treatment, where the low-temperature
step (600–800°C) leads to the generation or selection
of the nucleation centers and the high-temperature one
(�1000°C) to precipitate growth. Generally, precipitate
density increases with low-temperature anneal time and
precipitate size increases with high-temperature anneal
time [44]. Furthermore, ramping speed from the low
temperature to the high temperature will select the
nuclei capable of growing.
Complexity of manufacturing of silicon devices has
led to the work for finding standard heat treatments that
represent more complicated, multi-step ones, in order to
evaluate precipitation behavior of silicon material (Chiou,
1985). An outcome of such a work is the standard ASTM
F 1239. Basically, the standard heat treatment is a two
step Lo–Hi anneal. As a reference, a single Hi anneal is
also performed. The temperatures of Lo and Hi steps
are 750 and 1050°C, respectively. Further process details
have been explained in the ASTM F 1239 standard. In
the standard procedure, precipitation is monitored by
measuring the changes in interstitial oxygen concentration
with an infrared absorption spectrophotometer. Some
general conclusions can be drawn from the observed pre­
cipitation behavior. Because of the dependency of driving
force of precipitation (Eq. 4.3) on oxygen supersaturation,
the results of any precipitation test show three character­
istic regions as a function of initial oxygen concentration
of the tested wafers. Namely, zero precipitation, partial
precipitation and full precipitation. In Figure 4.4 the gen­
eral precipitation behavior has been plotted as a function
of initial oxygen concentration. Two observations are of
significance. The boundary value of initial oxygen concen­
tration when zero precipitation is observed is higher than
the equilibrium value from the phase diagram. This is
because driving force is needed for precipitation to occur.
Secondly, the slope of the curve is relatively steep in
the partial precipitation region. The consequence of this
type of behavior is that in the partial precipitation region,
the high slope of precipitation function transforms the
variation of initial oxygen concentration into variation in
66
Precipitated oxygen (Δ[Oi])
PA R T I
[oi]c
V,C,N,H,B Isi,P,As,Sb
Max.
ΔΔ[Oi]
Zero
precipitation
0
Partial
Min. precipitation
100%
precipitation
Initial oxygen concentration ([Oi]o)
Figure 4.4 ● Generic curve showing relation between oxygen
precipitation as a function of initial oxygen concentration [47].
precipitation. Comparison of the Hi and the Lo–Hi treat­
ments indicate the contribution of thermal history of the
wafers on precipitation, because the single Hi treatment
does not obviously involve a nucleation step at all [45].
In arbitrary Lo–Hi treatments, the position of zero
precipitation, partial precipitation and full precipitation
region in regard to initial oxygen concentration depend
primarily on the heat treatment temperature and time.
The additional factors include thermal history, doping
density and concentration of point defects and impuri­
ties. Lower pre-anneal temperature and/or longer preanneal time will push the partial precipitation region
toward lower oxygen concentrations as will a higher
concentration of vacancies, boron, carbon and nitrogen.
In Figure 4.5 micrographs of cross-sectional samples of
110 silicon surfaces are shown after ASTM F 1239 heat
treatments as examples. Silicon samples were of p-type
with two oxygen concentration levels. The concentration
levels were 10 ppma and 15 ppma. Samples were taken
from similar parts of the crystal to ensure uniform thermal
history. After heat treatments, samples were etched with
Wright etchant [46] in order to relieve microdefects.
Optical micrographs were taken using differential interfer­
ence contrast (Nomarski contrast). Precipitates are seen
as dots and stacking faults as oriented lines in the micro­
graphs. The micrographs of the samples with 10 ppma
oxygen concentration levels are in the upper row and the
micrographs of the samples with 15 ppma oxygen concen­
tration level are in the lower row, respectively. The micro­
graphs of the samples that have been heat treated only at
1050°C are in the left column. In the right column are the
micrographs of the samples that have been heat treated at
750°C and 1050°C. Full precipitation is seen only in the
sample with 15 ppma oxygen concentration level that has
been heat treated at 750°C and 1050°C. Micrographs
show clearly the effects of Lo–Hi heat treatment and
oxygen concentration on oxygen precipitation. If first
high-temperature heat treatment is long enough, a number
Oxygen in Silicon
100 μm
Cox = 10 ppma, T = 1050 °C
CHAPTER 4
100 μm
Cox= 10 ppma, T1 = 750 and T2 = 1050 °C
100 μm
Cox = 15 ppma, T=1050 °C
100 μm
Cox = 15 ppma, T1 = 750 and T2 = 1050 °C
Figure 4.5 ● Micrographs of silicon surfaces ASTM F 1239 heat treatments.
Figure 4.6 ● Example of a silicon wafer with stacking faults.
Figure 4.7 ● Example of a silicon wafer with DZ. Source: Figure
reproduced with permission of Okmetic Oyj.
of large precipitates grow beyond critical size and initiate
stacking faults. An example is presented in Figure 4.6.
In device processing, annealing programs are occa­
sionally carried out to “engineer” oxygen precipitation.
Probably the most popular of these treatments is a Hi–
Lo–Hi annealing, which is otherwise similar to Lo–Hi
annealing, but it comprises oxygen out diffusion annealing
at comparatively high temperature (�1100°C) as a first
step. The result of this treatment is a very low precipitate
density near the wafer surface, the denuded zone (DZ),
and a high defect density in the bulk, as consequence of
oxygen depletion at the top 20–100 μm under the wafer
surface. In Figure 4.7 a cross-sectional example of such a
wafer after Wright etching is presented. DZ formation in
this way is a direct consequence of earlier discussed high
slope of precipitation function (Figure 4.4). DZ width
67
PA R T I
Silicon as MEMS Material
(DZW) is influenced by time and temperature of the
out diffusion anneal in the case of similar silicon wafers.
For constant temperature anneal, experimental results of
DZW can be expressed with a following simple equation
(for more details see Ref. [2] and references therein):
DZW = A + B × t1 / 2
(4.16)
where A and B are experimental constants and t is
annealing time.
Another way to “engineer” oxygen precipitation
properties in silicon is rapid thermal processing (RTP).
DZ can be created by installing a proper vacancy con­
centration profile which rises from the wafer surface
into the bulk [6].
References
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solubility of oxygen in silicon, Mat.
Res. Soc. Proc. 59 (1986) 19–30.
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3. R.D. Doherty, R.W. Cahn, P. Haasen
(Eds.), Physical metallurgy, third ed.,
Elsevier, Netherlands, 1983, pp.
933–1030.
4. S.M. Hu, Effects of ambients on
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USA, 1994, pp. 353–390.
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V. Stojanoff, F.A. Ponce, S. Hahn,
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12. S. Hahn, F.A. Ponce, W.A. Tiller,
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doping upon oxygen precipitation in
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M. Yonemura, T. Ono, E. Asayama,
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Epitaxial Wafers, J. Electrochem. Soc.
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and defects in heavily doped
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(7) (1992) 2713–2723.
15. J.W. Cristian, The theory of
transformations in metals and alloys,
first ed., Pergamon Press,
1965 973 p.
16. N. Inoue, J. Osaka, K. Wada, Oxide
micro-precipitates in as-grown CZ
silicon, J. Electrochem. Soc. 129 (12)
(1982) 2780–2788.
17. T.Y. Tan, C.Y. Kung, Oxygen
precipitation retardation and recovery
phenomena in Czochralski silicon:
experimental observation, nuclei
dissolution model, and relevancy with
nucleation issues, J. Appl. Phys. 59 (3)
(1986) 917–931.
18. N. Inoue, K. Watanabe, K. Wada, J.
Osaka, Time-lag in nucleation of oxide
precipitates in silicon due to high
temperature preannealing, J. Cryst.
Growth 84 (1987) 21–35.
19. W. Wijranakula, Morphology of oxide
precipitates in Czochralski silicon
degenerately doped with boron, J.
Appl. Phys. 72 (9) (1992)
4026–4030.
20. H. Fujimori, Dependence on
morphology of oxygen precipitates upon
oxygen supersaturation in Czochralski
silicon crystals, J. Electrochem. Soc.
144 (9) (1997) 3180–3184.
21. F.S. Ham, Theory of diffusion limited
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(1958) 335.
22. J. Vanhellemont, Diffusion limited
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(1995) 4297–4299.
23. K. Sueoka, N. Ikeda, T. Yamamoto,
S. Kobayashi, Morphology and growth
process of thermally induced oxide
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Appl. Phys. 74 (9) (1993) 5437–5444.
24. S. Isomae, Computer-aided simulation
for oxygen precipitation in silicon,
J. Appl. Phys. 70 (8) (1991)
4217–4223.
25. M. Schrems, T. Brabec, M. Budil,
H. Pötzl, E. Guerrero, D. Huber,
P. Pongratz, Simulation of oxygen
precipitation in Czochralski grown
silicon, Mat. Sci. Eng. B 4 (1989)
393–399.
26. T. Okuyama, M. Nakayama, S.
Sadamitsu, J. Nakashima, Y.
Tomokiyo, Analysis of local lattice
strains around plate-like oxygen
precipitates in Czochralski-silicon
wafers by convergent-beam electron
diffraction, Jpn. J. Appl. Phys, 36 (6A)
(1997) 3359–3365.
27. M. Yonemura, K. Sueoka, K. Kamei,
Analysis of local lattice strain around
oxygen precipitates in silicon crystals
using CBED technique, Appl. Surf.
Sci. 130–132 (1998) 208–213.
28. M. Yonemura, K. Sueoka, K. Kamei,
Analysis of local lattice strain around
oxygen precipitates in Czochralski­
grown silicon wafers using convergent
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Phys. 38 (6A) (1999) 3440–3447.
29. H. Bender, Investigation of the
oxygen-related lattice defects in
Czochralski silicon by means of
electron microscopy, Phys. Stat. Sol.
A 86 (1984) 2245–2261.
30. W.A. Tiller, S. Hahn, F.A. Ponce,
Thermodynamic and kinetic
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for thermally induced microdefects in
Czochralski silicon, J. Appl. Phys. 59
(9) (1986) 3255–3266.
31. R.B. Fair, Oxidation, impurity
diffusion, and defect growth in
Oxygen in Silicon
silicon—an overview, J. Electrochem.
Soc. 128 (6) (1981) 1360–1368.
32. V.V. Voronkov, R. Falster, Vacancy-type
microdefect formation in Czochralski
silicon, J. Cryst. Growth, 194 (1998)
76–88.
33. D.M. Maher, A. Staudinger, J.R. Patel,
Characterization of structural defects
in annealed silicon containing oxygen,
J. Appl. Phys. 47 (9) (1976) 3813–
3825.
34. C. Clayes, H. Bender, G. Declerck,
J. van Landuyt, R. van Overstraeten,
S. Amelinckx, Impact of high
temperature processing on bulk
defects in Czochralski silicon, Physica
116B (1983) 148–161.
35. K. Marsden, T. Kanda, M. Okui,
M. Hourai, T. Shigematsu,
Determination of the criteria for
nucleation of ring-OSF from small
as-grown oxygen precipitates in CZ-Si
crystals, Mat. Sci. Eng. B 36 (1996)
16–21.
36. K. Marsden, S. Sadamitsu, T.
Yamamoto, T. Shigematsu, Generation
of oxidation-induced stacking faults
in Czochralski-grown silicon crystals
CHAPTER 4
exhibiting a ring-like distributed fault
region, Jpn. J. Appl. Phys. 34 (6A)
(1995) 2974–2980.
37. J.R. Patel, A. Authier, X-ray
topography of defects produced after
heat treatment of dislocation-free
silicon containing oxygen, J. Appl.
Phys. 46 (1) (1975) 118–125.
38. G. Kissinger, J. Vanhellemont, C.
Clayes, H. Richter, Observation of
stacking faults and prismatic punching
systems in silicon by light scattering
tomography, J. Cryst. Growth 158
(1996) 191–196.
39. W.J. Taylor, U. Gösele, T.Y. Tan, SiO2
precipitate strain relief in Czochralski
Si: self-interstitial emission versus
prismatic dislocation loop punching, J.
Appl. Phys. 72 (6) (1992)
2192–2196.
40. T.Y. Tan, W.K. Tice, Oxygen
precipitation and generation of
dislocations in silicon, Phil. Mag. 34
(4) (1976) 615–631.
41. K. Tempelhoff, F. Spiegelberg, R.
Gleichmann, D. Wruck, Precipitation
of oxygen in dislocation-free silicon,
Phys. Stat. Sol. 56 (1979)
213–223.
42. M.F. Ashby, L. Johnson, On the
generation of dislocation at misfitting
particle in a ductile matrix, Phil. Mag.
20 (1969) 1009–1022.
43. R. Falster, M. Cornara, D. Gambaro,
M. Olmo, M. Pagani, Effect of high
temperature pre-anneal on oxygen
precipitates nucleation kinetics in
Si, Solid State Phen. 57–58 (1997)
123–128.
44. J.G. Wilkes, The precipitation of
oxygen in silicon, J. Cryst. Growth 65
(1983) 214–230.
45. H.-D. Chiou, Oxygen precipitation
behavior and control in silicon crystals,
Solid State Tech. 30 (3) (1987) 77–81.
46. M. Wright-Jenkins, A new preferential
etch for defects in silicon crystals, J.
Electrochem. Soc. 124 (5) (1977) 757.
47. F. Shimura (Ed.), Oxygen in Silicon,
Semiconductors and Semimetals, vol.
42, Academic Press, USA,
1994. 679 p
Appl. Phys. 34 (SB) (1995)
L597–L599.
F. Shimura (Ed.), Oxygen in Silicon,
Semiconductors and Semimetals, vol.
42, Academic Press, USA, 1994. 679 p
M.D. Chiou, L.W. Shive, in W.M. Bulls,
S. Broydo, VLSI Technology, USA,
ECS, (1985) pp. 429–435.
Further reading
A. Borghesi, B. Pivac, A. Sassella, A. Stella,
Oxygen precipitation in silicon, J. Appl.
Phys. 77 (1995) 4169–4244.
S. Sadamitsu, M. Okui, K. Sueoka,
K. Marsden, T. Shigematsu, Jpn. J.
69
5
Chapter Five
Silicon Wafers: Preparation
and Properties
Markku Tilli
Okmetic Oyj, Vantaa, Finland
MEMS manufacturing sets, in many respects, special
requirements for silicon wafers, and in some processes—
for example, those based on bulk micromachining and
deep anisotropic wet etching—standard wafers intended
for normal semiconductor use may show poor results.
Standard polished silicon wafers used in semiconductor
manufacturing are extensively standardized by SEMI
(Semiconductor Equipment and Materials International)
[1, 2]. These standards stipulate most of the important
parameters, like dimensions, dimensional tolerances,
key measurement techniques, etc. Standards, however,
in many situations give only guidelines, and especially
when specifying wafers for MEMS use, care has to be
taken in actual specifications. Values needed for individual parameters commonly are much tighter than what
the standards suggest. This conclusion is obvious when
comparing the values found in the newest version of the
commonly used roadmap for IC’s, ITRS (International
Technology Roadmap for Semiconductors) to values of
SEMI standards [3].
MEMS processes are traditionally divided into surface micromachining and bulk micromachining. Unit
processes in surface micromachining are close to standard semiconductor processes, and thus wafer specifications usually follow closely the SEMI standards. Silicon
wafers used in bulk micromachining applications, however, deviate from features listed in SEMI standards.
This is because bulk micromachining processes and
techniques differ very much from each other, setting
process-specific specification requirements, and some
key characteristics of the final MEMS device may be
directly inherited from wafer properties and specifications. MEMS devices are often sealed from the environment with cap silicon wafers. These wafers used for
capping may require parameters uncommon to standard
IC-wafers, too. A few examples of these differences
are wafer thickness, thickness tolerances, flatness, and
the common requirement of double-sided polishing of
wafers (Table 5.1). There are also some “hidden” features, which are not commonly specified or are difficult
to specify—such as the bulk material behavior in different thermal treatments. Similarly, more advanced wafer
types for MEMS, epi wafers, and SOI wafers are covered by the SEMI standards only partly.
Independent of the final use of the silicon wafer, be
it for surface micromachining, bulk micromachining, or
Table 5.1 MEMS/IC wafer key parameter comparison
Parameter
MEMS wafer
IC wafer
Wafer diameter
(mm) (mainstream)
150, 200
200, 300
Wafer type
Technology
dependent: SSP,
DSP, EPI, ThickSOI
SSP, some EPI,
ThinSOI
Wafer thickness
Technology
dependent: Non
standard (common)
or SEMI standard
SEMI standard
Wafer resistivity
mΩcm to over
kΩcm
Typically up to
30 Ωcm
Bulk properties
Tailored, BMDs
often minimized
Gettering important,
BMD controlled
71
PA R T I
Silicon as MEMS Material
capping of the device, main steps of the wafer manufacturing are common. Wafers are cut from the grown
ingot, shaped, polished, and cleaned to be ready for further processing into Epi wafers or SOI-wafers, or for
device manufacturing. Unit process steps, like polishing,
may differ in detail, depending on the wafer thickness
or requirement of the double-sided polishing.
5.1 Silicon Wafer Manufacturing
Process
Silicon crystals, or ingots in the terminology commonly
in use, grown with either CZ (Czochralski) or FZ (float
zone) technique are typically up to 2 m in length, and
they have a small over-diameter to eliminate yield loss
in final wafers from diameter fluctuation and small
deviations from round shape. Silicon crystal growth and
properties are discussed in detail in Chapters 2 and 3.
A typical crystal can yield up to more than 2000
wafers, depending on the final thickness of the wafer.
The following concentrates on CZ silicon wafer manufacturing; this is because the vast majority of world
wafers are from CZ crystals. FZ-wafer manufacturing
is essentially similar; there are only some minor differences in the manufacturing. Figure 5.1 shows the
generic flow of wafer manufacturing from ingot to polished, cleaned product. The following presentation of
silicon wafer manufacturing is only an overview to help
the reader to understand the specifications of wafers
without going into deeper details.
5.1.1 Ingot Cutting and Shaping
As described in Chapters 2 and 3 of this book, CZ crystals have a resistivity distribution over the length of the
crystal, the seed end of the crystal having higher resistivity, and the tail end low resistivity. This distribution
depends on the dopant used, and also on the crystal
growth process parameters if easily volatile dopants,
arsenic or antimony, are used. For example, with phosphorus doping, the resistivity ratio between the neck
part and the tail part can exceed 4:1 (see Figure 3.4).
Some other characteristics, like oxygen content, can
also vary over the crystal length. These, combined with
practical manufacturability aspects, dictate that the
crystal for further processing needs to be cut in suitable
lengths. The limiting factor for length can be the customer resistivity window, the customer oxygen specification window, wafer order size, or optimum wafer lot
size in the production.
First step is to cut away the head part (shoulder) and
tail part of the ingot, leaving the cylindrical part for further processing. At the same time test pieces from both
ends of the ingot may be taken for laboratory measurements. For example, resistivity is measured, and thick
Packaging; to
Ingot cropping
Wafer marking (laser)
Edge shaping
– Epi
– SOI production
– End customer
Final inspections
Ingot cutting
Wafer clean
Lapping/grinding
– particles
– surface defects
Orientation measurement
Wafer cutting
(ID or wire cut)
Clean/etch
Final cleans
Cylindrical grinding
Flat/notch grinding
Polishing
Dimensional
measurements
Fig 5.1 ● Generic silicon wafer manufacturing flow.
72
Silicon Wafers: Preparation and Properties
CHAPTER 5
slug samples for dissolved oxygen and carbon concentration measurements are made. The operation of cutting
tails and shoulders is called cropping.
Cropped ingot is cut into pieces of suitable length.
If some other requirement (specific customer window)
does not limit the piece length, manufacturability optimization requires pieces of around 500 mm in length.
The cut piece is usually one manufacturing lot in the
subsequent process. First, the accurate orientation has to
be measured to locate and mark normally (110) or (100)
crystallographic plane or direction with (100) or (111)
oriented ingots. When the ingot is in (110) orientation,
some other planes or directions may be located. This
step is important, since the orientation plane or notch
is made according to this measurement. When the manufacturing process is carefully designed and stable, in
routine basis, ⫾0.2° final accuracy of the orientation flat
or notch is obtained, and ⫾0.1° accuracy is achievable
(compared to ⫾0.5° to 1° accuracy required in standard
wafer manufacturing, according to SEMI standards).
A grown ingot is not perfectly round, as there is
diameter fluctuation along the length of the ingot.
Cylindrical grinding with diamond tools shapes the ingot
round, and at the same time orientation flat or notch is
ground. The finished piece of ingot is then ready for
cutting to wafers.
wires in a wire-cutting machine. Today, wafers (and
from 200 mm up, extensively) are increasingly cut in
wire-cutting machines because of productivity reasons.
ID cutting, however, retains the flexibility of manufacturing smaller lots, but with higher cost. Table 5.2 shows
a comparison of these two cutting methods.
5.1.2 Wafering
5.1.2.1 ID Cutting
ID cutting is done with a thin tensioned diamond blade
having a hole in center, and on the inner edge of the
hole there is a thin diamond coating. The ingot piece
is fed against the blade, Figure 5.2. The blade does not
travel ideally straight through the ingot, but it makes a
small curve, and preferably the blade is curving towards
the ingot. Damage layer of the surface is different
between the ingot side and the wafer side surfaces.
Table 5.2 Wafer-cutting method comparison
The ingot to be sliced into wafers needs a support to
hold cut wafers; therefore, a ceramic or graphite beam
is glued on the piece of ingot. The ingot can be processed to wafers with two different methods. Either each
wafer is cut, one by one, with an ID cutting machine, or
the whole piece of ingot is cut with a web of tensioned
ID cutting
Wire cutting
Small lot manufacturing flexibility
⫹⫹
⫺⫺
Volume production, few
specifications
⫺
⫹⫹
Thin wafer cutting
⫺
⫹⫹
Wafer warp/bow
⫺
⫹
Wafer orientation control
⫹
⫺
Silicon utilization
⫺⫺
⫹⫹
Productivity
⫺
⫹
Ingot
Support
beam
Diamond
layer
Tensioned
blade
Fig 5.2 ● In an ID cutting machine the ingot is supported by a graphite beam. Tensioned cutting blade has a hole, which is coated with
diamond particles. Rotating blade is cutting the silicon at a speed of 50 mm/min or higher. Water with or without additives is used as a
coolant.
73
Silicon as MEMS Material
PA R T I
When wafers are measured after stress relief, they have
quite a large taper and warp/bow, and values are larger
if the wafer is thin. Typical bow and warp distributions
can be seen in Figure 5.3. The wafer taper from cutting
step can be removed in subsequent process steps, so
it does not appear in the finished wafer. Warp/bow of
the as-cut wafer is the sum of two components, permanent warp/bow originating from the irregular travel of
the blade through the ingot during cutting and from the
removable warp/bow coming from uneven residual damage on the wafer surface. Remaining process steps may
change permanent bow and warp only a small amount
unless there are thin films or deposited layers on the
wafer, which cause asymmetric stress. ID-cutting offers
good flexibility in small-lot production, since it makes a
wafer at a time, being suitable also for processing short
ingot pieces. Wafer orientation control is relatively easy
to achieve. The ability to slice thinner wafers is not as
good as when using wire cutting, however.
5.1.2.2 Wire Cutting
Wire cutting (principle in Figure 5.4) allows simultaneous cutting of hundreds of wafers routinely (depending
on the length of the ingot piece and cut wafer thickness), and larger machines are capable of processing
well over 1000 wafers at a time when several pieces
of ingot are cut at the same time. Figure 5.5 shows an
example of taper and warp/bow distribution in volume
production. Cutting is done by feeding abrasive, silicon
carbide containing slurry, on the wire web. Recently,
diamond-abrasive-coated wires have been available,
too. In practice the cutting can be done with two wire
feeding strategies. Oldest method is such, where wire
is traveling from a reservoir spool to an intake spool
some tens of meters, then the direction of wire movement is changed, and wire is rewound a little less than
what was the forward feed; then again the direction of
movement is changed, until the end of wire. In such a
(a)
way one section of the wire is used typically 3 times or
more. The latest practice is to feed wire in one direction
only, and when the wire is used, the direction of wire
movement is reversed. Of this method there are two
variations. The more common variant is where all wires
run in the same direction, and the other variant is where
wires are arranged in such a manner that every other
wire runs in the other direction. The latter is claimed
to have advantages, such as better taper control over
the method where wires are going in the same direction only. Both methods allow wire to be used several
times, too. Typical spool contains 200–400 km of wire.
Wires are around 120–160 μm thick, and while abrasive
is around 12 μm or less (median grain size), the kerf loss
is less than 200 μm, compared to ID-cutting where kerf
loss can be over 300 μm. Surface damage is also less than
that obtained from ID-cutting, but surface waviness
is higher. Advantage of wire-cutting in MEMS wafers
is that it allows cutting of thin wafers with acceptable
yield. Wire cutting is not efficient in producing small
lots; in practice tens of thousands of wafers have to be
cut with same specifications; otherwise, costs may be
prohibitive. Möller’s review [4] of wire cutting gives a
good oversight of the process.
Independent of the cutting method, wafers are
cleaned after cutting, and the supporting beam piece
is removed. In addition to cleaning, a slight etch may
be used to reduce surface damage to make the wafer
mechanically stronger, reduce surface damage, and
reduce the stress-related warp.
5.1.3 Wafer Marking
Wafer marking is done with a laser, according to SEMI
standard M12-0706 [5] or M13-0706, [6] with alphanumeric characters in a specified position near the primary flat or notch. These markings are readable even
with the unaided eye, and marks consist of an array of
(b)
300
300
Histogram of BOW (ave)
250
200
Frequency
Frequency
250
Histogram of WARP (ave)
150
100
50
200
150
100
50
0
0
–18
–12
–6
0
BOW (ave)
6
12
18
10
20
30
40
50
60
70
WARP (ave)
Fig 5.3 ● (a) Typical bow distribution of wafers in μms, (b) typical warp distributions in μms of wafers after ID cutting (x-axis scale in μm).
74
Silicon Wafers: Preparation and Properties
CHAPTER 5
dots, Figure 5.6. The difference between the standards
M12 and M13 is that Semi M13 standard gives more
information; with 18 characters it defines identification
number (8 character positions), wafer manufacturer
code (2 positions), resistivity identification (4 positions), dopant (1 position), crystal orientation (1 position), and check characters (2 positions). Semi M12
marks wafers with 12 positions, and resistivity, dopant,
and crystal orientation information is omitted. A custom marking with additional customer-specific information can be done, too, and the number of characters can
exceed 18 positions.
Two alternatives for marking are available: deep
marking or shallow marking. Deep marking is done usually after wafer slicing and cleaning in order to keep
maximum wafer identity information, or after-edge
grinding, when, e.g., the wafer location information
may be lost to some degree. The dots made by laser are
Fig 5.4 ● Principle of wire cutting.
(a)
(b)
Histogram of TTV (ave)
600
120
Frequency
500
Frequency
Histogram of Bow (ave)
140
400
300
200
100
100
80
60
40
20
0
0
8
12
16
20
24
28
–10
–5
0
5
10
15
20
Bow (ave)
TTV (ave)
(c)
Histogram of Warp (ave)
200
Frequency
150
100
50
0
0
8
16
24
32
40
Warp (ave)
48
56
Fig 5.5 ● (a) Typical taper, (b) bow, and (c) warp distributions of wafers after wire cutting (x-axis scale in μm).
Fig 5.6 ● An example of laser marking on a wafer. The code used is according to SEMI M13. (a) Deep laser mark done after slicing, (b)
shallow mark done after polishing.
75
Silicon as MEMS Material
PA R T I
deep enough to be visible after material removal in the
next processing steps. Shallow marking is done after
polishing, and in the mark the dots are small depressions with a small hump around the depressions, and
it is just visible under suitable illumination. There are
advantages and disadvantages with these methods. Deep
marking is making deep depressions on the wafer surface. These depressions attract particles, resist removal
from depressions is difficult or depression may initiate
slip during high-temperature processing steps. Shallow
marking may increase particulate levels in wafers, as it
is done after polishing. Also, if the “hump” is too high,
in wafer-bonding processes, shallow marked wafers may
show small voids around the marking. Both marking
types are widely used, and if front-side marking is critical, marking can be done on the wafer backside, too.
edges; rounded edge minimizes risk for slipping, too.
Edge shaping operation makes the wafer perfectly round
(off-cut wafers are oval shaped after slicing), the diameter is adjusted, and orientation flat(s) or notch is dimensioned or made. This operation is done normally with a
profiled diamond wheel, and the edge profile is following the shape given by SEMI M1-0307 [2], Figure 5.7.
The SEMI standard profile is often not suitable or ideal
for MEMS applications. If the wafer will be thinned
after processing, wafer edge may as a result be sharp
and thus brittle using the standard profile; therefore,
asymmetric edge profile can be used. Also, wafer bonding may set specific requirements for the wafer edge
shape; typically, for bonding applications, more blunt
profile is recommended in order to achieve a good bond
up to wafer edge. Examples of some feasible profiles are
shown in Figure 5.8.
This standard is also specifying identification flats
according to Figure 5.9 for wafers up to 150-mm diameter and a notch for wafers 200 mm and larger. However,
it is common that 150-mm and smaller wafers deviate from the standard having only one flat, and the
5.1.4 Edge Grinding
Silicon wafers after cutting have sharp edges, and they
chip easily. Wafer edge is shaped to remove sharp, brittle
B
x
A
D
Point
x (μm)
y (μm)
A
120
0
B
508
0
C
100
231
D
0
50
C
C/L
y
Fig 5.7 ● The wafer edge profile template according to SEMI M1-0707 standard. The actual shape of the wafer edge has to fall within
the template.
Table 5.3 Wafer marking codes according to SEMI M13
Character location
Character style
Parameter
Code
Definition
[1–7]
Alpha/numeric
Identification #
A–Z and 0–9
Manufacturer defined
[8]
Numeric
Identification #
0–9
Manufacturer defined
[9–10]
Alpha
Supplier identification
A–Z
Semi assigned codes for each manufacturer
[11–14]
Numeric
Resistivity
identification
0–9 and (period)
Resistivity (Ωcm) identification, no accuracy
implication
[15]
Alpha
Dopant
B,F,A,S,–
B, P, As, or Sb, or no identification
[16]
Numeric
Crystal orientation
0,1,2,3,5,–
(100),(111),(110),(011), (511), or no identification
[17]
Alpha
Check character
A–H
[18]
Numeric
Check character
0–7
76
Silicon Wafers: Preparation and Properties
flat length may be shorter than specified in the standard. This is to save the wafer surface area for devices.
A further deviation from the standard may be that the
150 mm wafer has a notch instead of flat. Primarily, flat
or notch is usually according to standard along {110}
crystallographic plane; however, {100} plane is in some
applications used, too.
5.1.5 Lapping/grinding
Wafers have, after cutting, a large average wafer-to-wafer
thickness variation, as well as large total thickness variation (TTV) within the wafer. TTV in as-cut wafers may
exceed 5 μm, and average thickness variation from wafer
to wafer can be over 20 μm. Wafer surface is nonuniform,
and the residual damage may be uneven and different on
different sides. Traditionally, dimensional variations are
reduced and an even damage layer is made with dual-side
lapping. This is an operation where wafers are rotating
in carriers between two very flat, large cast-iron plates,
and material removal is done with abrasive slurry containing alumina, optical emery, or silicon carbide powders. After total removal of 50–100 μm wafer, TTV will
be well below 1 μm, and average thickness range within a
production lot is a few μms. Surface roughness of lapped
wafers depends on the lapping slurry, but it is generally
less than 0.3 μm (Ra).
Lapping can be replaced or supplemented with single-side grinding, Figure 5.11. Good introduction to
silicon wafer grinding can be found in references [7–9].
Advances in this technique have been made in recent
years, and grinding gives very good flatness and thickness
control and low damage depth in finished wafers, and the
surface roughness is typically ⬍0.1 μm (Ra). With fine
grinding tools, surface roughness values of ⬍2 nm (Ra)
and ⬍20 nm (Rz) are achievable. Surface finish, however,
(a)
(c)
depends on whether grinding is done in ductile or in brittle mode, and in general on the stiffness and on resonance
frequencies of the grinding system. Ground wafers show
very shallow grinding marks visible to unaided eye under
suitable illumination, and this feature has generated
resistance to wide acceptance in the history. However, in
double-sided polishing these marks are easily removed.
Novel grinding systems, simultaneous double-sided
grinding, have been introduced, and the results are
promising, especially in machining large-size wafers [10].
The ability of these machines to handle thin wafers typical to MEMS applications is still to be proven.
5.1.6 Chemical Etching
Lapping or grinding leaves residual mechanical damage on the wafer surface, and wafer edges have residual
damage from both lapping and edge-grinding operations.
This damage is removed, and wafer is cleaned from
impurities coming from mechanical operations in the
etching step. The amount of silicon removed depends
on the damage depth from previous operations. For
etching there are two choices, acidic etch or alkaline
etch. Acidic etch can produce smooth surfaces and it is
suitable for all wafer orientations and dopants, including
very heavily doped silicon; but as an exothermic process,
process control is a challenge. Also, the decomposition
of chemicals in the acidic mixture makes it challenging
to master. Dopant and doping level in wafers affect the
final results, too. Especially the brightness of the surface
is affected by the dopant level. A typical classical acidic
mixture consists of hydrofluoric acid, nitric acid, and
acetic acid, based on the classical works of Robbins and
Schwartz [11–13]. It has been reported that some additives, either oxidants or, for example, ammonia, can be
used to improve the performance of the etchant [14].
P(111)
N(100)
≤125 mm
N(100)
≥150 mm
P(100)
N(111)
≥ 200 mm
(b)
(d)
Fig 5.8 Examples of the wafer edge profiles. Profiles (a) and
(b) are conventional. Profiles (c) and (d) are optimized for wafer
thinning after processing. Profile (d) is also suitable for various
bonding applications.
●
CHAPTER 5
Fig 5.9 ● Orientation flats for different wafer types and reference
notch for 200 mm and larger wafers according to SEMI. Note
that, commonly, wafer specifications differ from SEMI standards
and are customer specific.
77
PA R T I
Silicon as MEMS Material
Second choice is to use alkaline etching. This is done
usually with hot potassium hydroxide solution. The
process is stable, and thus easy to control. The disadvantage is that certain atomic planes, like (111), etches
slowly, and therefore the etchant is practical to (100)
wafers. Very heavy boron doping slows the etch speed
down, and N-type dopants with very high dopant levels generate unsafe levels of noxious gases unless special
ventilation and gas treatments are not made properly.
Second difference is that the wafer surface roughness is
higher compared with acidic etched surface. However,
alkaline etch is superior to retain the flatness of the
wafer, and it is as a waste environmentally better than
hydrofluoric-containing acidic mixtures.
Surface after etching is damage-free if etching is done
properly, and appearance is bright. It should be remembered that the surface appearance is not only governed
by the etchant, but also prior process steps have a
role—how uniform the residual damage from previous
processes has been, what has been the depth of damage
vs. etch dept, and does the damage have a texture or
fine structure, as is the case in grinding.
5.1.6.1 Donor Killing
Donor killing (for donors, see Section 3.6) can be done
in several manufacturing phases; often, it is done after
etching and cleaning by heating the wafer above 650–
700°C for a short time, followed by fast cooling. By
doing so, the effect of donors in resistivity is eliminated.
Cleaning before donor kill has to be effective to remove
surface metals to prevent penetration of fast-diffusing
metals into silicon. Donor kill is usually not necessary
for heavily doped wafers.
5.1.7 Polishing
Wafers for MEMS applications are commonly doubleside polished. This can be done either by polishing first
one side, then flipping the wafer over and polishing
the second side, or polishing both sides simultaneously
between two rotating polishing pads. The latter method
is preferred, because it retains the wafer flatness well;
however, with thin wafers it is more difficult to master.
Polishing is done using alkaline colloidal silica slurry as
polishing media. The required material removal depends
on the wafer surface roughness. Polishing pads are made
of porous polyurethane. The process is mainly chemical,
and surface after polishing is free of mechanical damage. Traditional processes are batch-type processing tens
of wafers at the same time. Also, CMP-type processes
where each wafer is polished individually are today
in use. Challenge is to retain the good wafer flatness
achieved in previous process steps.
Polishing is done in several steps. First there is a material removal step with aggressive slurry, with polishing
speed of approx. 1 μm/min or more, resulting in rough but
flat surface. There can be a second step, with less aggressive slurry, and final polish is done with a slurry having very
low material removal rate and producing a smooth surface.
Surface roughness measured with AFM over 1 μm2 field
after final polishing is approximately 0.1 nm (RMS).
Depending on the process type, wafers can float on
the polishing head recess almost freely, wafers can be
mounted with wax on polishing blocks, or wafers can be
in carriers resembling lapping carriers (see Figure 5.10b).
Material removal depends on the previous process
steps: A rough surface needs more polishing, in excess
Fig 5.10 ● Lapping machine (a). Wafers are placed in carrier disk holes on lapping plate (b). Carrier disks are rotated by outer and inner
pin rings rotating independently from each other and from upper and lower lapping plates. Abrasive slurry (alumina, optical emery, or
silicon carbide slurry) is fed between lapping plates, and with carefully selected rotation rates and directions of lapping plates and carrier,
the best possible flatness and thickness uniformity of wafers can be achieved.
78
Silicon Wafers: Preparation and Properties
of 20 μm; a smooth, regular surface manages with less
than 10 μm.
Although polishing slurry contains very fine particles
which are easily emitted from the machine, polishing
is done in clean room environment; the polishing clean
rooms are isolated, however, to control particle introduction to other clean room areas.
Polishing accuracy (final thickness, retention of
TTV, and flatness) is not as good as in precision grinding or lapping. However, routinely sub-μm TTV values,
important, for example, in bulk micromachining, can
be obtained. Figure 5.12 shows an example of TTV and
thickness distribution in a 150-mm wafer lot.
5.1.8 Clean Room Operations
Polished wafer has chemical residues from polishing
and particles. A good, and still valid, basic review of silicon wafer cleaning techniques is given, for example, by
Hattori [15]. An updated view with references to modern techniques can be found in Reinhardt’s and Kern’s
F
Diamond wheel
Silicon wafer
Fig 5.11 ● Principle of silicon wafer surface grinding. A cup wheel
with segmented diamond rim is pressed against co-rotating or
counter-rotating silicon wafer sitting on a flat vacuum chuck.
(a)
handbook on silicon wafer cleaning technology (2nd
edition) [16].
Typically silicon wafers are cleaned by RCA-type
cleaning sequence invented in the 1960s or by more
modern modified cleaning solutions [17]. The aim of
the cleaning is to remove organics, surface metals, and
particles. Organics are removed usually by alkaline solutions with presence of oxidizing agent, and the effect
may be enhanced by megasonic agitation and elevated
temperature. Oxidizer is important; otherwise, alkaline
chemical attacks and etches silicon in an uncontrolled
way. The tendency today is to have as diluted chemicals
as possible for environmental and cost reasons. A typical effective chemical mixture to remove light organic
contamination is DIW (deionized water), ammonia
and hydrogen peroxide mixture (APM), or SC-1 in
RCA clean terminology, at above 60°C with megasonic
(⬎900 kHz) agitation. Organic contaminants as well as
metals decompose hydrogen peroxide, and it is possible to use some stabilizers, similar to CDTA, cyclohexane-1,2-diaminetetra-acetic acid (see, for example, Ref.
[18]), to enhance the useful lifetime of the cleaning
bath. If the organic contamination is very heavy, sulfuric acid–hydrogen peroxide mixture (SPM) eventually
diluted with water at temperatures above 100°C can
be used. This mixture is called Piranha clean, and it is
most commonly used in device-making steps to remove
organic thin films, for example, wax residues from waxmounting polishing process. This mixture is also growing a dense oxide layer on the wafer.
Silicon dioxide on the wafer surface is removed normally by very diluted (1:100) hydrofluoric acid–water
mixture (DHF). Small amounts of hydrochloric acid
(HCl) addition are sometimes used; the role of HCl is to
remove, for instance, copper from the bare wafer surface.
Traditionally, the last steps of cleaning sequences have
been metal removal steps in hydrochloric acid–hydrogen
peroxide–water mixture (HPM), SC-2 in RCA clean
terminology; and elevated temperatures may be used to
(b)
LB
–0.00
CHAPTER 5
USL
0.12
0.24
0.36
0.48
0.60
0.72
0.84
LSL
375.0
USL
376.5
378.0
379.5
381.0
382.5
384.0
Fig 5.12 ● TTV (a) and thickness (b) distributions obtainable for double-side-polished 150-mm silicon wafers. Horizontal scale is μm.
79
PA R T I
Silicon as MEMS Material
enhance the cleaning effect. This mixture leaves on the
wafer surface a thin native oxide containing OH-groups.
After final rinses, wafers are dried. Drying can be done
by centrifugal drying or with Marangoni method, where
wafers are pulled slowly out of wafer under nitrogen flow
with a small amount of isopropyl alcohol vapor added
[19]. This technique is useful in drying structured wafers.
In rinsing step there may be additional metal removals with very diluted acidic water [20]. For example,
HCl-concentration in the ppm-range is effective at
removing iron on the wafer surface.
Figure 5.13 shows an example of a classical (full) cleaning sequence. Today the trend is to minimize chemical
usage and simplify the process as much as possible. When
the polishing process is producing wafers without heavy
organic contamination, sulfuric acid cleans can be omitted, and dilute ammonia–hydrogen-peroxide based chemistries at elevated temperatures with megasonic agitation,
combined with dilute hydrofluoric acid or hydrofluoric/
hydrochloric acid clean, followed by hydrochloric acid–
hydrogen-peroxide cleans, remove effectively particles
SPM
DIW
DHF
DIW
SPM: Sulphuric acid–Hydrogen
peroxide–water mixture
APM (SC-1)
DIW: De-Ionized water
DIW
DHF
DIW
HPM (SC-2)
DHF: Dilute Hyrofluoric acid–
water mixture (classically,
1:100 to 1:50)
APM : Ammonium hydroxide–
Hydrogen peroxide–water
mixture (classically 1:1:5)
HPM: Hydrochloric acid–
Hydrogen peroxide–water
mixture (classically 1:1:5)
DIW
(DHF)
DIW
Dry
Fig 5.13 ● A classical cleaning sequence used after polishing,
effectively removing organic, metallic, and particulate
contamination. Steps in gray are commonly used.
80
and organic and metallic contamination. Ozone addition
in water can be used to increase the oxidation potential of
water to produce a dense oxide layer on the wafer surface.
Generally, the surface concentrations of the transition metals levels of copper, nickel, and iron after clean
are below 1 ⫻ 1010 atoms/cm2; aluminum, zinc, and
calcium levels are slightly above typical transition metal
levels; and alkaline elements like sodium are below
5 ⫻ 1010 atoms/cm2. If maximum metal concentrations
are specified in wafer specifications, iron can be used
as an indicator: (1) if iron level is increased on wafer
surfaces, normally other metals are also at higher level;
(2) iron is the most common contaminant coming from
chemicals (especially in alkaline cleans); and (3) iron is
easy to detect and measure at very low concentrations
with several methods, with minority carrier lifetime,
with DLTS, and with VPD-TXRF techniques.
It should be noted that the contribution of surface
metals is much higher than contribution from bulk
metals from crystal growing in processed wafer with
devices. If wafer is 400 μm thick, which is quite common in MEMS applications, and the metal concentration on wafer surface is 1 ⫻ 1010 atoms/cm2 (both on
front and backside), and if in thermal treatments all
surface metals are diffusing in the bulk, the bulk concentration increases to 5 ⫻ 1011 atoms/cm3. This figure
exceeds the contamination level that is found in crystals. If in device manufacturing line ammonia-based
clean with uncontrolled chemicals is used as a last
step, iron concentration can be up to 1012 atoms/cm2,
resulting in, potentially, 5 ⫻ 1013 atoms/cm3 bulk iron
contamination level. Here is presented an extreme situation, and in practice only part of the potential metal is
diffused in. Surface metal contribution has to be taken
into account in designing the device manufacturing
process and cleans in it, and this is often neglected, even
when the incoming wafer cleanliness is well in control.
Surface metals have adverse effects, both in electrical
properties (for instance, iron reducing heavily minority
carrier lifetime), bulk properties (many metals promoting bulk crystal defect formation), or surface properties
(promoting stacking fault generation in oxidation, reducing oxide integrity, or generating epi defects). Especially,
crystal defects generated during device processing can
decrease MEMS device yield or performance. A good
review to the subject can be found—for instance, for
iron and for copper—in Refs [21] and [22], respectively.
5.2 Standard Measurements
of Polished Wafers
Customer wafer specifications define what is measured
and reported on finished wafers and are the measurements done either on a specified sampling plan or on all
Silicon Wafers: Preparation and Properties
wafers. Some of the measurements, for example, oxygen concentration, have to be done from special samples
made after crystal is grown from thick samples. Many
measurements destroy the wafer, increasing the cost of
manufacturing—these kind of measurements, if possible,
are made at the minimum necessary level. In the following, a brief description of each measurement is given.
A list of selected SEMI specifications and standards of
commonly used measurements is given in Section 5.4.
For a complete list of measurements, the reader should
consult Ref. [1].
5.2.1 Oxygen and Carbon Concentration
Oxygen is in interstitial sites in silicon lattice, and in CZ
silicon it is supersaturated at normal processing temperatures. Typical achievable range in CZ growth process
is approximately 6–18 ppma, or 3…9 ⫻ 1017 atoms/cm3
Si expressed in units of SEMI MF 1188-1107 [23].
Carbon lies in substitutional lattice sites, and concentration is typically ⬍0.3 ppma or ⬍1.5 ⫻ 1016 atoms/cm3
Si; measurement is made according to SEMI MF13911107 [24].
Precision measurements are made using double-sidepolished, or bright-etched, 2–4-mm-thick samples cut
from grown crystals, using purpose-build FTIR spectrometers. Interstitial oxygen absorbs at 1107 cm⫺1
wave number (9.03 μm wavelength IR-radiation).
Current (IOC-88) conversion factor from net absorption coefficient to concentration in ppma is 6.28, and to
atoms/cm3 Si 3.14 ⫻ 1017. Earlier conversion factors to
ppma were 4.9 (ASTM 1983-factor) and 9.62 (ASTM
1979-factor) and, correspondingly, to atoms/cm3 Si
2.45 ⫻ 1017 and 4.81 ⫻ 1017. Thus, major errors can
be made if the conversion factor is not clearly defined,
especially as the industry veterans still use the outdated
ASTM 1979 definitions. For listings of current conversion factors between old ASTM, new ASTM, JEIDA
(Japanese), Gun Biao (Chinese), and IOC-88, see SEMI
M44-0305 standard [25].
Carbon is absorbing at 605cm⫺1 wave number, or
16.53 μm wavelength. At room temperature a phonon
band has a strong absorption at 610 cm⫺1, which makes
a known zero-carbon content reference sample of same
thickness and surface properties necessary at room temperature measurements.
Oxygen and carbon content measurements can be
made also from actual wafers, but with lower accuracy. Accuracy can be improved if a known reference
with same thickness and surface properties is available. Especially if only one wafer surface is polished,
accuracy is poor, since calculation algorithms are based
on the polished silicon surface reflection factor of 0.3.
Unpolished surface has lower reflection factor, which
CHAPTER 5
changes internal reflections contributing to the total
IR absorption. There are published methods of how to
measure oxygen concentration in thin wafers [26].
5.2.2 Metal Concentration
Measurements
Bulk metal concentrations in silicon wafers are generally
very low, and standard practice is to follow only bulk iron
level through minority carrier lifetime measurements
in lightly boron-doped silicon. Common technique in
use is μPCD (photoconductivity decay) method based
on photo-induced minority carrier lifetime, according to
SEMI MF1535-0707 standard [27]. Carriers are generated by light pulses, and the decay of the carrier density
is measured by microwave reflection. Iron concentration can be calculated by comparing minority carrier
lifetimes before and after iron–boron pair dissociation
in p-type material. Expected minority carrier lifetime
result of a good quality ⬎10 ohm-cm p-type material,
when surface recombination effects are prevented, for
example, with corona-discharge, is above 300 μs. It
should be noted that bulk defects, like oxide precipitates from annealing steps, are reducing lifetime, and
the real picture of the contamination level can be had
only from received wafers without processing. Wafer
surface passivation to prevent surface recombination is
also important. This passivation can be made with the
iodide-methanol method, or with growing an oxide in
dry oxygen. Further information on this technique and
comparison to results from other common techniques
based on surface photovoltage (SPV) and photocurrent
collected by a silicon-electrolyte contact (Elymat) can
be found, e.g., in the paper of Polignano et al. [28].
Surface metals are commonly analyzed with three
techniques: light elements with AAS (atomic absorption
spectroscopy) or ICP-MS (inductively coupled plasma
mass spectroscopy) and heavier elements with a TXRF
(total X-ray reflection fluorescence) analysis. Especially
if these techniques are combined with a VPD-method
(vapor phase decomposition), [29] where contamination is collected to a small chemical droplet traversed
over the wafer, the sensitivity is enhanced in best case
to levels of 1 ⫻ 108 atoms/cm2. SEMI MF1724-1107
describes the AAS-method, [30] and SEMI M33-0998
describes the TXRF-method [31].
Surface metals are important, because most of the
bulk impurities are coming from surface metals introduced from various process steps. Thus, surface analysis is used not only to control incoming wafers, but
especially to control chemicals and process equipment.
A common practice is to use high-resistivity p-type
wafers with known, high minority carrier lifetime as
control wafer for monitoring purposes.
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PA R T I
Silicon as MEMS Material
5.2.3 Resistivity
Resistivity of the wafer is measured with a contact
method using a 4-point probe according to SEMI
MF43-0705 and MF84-0307 [32, 33]. This method
can be used to map wafer resistivity or to measure the
resistivity gradient, SEMI MF81-1105 [34]. As contact
methods damage and thus destroy the wafer surface,
these methods are used typically for monitoring purposes only with monitor wafers.
Polished prime wafers are measured with noncontact
methods based on eddy current measurement, according
to SEMI MF673-1105 [35]. Noncontact measurements
have an accuracy and repeatability of ⬍2–3% once properly calibrated. As measurement systems are used in volume production environment, it is practical to measure
only two points from the wafer, centerpoint and R/2- or
edge-point (typically, 6 or 10 mm from edge). Probe is
collecting information from a large surface area; thus,
the method is not able to resolve small-scale variations,
like dopant striations. If small-scale resistivity variations need to be measured, a spreading resistance (SPR)
measurement is done according to SEMI MF535-0307
[36] and other SPR-related standards. However, the silicon surface preparation and the SPR measurement itself
require special skills, and the accuracy of the resistance
or carrier density is only indicative, not as good as with a
4-point probe or with eddy-current method results.
5.2.4 Wafer Geometry
Wafer measurements for thickness, thickness variation
(TTV), and shape (warp, bow) are done with a noncontact
capacitive method according to SEMI 1530-0707, [37]
and commonly, 100% of wafers are measured. Production
equipment frequently combines the resistivity and geometry measurements. One probe station is for resistivity, one
station is for dimensions, and typically the equipment has
also receiving stations for accepted and rejected wafers.
Routinely each wafer is measured for thickness, TTV, flatness, and bow/warp. Since there are many different definitions for flatness and, especially, site flatness, care has to
be taken to define correct site size and reference planes,
should they be 3-point, global best fit, global front side,
global backside, site best fit, what is the PUA percentage
(usable area within specs), etc. For instance, lithography
process steps may set specific requirements for the flatness definition. SEMI M12 shows flatness decision tree for
all possible flatness definition alternatives.
5.2.5 Particles
Particles can be controlled visually under bright collimated light according to SEMI MF523-0706 [38]. The
82
human eye is quite sensitive to particles capable of seeing down to 0.3 μm particles. Visually, also, high levels
of haze can be seen easily. Haze consists typically of
small densely spaced scatterers, like pits, fine particles,
or localized roughness; or it can evolve during storage as
a result of the atmosphere in the storage cassette combined with suitable incubator. (Then it is called delayed
haze or time-dependent haze.)
Small (⬍0.3 μm) particles can be seen reliably only
with dedicated laser scanners [39]. Automated laser
scanners allow measurement of every wafer, too. Care
has to be taken when measuring small particles in the
0.1 to approximately 0.16 μm range not to mix particles
with COPs born from crystal growth. Crystal originated
particles (COP) are small vacancy agglomerates that are
harmful in certain CMOS processes.
It is common to specify particles only in such size
classes, which are known to be harmful for the device
manufacturing process.
5.2.6 Other Measurements
In each major process step in Figure 5.1 there are several values which are monitored in SPC (statistical
process control) programs to keep the manufacturing
process stable. Stable process helps to reduce laboratory
monitoring of the wafers once correlations between stable process and actual wafer results are established. As a
sample basis (ranging from a wafer/lot to daily or weekly
frequency), several features in wafers can be measured,
like subsurface damage, with preferential etching,
oxidation-induced stacking fault content (OISF’s), crystallographic perfection, exact crystallographic orientation, or oxygen precipitation with thermal treatments
simulating device manufacturing processes.
5.3 Sample Specifications
of MEMS Wafers
SEMI provides sample specifications for wafers used in
semiconductor application (SEMI, 2007) in standards
M1-0707, “Specifications for polished monocrystalline
silicon wafers,” [2] and M24-0307, “Specifications for
polished monocrystalline silicon premium wafers” [40].
The previous standard’s aim is to specify wafers for
general semiconductor use up to 300 mm wafer diameter, while the latter is specifying 150–300 mm wafers
for high-end IC’s made with deep submicrometer technologies. In addition, there are other standards focusing
on particular issues like M59 “Terminology for Silicon
Technology.” Those interested to get the complete view
should consult SEMI book of standards [1].
Silicon Wafers: Preparation and Properties
Standardization of wafers for MEMS applications
is still in nascent phase. This is because in the past
manufacturing processes and device designs and their
requirements differ very much from each other; in
worst case, every process and device design had its own
company-specific wafer specification. The situation is
changing because many new manufacturing processes
are designed to maximize compatibility with standard CMOS process and because of the introduction of
new processes, like deep reactive ion etching. However,
CHAPTER 5
there will still be some unique specified properties left
in which MEMS wafers differ from standard CMOS
wafers. Dimensional parameters, like TTV, or wafer
thickness distribution and the common requirement
of double-side polishing are examples. Table 5.4 gives
an example specification for 150-mm double-side polished wafers. 200-mm wafer specification is essentially
similar; the only difference is that the orientation flat
is replaced by a notch. SEMI M1-0707 [2] gives a complete list of properties which may be defined.
Table 5.4 Sample wafer specification
Crystal characteristics
Crystal pulling method
MCZ
Crystal orientation
(100) ⫾ 0.2°
Dopant
Boron
Resistivity
3–5
ohm-cm
Centerpoint, SEMI MF673
Radial resistivity variation, max
4
%
Measured at R/2 SEMI MF81
Oxygen content
6–10
ppm
SEMI MF1188
Carbon content
具0.3
ppm
SEMI MF1391
Minority carrier lifetime
NS (not specified)
μs
µPCD, SEMI MF1535
Wafer diameter
150 ⫾ 0.3
mm
SEMI MF2024
Wafer thickness
400 ⫾ 5
mm
SEMI MF533
Orientation flat
[110] ⫾ 0.2°
Flat length
57.5 ⫾ 2.5
mm
SEMI M1
Wafer TTV
具1.0
μm
SEMI MF533
Flatness, global
具1
μm
GBIR, SEMI MF1530
Wafer edge profile
Round
Warp
具40
μm
SEMI MF657
Bow
具40
μm
SEMI MF534
SEMI MF26
Wafer characteristics
SEMI MF847
SEMI M1, SEMI MF928
Front surface characteristics
Front surface
Polished, damage-free
Scratches
None
Visual inspection SEMI MF523
(Continued )
83
PA R T I
Silicon as MEMS Material
Table 5.4 (Continued)
Stains, pits, mounds
None
Visual inspection SEMI MF523
Particles
⬍20
⬎0.3 μm
Visual inspection SEMI MF523
OISF
⬍100
1/cm2
SEMI MF1727
Metals (Fe,Cu,Ni,Zn,Ca)
⬍1 ⫻ 1010
1/cm2
SEMI M33
Metals (Al)
⬍1 ⫻ 1011
1/cm2
AAS
Laser marking
Deep marking
SEMI M12
Back surface characteristics
Back surface
Polished, damage-free
Scratches, mm max
20
Visual inspection SEMI MF523
Stains, pits, mounds
None
Visual inspection SEMI MF523
Wafer packing
Cassette
Empak
Wafers in cassette
24
Cassette sealing
Double bag
Inert gas fill
5.4 Standards of Silicon Wafers
Throughout the industry, SEMI standards annually
updated by SEMI are used as a reference and guideline in
specifications. These standards have a good coverage over
different aspects of silicon technology: from equipment
automation, facilities, gases, materials, MEMS, microlithography, packaging, process chemicals, safety guidelines, silicon materials, and process control, to traceability.
Sometimes, also national standards, like JEIDA standards in Japan or DIN standards in Germany, are in use.
Earlier, commonly used ASTM standards from USA now
have been replaced by corresponding and updated SEMI
standards. Generally, comparable new standards from
different sources are in good harmony with each other.
However, oxygen content in silicon wafers is often still,
after decades of first conversion factor changes, still specified using old standards of ASTM, pre-1980s, in spite
of there having been 2 major revisions after that date.
JEIDA and DIN standard conversion factors also differ
from early ASTM standards. Thus, care has to be taken
when verifying which standard has been in use, to avoid
84
pcs
First slot empty
Outer bag aluminum laminate,
inner clear plastic
fundamental mistakes, especially when a common (bad)
practice here is not to specify the year of the standard.
Standards for materials give only guidelines, and their
values are applied only if no other value or definition is
agreed upon. For instance, wafer thickness variation for
150 mm and 200 wafers according to Semi MI-0307 has
to be ⫾ ⱕ 15 (for 200 mm 20) μm and TTV ⱕ 10 μm.
For many MEMS applications, these values are far too
high—the TTV requirement may be ⱕ1 μm or even in
submicrometer range.
Semi has published, in November 2007 standard edition, only 5 directly MEMS specific standards. Therefore,
general silicon-wafer-related standards are applied if
there is no specific MEMS standard available. Below
are listed selected standards related to silicon in MEMS
applications, (in the order of appearance in November
2007 standard collection):
E89-0707 Guide for Measurement System Analysis
(MSA)
M1-0707
Specification for Polished Monocrystalline
Silicon Wafers
Silicon Wafers: Preparation and Properties
CHAPTER 5
Unpatterned Semiconductor Wafer
Surfaces
M8-0307
Specification for Polished
Monocrystalline Silicon Test Wafers
M12-0706
Specification for Serial Alphanumeric
Marking of the Front Surface of
Wafers
M13-0706
Specification for Alphanumeric
Marking of Silicon Wafers
M16-1103
Specification for Polycrystalline Silicon
M17-0704
Guide for a Universal Wafer Grid
M61-0307
M18-1107
Guide for Developing Specification
Forms for Order Entry of Silicon
Wafers
Specification for Silicon Epitaxial
Wafers with Buried Layers
M62-1107
Specification for Silicon Epitaxial
Wafers
M20-1104
Practice for Establishing a Wafer
Coordinate System
MS1-0307
Guide to Specifying Wafer–Wafer
Bonding Alignment Targets
M24-0307
Specification for Polished
Monocrystalline Silicon Premium
Wafers
MS3-0307
Terminology for MEMS Technology
MS5-1107
Test Method for Wafer Bond Strength
Measurements Using Micro-Chevron
Test Structures
M32-0307
Guide to Statistical Specifications
M33-0998
Test Method for the Determination
of Residual Surface Contamination
on Silicon Wafers by Means of Total
Reflection X-Ray Fluorescence
Spectroscopy
M57-0706
Guide for Specifying Silicon Annealed
Wafers
M59-1107
M60-0306
Terminology for Silicon Technology
E2
Test Method for Time Dependent
Dielectric Breakdown Characteristics
of SiO2 Films for Si Wafer Evaluation
ME1392-0305 Guide for Angle Resolved Optical
Scatter Measurements on Specular or
Diffuse Surfaces
MF26-0305
Test Methods for Determining the
Orientation of a Semiconductive
Single Crystal
MF28-0707
Test Methods for Minority Carrier
Lifetime in Bulk Germanium
and Silicon by Measurement of
Photoconductive Decay
M34-0299
Guide for Specifying SIMOX Wafers
M35-1107
Guide for Developing Specifications
for Silicon Wafer Surface Features
Detected by Automated Inspection
M38-0307
Specification for Polished Reclaimed
Silicon Wafers
MF42-1105
M40-0200
Guide for Measurement of Surface
Roughness of Planar Surfaces on
Silicon Wafer
Test Methods for Conductivity Type of
Extrinsic Semiconductor Materials
MF43-0705
Test Methods for Resistivity of
Semiconductor Materials
M41-0707
Specification of Silicon-on-Insulator
(SOI) for Power Devices/ICS
MF81-1105
Test Method for Measuring Radial
Resistivity Variation on Silicon Wafers
M43-0301
Guide for Reporting Wafer
Nanotopography
MF84-0307
M44-0305
Guide to Conversion Factors for
Interstitial Oxygen in Silicon
Test Method for Measuring Resistivity
of Silicon Wafers with an In-Line FourPoint Probe
M46-1101E
MF95-1107
Test Method for Measuring Carrier
Concentrations in Epitaxial Layer
Structures by Electrochemical
Capacitance Voltage (ECV) Profiling
Test Method for Thickness of Lightly
Doped Silicon Epitaxial Layers on
Heavily Doped Silicon Substrated
Using an Infrared Dispersive
Spectrometer
M51-0303
Test Method for Characterizing Silicon
Wafer by Gate Oxide Integrity
MF110-1107
M53-0706
Practice for Calibrating Scanning
Surface Inspections Systems Using
Certified Depositions of Monodisperse
Polystyrene Latex Spheres on
Test Method for Thickness of Epitaxial
or Diffused Layers in Silicon by the
Angle Lapping and Staining Technique
MF154-1105
Guide for Identification of Structures
and Contaminants Seen on Specular
Silicon Surfaces
85
PA R T I
Silicon as MEMS Material
MF374-0307
Test Method for Sheet Resistance of
Silicon Epitaxial, Diffused, Polysilicon,
and Ion-Implanted Layers Using an
In-Line Four-Point Probe with SingleConfiguration Procedure
MF391-1106
Test Method for Minority Carrier
Diffusion Length in Extrinsic
Semiconductors by Measurement of
Steady-State Surface Photovoltage
MF397-1106
Test Method for Resistivity of Silicon
Bars Using a Two-Point Probe
MF523-1107
Practice for Unaided Visual Inspection
of Polished Silicon Wafer Surfaces
MF525-0307
Test Method for Measuring Resistivity
of Silicon Wafers Using Spreading
Resistance Probe
MF533-0706
Test Method for Thickness and
Thickness Variation of Silicon Wafers
MF534-0707
Test Method for Bow of Silicon Wafers
MF576-0706
Test Method for Measurement of
Insulator Thickness and Refractive Index
on Silicon Substrates by Ellipsometry
MF657-0707
MF671-0707
Test Method for Measuring Warp and
Total Thickness Variation on Silicon
Wafers by Noncontact Scanning
Test Method for Measuring Flat
Length on Wafers of Silicon and Other
Electronic Materials
MF950-1107
Test Method for Measuring the Depth
of Crystal Damage of a Mechanically
Worked Silicon Wafer Surface by
Angle Polishing and Defect Etching
MF951-0305
Test Method for Determination of
Radial Interstitial Oxygen Variation in
Silicon Wafers
MF978-1106
Test Method for Characterizing
Semiconductor Deep Levels by
Transient Capacitance Techniques
MF1048-1105 Test Method for Measuring the
Reflective Total Integrated Scatter
MF1049-1107 Practice for Shallow Etch Pit
Detection on Silicon Wafers
MF1152-0305 Test Method for Dimensions of
Notches on Silicon Wafers
MF1153-1106 Test Method for Characterization
of Metal-Oxide-Silicon (MOS)
Structures by Capacitance-Voltage
Measurements
MF1188-1107 Test Method for Interstitial Oxygen
Content of Silicon by Infrared
Absorption with Short Baseline
MF1239-0305 Test Method for Oxygen Precipitation
Characteristics of Silicon Wafers by
Measurements of Interstitial Oxygen
Reduction
MF1366-0305 Test Method for Measuring Oxygen
Concentration in Heavily Doped
Silicon Substrates by Secondary Ion
Mass Spectroscopy
MF672-0307
Test Method for Measuring Resistivity
Profiles Perpendicular to the Surface
of a Silicon Wafer Using a Spreading
Resistance Probe
MF673-1105
Test Method for Measuring Resistivity
of Semiconductor Wafers or Sheet
Resistance of Semiconductor Films with
a Noncontact Eddy-Current Gauge
MF674-0705
Practice for Preparing Silicon for
Spreading Resistance Measurements
MF723-0307
Practice for Conversion between
Resistivity and Dopant or Carrier
Density for Boron-Doped, PhosphorusDoped, and Arsenic-Doped Silicon
MF847-0705
Test Method for Measuring
Crystallographic Orientation of Flats
on Single Crystal Silicon Wafers by Xray Techniques
MF1392-0307 Test Method for Determining Net
Carrier Density Profiles in Silicon
Wafers by Capacitance-Voltage
Measurements with a Mercury Probe
MF928-0305
Test Method for Edge Contour of
Circular Semiconductor Wafers and
Rigid Disk Substrates
MF1451-0707 Test Method for Measuring SORI on
Silicon Wafers by Automated NonContact Scanning
86
MF1388-0707 Test Method for Generation Lifetime
and Generation Velocity of Silicon
Material by Capacitance-Time
Measurements of Metal-Oxide-Silicon
(MOS) Capacitors
MF1390-0707 Test Method for Measuring Warp
on Silicon Wafers by Automated
Noncontact Scanning
MF1391-1107 Test Method for Substitutional Atomic
Carbon Content of Silicon by Infrared
Absorption
Silicon Wafers: Preparation and Properties
MF1527-0307 Guide for Application of Certified
Reference Materials and Reference
Wafers for Calibration and Control of
Instruments for Measuring Resistivity
of Silicon
MF1528-1107 Test Method for Measuring Boron
Contamination in Heavily Doped NType Silicon Substrates by Secondary
Ion Mass Spectrometry
MF1530-0707 Test Method for Measuring Flatness,
Thickness, and Total Thickness
Variation on Silicon Wafers by
Automated Non-Contact Scanning
MF1535-0707 Test Method for Carrier
Recombination Lifetime in Silicon
Wafers by Non-Contact Measurement
of Photoconductive Decay by
Microwave Reflectance
MF1617-0304 Test Method for Measuring Surface
Sodium, Aluminum, Potassium, and
Iron on Silicon and Epi Substrates by
Secondary Ion Mass Spectrometry
MF1618-1104
Practice for Determination of Uniformity
of Thin Films on Silicon Wafers
MF1619-1107
Test Method for Measurement
of Interstitial Oxygen Content of
Silicon Wafers by Infrared Absorption
Spectroscopy with P-Polarized Radiation
Incident at the Brewster Angle
MF1724-1104 Test Method for Measuring Surface
Metal Contamination of Polycrystalline
CHAPTER 5
Silicon by Acid Extraction-Atomic
Absorption Spectroscopy
MF1725-1103 Practice for Analysis of
Crystallographic Perfection of Silicon
Ingots
MF1726-1103 Practice for Analysis of
Crystallographic Perfection of Silicon
Wafers
MF1727-0304 Practice for Detection of Oxidation
Induced Defects in Polished Silicon
Wafers
MF1771-0304 Test Method for Evaluating Gate
Oxide Integrity by Voltage Ramp
Technique
MF1809-0704 Guide for Selection and Use of
Etching Solutions to Delineate
Structural Defects in Silicon
MF1810-0304 Test Method for Counting
Preferentially Etched or Decorated
Surface Defects in Silicon Wafers
MF1982-1103 Test Method for Analyzing Organic
Contaminants on Silicon Wafer
Surfaces by Thermal Desorption Gas
Chromatography
MF2074-0707 Test Method for Measuring Diameter
of Silicon and Other Semiconductor
Wafers
MF2139-1103 Test Method for Measuring Nitrogen
Concentration in Silicon Substrates by
Secondary Ion Mass Spectrometry
References
1. International SEMI Standards,
Semiconductor Equipment and
Materials International, November
2007, www.SEMI.org.
2. SEMI M1-0707, Specifications for
Polished Monocrystalline Silicon Wafers,
Semiconductor Equipment and Materials
International 2007, www.semi.org.
3. http://www.itrs.net/
4. H.J. Möller, Basic mechanisms and
models of multi-wire sawing, Adv. Eng.
Mater. 6 (2004) 501–513.
5. M12-0706 Specification for Serial
Alphanumeric Marking of the Front
Surface of Wafers, Semiconductor
Equipment and Materials International
2007, www.semi.org.
6. M13-0706 Specification for
Alphanumeric Marking of Silicon
Wafers, Semiconductor Equipment and
Materials International 2007, www.
semi.org.
7. Z.J. Pei, G.R. Fisher, M. Bhagavat, S.
Kassir, A grinding-based manufacturing
method of silicon wafers: an
experimental investigation, Int. J. Mach.
Tools Manufact. 45 (2005) 1140–1151.
8. Z.C. Li, Z.J. Pei, G.R. Fisher,
Simultaneous double side grinding of
silicon wafers: a literature review, Int.
J. Mach. Tools Manufact. 46 (2006)
1449–1458.
9. J.H. Liu, Z.J. Pei, G.R. Fisher, Grinding
wheels for manufacturing of silicon
wafers: a literature review, Int. J. Mach.
Tools Manufact. 47 (2007) 1–13.
10. G. Pietsch, M. Kerstan, Understanding
simultaneous double-disk grinding;
operation principle and material
removal kinematics in silicon wafer
planarization, Precis. Eng. 29 (2005)
189–196.
11. H. Robbins, B. Schwartz, Chemical
etching of silicon I. The system HF,
HNO3, and H2O, J. Electrochem. Soc.
106 (1959) 505–508.
12. H. Robbins, B. Schwartz, Chemical
etching of silicon II. The system
HF, HNO3, H2O and HC2H3O2, J.
Electrochem. Soc. 107 (1960) 108–111.
13. R. Schwartz, H. Robbins, Chemical
etching of silicon III. A temperature
study in the acid system, J.
Electrochem. Soc. 108 (1961) 365–372.
14. Z. Liu, T. Sun, J. An, J. Wang, X. Xu,
R. Cui, Silicon etching in HF/HNO3/
NH3*H2O/H2O system, J. Electrochem.
Soc. 154 (2007) D21–D29.
15. T. Hattori, Trends in wafer cleaning
technology Chapter 32, in: T. Hattori
87
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Silicon as MEMS Material
(Ed.), Ultraclean Surface Processing of
Silicon Wafers, Springer-Verlag, 1995.
16. K. Reinhard, W. Kern, Handbook on
Silicon Wafer Cleaning Technology,
William Andrew Inc., Norwich, 2007.
17. W. Kern, The evolution of silicon wafer
cleaning technology, J. Electrochem.
Soc. 137 (1990) 1887–1892.
18. H. Saloniemi, T. Visti, S. Eränen, A.
Kiviranta, O. Anttila, Improvement
of SC-1 bath stability by complexing
agents, Phys. Scr. T101 (2002) 226–229.
19. A. Leenaars, J. Huethorst, J. van
Onkel, Marangoni drying: a new
extremely clean drying process,
Langmuir 6 (1990) 1701–1703.
20. O. Anttila, M. Tilli, Metal contamination
removal on silicon wafers using dilute
acidic solutions, J. Electrochem. Soc.
139 (1992) 1751–1756.
21. A. Istratov, H. Hieslmair, E. Weber,
Iron contamination in silicon
technology, Appl. Phys. A 70 (2000)
489–534.
22. A. Istratov, E. Weber, Physics of
copper in silicon, J. Electrochem. Soc.
149 (2002) G21–G30.
23. SEMI MF1188-1107 Test Method for
Interstitial Oxygen Content of Silicon
by Infrared Absorption with Short
Baseline, Semiconductor Equipment
and Materials International 2007,
www.semi.org.
24. SEMI MF1391-1107 Test Method for
Substitutional Atomic Carbon Content
of Silicon by Infrared Absorption,
Semiconductor Equipment and
Materials International 2007, www.
semi.org.
25. SEMI M44-0305 Guide to Conversion
Factors for Interstitial Oxygen in
Silicon, Semiconductor Equipment
and Materials International 2007,
www.semi.org.
26. H. Shirai, Oxygen measurements on
acid-etched Czochralski-grown silicon
88
wafers, J. Electrochem. Soc. 139
(1992) 3272–3275.
27. SEMI MF1535-0707 Test Method
for Carrier Recombination Lifetime
in Silicon Wafers by Non-Contact
Measurement of Photoconductive
Decay by Microwave Reflectance,
Semiconductor Equipment and
Materials International 2007, www.
semi.org.
28. M. Polignano, F. Cazzaniga, A.
Sabbadini, G. Queirolo, A. Cacciato,
A. DiBartolo, Comparison among
lifetime techniques for the detection
of transition metal concentration,
Mater. Sci. and Eng. B. 42 (1996)
157–163.
29. C. Neumann., P. Eichinger, Ultra-trace
analysis of metallic contaminants
on silicon wafer surfaces by vapour
phase decomposition/total reflection
X-ray fluorescence (VPD/TXRF),
Spectrochim. Acta, Part B 46 (1991)
1369–1377.
30. SEMI MF1724-1104 Test Method
for Measuring Surface Metal
Contamination of Polycrystalline
Silicon by Acid ExtractionAtomic Absorption Spectroscopy
Semiconductor Equipment and
Materials International 2007, www.
semi.org.
31. SEMI M33-0998 Test Method
for the Determination of Residual
Surface Contamination on Silicon
Wafers by Means of Total Reflection
X-Ray Fluorescence Spectroscopy,
Semiconductor Equipment and
Materials International 2007, www.
semi.org.
32. SEMI MF43-0705 Test Methods
for Resistivity of Semiconductor
Materials, Semiconductor Equipment
and Materials International 2007,
www.semi.org.
33. SEMI MF84-0307 Test Method
for Measuring Resistivity of Silicon
Wafers with an In-Line Four-Point
Probe, Semiconductor Equipment and
Materials International 2007,
www.semi.org.
34. SEMI MF81-1105 Test Method for
Measuring Radial Resistivity Variation
on Silicon Wafers, Semiconductor
Equipment and Materials International
2007, www.semi.org.
35. SEMI MF673-1105 Test Method
for Measuring Resistivity of
Semiconductor Wafers or Sheet
Resistance of Semiconductor Films
with a Noncontact Eddy-Current
Gauge, Semiconductor Equipment and
Materials International 2007,
www.semi.orgwww.semi.org.
36. SEMI MF525-0307 Test Method
for Measuring Resistivity of Silicon
Wafers Using Spreading Resistance
Probe, Semiconductor Equipment and
Materials International 2007, www.
semi.org.
37. SEMI MF1530-0707 Test Method for
Measuring Flatness, Thickness, and
Total Thickness Variation on Silicon
Wafers by Automated Non-Contact
Scanning, Semiconductor Equipment
and Materials International 2007,
www.semi.org.
38. SEMI MF523-1107 Practice for
Unaided Visual Inspection of Polished
Silicon Wafer Surfaces, Semiconductor
Equipment and Materials International
2007, www.semi.org.
39. SEMI M35-1107 Guide for
Developing Specifications for Silicon
Wafer Surface Features Detected by
Automated Inspection, Semiconductor
Equipment and Materials International
2007, www.semi.org.
40. SEMI M24-0307 Specification for
Polished Monocrystalline Silicon
Premium Wafers, Semiconductor
Equipment and Materials International
2007, www.semi.org.
6
Chapter Six
Epi Wafers: Preparation and
Properties
Douglas J. Meyer
AZonic Solar, Mesa, AZ, USA
The epitaxial deposition of Si, often referred to as epi,
is an essential step in the formation of many MEMS
structures. Epi is used as etch stops for forming BESOI
(bonded etch-back silicon on insulator) structures, on
SIMOX SOI structures to increase the Si thickness
above the buried oxide (BOX) and as a means for build­
ing a combination monocrystalline/polycrystalline struc­
ture referred to as epi-poly. Epi layers of up to 100 μm,
or even more, are used in MEMS structures, although
most applications require only 2–20 μm of epi.
This brief treatise on epitaxy touches on the funda­
mentals of epitaxial deposition as well as some specific
examples relevant to MEMS. A comprehensive discus­
sion of Si epitaxy can be found in the tome edited by
Crippa et al. [1].
Load wafer(s) into the process chamber
Purge process chamber
Heat to H2 bake temperature
Perform H2 bake
Heat or cool to deposition temperature
Deposit the epi layer
Cool to wafer unload temperature
6.1 Silicon Epitaxy—The Basics
Unload wafer(s)
Epitaxy was invented at AT&T Bell Labs [2] circa 1960
in order to improve doping profile abruptness and
increase the operating frequencies of bipolar transis­
tors. Since then, the use of epitaxy has spread through­
out the semiconductor industry and can be found in
nearly all fabrication disciplines. Although the details of
epitaxial deposition recipes are often highly specific to
the precise goals of the process, with respect to MEMS
applications, the process can often be represented by
Figure 6.1.
Silicon substrates (wafers) are loaded into the proc­
ess chamber and the chamber is then purged with N2,
if loading required exposure to air. Hydrogen is intro­
duced and the process chamber then remains in an H2
ambient throughout the entire process. The chamber is
Etch the process chamber
Fig 6.1 ● The basic epitaxy process recipe.
heated to a temperature sufficient for removing native
oxide from the wafer surface as described in Section
6.1.1. Following native oxide removal, the chamber is
then cooled, if necessary, to the desired temperature for
deposition of the epitaxial layer. The choice of deposi­
tion temperature, pressure, silicon precursor and doping
species are discussed in Sections 6.1.2, 6.1.3 and 6.1.4.
After depositing the epi layer, the system is briefly
purged in H2 to remove any residual Si and doping gas
89
Silicon as MEMS Material
species and then cooled to the appropriate tempera­
ture for unloading the processed substrates. After the
substrates have been unloaded the chamber may be
heated to 1200°C and etched with HCl (gas phase
concentration of 50% HCl in H2 in the chamber) or
the process chamber is loaded with a new set of wafers
and another epi process run is begun. The frequency
of process chamber etching is determined by the type
of epi reactor (single wafer or batch), the build-up of
dopant background in the chamber and the amount of
Si accumulated in the process chamber.
6.1.1 Surface Preparation
The growth of epitaxial Si fundamentally requires that
the deposition occur over a surface that has an atomic
spacing very nearly equal to that of Si. The most com­
mon case of Si epitaxy is that of homoepitaxial growth,
where Si epi is deposited on a Si substrate. Si sub­
strates are normally covered with a native oxide consist­
ing of 1–3 nm of SiO2 and this amorphous layer must
first be removed to expose the Si surface. Removal is
commonly accomplished by reduction in H2 at an ele­
vated temperature of 1100°C or more through the
reactions:
SiO2(s)
H2 (v) SiO(v)
H2O(v)
(6.1)
and
SiO2(s)
Si(s) 2SiO(v)
(6.2)
Equation 6.1 is the dominant process for native oxide
removal at low temperatures with Eq. 6.2 becoming
important at higher temperatures. This process step is
referred to as the hydrogen bake. The presence of H2O
in Eq. 6.1 suggests that the H2 bake step is sensitive
to the water vapor content of the H2 used in the proc­
ess. This is indeed highly significant and H2O contents
of 1 ppm, and preferably 100 ppb, are essential for
high quality, stacking fault-free epitaxial processing.
Figure 6.2 demonstrates the impact of temperature on
the SiO2 reduction rate with a H2 source containing
10 ppb of H2O.
Some epitaxial processes have severe thermal budget
limitations due to the presence of other structures on
the wafer prior to epi. In these cases the native oxide
can be removed by liquid phase etching with a dilute
HF solution, typically 100:1 deionized water to reagent
HF by volume, for a duration of 2–5 minutes at room
temperature. Native oxide removal proceeds via the
reaction:
SiO2(s)
90
6HF(l) H2(v) + SiF6 (l)
10
SiO2 etch rate (nm/min)
PA R T I
1
0.1
1200°C 1100°C 1000°C
0.01
0.6
(6.3)
0.8
0.9
1000/T (K–1)
Fig 6.2 ● SiO2 etch rate in H2 at 100 kPa.
Rinsing the wafers in ultrapure deionized water
(total ionized C content 5 ppb, dissolved O content
50 ppb) after the etch will result in a hydrogen ter­
minated surface that resists oxidation for several hours
in ambient conditions. This allows transportation of the
etched wafers to an inert gas purged or vacuum loadlock for staging prior to epitaxial processing. The ex-situ
removal of the native oxide enables the hydrogen bake
to be performed at a temperature of 850°C or so for 5
minutes and yields an O-free epi/substrate interface.
Failure to remove the native oxide prior to deposition
will result in amorphous or polycrystalline film growth,
depending on the temperature of deposition. If a chlorosi­
lane is used as the Si precursor, the film deposited over
the native oxide will most likely be discontinuous, or at
sufficiently low temperatures, no growth will occur at all.
6.1.2 Silicon Precursors and Deposition
Temperature
The choice of a Si precursor and the deposition temper­
ature are strongly related to the dopants and structure
present on the wafer prior to epitaxy. An Arrhenius plot
of the commercially available Si precursors most often
used for Si epitaxy is shown in Figure 6.3.
The deposition of Si from chlorosilanes can be
described by the overall reaction as in
SiH(4n )C l n ( v )
2H2O(l)
0.7
900°C
(n 2)H2(v) Si(s) nHCl(v) n 2, 3 or 4
(6.4)
Epi Wafers: Preparation and Properties
and for non-chlorinated silanes as
Si m H2(m 1)(v) Si(s)
(m
1)H2 (v) m 1, 2 or 3 (6.5)
Precursors such as Si2H6 and Si3H8 are extremely
expensive compared to SiH4 and the chlorosilanes.
Thus, their application is reserved for processes requir­
ing very thin epitaxy at low deposition temperatures, for
example, T600°C. Fortunately, MEMS applications
do not normally require such low epi process temper­
atures, thereby enabling the use of less expensive pre­
cursors which have higher deposition rates and higher
productivity. Further, the use of SiCl4, which was quite
common in the 1970s and 1980s, has been curtailed sig­
nificantly in recent times since it provides no deposition
rate advantage over SiHCl3 [3].
In general, it is desirable to choose the Si precursor
which provides the highest deposition rate, at the cho­
sen deposition temperature, in order to maximize pro­
ductivity. If there are no temperature restrictions on the
10
Deposition rate (μm/min)
SiHCl3
SiH2Cl2
1
SiCl4
0.1
SiH4
Si2H6
0.01
Si3H8
0.001
1200°C1000°C
800°C 700°C
0.0001
0.65
0.85
1.05
600°C
1.25
1000/K (K–1)
Fig 6.3 ● Arrhenius plot for inorganic Si precursors.
CHAPTER 6
process, SiHCl3 is the obvious choice. Coincidentally,
it is also the lowest cost Si precursor for epi. There is,
however, a practical limitation to this rule. All commer­
cial epi reactors rotate the wafer support, referred to
as a susceptor, in order to achieve acceptable film uni­
formities by a superposition of the deposition profiles at
various locations within the process chamber. Although
there is no hard and fast rule, it is usually desirable to
allow the susceptor to make at least 10 revolutions dur­
ing the deposition step. Thus a single wafer epi reac­
tor, with a rotation rate of 30 rpm, would suggest a
minimum deposition time of around 20 seconds. At a
growth rate of 4 μm/min a minimum epi thickness of
about 1.5 μm is needed to achieve good film uniformity
with this precursor.
The special case of epi-poly, where both monocrys­
talline and polycrystalline Si are to be deposited on a
wafer, is discussed in greater detail in Section 6.2.
Briefly, SiH4 must be used, at least initially, in order to
achieve a continuous film over the dielectric regions.
Epi layers having a thickness 1 μm often use a chlo­
rosilane (SiHCl3 or SiH2Cl2) following an initial growth
with SiH4.
The use of SiH2Cl2 as a precursor is usually limited
to films 2 μm in thickness. Such films are common in
bipolar and BiCMOS structures where reduced pressure
(RP) processing is often required to control As autodop­
ing, or for selective epitaxy as described in Section 6.5.
A comparison of the applicability of the various Si pre­
cursors is provided in Table 6.1.
The choice of deposition temperature is usually
imposed upon the epi process by structures (physical
and/or doping) which are on the wafer prior to epi. The
diffusion of dopants, particularly B and P, in the substrate
may place a constraint on the upper temperature of the
process. The choice of deposition temperature must
then be made with respect to the overall process integra­
tion strategy. The presence of SiO2 on the wafer surface,
Table 6.1 Comparison of common precursors for Si epitaxy
Thickness
range
(μm)
Deposition
temp.
(°C)
Dep. rate
range
(mm/min)
Reduced
press?
Selective
epi?
SiGe
epi?
Chamber
coating
SiCl4
2–100
1150–1250
0.5–2
No
Rare
No
Lowest
SiHCl3
2–100
1050–1200
0.5–5
Rare
No
Rare
Low
SiH2Cl2
0.001–5
650–1100
0.001–2
Yes
Yes
Yes
Moderate
SiH4
0.001–2
500–1000
0.001–1
Yes
Yes
Yes
Significant
Si2H6
0.001–0.5
400–800
0.001–0.2
Yes
Yes
Yes
Significant
Si3H8
0.001–0.5
400–600
0.001–0.2
Yes
Yes
Yes
Significant
91
Silicon as MEMS Material
The choice of process pressure is most often based on
structures present on or in the substrate. Control of
autodoping, where dopants in the substrate impact the
doping of the epi layer during the initial growth stages,
is the primary motivator for process pressure choice.
There are, however, two situations in MEMS where
the nature of the epi deposition process motivates the
choice of process pressure: selective epitaxy and epi-poly
92
T = 1100C
P = 760 torr
SiHCl3= 12 g/min
Dep. rate = 4 μm/min
1019
1018
1017
1016
1015
Transition width ~ 0.35 μm
1014
1013
0
1
2
3
4
Depth (μm)
Fig 6.4 ● Transition region for p-epi on a p
substrate.
6
0.5
5
T.W
.a
t ra
te
=
0.4
3
pos
itio
n ra
te
0.3
4
0.2
2
Deposition rate (μm/min)
1μ
m/
mi
n
Overall
Trans. Width
3 de
6.1.4 Choosing an Operating Pressure
1020
Cl
Epitaxial layers are doped in-situ during the growth of
the layer. The dopants used for epi are usually As or
P, for n-type epi layers, and B for p-type epi. The gas
phase species for these dopants are AsH3, PH3, B2H6
or, much less commonly, BCl3. The hydride doping spe­
cies are typically purchased in high pressure gas cylin­
ders containing 10–100 ppm of the hydride in H2. If
exceptionally high concentrations of doping are neces­
sary in the epi layer these dopants can be purchased
as pure components. However, concentrations in the
range of 1–10% diluted with H2 or an inert gas are more
common.
The use of Sb as an n-type dopant in Si epi is excep­
tionally rare due to the poor stability (shelf life) of
SbH3 and low vapor pressure of SbCl5. If BCl3 or
SbCl5 is used as the doping source, a liquid-vapor deliv­
ery system (often referred to as a bubbler) is required
where H2 or an inert carrier gas is passed through the
pure component liquid and the resulting mixture of the
dopant in H2 is delivered to the process chamber.
The incorporation of n-type and p-type dopants as
a function of temperature can be summarized as fol­
lows: Under the conditions of fixed deposition rate,
fixed pressure and fixed doping species partial pres­
sure, n-type doping incorporation decreases (resistivity increases) with increasing temperature while p-type
doping incorporation increases (resistivity decreases)
with increasing temperature. Increasing the deposition
rate, at fixed temperature and pressure, will result in a
decrease of n-type or p-type doping incorporation at a
fixed partial pressure of the doping species.
The choice of doping species is almost always deter­
mined by the type of epi layer (p-type epi requires B)
and diffusion caused by subsequent processing of the
wafer (P diffuses faster than As). Thus, the epi engineer
rarely has any freedom of choice with regard to doping
species selection.
SiH
6.1.3 Choice of Doping Species
deposition. Finally, the substrate surface crystal orienta­
tion may also motivate the pressure of deposition.
The growth of epitaxy over a substrate contain­
ing only B as the dopant species is best performed at
atmospheric pressure (AP). Figure 6.4 shows the transi­
tion region for p-type epi deposited on a p (heavily B
doped) substrate.
The impact of temperature on the transition region
for p epi on a p substrate is demonstrated in Figure 6.5.
As the temperature increases, the vapor pressure of
B, due to out-gassing from the substrate, also increases
B concentration (atoms/cm3)
typically found in selective epi processes or the epi-poly
process, may put a constraint on the maximum H2 bake
temperature, as discussed in Sections 6.2 and 6.5.
Transition width (μm)
PA R T I
0.1
0
900
1
1000
1100
0
1200
Temperature (°C)
Fig 6.5 Transition width temperature dependence for p-epi on a
p substrate.
●
Epi Wafers: Preparation and Properties
providing more available B for incorporation into the
growing epitaxial layer and thereby increasing the
transition width. As the deposition rate increases,
the transition width is reduced due to the surface of the
substrate rapidly becoming covered by the epi layer.
Based on Figures 6.3 and 6.5, it can be seen that the
deposition rate decreases, in the surface reaction rate
limited region of the Arrhenius plot as the tempera­
ture decreases. The combination of B out-gassing and
the change of deposition rate yields the resulting graph
of transition width vs. temperature, as shown in Figure
6.5. The issue of B autodoping is critical to the success­
ful growth of high resistivity p-type epi layers over heav­
ily doped p-type regions such as etch stops discussed in
Section 6.3.1.
The issue with n-type dopants is more complex.
Figure 6.6 compares AP processing with RP (reduced
pressure) processing for n-epi deposited over a substrate
with n As buried layers.
The impact on vertical transition region and lat­
eral autodoping is clearly demonstrated. This effect is
explained by the fact that the gas phase diffusion coef­
ficient of the As, which out-gasses from the substrate,
increases with decreasing pressure, thus providing a
means for the As to diffuse away from the wafer sur­
face, thereby reducing the opportunity for incorpora­
tion into the epi layer. Thus, operating at RP (P 100
torr) during epi growth over substrates heavily doped
with As, either as a buried layer or as the dopant in the
substrate itself, is extremely valuable in controlling As
autodoping.
1021
Epi
Substrate
1019
AP
1018
When P or B is used as a dopant in the substrate or
buried layer, pressure has very little impact on autodop­
ing. This is due to the rapid solid phase diffusion coef­
ficients of P and B, compared to that of As, which allow
the surface to be replenished with P or B as they out­
gas from the substrate.
In theory, Sb should behave similarly to As with
respect to autodoping. However, due to the very low
vapor pressure of Sb, the effect of pressure on transi­
tion region and lateral autodoping cannot be observed
by spreading resistance analysis. The use of SIMS (sec­
ondary ion mass spectrometry) on very thin layers of
undoped Si deposited over Sb buried layers does indeed
confirm that Sb and As behave similarly [3]. However,
the impact of RP on Sb autodoping is only significant
for layers having thicknesses of 100 nm or so and is,
therefore, not of interest for most MEMS applications.
There exists a phenomenon known as pattern shift
[1], which will cause a buried layer structure to appear
at a different position on top of the epi layer than its
actual location in the substrate. A diagram of this phe­
nomenon is provided in Figure 6.7 along with a graph
depicting the impact of pressure on pattern shift for a
substrate having a (111) surface orientation.
This effect is caused by anisotropic etching and growth
when a chlorosilane is used as the Si precursor. Substrates
which have a surface orientation of (100) do not suffer
from pattern shift due to the symmetry of the atomic
structure. It should be noted that (100)-oriented sub­
strates may be cut off-orientation, usually in the direction
of the (110) crystal plane. A small off-orientation of 1°
or so will not result in a significant amount of pattern
shift. Larger amounts of off-orientation, say 10° or more,
will result in a very observable pattern shift and may
motivate the use of RP processing.
Selective epitaxy is usually processed at RP (10–100
torr) in order to mitigate loading effects. Selective epi­
taxy is discussed in greater detail in Section 6.5.
The epi-poly process, which is often used in MEMS
structures, may need to operate at RP in order to
adjust the relative thickness of the monocrystalline and
2
1017
RP
Pattern shift ratio
Doping concentration (atoms/cm3)
1020
1016
1015
1014
0
1
2
Depth (μm)
Fig 6.6 ● Vertical and lateral autodoping over an n As
buried layer.
3
CHAPTER 6
1.5
1
Buried
layer
Apparent position
of b.l. after epi
epi
SiHCl3
Si substrate
SiH2Cl2
0.5
0
–0.5
10
100
1000
Pressure (torr)
Fig 6.7 ● Pattern shift on a (111)-oriented substrate using
chlorosilane Si precursors for epi.
93
Silicon as MEMS Material
The epi-poly process is used to deposit both mono­
crystalline and polycrystalline Si films on the wafer.
Epi (monocrystalline Si) will grow over the exposed
Si regions while polysilicon will grow over a dielectric
region (either SiO2 or Si3N4), as shown in Figure 6.8.
In this application a chlorosilane cannot be used for
deposition since the Cl atoms in the gas phase will result
in discontinuous growth over the dielectric regions [4].
Thus, SiH4 is most often used as the Si precursor for
thin (e.g., 2 μm) films. The use of SiH4 for depositing
thicker films will often result in unacceptable coating
of the fused silica process chamber enclosure. In order
to deposit films 2 μm in total thickness, an initial thin
layer of Si (e.g., 0.5 μm or so) is grown from SiH4.
The growth is then interrupted and the precursor is
switched to chlorosilanes such as SiHCl3. This strategy
allows much thicker layers of Si to be deposited with­
out excessive chamber coating and greatly improves the
overall productivity of the process. The switch from one
Si precursor to another occurs within the process recipe
requiring less than one minute to affect this change.
It is also possible to deposit a thin poly-Si or α­
Si layer over the dielectric in a low pressure chemical
vapor deposition (LPCVD) furnace prior to depositing
the epi-poly layer. A photolithography step and etch
step to expose the monocrystalline Si region which will
receive epitaxial growth must then follow this LPCVD
process prior to epi. Using this strategy enables a chlo­
rosilane to be used throughout the entire epi-poly depo­
sition process, since exposed dielectric regions will not
be present on the substrate surface.
The presence of dielectric structures on the substrate
surface may impose a constraint on H2 bake tempera­
ture, as discussed for selective epitaxy in Section 6.5.
Further, if a certain grain size is required for the depos­
ited polysilicon region, a specific temperature will be
necessary to achieve that grain size [4]. The impact of
deposition temperature on as-deposited, undoped polysilicon grain size, is shown in Figure 6.9 for a total film
thickness of 200–300 nm.
250
200
150
100
Amorphous
6.2 The Epi-Poly Process
Due to the different crystalline structures of epi­
taxy and polysilicon, these two layers will often grow
at different rates. At low temperatures (T800°C)
it has been observed during Si and SiGe epitaxy that
epi grows faster than polysilicon at AP [5]. As shown
in Figure 6.10, pressure can be used to control this dif­
ference in order to achieve a polysilicon region thicker
than the epi region or vice versa.
Poly-Si grain size (nm)
polycrystalline regions. The epi-poly process is discussed
in greater detail in Section 6.2.
50
0
500
700
900
1100
Temperature (°C)
Fig 6.9 ● As deposited poly-Si grain size from SiH4 at AP.
1.5
Si Deposited from SiH4 at 700°C
Si Poly:Epi growth rate ratio
PA R T I
1.0
0.5
0
20
40
60
80
100
Pressure (torr)
Fig 6.8 Deposition of Si on a substrate with oxidized regions
resulting in the epi-poly structure.
●
94
Fig 6.10 The impact of process pressure on the poly-Si:epi-Si
growth rate ratio.
●
Epi Wafers: Preparation and Properties
6.3 Etch Stop Layers
There are two epi layer structures that are used as
etch stops in MEMS applications. The most common
method is the use of a very heavily B doped epi layer,
as described in Section 6.3.1. A second method using
pseudomorphic SiGe is described in Section 6.3.2.
The choice of etch stop is dictated by the liquid phase
chemistry to be used in the etch process.
6.3.1 Heavily Boron Doped Epitaxial
Etch Stop Layers
Extremely heavily B doped epitaxy, referred to as p
epi, is often used as an etch stop layer when KOH is
used in a liquid phase etching solution [6]. An etch
selectivity of 1000:1 is observed for Si doped with B
at 1019 cm3 compared to a doping concentration of
1020 cm3, with the higher etch rate observed for the
lower doped material [6].
Achieving such high doping concentrations is no small
task. Although the solid solubility of B is approximately
1 1020 cm3 at 900°C increasing to 4 1020 cm3
at 1200°C [7] there are several issues which compli­
cate the process. Very high partial pressures of B2H6 are
necessary in the process chamber in order to dope the
epi layer to such high levels. Thus, a gas phase doping
source of 1–10% B2H6 in H2 is commonly used. Safety
concerns are paramount when using such a high concen­
tration source, since the TLV for B2H6 is 0.1ppm and
the LC50 is 80°ppm/h [8] (cf. the TLV of BCl3 is 1ppm
while the LC50 is 2541ppm/h, [9].
The decomposition of high concentration doping
sources often results in B being deposited on the fused
silica process chamber walls and is observed as black
lines. These deposits do not etch significantly in HCl,
but will sublime if heated to very high temperatures
(T 1200°C). Even so, it is not possible to clean the
chamber adequately with an HCl etch or by sublima­
tion to allow high resistivity epi layers (ρ 50 Ω-cm)
to be deposited with adequate control. Thus, the proc­
ess chamber used for p etch stops is often dedicated
to this heavily doped process and subsequent higher
resistivity epi layers must be grown in a separate process
chamber. Cleaning of the fused silica process chamber
walls must be accomplished by an ex-situ liquid phase
etch in an HF:HNO3 solution.
The behavior of dopant incorporation with tempera­
ture, discussed in Section 6.1.3, suggests that a high
deposition temperature and low deposition rate is ben­
eficial for incorporating high concentrations of B in Si.
This is indeed the case for p
epitaxy etch stop dep­
osition. Thus, deposition temperatures of 1150°C or
CHAPTER 6
more with reduced flow rates of SiHCl3, to reduce the
deposition rate, are used in these processes. Further,
since incorporation of the dopant is roughly propor­
tional to the partial pressure in the gas phase, high total
pressures of operation are desirable and, therefore, the
process is carried out at AP.
The B atom is very small compared to Si and, there­
fore, the large concentration of B in Si causes the p
epitaxial Si layer to have a smaller lattice constant than
that of undoped or lightly B doped Si. As a result, a
misfit dislocation matrix between the p
epi layer
and the substrate beneath it will often be observed as
shown in Figure 6.11 (Private comm. 2007, M. Tilli and
V. M. Airaksinen).
These line defects are present at the epi/substrate
interface and may cause a corresponding surface rough­
ness on the top of the epi layer. The smaller lattice con­
stant of the epi layer on top of the substrate can also
lead to bowing of the wafer.
The misfit dislocation matrix and wafer bowing issues
can be solved by counter doping the p epi layer with
Ge, which is a larger atom than that of Si. In theory, 5.6
atoms of Ge per atom of B are required in order to per­
fectly compensate for the effects of B [10]. Thus, a Ge
atomic concentration of 2.2% is needed to compen­
sate for a B doping level of 2 1020 cm3.
6.3.2 Pseudomorphic Epitaxial SiGe
Etch Stop Layers
The use of pseudomorphic SiGe as an etch stop is
typically driven by the need for very thin layers (e.g.,
100 nm) after etching [11]. The KOH etch associated
with p
etch stops is not sufficiently selective to
allow etching to stop in time to achieve the desired
Fig 6.11 ● Misfit dislocation matrix with 10 μm of 1 mΩ-cm B
doped Si Epi over a p- substrate [9].
95
Silicon as MEMS Material
layer thickness. Thus, other etch chemistries such as
ethylene diamine pyrolcatechol can be used to achieve
the desired post-etch layer thickness for BESOI struc­
tures [12]. Ge contents of 25–30% are required in
order to achieve the needed etch selectivity for such
structures.
Strain in the SiGe layer is used to achieve etch selec­
tivity. The layer must be pseudomorphic and, therefore,
very thin for high Ge content SiGe layers deposited on
Si. Further, the deposition and all subsequent processes
must be carried out at very low temperatures (e.g.,
T 700°C). The critical thickness for SiGe, calculated
using the Matthews-Blakeslee methodology [13], is pre­
sented in Figure 6.12.
The deposition of SiGe is usually performed at RP
(100 torr). However, for substrates without dielectric
features, it can be carried out at AP. Figure 6.13 demon­
strates the impact of Ge content of the film on deposi­
tion rate and activation energy.
Figure 6.14 shows the incorporation behavior of Ge
as functions of Ge partial pressure and temperature.
A detailed discussion of SiGe deposition is provided
in Chapter 10 of reference [1].
the BOX of the as-implanted and annealed sub­
strate of 2 μm. Increasing this thickness to a total of
10 μm via epitaxial growth is a common requirement.
Since the formation of a SIMOX substrate includes a
1250°C anneal, there are no fundamental temperature
limitations to the epi process. Therefore, the SiHCl3
process outlined in Figure 6.1 is commonly used for this
application.
100
Si from SiH4
Ea = 1.6 eV
Deposition rate (nm/min)
PA R T I
Ge from GeH4
Ea= 0.2 eV
10
SiGe, Ea = 1.0 eV
PSiH4:PGeH4= 20
6.4 Epi on SOI Substrates
Epi is commonly used to increase the thickness of Si
above a BOX in SOI wafers used for MEMS. SIMOX
substrates, often used in sensor applications such as
accelerometers [14], have a Si layer thickness over
800°C 700°C
600°C
1
0.9
1.0
1.1
1.2
500°C
1.3
1.4
1000/T (K–1)
Fig 6.13 ● Arrhenius plot of Si and SiGe deposition.
200
30
625°C
Ge content of SiGe alloy (%)
Critical thickness (nm)
150
100
50
20
700°C
10
SiGe layer
thickness limit
0
0
0
20
40
60
80
100
Ge content (%)
Fig 6.12 SiGe layer critical thickness for pseudomorphic
structure.
●
96
0
2
4
6
GeH4 partial pressure (mtorr)
Fig 6.14 ● Ge content of SiGe alloy as functions of the deposition
temperature and PGeH4.
Epi Wafers: Preparation and Properties
6.5 Selective Epitaxy and Epitaxial
Layer Overgrowth
Selective epitaxial growth (SEG), where deposition
occurs only on exposed Si regions and not on dielectric
materials, is achieved by creating a competition between
etching and deposition. This is accomplished by using
SiH2Cl2 and HCl together during the deposition proc­
ess. The ratio of HCl:SiH2Cl2 required to achieve
selectivity is a function of the deposition temperature
and the dielectric material present on the substrate.
Figure 6.15 presents the HCl:SiH2Cl2 ratio for selec­
tive growth in the presence of SiO2. If Si3N4 is present
on the substrate higher HCl:SiH2Cl2 ratios are required
and the net deposition rate is reduced.
Selective epitaxy is processed at RP to reduce the
impact of micro-loading effects. Figure 6.16 demon­
strates the impact of pressure on the SEG deposition
rate on features with sizes varying from 1 μm 1 μm to
500 μm 500 μm.
The mechanism behind the micro-loading effect is
simply one of mass transport via gas phase diffusion.
Large exposed Si areas consume more Si precursor than
small areas to achieve a given thickness. At high pres­
sure, the Si precursor becomes depleted while the HCl
and Cl etching species are enhanced due to decompo­
sition of the chlorinated Si precursor. This happens to
a greater extent over the larger exposed Si areas than
smaller areas. Further, at high pressure, the additional
etching species generated by decomposition of the
Si precursor cannot diffuse away from the surface as
quickly as at lower pressures.
There is also an impact on SEG deposition rate due
to macro-loading effects. The macro-loading effect is
2 Cl
2 ra
50
1
tio
De
po
sit
ion
rat
e
75
HC
25
0.5
HCl:SiH2Cl2 ratio
1.5
l:S
iH
Deposition rate (nm/min)
100
0
700
750
800
850
0
900
Temperature (°C)
Fig 6.15 ● Deposition rate and HCl:SiH2Cl2 gas phase ratio for
SEG in the presence of SiO2 dielectric.
Selective epi thickness (nm)
Other more complex epi processes, such as epi over
Al2O3, which was itself hetero-epitaxially deposited
over a Si substrate, can be used to build unique struc­
tures [15]. The growth of Si on Al2O3 requires the use
of a non-chlorinated Si precursor, since the presence
of Cl will remove Al from the material matrix. Thus,
SiH4, processed at AP and a deposition temperature of
900–1000°C, would be the recommended methodology
for films 2 μm in thickness. If a substantially thicker Si
epi layer is required, a chlorosilane can be used follow­
ing an initial deposition of 0.5 μm of Si from SiH4, as
described in the epi-poly process in Section 6.2.
It is convenient at this point to note that silicon on
sapphire (SOS) is processed in the same manner, using
r-plane Al2O3 substrates. Thus, the development of
unique RF MEMS structures, which require high Q
inductors in the device circuitry, are enabled through
epitaxial technology on a sapphire substrate.
CHAPTER 6
100
90
80
760 torr
200 torr
70 100 torr
60
25 torr
50
1×1
5×5
10×10
100×100 500×500
Feature size (μm× μm)
Fig 6.16 ● Micro-loading effects during selective Si epitaxy 50.
caused by the amount of bare Si exposed on the sub­
strate surface relative to the fraction of the surface cov­
ered by dielectric. As an example, a substrate with 99%
exposed Si will have a much lower overall SEG deposi­
tion rate than a substrate with only 1% exposed Si.
Epitaxial layer overgrowth is a technique which
exploits the characteristics of selective epitaxy and is
shown diagrammatically in Figure 6.17.
SEG Si grows only in the vertical direction until the
first atomic layer appears above the dielectric. Once
this occurs, Si grows both vertically and horizontally. As
a result, the region at the center of the dielectric will
be thinner than the regions adjacent to the exposed Si
regions.
The presence of SiO2 regions among single crys­
tal regions, essential for selective epitaxial structures,
may place a constraint on the maximum H2 bake tem­
perature used for surface preparation. This is due to
undercutting of the oxide, as described by Eqs 6.1 and
6.2, in Section 6.1.1 at temperatures 900°C. A dia­
gram of oxide undercutting is shown in Figure 6.18.
97
PA R T I
Silicon as MEMS Material
Epi after growth
SiO2
Epi during growth
Si substrate
Fig 6.17 ● Epitaxial layer overgrowth during and after deposition.
Oxide undercutting from excessive H2 bake
SiO2
Si substrate
Fig 6.18 ● Oxide undercutting of an SiO2 feature due to excessive
hydrogen bake temperature.
It is important to recognize that even when Si3N4
regions are used as the dielectric on the substrate sur­
face, a “pad-oxide” of SiO2 lies beneath the Si3N4 and,
therefore, undercutting may still occur.
6.6 Metrology
A brief overview of metrology as it applies to epitaxial
layers for measurements of thickness, resistivity and
defect densities is provided in this section. For greater
detail, please refer to Chapter 7 of reference [1] as well
as Chapter 16 in Part III of this handbook.
6.6.1 Measurement of Si Epi Layer
Thickness
Epitaxial thickness measurements are most often per­
formed using the FTIR (Fourier Transform Infrared
spectrometry) technique [16]. This method requires a
structure where the epi layer has a relatively low doping
concentration (Ndope 1018 cm3) and the region
underlying the epi layer has a high doping concentration
(Ndope 5 1018 cm3). The refractive index change
of Si at high doping concentrations provides the reflec­
tion from the epi/substrate interface necessary for form­
ing the interferogram essential to this measurement.
98
Most epi layers grown over heavily n-type or p-type
substrates meet the doping structural requirements for
FTIR measurements of epi layer thickness. It is not
necessary, however, that the entire substrate be heavily
doped. Indeed, it is often possible to measure epi thick­
ness over a substrate which has discrete buried layer
regions present, if the doping level and surface density
of the buried layers is sufficient to appear like a con­
tinuous region to the beam of incident IR radiation,
which is typically 1 mm in diameter for commercial
applications.
The FTIR technique is capable of measuring epi film
thickness from 0.5 to over 100 μm. Exceptionally thin
epi layers are often measured by spectroscopic ellip­
sometry [17] or SIMS [18]. Such techniques are rarely
needed for MEMS applications, with the notable excep­
tion of SiGe, as discussed in Sections 6.3.2 and 6.6.3.
6.6.2 Measurement of Epi Layer
Resistivity
The measurement of resistivity, or doping concentra­
tion, in epitaxial layers is commonly performed using
4-point probe [19], capacitance-voltage (CV) [20], sur­
face potential [21] and spreading resistance profiling
(SRP) [22]. In the extreme case of very thin films,
SIMS [18] can be used.
The 4-point probe measurement does not determine
resistivity directly but instead measures the sheet resist­
ance of the layer with which it is in contact. In order to
extract the resistivity of the epi layer, knowledge of the
layer thickness is required. The resistivity is then calcu­
lated by
ρ(Ω cm) 104 × t epi × R s
(6.6)
where tepi is the epi layer thickness (μm) and Rs
is the measured sheet resistance (Ω or Ω/square).
Measurement of the epi layer sheet resistance requires
that the underlying substrate be an insulator (e.g., SOI)
or of the opposite resistivity type of that of the epi layer
(p-type epi requires an n-type substrate and vice versa),
where the p-n junction between the epi layer and the
substrate electrically isolates the epi layer from the
substrate.
Often, a single epi layer thickness is used for calcu­
lating the on-wafer epi resistivity profile. However, in
order to accurately determine the epi resistivity profile,
the epi thickness at each point where the sheet resist­
ance is measured must be known. This creates a metrol­
ogy dilemma since epi thickness, measured by FTIR,
must be measured over a heavily doped substrate, as
discussed in Section 6.6.1. Further, the use of a heavily
doped substrate of opposite type can result in grossly
Epi Wafers: Preparation and Properties
1. The epitaxial layer thickness required to achieve
a doping concentration change from 50% of the
heavily doped substrate region to 2 times that of the
epi layer. This method yields a 5 μm transition width
in Figure 6.19.
2. The epitaxial layer thickness required to achieve
a doping concentration change of 3 orders of
magnitude from the heavily doped substrate into the
epi layer. This method results in a 2 μm transition
width in Figure 6.19.
3. The epitaxial layer thickness required to achieve a
resistivity change from 2 times that of the heavily
doped substrate region to 50% that of the epi
layer. Note that this is not the same as technique
1 due to degenerate doping effects at high doping
concentrations which lead to non-linearity in the
doping concentration to resistivity relationship. This
technique will result in a value slightly larger than
that of method 1.
SRP measurements are extremely useful since they
can be performed directly on the product substrate.
Precision of measurement is /–10% or so, and calibra­
tion to known standards is essential.
The CV technique often uses a mercury (Hg) dot for
formation of a Schottkey contact. This technique can be
performed on either p or n-type epi layers, however the
surface preparation technique for each is different.
1019
1018
Concentration (atoms/cm–3)
erroneous sheet resistance values if the epi layer is thin.
This is due to autodoping from the substrate which will
compensate the dopant in the epi layer. Thus, a lightly
doped test wafer is commonly used for sheet resistance
measurement by 4-point probe while epi thickness is
measured over a heavily doped substrate.
The 4-point probe technique is extremely precise com­
pared to other techniques discussed below. It is capable of
providing repeatable measurements approaching /–0.1%
over an extremely wide range of sheet resistances.
Depth profile resistivity information for the epi
layer is often determined by SRP [22]. The SRP tech­
nique requires that a small sample be beveled, with the
spreading resistance measured by two probes at differ­
ent positions along the bevel. The extraction of resis­
tivity from spreading resistance is dependent upon the
structure. Thus, if a heavily doped region is immediately
beneath the epi layer the algorithm is different from a
lightly doped region, which is in-turn different from a
region of different doping type [22].
Figure 6.19 shows the SRP of an n-type epi layer on
an n substrate.
Regrettably, there is no formal definition for the tran­
sition region from low to high resistivity (or from high
to low doping concentration). However, three tech­
niques are commonly used.
CHAPTER 6
1017
1016
2 μm
1015
5 μm
1014
0
5
10
15
Depth (μm)
Fig 6.19 ● 20 Ω-cm n-epi layer on n
Sb substrate.
P-type epi surface preparation can be achieved by
simply allowing the substrate to oxidize in air for 1
hour after epitaxial deposition. Alternatively, the sub­
strate can be prepared by a wash in SC-1 [23] solution
to motivate oxide formation. N-type epi layers often
require that the substrate surface be exposed to a hot
HNO3 solution for 1 hour and then rinsed prior to
making the CV measurement.
The CV measurement is limited by doping concen­
tration and thickness by avalanche breakdown and the
requirement of a minimum of 3 Debye lengths of sepa­
ration from the surface. A plot of the accessible resistiv­
ity vs. thickness is shown in Figure 6.20.
The CV measurement can often be applied to prod­
uct wafers. Epitaxial p-type on p substrates, or n-type
on n substrates can be measured with a single frontside contact in conjunction with a contact on the back­
side of the substrate (all dielectric materials must be
removed from the back of the substrate in order to
achieve a low resistance backside contact). The meas­
urement of opposite types (i.e., p epi on an n substrate
or vice versa) require a double front-side contact, since
the p-n junction will electrically isolate the backside of
the wafer from the region under measurement.
Although the CV measurement is not strictly
destructive, wafers exposed to the Hg probe are not
likely to be returned to the production line out of fear
of contamination.
Measurement of epi layer resistivity by surface
potential provides a noncontact technique applicable
99
Silicon as MEMS Material
PA R T I
imu
ma
cce
ssib
le d
epth
Max
10
Minim
um a
cc
Resistivity (Ω-cm)
essib
le
depth
100
1
0.1
1
10
100
1000
Depth (μm)
Fig 6.20 ● Limits of depth accessible to CV analysis.
to product wafers [21]. A beam of photons is chopped
to provide an alternating source of exciting radiation on
the wafer surface. The measured surface photo-voltage
is then related to the doping level of the Si near the
surface. Details of the method are discussed in Refs
[21] and [24]. The noncontact nature of this method
makes the use of SPV, also referred to as AC-SPV or
SCP, truly a unique, nondestructive method for resistiv­
ity measurement.
The use of SIMS [18] for doping concentra­
tion determination is relegated to very thin layers,
typically 100 nm. SIMS is an expensive technique,
often costing US $ 1000 per measurement on an out­
source basis. Accuracy and precision of the measurement
are in the order of / 10% at best, assuming a nearly
religious adherence to calibration methodologies. The
use of SIMS in MEMS applications is extremely rare.
6.6.3 Measurement of Ge in Si and SiGe
Epi Layer Thickness
The determination of Ge content in Si and SiGe epi­
taxial layer thickness can be accomplished by a number
of different techniques. Rutherford Backscattering
(RBS) [25], SIMS [18], spectroscopic ellipsometry
[26], photoluminescence (PL) spectroscopy [27], scan­
ning Auger [28] and X-ray diffraction (XRD) [29] are
commonly used. Of these techniques, RBS requires no
standards or calibration and is, therefore, often used for
100
generating standards for the others. RBS is capable of
providing both SiGe layer thickness and Ge composi­
tion information.
The use of SIMS requires careful calibration to
standards and, as previously noted, is an expensive tech­
nique. It does, however, provide the capability to deter­
mine depth profile information for Ge content as well
as B, P, As, C and O down to a limit of detection in the
1 1016 cm3 concentration range. Regrettably, not
all of this information can be obtained in a single meas­
urement scan, since an O sputtering beam must be used
for accurate B measurements and a Cs sputtering beam
must be used for O determination.
Spectroscopic ellipsometry has demonstrated a capa­
bility for measuring Ge content in Si and also SiGe layer
thicknesses. The use of multi-angle multi-wavelength
spectroscopic ellipsometry has been the most successful
approach. Fixed-angle, single wavelength ellipsometry
has shown some similar capability but does not appear
to have a sufficient number of degrees of freedom to
yield unique solutions to the mathematical models
needed for the independent determination of Ge con­
tent and SiGe thickness. The ellipsometry technique is
considered to be nondestructive.
Photoluminescence spectrometry is often carried out
at low temperatures (e.g., 77 K or even 4 K) in order to
achieve narrow well-defined spectral peaks of high inten­
sity due to the small energy distribution of electrons
at low temperature [30]. More recently, room tem­
perature PL has been demonstrated in order to make
this technique applicable as an in-line analysis tool for
semiconductor fabrication [31]. In general, the tech­
nique involves the optical excitation of carriers in the
crystal lattice which are then allowed to recombine in
the absence of photons. The resulting location of the
spectral peaks, as well as the peak width is used to
determine degree of strain, Ge composition and layer
thickness.
Scanning Auger is useful for the determination of Ge
in Si over a concentration range of 5–100% Ge. It is
primarily useful for high concentration Ge measure­
ments where RBS, SIMS, PL and scanning ellipsometry
have difficulties.
Double crystal XRD is a technique which measures
the crystal lattice and can, therefore, be applied to Ge
content in pseudomorphic SiGe films. This technique
is relatively fast, allowing a wafer to be profiled in less
than 1 hour. Commercial tools are available for full
wafer inspection and the technique is considered to be
nondestructive.
The reader is referred to Chapter 10 of reference
[1], in addition to Refs [18] and [25] through [31], for
further details regarding the measurement of Ge in Si
and SiGe layer thickness.
Epi Wafers: Preparation and Properties
6.6.4
Defectivity Measurements
The most distinguishing characteristic of epitaxy over
all other semiconductor manufacturing processes is
that epi, like substrate manufacturing, is a single crys­
tal process. Thus, many defects which may occur during
epi processing require inspection techniques outside the
norm for other processes.
Slip is the result of crystal plane movement caused
by thermally induced mechanical stresses in a substrate
during high-temperature processing. Figure 6.21 dem­
onstrates the geometric patterns of slip on (100) and
(111)-oriented substrates.
In extreme cases, slip can be observed by simply
looking at a wafer with unaided eyesight. More com­
monly, wafers are inspected using phase contrast micro­
scopy (sometimes referred to as dark field or Nomarski
microscopy) [32], automated optical laser-based surface
scanning tools [33] or x-ray analysis [34].
Stacking faults occur when a contaminant on the
wafer surface interrupts the growth of a contiguous sin­
gle crystal layer and polysilicon islands, surrounded by
single crystal silicon, are established. Figure 6.22 shows
the types of geometries observed for stacking faults on
(100) and (111) silicon. Stacking faults can be observed
using phase contrast microscopy [32].
In the case where slip is very difficult to observe, or
stacking faults are very small (due to a thin epi layer)
it can be desirable to decorate these defects with
chemical etching prior to observation in a microscope.
For (100)-oriented substrates the Secco [35], Schimmel
[36] or Wright [37] etch chemistries may be used.
Substrates having a (111) surface orientation require
(100) Si
(111) Si
Fig 6.21 ● Slip line geometries on (100) and (111) Si.
CHAPTER 6
the use of Sirtl [38] etch chemistry. Decorative etching
is always a destructive technique. The reader is referred
to an atlas of crystal defect micrographs [39] for a visual
depiction of many macroscopic crystal defects.
The measurement of metal contamination on the
substrate surface may be accomplished through sev­
eral methods. For Fe, surface photovoltage [40], is a
very sensitive technique which exploits the Fe-B bond
energy in p-type Si. Other metals can be detected using
a vapor phase decomposition (VPD) technique where
the native oxide on the surface of the wafer is captured
with a small amount of HF liquid, and the resulting
liquid is then analyzed spectroscopically by TXRF or
ICP-MS [41].
The measurement of particulate contamination on
the substrate surface is accomplished using automated
optical laser-based surface scanning tools [33].
Edge crown, shown diagrammatically in Figure 6.23,
occurs when mass transport effects at the wafer edge
in the epi deposition system cause increased epi growth
rate at this area, compared to the rest of the wafer.
Surface profilometry, using either a stylus which
contacts the wafer surface [42], or a non-contact opti­
cal profilometer, are the most common methods for
measuring edge crown [43]. Edge crown becomes a sig­
nificant issue as the epi layer thickness increases and is
usually only important for layers 10 μm in thickness.
6.7 Commercially Available Epitaxy
Systems
The choice of a single wafer or batch processing
approach for epitaxy is a compromise between film
properties, productivity and cost. At first blush one
might expect that productivity and cost are nearly syn­
onymous. However, the yield to specifications for sin­
gle wafer process tools is often higher than batch tools,
particularly when exceptionally unforgiving film prop­
erties are specified. Further, some epi process tools
can be purchased on a pre-owned basis for a much
Edge Crown
Epi Layer
Si substrate
(100)
(111)
Fig 6. 22 ● Stacking fault geometries on (100) and (111) Si.
Fig 6.23 ● Edge crown formation often associated with thick
(tepi 10 μm) epitaxial layers.
101
PA R T I
Silicon as MEMS Material
lower capital cost than a new tool, thus greatly reduc­
ing the cost-of-ownership (CoO) for processing due to
a lower depreciation contribution compared to a new
process tool. The reader is referred to the standard
SEMATECH model for CoO [44] in order to compare
the economics of various process tools.
A comparison of process throughput between a sin­
gle wafer and batch process chamber is provided in
Figure 6.24.
As the epi layer thickness increases, the batch proc­
ess tool provides a higher productivity than single wafer
processing. The crossover point is a very strong function
of substrate diameter, as well as the details and require­
ments of the process. Thus, it is impossible to quantify
this graph without a direct reference to a specific proc­
ess requirement and application. The following 2 exam­
ples illustrate the challenge between batch and single
wafer process tool choices.
A high-temperature process, for example, growing
20 μm of Si epi from SiHCl3 at 1100°C, would be car­
ried out at a deposition rate of 4 μm/min on a single
wafer process tool, while a batch process tool would
only be able to achieve 2 μm/min of deposition rate,
due to mass transport limitations in the large batch
process chamber. Further, the much larger thermal mass
of the batch process tool would require substantially
longer heat-up and cool-down times compared to sin­
gle wafer processing, as well as longer times for loading
and unloading a batch of wafers, compared to only one
wafer. On the other hand, the single wafer process tool
would, by necessity, need to have the chamber etched
Throughput (wafers/hour)
Single wafer epi system
Batch epi system
150 mm substrates
Batch epi system
200 mm substrates
Epitaxial layer thickness (μm)
Fig 6.24 Comparison between batch and single wafer process
tool productivities.
●
102
between each run, where the batch system may only
need to be etched once every 100 μm or so (every
5 runs in this example). Obviously, the batch process
tool has many more wafers present during the proc­
ess, but the precise number depends upon the design of
the batch tool and the wafer diameter. Clearly, a final
answer cannot be found without at least specifying the
details of the batch tool and the wafer diameter.
Low temperature processes have both similar and
different issues. A selective epi deposition at, say 800°C
or less, would likely have similar deposition rates for
both the batch and single wafer tools since the deposi­
tion would be reaction rate limited, not mass transport
limited. However, this deposition rate will be quite low.
Therefore even a 1 μm film may require tens of min­
utes of deposition, providing an advantage for the batch
tool. But the film thickness is so thin that the single
wafer tool would not require etching between each run.
The issues of wafer diameter and batch load/unload
time compared to single wafer processing still remain,
as do heat-up and cool-down time.
Based on these two abstract examples, neither thin­
epi low-temperature processes nor thick-epi hightemperature processes can be simply assigned to a single
wafer or batch process tool. The details of the process
specifications, wafer diameter and specific process tools
available must be considered carefully in order to make
the best choice.
6.7.1 Single Wafer Systems
Commercial single wafer process tools for Si epitaxy
first became available in 1988 with the introduction
of the Epsilon One from ASM Epitaxy [45], followed
by the introduction of the Centura HT by Applied
Materials in 1993 [46]. The development of an epi proc­
ess chamber around the requirements of a single wafer
enabled unprecedented control of many issues suffered
by batch process tools, most notably the control of slip
as well as film thickness and resistivity uniformities.
On-wafer film thickness and resistivity uniformities of
1 and 2%, respectively, are commonly achievable on
200 mm substrates. The basic design concept of the sin­
gle wafer epi process tool is shown in Figure 6.25.
Single wafer process tools use a wafer holder, or sus­
ceptor, of very low thermal mass compared to batch
processing systems. This allows much faster heating and
cooling of the process chamber, which in turn greatly
reduces the thermal budget of the process. The use of
rapid thermal chemical vapor deposition (RTCVD) is
essential for high productivity in such architectures.
The process chambers used in RTCVD single wafer
epi systems are very small in volume, which provide for
a much higher mass transport capability compared to
Epi Wafers: Preparation and Properties
batch epi tools. Thus, substantially higher growth rates
can be achieved in the mass transport limited regime, as
much as 5 μm/min at 1150°C in a single wafer system
compared to 2 μm/min in a batch process tool using
SiHCl3. Further, autodoping from the substrate is less
in single wafer systems due to the increased mass trans­
port allowing dopant species emanating from the sub­
strate to escape from the region adjacent to the growing
epi layer.
The use of a load-lock in conjunction with the proc­
ess chamber enables loading and unloading of the sub­
strate at high temperatures, typically in the range of
700°C to as much as 1000°C. The use of such high
load/unload temperatures is critical to productivity as
it reduces the heat-up time and, far more importantly,
greatly reduces the cool-down time to unloading. Due
to these high temperatures, and the environment in
which the substrates are handled, all substrate load­
ing and unloading is automated. A very significant sec­
ond benefit of load-locked loading/unloading is that
such a configuration enables low-temperature epitaxy,
by eliminating exposure of the process chamber to air.
This allows the process chamber to maintain a very low
background partial pressure of oxygen and water vapor,
essential to the successful low-temperature processing
of Si and SiGe. Finally, the low background water vapor
partial pressure essentially eliminates stacking fault
formation (other than oxygen induced related stack­
ing faults or OSF) since oxide free surfaces are easily
achieved by hydrogen bake prior to epitaxy.
The single wafer approach to epitaxy has become the
work-horse of the Si and SiGe epi industries since the
CHAPTER 6
mid-1990s. However, as previously mentioned, it may
not be the optimum choice for some epi processes due
to economic and productivity concerns.
6.7.2 Batch Systems
Epitaxial deposition systems using batch technology
were the dominate methodology for substrate diame­
ters of 150 mm and less. To a first order approximation,
a batch epi reactor processes a fixed area of Si (m2) per
run, whereas a single wafer tool processes one wafer per
run, regardless of substrate diameter. On a throughput
basis, the batch process tool has an obvious advantage at
smaller substrate diameters.
The inductively heated pancake reactor, shown in
Figure 6.26 [47], uses RF energy to heat the SiC coated
susceptor via eddy currents. This design was hampered
by the backside of the wafer being at a higher temper­
ature than the front-side, which resulted in bowing of
the wafer and slip. Cutting a spherical profile into the
pockets where the wafers reside greatly reduced this
problem.
The radiantly heated barrel reactor in Figure 6.27
[48] further reduced the occurrence of slip by heating
the substrates from the front using tungsten-halogen
lamps.
The inductively heated barrel reactor in Figure 6.28
[49] uses RF energy to heat the susceptor. In this
design, the induced current flows around the susceptor,
unlike the RF pancake where the susceptor is heated by
eddy currents.
N2 purged
load-locks
Fused silica
bell jar
N2 purged
wafer xfr
chamber
Wafer xfr
robot
Process
module
Process
module
SiC coated
graphite
susceptor
Process
module
Fig 6.25 Single wafer epi system architecture showing up to 3
process modules on an integrated tool.
●
Gas
exit
Gas
inlet
RF coils
Fig 6.26 ● The inductively heated “pancake.”
103
Silicon as MEMS Material
PA R T I
Fused silica
bell jar
Gas
inlet
Wafer
Waf
er φ
Batch
100 mm
125 mm
150 mm
200 mm
>30
32
21
5
Fig 6.29 ● The PE2061S inductively heated barrel epi system
from LPE Epitaxy. Used by permission. (Courtesy LPE)
Lamps
SiC coated
graphite susceptor
Gas
exit
Fig 6.27 ● The radiantly heated “barrel.”
Gas
inlet
Fused silica
bell jar
RF
coils
Wafer φ
125 mm
150 mm
200 mm
Batch
10
8
5
Fig 6.30 ● The PE3061D inductively heated pancake epi system
From LPE Epitaxy. Used by permission. (Courtesy LPE)
The PE2061S, shown in Figure 6.29 and PE3061D,
shown in Figure 6.30, have claimed process capability
approaching that of single wafer process tools [49, 50].
The CSD EpiPro-5000, shown in Figure 6.31, claims
on-wafer thickness and resistivity uniformity capability
of, nominally 1% and 2%, respectively, for processing on
150 mm substrates [51].
As noted previously, the best choice of epi process
tool requires consideration of the technical require­
ments, as well as productivity and economic perform­
ance. A detailed assessment of what is required and
what is desired is essential to realizing the optimal
choice.
6.8 Summary
Gas
exit
SiC coated
graphite susceptor
Fig 6.28 ● The inductively heated “barrel.”
104
Si epitaxy processing for MEMS applications is most
often performed at AP and high temperature using
Epi Wafers: Preparation and Properties
Fig 6.31 ● The EpiPro-5000 inductively heated pancake epi
system from CSD Epitaxy. Used by permission. (Courtesy CSD)
SiHCl3 as the silicon precursor. Doping of the epi layer
is accomplished in-situ using B from B2H6 for p-type
CHAPTER 6
epi and As or P from AsH3 or PH3, respectively, for
n-type epi.
Epi layers used for etch stops may be either heavily
p-type doped, where NA 1020cm3, or pseudomor­
phic SiGe, with Ge contents of 30%. The choice of
epi structure used for the etch stop is based on etch
chemistry and the layer thickness required.
The epi-poly process, where epi is deposited over
single crystal Si and polysilicon is deposited over a die­
lectric region, is often used in MEMS structures. If the
dielectric region is not covered with Si prior to deposi­
tion, the use of a non-chlorinated Si precursor, usually
SiH4, is essential to successful processing.
Selective epi can be used to grow Si only on exposed
Si regions without deposition on adjacent dielectric
areas. Epitaxial layer overgrowth is based on the selec­
tive epi process methodology and can be used to grow
lateral monocrystalline silicon regions over dielectrics.
Although single wafer epi systems dominate the Si
semiconductor industry as a whole, batch epi systems
still play an important role for MEMS. Thick epi lay­
ers require long deposition times and the CoO for sin­
gle wafer processing, compared with batch processing
for thick epi layers, can far out-weigh the performance
advantages of single wafer systems for cost sensitive,
high volume commodity MEMS products. Hard, honest
cost and technical performance evaluations are essential
to choosing the correct epi system architecture.
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7
Chapter Seven
Thick-Film SOI Wafers:
Preparation and Properties
Jari Mäkinen
Okmetic Oyj, Vantaa, Finland
7.1 Introduction
Silicon-on-insulator (SOI) is a semiconductor structure
consisting of a layer of single crystalline silicon separated
from the bulk substrate by a thin layer of insulator. In
SOI wafers the insulator is almost invariably a thermal
silicon oxide (SiO2) layer, and the substrate is a silicon
wafer. Depending on the type of application, the silicon
film can be very thin (50 nm for fully depleted transis­
tors), or it can be tens of micrometers thick. Likewise,
the buried oxide thickness ranges from tens of nanom­
eters to several micrometers. Manufacturing methods
of wafers vary accordingly. Silicon-on-sapphire (SOS)
is another SOI technology that has some further advan­
tages for fabrication of CMOS circuitry in microwave
applications because of the low-loss dielectric substrate.
The SOI structure was created for the first time using
silicon on sapphire. SOI technology (here referring to
forming the SOI structure on a silicon wafer) was devel­
oped during the 1980s for high-frequency and radiationhard circuit applications [1]. The concept was quickly
adopted for the manufacture of pressure sensors [2] and
acceleration sensors, and it is now widely accepted as a
basic technique for fabrication of sensor elements. Thin
SOI wafers for mainstream CMOS applications as well
as thick-film SOI wafers typically used for microelectro­
mechanical systems (MEMS) applications are commer­
cially available from several silicon wafer manufacturers.
SOI layer thickness of 1 μm and above is classified as
thick-film SOI. Device types using thick SOI include
bipolar devices, high voltage and smart power applica­
tions, and MEMS. Because of the thick SOI and buried
oxide layers, the wafers are generally fabricated by
direct wafer bonding. MEMS processes that use thickfilm SOI wafers as a substrate have greatly benefitted
from the development of the deep reactive ion etch­
ing (DRIE) techniques, which enable etching of deep,
high-aspect-ratio structures. Fundamentally, they com­
bine typical features of surface micromachining such
as comb-like structures and thick device layers of bulk
micromachining, enabling sensor elements with small
lateral dimensions. Especially when combined with
DRIE technology, thick-film bonded SOI wafers bridge
nearly the entire range of microstructure thicknesses
between the conventional surface and bulk microma­
chining techniques, using only single-crystalline silicon
as mechanical material. The technology is not limited
by the crystal planes since the SOI layer is patterned
with dry etching that is not affected by the crystal ori­
entation. The mechanical layer is originally from a bulk
silicon wafer; therefore it is relatively free of mechani­
cal stresses. Moreover, the mechanical properties of
single crystalline silicon are consistent, and they do not
depend on processing of the wafers.
In this review the methods of manufacturing bonded
thick-film SOI wafers used in MEMS applications are
described, and typical properties of wafers are sum­
marized, focusing on data from large-series production
of wafers. Emphasis is on the approach that relies on
mechanical back-grinding and optical precision polish­
ing for final thinning of the SOI film. A comprehensive
discussion of semiconductor wafer bonding technology
and applications can be found in Refs [3–5], and with a
historical perspective in Ref. [6].
107
PA R T I
Silicon as MEMS Material
7.2 Overview of SOI
In the following paragraphs an overview of SOI technol­
ogies with emphasis on MEMS applications is given.
7.2.1 SOI Technologies
The interest in SOI wafers for integrated circuits came
from the intrinsic performance advantages including
high speed, low dynamic power consumption, and sup­
pression of the parasitic bipolar latch-up effects. At a
fixed operating voltage, circuit speed is up to 30% faster
and the power consumption can be reduced by a fac­
tor of three compared with what one can achieve with
a standard bulk silicon or epitaxial silicon substrate. The
relative advantage over bulk silicon grows even bigger
when low operating voltages are used. These advantages
are due to two main features, the greatly reduced para­
sitic junction capacitance and the complete dielectric
isolation of individual transistor elements. With sup­
pressed latch-up it becomes easier to reduce the transis­
tor size and to increase the packing density. Today SOI
is a mainstream CMOS technology with the roadmap
(International Technology Roadmap for Semiconductors
[ITRS]) for SOI wafers, and with 300-mm diameter
wafers for sub-65-nm technology. An exhaustive review
on the use of thin SOI material for VLSI CMOS tech­
nology can be found in Refs [7] and [8].
Historically, several manufacturing techniques were
proposed for producing SOI structures. The key chal­
lenge was to produce a high-quality single crystalline
silicon film of device grade on top of silicon oxide. The
early techniques included zone-melt recrystallization
(ZMR) techniques. In ZMR the substrate is a silicon
wafer that is thermally oxidized, and the oxide is pat­
terned to form openings through which the silicon sur­
face is exposed. A thin, amorphous or polycrystalline
silicon layer is deposited on the surface and melted.
When the layer solidifies, a single crystal growth is initi­
ated at the silicon surface. Epitaxial growth is seeded by
the substrate, and the growth proceeds laterally from the
openings until the lateral growths meet to form a contin­
uous layer. Epitaxial lateral overgrowth (ELO) relies on a
similar kind of approach of growing epitaxial silicon lat­
erally on a thermal oxide layer with openings to seed the
single crystalline growth. It was overly difficult using any
of the early techniques to reach the yield and reliability
needed for large-series production of wafers.
The industry has settled on two manufacturing meth­
ods. The first is SIMOX (Separation by Implantation of
Oxygen), and the other is bonded silicon on insulator
(BSOI). Both technologies provide the capability of
preparing a thin, dielectrically isolated silicon film over
a large-diameter silicon wafer. In SIMOX, the buried
108
oxide layer is formed by high-dose oxygen ion implanta­
tion into a silicon wafer. At a sufficiently high dose the
implanted oxygen atoms can produce a stoichiometric
silicon oxide (SiO2) layer. The structure resulting from
oxygen implantation strongly depends on the dose and
the implant ion energy. During implantation the wafer
is kept at the temperature of 400–600°C to anneal the
crystal defects and to prevent the crystalline to amor­
phous transition of silicon. In the subsequent high
temperature annealing step, which takes place around
1350°C, most crystal defects are annealed; small oxy­
gen precipitates dissolve, leaving only the buried oxide
layer, and the interface between the buried oxide and
silicon becomes planar. The original standard-dose
SIMOX material was produced with an oxygen dose of
2 1018 cm2, yielding a 200-nm thick silicon layer and
a 400-nm thick BOX layer. The defect density of early
SIMOX wafers in excess of 1 109 cm2 was very
high. More recent processes combine multiple low-dose
implantation and annealing steps, and use the internal
oxidation process in order to produce material with
thinner BOX and superficial silicon layers, to reduce the
defect density in the top silicon layer and to increase
the manufacturing throughput [9].
Wafer bonding techniques include the bonding and
etch-back SOI (BESOI), Smart Cut, and Epitaxial
Layer Transfer (ELTRAN) processes. In all these
approaches the process starts with two silicon wafers
bonded together. The major difference lies in thin­
ning of the structure until the top wafer is reduced to
its target thickness. A straightforward approach relies
on back-grinding and precision polishing of one of the
wafers. This method is much applied to thick-film SOI
wafers for MEMS applications, and it will be discussed
in detail. In the bonding and etch-back technique a
selective chemical etch is applied. A highly doped
p-type ( p
) epitaxial silicon layer is used as an etch
stop. A second n- or p-type epitaxial silicon layer that
will ultimately form the SOI layer is grown on top of
the first p
epitaxial layer. This technology attracted
attention because of its high crystal quality compared
with early SIMOX wafers that were developed around
the same time. The newer thin-film technologies, Smart
Cut and ELTRAN, developed independently at about
the same time. The Smart Cut technique uses hydro­
gen implantation and wafer bonding, followed by split­
ting of a thin layer along the hydrogen implantation line.
It is applied for large-scale manufacturing of thin-film
SOI wafers for the mainstream CMOS processes. The
ELTRAN process was developed by Canon. In its origi­
nal form it was a bonding and etch-back type of process
making use of the extremely high etch rate of porous
silicon; later on the process was developed to enable
splitting of the bonded wafer pair through the porous
silicon layer.
Thick-Film SOI Wafers: Preparation and Properties
Applications can be broadly divided into two areas,
CMOS and bipolar devices. This division is seen in the
types of SOI wafers used. Thin-film SOI wafers suitable
for low-power, low-voltage, high-speed CMOS applica­
tions are limited to SIMOX and Smart Cut methods
because of the thickness uniformity requirements. SOI
wafers with a 50–80-nm thick silicon layer on 100–140­
nm buried oxide are in large-scale production. Typical
thickness uniformity requirement is 5% or better.
Bipolar applications use thicker SOI in the range of
1–2 μm and above. Thick-film SOI can be produced by
the BESOI method or, in the higher thickness range, by
the back-grinding and polishing method. Starting from
an SOI wafer prepared by one of the thin-film processes
and growing an epitaxial silicon layer is another option
to increase the SOI layer thickness.
7.2.2 Processing of Mechanical Devices
on SOI
Quite apart from the electronic applications, where the
dielectric isolation of transistors is the primary advan­
tage, SOI technology has found applications in MEMS.
It provides a precise control of several material param­
eters and enables unique device configurations that are
not easy to make otherwise. A simplified process for
fabrication of micromechanical devices on thick-film
SOI wafer using DRIE is illustrated in Figure 7.1. The
SOI layer is etched from the front face of the wafer
Figure 7.1 ● A simplified process of MEMS fabrication on an SOI
wafer by DRIE with only one mask level, modified from Ref. [10].
The SOI layer is thick, most commonly from 4 to 100 μm. The
buried oxide (thermal SiO2) layer acts as an etch stop for DRIE
because of the high selectivity that can be achieved to silicon
etches, and it confines the isotropic HF release etch.
CHAPTER 7
with DRIE retaining near-vertical sidewalls. The bur­
ied silicon oxide acts as an effective etch stop for the
anisotropic dry etch. After plasma stripping of the pho­
toresist, HF etching of the buried oxide layer is used to
release the mechanical structures. Selective etching of
thermal oxide confines the isotropic release etch to the
oxide layer. Basically very few mask levels are needed to
fabricate working devices. Figure 7.2 shows an example
of such a micromechanical element on a 20-μm thick
SOI film. It is a detail of a bulk acoustic mode resonator
showing the narrow gap for electromechanical coupling.
The structures were etched using high-aspect-ratio
reactive ion etching to form the 0.5-μm wide gap with
an aspect ratio of 40:1. The buried oxide was etched
away via the openings in the device layer to release the
mechanical structures. Buried oxide is also used for
mechanical anchoring of the fixed structures, and it pro­
vides electrical isolation.
SOI wafers for MEMS are nearly always fabricated by
wafer bonding. Figure 7.3 shows a sampling of silicon film
and buried oxide thicknesses based on a large number of
SOI wafer specifications for MEMS applications. For all
practical purposes the SOI film thickness varies from 4 to
200 μm. The most common range in this sample is from
5 to 20 μm, but in nearly half of the applications the SOI
layer is thicker than 20 μm. The buried oxide thickness
is typically from 500 nm to 2 μm. In bonded silicon the
thickness of the insulating material can be independently
determined prior to the bonding process. This is valid
for all wafer bonding techniques discussed above. Of the
Figure 7.2 ● A detail of a bulk acoustic mode resonator showing
the narrow gap for electromechanical coupling. The SOI layer is
20 μm thick and the gap is 0.5 μm in width. The structure was
fabricated with DRIE using the buried oxide for etch stop and for
release etching of the laterally moving parts.
Source: Courtesy of J. Kiihamäki, Micronova, VTT.
109
>100
75 – 100
50 – 75
40 – 50
20 – 30
10 – 20
4 – 10
≤4
30 – 40
Silicon as MEMS Material
PA R T I
>4
3.0 – 4.0
2.0 – 3.0
1.0 – 2.0
0.5 –1.0
≤ 0.5
Frequency
(a)
BOX film thickness (μm)
Figure 7.3 ● (a) SOI layer and (b) buried oxide thicknesses in
bonded SOI wafers for MEMS use. Data are based on a large
number of SOI wafer specifications covering a wide range of
microsystem applications.
different manufacturing techniques, back-grinding and
polishing can readily produce thick-film SOI in this
range. A characteristic property of the mechanical thin­
ning process is that the thickness variation of the SOI
film is not correlated to the film thickness. For the low­
est thickness range the silicon film can be realized also by
starting with thin-film SOI and then growing a layer of
epitaxial silicon. As the thickness increases, the cost of
growing thicker epitaxial layers becomes prohibitive and,
in addition, the thickness uniformity becomes worse. Use
of SIMOX wafers is very limited because of the maxi­
mum buried oxide thickness around 400 nm, which is
thin for the majority of MEMS designs and processes. As
a result, the bond, grind-back, and polish type of thickfilm SOI wafers are prevailing in MEMS use.
This summary does not permit detailing MEMS
devices based on bonded SOI wafer technology.
Numerous examples can be readily found from the liter­
ature. Instead, a few examples demonstrating the ways
of using the SOI structure in processing of microsystems
are given below.
110
MEMS fabrication on thick-film SOI substrates
has greatly benefitted from the development of mod­
ern plasma etching techniques for DRIE of silicon.
The most commonly applied method of deep silicon
dry etching is the Bosch process [11], which relies on
switching between two plasmas, one for isotropic etch­
ing of Si (SF6) and one for deposition of a fluorocarbon
polymeric layer for passivation (C4F8). It allows etching
of vertical sidewalls at geometries that are controlled by
standard photolithography masks, which is a key to a
high-aspect-ratio microstructure technology. Compared
to wet etching of silicon, more accurate dimensional
control is available when using DRIE, which also allows
the overall dimensions of MEMS devices to shrink. The
etch depth control is more challenging in DRIE process­
ing than, for example, in anisotropic wet etching. In
optimum conditions it is possible to achieve 0.1% uni­
formity over the wafer in wet etching, but in DRIE
etching 1% uniformity is difficult to achieve with largeseries production processes. Standard values are in the
range of /1… /2.5%, and in addition the etch
rate depends on the aspect ratios. The buried oxide of
an SOI substrate can be used as etch-stop because the
silicon oxide selectivity is over 100:1 in fluorine-based
plasmas used for silicon etching. The SOI device layer
uniformity then practically defines the etch depth.
DRIE to the buried oxide layer leads to charging of the
oxide in the bottom of the trench by accumulation of
the positive ions. Charging causes sideways etching of
silicon near the interface and notches are formed. Toolwise the problem has been solved by pulsing of the RF
bias as the buried oxide layer is approached to allow
for time to discharge the oxide surface. Interestingly,
horizontal etching by the notching effect has also been
employed to release etching of comb-like structures in
SOI wafers [12].
The first example is a silicon micromechanical resonator
for RF applications (Figure 7.4) demonstrating release of
large mechanical structures [13]. It is a two-dimensional
bulk-acoustic-wave resonator with a 10-μm thick resona­
tor plate with dimensions 320μm 320μm. The compo­
nent was made on thick-film SOI wafer using DRIE. The
resonator plate was released by HF etching of the buried
oxide film through 1.5-μm diameter holes arranged in a
square matrix to perforate the resonator plate.
Another example demonstrates the use of the buried
oxide as an etch stop and sacrificial layer to form vacuum
cavities in SOI wafer [14]. It uses a standard thick-film
SOI wafer as a starting material. The vacuum cavities
are formed by first etching an array of micrometer-sized
openings through the device layer by DRIE using BOX
as etch-stop. A conformal permeable polysilicon film
is deposited over the surface. The buried oxide layer
is locally removed by HF etching through the pinholes
inherent in the thin polysilicon film. The openings are
Thick-Film SOI Wafers: Preparation and Properties
CHAPTER 7
Figure 7.4 ● A silicon micromechanical bulk resonator made on SOI wafer using DRIE. The resonator plate dimensions are
320 μm 320 μm, and SOI film thickness is 10 μm. The HF release etching was done through 1.5-μm diameter holes (detail on the
resonator plate on right) arranged in a square matrix to perforate the resonator plate [13].
Source: Courtesy of J. Kiihamäki, Micronova, VTT.
then refilled with low-pressure chemical-vapor-deposited
(LPCVD) polysilicon, leaving the cavities in low vacuum.
After etch-back, a single crystal silicon surface is
revealed. The top view infrared photograph of a cavity
structure in Figure 7.5 shows the etched and sealed hex­
agonal cavity as well as the plugs to close the openings
that were used for buried oxide etching. The “plug-up”
approach provides several attractive features. It forms a
vacuum cavity on wafer level, for example, for pressure
sensors with internal pressure depending on the closing proc­
ess. Risk of damage to metallization by HF release etch­
ing is eliminated, and no lithography over high surface
topography is needed. The process uses IC-compatible
process steps only, and monolithic integration with
CMOS is possible. The approach was demonstrated for
making a CMOS integrated pressure sensor [15].
Two further examples include a very high-aspect-ratio
structure etched in a thick-bonded SOI layer, sharing
features both from surface and bulk micromachining,
and a buried cavity etched into silicon under a silicon
diaphragm [16, 17]. DRIE provides a way of processing
similar comb-drive devices with finger capacitors that
are frequently used in surface micromachining for accel­
eration sensors or gyroscopes with capacitive readout
but using much thicker active layers. Today’s processes
make possible etching through a 100-μm SOI layer with
a 4-μm gap in large-series sensor element fabrication,
implying a 25:1 aspect ratio. This approach provides a
high moving proof mass and high capacitance generated
from the large area of the vertical sidewalls of the finger
capacitors with highly stable capacitive detection.
A buried cavity under a silicon diaphragm is illus­
trated in Figure 7.6. This has been a primary applica­
tion of direct bonding in fabrication of MEMS devices
[16], but it has more recently been integrated also into
the thick-film SOI wafer manufacturing process. To
Figure 7.5 ● Top view near infrared micrograph of a hexagonal
buried cavity that is formed by HF-etching the buried oxide in an
SOI wafer through thin permeable polysilicon film that is grown in
micrometer-sized openings etched through the device layer. After
etching the buried oxide is complete, the holes in the structure
layer are filled with low-pressure CVD polysilicon (see text). The
dark ring indicates that the silicon membrane above the cavity is
deflected by the ambient pressure [14].
Source: Courtesy of J. Kiihamäki, Micronova, VTT.
form a buried cavity under a single crystalline silicon
diaphragm, a cavity is first etched in the handle silicon
wafer. A second wafer is bonded to the cavity wafer
and thinned using any of the techniques described later
in this section, including mechanical grinding and pol­
ishing or selective etching. After intermediate proc­
ess steps, which can also include integration of bipolar
or CMOS circuitry, the mechanical structures can be
released by dry etching at the very end of the process.
The physical dimensions in this process can be varied
over a wide range, and they can be controlled with high
accuracy. This approach provides several attractive fea­
tures including release of the mechanical structure at
111
PA R T I
Silicon as MEMS Material
process times that are not practical when growing very
thick thermal oxides.
BESOI wafers or thick-film SOI wafers based on
mechanical thinning of the device layer are fabricated in
three basic process steps:
1. Formation of the device layer. When the thinning
process is based on nonselective chemical–
mechanical polishing, a bare polished silicon wafer is
used. In BESOI wafers the etch-stop can be formed
by ion implantation or more commonly by silicon
epitaxy by growing a two-layer epi structure.
2. Direct bonding of the polished face of the device
wafer with another silicon wafer with thermal oxide,
and annealing the wafer pair. The bonded wafer
consists of the handle silicon wafer, thermal SiO2
layer, and the device wafer.
3. Thinning down the device layer employing the
Figure 7.6 ● A sequence of process steps to form buried cavities
under silicon diaphragm by wafer bonding. Cavities are etched
by DRIE in the handle silicon wafer and the wafer is bonded to a
second wafer (a). The second wafer is thinned using any of the
techniques applied in standard bonded SOI wafer manufacturing,
such as mechanical grinding and polishing or selective etching
(b). The mechanical layer is patterned with dry silicon etching,
which releases the mechanical devices (c). Between steps (b) and
(c), for example, implantation to form piezoresistors, metallization,
or integration of CMOS circuitry can be performed.
the very end of the process with no sacrificial etching,
and suppression of electrical and mechanical interaction
between the moving microstructures and the substrate.
The remainder of this chapter will describe fabrica­
tion methods for bonded SOI wafers and basic proper­
ties of wafers, concentrating on thick-film SOI wafers.
7.3 Silicon Wafer Parameters for
Direct Bonding
Bonded SOI wafers are composed of two silicon wafers
bonded face-to-face with a buried oxide layer. One can
choose the SOI parameters quite freely as the manufac­
turing process allows a wide range of independent wafer
parameter values. The type, thickness, resistivity, and
crystal orientation of the SOI layer are independent of
those of the handle silicon wafer. The oxide is formed
by thermal oxidation before the wafer bonding step,
and the thickness of the oxide can be selected according
to the considerations of the design of the MEMS device
or its fabrication process. The limits to the buried oxide
thickness are associated with hydrogen-related voids
in the case of very thin oxides (thickness 100 nm) or
112
back-grinding and polishing or selective etching
techniques.
In this section the factors that influence direct wafer
bonding are discussed; the different techniques for thin­
ning the device layer are presented in the following sec­
tions. The requirements for direct wafer bonding are
similar for all BSOI wafer manufacturing processes.
The first reports of direct bonding of polished silicon
wafers without an external force such as hydrostatic
pressure or electric field were reported in 1985–1986
by Lasky [18] and Shimbo and colleagues [19]. In
bonded SOI wafer fabrication the bonding is nearly
always between two hydrophilic silicon or thermal sili­
con oxide surfaces. The contacting force is caused by
attraction between OH-groups and water molecules on
the hydrophilic surfaces, and hydrogen-bridge bonds
between the adsorbed water molecules across the two
wafer surfaces can form. Once initiated, the bonding
area or wave spreads across the entire surface of the sili­
con wafers. The process is sensitive to the properties of
the silicon wafers, and success of direct bonding depends
on the flatness of the wafers, quality of the wafer sur­
face, and the wafer cleaning process. Mirror-polished
silicon wafers used in the semiconductor industry today
meet such requirements for reasons not associated with
direct wafer bonding. The approach based on thinning
by mechanical back-grinding and polishing starts from
prime polished silicon wafers. The other techniques
(BESOI, Smart Cut, or ELTRAN) need additional
processing steps such as silicon epitaxy or ion implan­
tation before bonding the wafers, and those processes
must be designed to meet the requirements of direct
bonding. The fact that silicon wafers are thin also works
in favor of direct bonding, making the requirements less
stringent than in the case of bonding thick bulk parts.
The direct bonding process requires that tight flatness and roughness tolerances are maintained on the
Thick-Film SOI Wafers: Preparation and Properties
wafers. Macroscopic wafer scale geometry variation such
as wafer bow and wafer flatness deviations are accommo­
dated by elastic deformation of the silicon wafers. Effects
of wafer shape on direct bonding have been predicted by
comparing the reduction of the total surface energy to
the increase of the elastic strain energy accumulated in
the bonded wafers [20–22]. The requirement for direct
bonding is set by the work of adhesion (energy available
per unit area to bond to silicon surface W 2γ, where γ
is the surface energy of silicon) that must be sufficient to
overcome the increase of the elastic strain energy. Turner
and Spearing [22] gave the criterion for direct bonding as
(dU/dA)W, where U is the elastic energy accumulated
in the wafers, A is the area of the bonded interface, and
W is the work of adhesion. This relationship says that the
bond front will spread as long as the change in the strain
energy per unit area is smaller than the work of adhesion.
The quantity dU/dA is a function of the geometry of the
wafers and the elastic properties of silicon, whereas W is
determined by the type of the two bonding surfaces.
One problem in correlating the models with the
wafer shape is that the standard measurements of the
wafer geometry, such as the total thickness variation
(TTV), bow, and warp usually do not give information
on the length scale of the variation. Turner and Spearing
[22] used their model to predict the effect of wafer
bow on direct bonding of blank silicon wafers. For one
thing it showed that if bonding begins, the bonding area
will advance to the edge of the wafer pair. The other
important point to note is the strong dependence on
the wafer thickness, which was explicitly noted also in
the work of Tong and Gösele [21]. The wafer diam­
eter does not affect wafer bonding assuming identical
wafer thicknesses and curvature of the wafers. In prac­
tice the effect of wafer diameter comes from standard
wafer thickness, which correlates to the wafer size and
increases with the wafer diameter. Finally, a specific
case of 100-mm-diameter silicon wafers implies that for
a thin wafer (thickness ≤500 μm) the bow can be sev­
eral tens of micrometers without being an obstacle to
direct bonding. Like the bow of the wafer, gaps arising
from the TTV of the wafers can be quite easily closed
up by the elastic deformation assuming hydrophilic sili­
con surfaces. Conventional silicon polishing methods
can produce wafer flatness in the range of 2–3 μm or
smaller, and with the double-side polishing techniques
the standard process capability for TTV is 1.0 μm. In
grind-back and polish SOI or BESOI wafer manufac­
turing the device wafer is removed apart from the thin
silicon layer sitting on top of the silicon oxide film, and
one can start with 500-μm-thick device wafers even in
the case of a 200-mm wafer diameter. Such wafers can
quite easily accommodate the surface flatness variation
of a few micrometers by elastic deformation in wafer
bonding.
CHAPTER 7
In addition to the wafer geometry, surface nanoto­
pography is the other flatness parameter that influences
direct wafer bonding and is accommodated through
elastic deformation of the wafers. It measures the sur­
face topography on a length scale of fractions of a mil­
limeter to approximately 10–20 mm, and typically has
peak-to-valley heights of nanometers or tens of nanome­
ters. The amplitude and pattern of surface nanotopogra­
phy is to a large extent defined by the type of polishing
(single-sided or double-sided) and the details of the
polishing process. In single-side polishing, because of
the wax mounting of the wafers, the topography of the
etched back surface of the wafer and the ceramic carrier
are transmitted to the polished front surface. In a dou­
ble-side polishing process the wafer is floating, which
basically yields significantly lower surface topography.
In semiconductor device manufacturing, surface topog­
raphy can result in variation of the thickness of dielec­
tric films after CMP polishing, with a potential negative
effect on the circuit performance and the process yield,
and in the latest generations of devices wafer flatness
control requires the control of topographical features at
the nanometer scale.
Turner et al. [23] estimated the effect of surface nan­
otopography on direct bonding by comparing the elastic
strain energy to the work of adhesion. The conclusion
was that such topographical features have only a very
small effect on bonding of hydrophilic silicon surfaces,
and that such variations are easily accommodated by
elastic deformation of the wafers. The change of strain
energy is small compared even with typical work of
adhesion values of 10–20 mJ/m2 reported for direct
bonding of hydrophobic silicon surfaces. Compared with
typical wafer scale shape variations induced by the TTV
or wafer bow, surface nanotopography leads to much
smaller values of accumulated elastic strain energy in
direct wafer bonding. Clearly, standard polishing proc­
esses yield silicon wafers with surface nanotopographical
features that are unlikely to cause bonding failures.
The wafer-bonding-induced local elastic strain in
bonded wafers arising from surface nanotopography can
be imaged using X-ray topography [24, 25]. X-ray topog­
raphy of the bonded interface exhibits a roughness-like
image of periodic strain contrast. The length scale in
the strain pattern resulting from elastic strain qualita­
tively corresponds to the surface topography. Most of
the deformation occurs already during direct bonding of
wafers at room temperature, and the high temperature
annealing has little influence on the local stress or the
strain pattern. The residual stresses induced by surface
nanotopography have been detected and measured also
by the infrared grey-field polariscope (IR-GFP) [26].
It utilizes transmission of circularly polarized infrared
light and measures optical interference generated by
stress-induced birefringence. In the presence of stress,
113
PA R T I
Silicon as MEMS Material
transmitted light becomes elliptically polarized, and
change in polarization depends on the applied shear
stress. Figure 7.7 shows a shear stress image of a bonded
silicon wafer from IR-GFP. It reveals the character­
istic stress contrast pattern that is related to the sur­
face topography. The contrast pattern does not appear
in the area of the large void of Figure 7.7a that is not
bonded, indicating that the residual stress across the
noncontacted area is constant. No local stress variation
is expected, as there is no surface-topography-induced
deformation of the wafer in the area of a void.
Another parameter critical to direct wafer bonding is
the surface roughness. It is usually quantified by local
microscopic roughness in very small wavelengths of less
than 10 μm and is typically measured using atomic force
microscopy (AFM). In this regime wafer bonding capa­
bility can no longer be characterized by a single parame­
ter, such as work of adhesion, which describes the initial
bonding for wafer deformations significantly larger than
1 nm. For known material properties and surface adhe­
sion force the critical surface roughness at which direct
bonding of two pieces will become possible has been
estimated using a statistical surface roughness model
[27], and an empirical correlation between bonding
of silicon wafer surfaces and the roughness spectrum
from AFM has been established [28]. An experimental
analysis shows a strong correlation between the surface
roughness characterized as the root-mean-square (rms)
average roughness and the effective work of adhesion
[29]. The bonding energy was reported to decrease by
a factor of four as the rms-roughness increases from
0.2 to 0.5 nm (Figure 7.8). Compared, for example, to
the power spectral density which relates information
about the amplitude and spatial frequency of surface
roughness, the use of rms average roughness to predict
direct bonding of surfaces is oversimplified. However,
in practice hydrophilic polished silicon surfaces will
bond spontaneously if the surface rms-roughness is less
than 0.5 nm. In direct bonding of hydrophilic surfaces
the surface roughness is accommodated by water mol­
ecules adsorbed on the surface, and by the viscous flow
of the interface oxide at elevated temperatures. In case
of microscopic surface roughness, elastic deformation of
the silicon wafers is insignificant.
1.0
Bonding energy
0.8
0.6
0.4
0.2
0.2
Figure 7.7 ● Infrared gray-field polariscope (IR-GFP) images
of a bonded wafer [26]. (a) The shear stress image shows a
contact stress field at the center of the void, a clearly delineated
noncontacted area, and a residual stress pattern characteristic of
wafer nanotopography. (b) Shear stress image of fusion-bonded,
double-side-polished wafers with large surface nanotopography.
(c) A plot of shear stress vs. distance along the line scan in (b).
114
0.3
0.4
RMS surface roughness (nm)
0.5
Figure 7.8 ● Bonding energy as a function of rms surface
roughness. Surface roughness was measured with AFM, and it
was modified by means of chemical etching (BOE or BOE/KOH).
Bonding energy is normalized with respect to a reference wafer
work of adhesion. Source: Data was replotted from Ref. [29].
Thick-Film SOI Wafers: Preparation and Properties
Optical mirror polishing of silicon surfaces with col­
loidal silica slurries can meet this requirement quite
routinely. A typical rms value of the roughness of final
polished silicon surface is in the range of 0.1–0.2 nm or
smaller. The final polishing steps used as the last step
in production of prime silicon wafers are designed to
produce extremely smooth surfaces that are crucial for
semiconductor device manufacturing, in particular the
gate oxide quality.
The techniques for wafer cleaning must be able to
remove contamination on surfaces including particles,
organic surface contamination, and metal contamina­
tion. Another function of the final cleaning step is to
make the wafer surface hydrophilic, which is the pre­
ferred state of the surface for direct bonding. Direct
bonding of hydrophobic surfaces is possible, but the
highly reactive silicon surface could present a problem.
After HF dip the surface attracts particle and organic
contamination from the HF solution, DI water used for
rinsing, and from the ambient air. Moreover, the work
of adhesion at room temperature is significantly lower
for hydrophobic silicon surfaces. Particle contamina­
tion is responsible for the voids formed during the
contacting of wafers at room temperature. Even a rela­
tively small particle can result in a large noncontacted
area around the particle. The void size has been inves­
tigated by measuring the crack length as a function of
the step height using wafers with steps defined by pho­
tolithography techniques [30]. A step with a height
of 0.5 μm between two standard silicon wafers leads
to noncontacted area with a diameter of several mil­
limeters. Thin wafers deform more easily, and reduc­
tion in wafer thickness leads to a significant decrease
in the size of the noncontacted area. The change in
the sizes of particle originated voids in bonded wafers
remains generally small after annealing at elevated tem­
peratures. One should note that much of the particle
contamination is of organic origin, and it is likely that
such particles break down or decompose at elevated
temperatures.
Organic contamination in form of hydrocarbons
adsorbed on the silicon surface usually does not lead
to void formation at room temperature. However, sur­
face hydrocarbons act as nucleation sites for voids that
are generated upon annealing the wafers above 200°C
for the most part by diffusion of hydrogen. Examples
of procedures to remove surface organic contamination
to prevent the void formation include exposure of the
wafers to O2 or Ar at elevated temperatures [31] or
treatment of silicon surfaces with periodic acid (H5IO6)
aqueous solution, which efficiently removes relatively
short-chain hydrocarbon molecules from silicon surfaces
[32]. Trace metal contamination or airborne molecu­
lar contamination from the clean room air, introducing
boron or phosphorus onto the surface of the wafers, can
CHAPTER 7
be harmful since these elements can change the electric
properties of the silicon material.
The requirements for surface cleaning in wafer bond­
ing are fully matching with those in VLSI technology.
Therefore, the wafer cleaning procedures based on wet
chemistry that are commonly used in semiconductor
industry are commonly applied. They are specifically
designed to remove particle contamination, organic
contamination as well as surface metals. To give an idea
of the cleaning process capability, the particle counts
assuming a critical particle size of 90 nm are some tens
of particles on a 200-mm-diameter wafer, and today much
smaller particle sizes are considered. Typical metal contam­
ination levels for critical surface metals are much smaller
than 1 1010 atoms/cm2. Also, the cleaning proc­
esses are designed to not increase the surface rough­
ness which is very critical to wafer bonding. The SOI
and advanced CMOS technologies require extremely
low silicon and silicon oxide consumption in the clean­
ing steps with the same or higher performance in terms
of particle and metal removal efficiency as the thickness
of the SOI film will decrease to 20 nm. Considering
the SC1 step as an example, the tendency is to further
decrease the NH4OH concentration, which leads to
smaller consumption of silicon and practically no change
in the roughness of the silicon surface.
In conclusion, standard mirror-polished silicon wafers
are good for direct bonding applications in terms of
the wafer geometry and the surface quality. The wafer
cleaning techniques that are in use in VLSI technology
are consistent with the requirements of direct bond­
ing. The critical features and the processes in wafer
manufacturing were originally developed for reasons not
related to direct wafer bonding, but primarily to meet
the requirements of optical lithography, gate oxide qual­
ity and the uniformity of thin dielectric films.
7.4 Fabrication of Thick-Film
BSOI by Mechanical Grinding and
Polishing
The sequence of steps required to make thick-film SOI
wafers by mechanical thinning of the device layer is
illustrated in Figure 7.9. After wet cleaning and surface
inspection, which form the last two process steps of sili­
con wafer manufacturing, a thermal oxide is formed on
the wafers. This oxide later becomes the buried oxide
of the SOI structure. The oxide thickness is defined by
the requirements of the application, and it most com­
monly falls in the range from 400 nm to 2 μm (Figure 7.3).
In direct bonding the wafers are aligned, keeping a nar­
row gap between them. In SOI wafer manufacturing
the alignment is most commonly based on mechanical
115
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Silicon as MEMS Material
Device wafer
Handle wafer
SOI film is originally part of the bulk silicon wafer.
Cleaning to eliminate particle and surface
contaminants.
Serves as a substrate for the SOI wafer. Typically a
double-side polished wafer with good thickness
uniformity. Final cleaning of wafers.
Oxidation
Thermal oxidation to form a surface oxide layer that
later becomes the buried oxide of the SOI structure.
Direct bonding
Cleaning, mechanical alignment, and contacting of the
wafer pair integrated in an automated wafer bonder.
Bonding in controlled gas ambient or in low vacuum.
Post-bond inspection by transmission of infrared light.
Thermal annealing
Annealing of the bonded wafer pairs at 1100–
1200°C. Inspection of the bond quality by scanning
acoustic microscopy.
Surface grinding
Two-step grinding of the device silicon wafer to a
target thickness using a high-precision grinder.
Polishing
CMP polishing of the device silicon layer to its final
thickness. Stock removal and final polishing steps.
Cleaning and final inspection
Figure 7.9 ● The sequence of steps required to make a thick-film SOI wafer by bonding and mechanical thinning of the silicon device
layer. Typically there are some additional process steps (e.g., to form the edge of the bonded SOI wafer, not shown).
flat-to-flat or notch alignment. The initial contact
between the wafers is created at a single point so that
the bonding wave can propagate in a controlled way
across the wafer surface. A batch of bonded wafers is
loaded in a furnace and annealed to a temperature of
1100–1200°C. Stepwise mechanical thinning of the
device silicon wafer includes a sequence of steps of
mechanical grinding and chemical–mechanical polishing
for final thinning of the SOI film. Both are single-wafer
processes. The final cleaning steps and inspection of the
SOI wafers are basically similar to those for standard
prime silicon wafers, including measurement of wafer
116
geometry and inspection of surface quality. The differ­
ent practical aspects of the process are discussed below.
7.4.1 Direct Bonding of Wafers
A bonded SOI wafer process typically starts with a
wet chemical cleaning of the silicon wafers in a sequen­
tial immersion batch process. Silicon wafer cleaning
sequences based on RCA cleaning provide a practical
method for cleaning silicon surfaces for direct wafer
bonding. RCA cleaning consists of two solutions, SC-1
Thick-Film SOI Wafers: Preparation and Properties
(Standard Clean 1), which is a mixture of ammonium
hydroxide, hydrogen peroxide, and DI water (NH4OH:
H2O2:H2O), and SC-2, which is a mixture of hydro­
chloric acid, hydrogen peroxide, and DI water (HCl:
H2O2:H2O). Adaptation of these cleans to the full
RCA cleaning sequence includes removal of organic
compounds by sulfuric peroxide, SC-1 step to remove
particles, and SC-2 step to remove metallic impuri­
ties [33]. Between the cleaning steps the native oxide
is frequently removed from the wafer using dilute
hydrofluoric acid. The RCA-based wet-chemistry
cleaning processes for VLSI technology are designed
to remove particles and other contamination, to make
a hydrophilic surface, and to not increase the surface
roughness. These requirements are fully compatible
with wafer bonding.
Variations on the cleaning sequence exist and fre­
quently some steps of the cleaning process are cut out,
or alternative cleaning solutions or solution composi­
tions are used to achieve higher cleaning efficiency or
to simplify the cleaning process. Examples of such
improvements and modifications include use of sur­
factants in chemicals to control the surface roughness,
ozone cleaning as an alternative to the H2SO4/H2O2
step, combined use of megasonics to enhance particleremoving capability, removal of hydrogen peroxide from
SC-2 as HCl is effective in removing metallic impurities
by itself, or addition of HCl to dilute HF to increase
capability to remove metallic impurities and omission of
SC-2 [33]. Figure 7.10 gives an example of a wet clean­
ing process that is based on the RCA cleaning cycle and
that has been successfully used in thick-film bonded
SOI wafer manufacturing. It only uses the SC-1 clean­
ing solution which removes particles efficiently, but is
effective also for removing light organic contamina­
tion, and uses dilute HCl to remove metallic impuri­
ties. Drying of the wafer can be a source of substantial
particle contamination if it is not performed in a cor­
rect way. In Marangoni drying the wafer is pulled from
the rinse through a layer of liquefied IPA. The wafer is
drawn from a water bath while passing a flow of nitro­
gen with a trace of IPA along the wafer surface. IPA
will dissolve in the water, lowering the surface tension.
The surface tension gradient induces a Marangoni flow
towards the bulk liquid. This will lead to drying of the
surface during the slow raising of the wafer. The details
of the wafer cleaning processes adopted for large-series
SOI wafer production are infrequently disclosed, and it
is possible that different proprietary surface treatments
are in use to routinely obtain void-free bonded wafers.
In Figure 7.11, scanning acoustic microscope images
of the bonded interface after annealing at various tem­
peratures are shown, based on the cleaning process in
Figure 7.10. No interface voids are generated upon
annealing at any of the intermediate temperatures. Voids
CHAPTER 7
APM (SC-1) + Megasonic
Removal of organic contamination and particles.
DI water rinsing
Dilute HF (DHF)
Removal of surface oxide
DI water rinsing
APM (SC-1) + Megasonic
Removal of particles.
DI water rinsing
Dilute HCl
Removal of metallic impurities.
Drying
Marangoni drying.
Figure 7.10 ● An example of a wet cleaning process for blank
silicon wafers for direct wafer bonding. It is a typical wafer
cleaning sequence based on modified RCA cleaning.
are frequently formed during heat treatment of the
bonded wafer pair, mainly due to hydrogen molecules
that are released in the reaction of water in the bonding
interface with silicon. Besides the cleaning process, the
presence of the thermal oxide forming the buried oxide
of the SOI wafer reduces formation of hydrogen-related
voids. The open structure of thermal silicon oxides can
incorporate hydrogen and other impurities resulting in
significant reduction of gases in the interface. In case
of very thin oxides (thickness 100 nm) formation of
voids in the bonded interface is more difficult to avoid,
and in silicon-to-silicon bonding void generation almost
invariably occurs at 300–400°C anneal [3].
One key function of the wafer cleaning process is to
make the wafer surface hydrophilic to enable hydrogen
bonding between the surfaces. The hydrophilic proper­
ties of a silicon surface originate from termination of
the surface by polar OH-groups. The aforementioned
cleaning solutions typically form a new, clean native
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PA R T I
Silicon as MEMS Material
Figure 7.11 ● Scanning acoustic microscope images of the
bonded interface after annealing at 600°C (a), 800°C (b) and
1100°C (c). Buried oxide thickness was 500 nm. The wafer
cleaning process is basically similar to that described in
Figure 7.10.
oxide on the wafer surface after oxide removal in dilute
HF. Such native oxides are highly hydrophilic [34]. For
example, the SC-1 cleaning step after surface oxide
removal forms a thin chemical oxide on silicon with a
contact angle 10° indicating a highly hydrophilic OHterminated surface. In case of a native oxide formed by
wet chemical cleaning, the reaction to form OH-groups
is facilitated by the fact that the surface siloxane bonds
are strained and react readily with water. The surface of
thermally grown oxide is essentially hydrophobic with
only a few OH-groups. Commonly the very last clean­
ing step is integrated into the wafer bonder. It can be
simply a megasonic DI water cleaning but dilute chemi­
cal cleaning processes are also in use.
The initial bonding of wafers right after chemical
cleaning is performed in a class ISO 3 or better (class 1,
old classification) clean room environment. The time
between the last cleaning step and bonding is control­
led to avoid airborne molecular contamination on wafer
surfaces. One example of such contamination is boron.
In wafer bonding boron becomes trapped in the bonded
interface and changes the resistivity or even the type of
silicon material next to the bonded interface by boron
diffusion. The amount of boron present in the bonded
interface increases with the time the wafers are left under
cleaning benches. A very low concentration of boron on
the surface, on the order of 1 1010 atoms/cm2, is suffi­
cient to significantly change the resistivity of 10 Ohm-cm
118
silicon material within the diffusion length of boron.
Consideration of the material in the filters used in the
clean room, adding chemical filters that absorb boron, and
choosing clean room materials that generate less boron
can suppress the amount of airborne molecular contami­
nation on the wafer surface.
Wafer pairs are aligned and an initial contact is
formed after which bonding proceeds spontaneously
across the wafer. In SOI wafer manufacturing mechani­
cal flat-to-flat (or notch-to-notch) alignment of the two
wafers is usually applied. Alignment accuracy is typi­
cally 50 μm for X, Y-displacement and 0.1° for the
rotation of the wafers. The initial contact point can be
created at the periphery of the wafers or the initial con­
tact can start in the center of the wafers. In both cases
it is critical to assure that bonding starts from a single
point and that the bonding wave can propagate laterally
from that point onwards across the entire interface.
Bonding under low vacuum (103…102 mbar) is
also used in SOI wafer manufacturing. A strong adhe­
sion at low temperatures has been reported for vacuum
bonding [35]. High fracture surface energies can be
reached already at temperatures as low as 200°C. It,
however, requires very long annealing times not prac­
tical in large-series wafer manufacturing. Bonding in
vacuum has the advantage that no mechanical force
is needed to initiate the bonding between the wafers.
Also, there is an experimental finding that in some cases
bonding under reduced pressure tolerates higher sur­
face topography than bonding under normal pressure.
The differences between vacuum and ambient air direct
wafer bonding were attributed to the increase in the
effective contact area and the lack of trapped nitrogen
or air when contacting the wafers in low vacuum [36].
The pressure also has a strong effect on the speed of
the spreading of the bonded area as the lateral bonding
speed is mainly determined by pressing the ambient gas
between the wafers close to the propagating bonding
front. Typical speed at ambient pressure is in the order
of 10 mm/s, and it increases up to 1 103 mm/s when
the pressure is 0.1 mbar [37].
For large-series industrial production of SOI wafers,
automated production equipment typically integrates
some of the process steps for direct bonding. Cleaning
of the wafers, mechanical or optical wafer alignment,
prebonding at room temperature, and initial analysis of
the bonding quality are incorporated in a bonding tool
enabling cassette-to-cassette wafer processing. The sin­
gle wafer cleaning stations combine, for example, brush
scrubbing, megasonic cleaning, and wet chemical cleaning
procedures; for automated SOI wafer bonding there are
also systems with process control for megasonic cleaning,
drying, alignment, and bonding in one process chamber.
The bonding process is performed automatically, and
there are options for wafer bonding in controlled gas
Thick-Film SOI Wafers: Preparation and Properties
ambient or in vacuum. Initial postbond infrared inspec­
tion of the bonding quality is most commonly checked
on the basis of the transmission of infrared light. It can
detect voids larger than 0.5–1 mm in diameter and allows
for macroscopic bond quality inspection.
In case of two hydrophilic silicon or silicon oxide
surfaces the bond strength right after direct bond­
ing at room temperature is around 0.1 J/m2; values
reported in the literature typically fall in the range of
0.06–0.2 J/m2. Thermal treatment of the bonded wafer
pair is carried out to form a permanent chemical bond
whereby the surfaces attach through strong siloxane
(Si–O–Si) bonds. A typical condition for the heat treat­
ment is 1100–1200°C. It is often done in wet oxygen
ambience but the ambient gas has no influence on the
bond strength. After 1100°C annealing the strength of
the bonded interface is very similar to that of a ther­
mal SiO2/Si interface, with a crack opened between the
bonded wafers propagating randomly inside the oxide
and along the two interfaces.
The mechanism of hydrophilic wafer bonding and the
reactions occurring on the bonding interface are quite
well understood. It is based on analysis of the surface
energy and correlation of those energies with the dif­
ferent chemical interactions that can take place in the
interface and on spectroscopic information primarily
from the multiple internal transmission infrared spec­
troscopy (MIT-IR). Comprehensive summaries of the
bonding mechanism can be found, for example, in Refs
[3] and [38]. The initial joining is due to hydrogen
bonds between the water molecules bridging the two
hydrophilic surfaces. The surface energy around 0.1 J/m2
is in fair agreement with the energy of the hydrogen
bond characteristic of OH groups in water and the den­
sity of OH groups on hydrophilic surfaces, which for a
fully hydroxylated silica surface is 4.6 1014 cm2. MIT­
IR measurements indicate from three to five layers of
molecular water trapped in the interface, and from one
to two layers of OH-groups. Annealing of the bonded
wafer pair at T 300°C leads to diffusion of the water
through the oxide layer to the Si/SiO2 interface where
it reacts to form additional low-temperature oxide and
molecular hydrogen. The loss of water from the inter­
face region enables direct coupling of the OH-groups on
the opposing surfaces and strong bridging Si–O–Si bonds
begin to form. At a given temperature in this range the
surface energy increases with time, and the stable state of
the bonding interface is achieved only after long anneal­
ing times. The saturated value of the surface energy is
almost constant in the temperature range of 150–800°C
[3], indicating that the greater part of the silanol groups
in the contacted area are converted to siloxane bonds
already at the lower end of this temperature range. The
contacted area over which bonding occurs is limited due
to the surface roughness. In the temperature range from
CHAPTER 7
300°C to 800°C remaining water from the interface
region is lost allowing direct coupling of the OH groups
to form Si–O–Si bonds. Water molecules formed in the
reaction cause further oxidation of silicon by diffusion
to the Si/SiO2 interface. Complete closure of the inter­
face between the two surfaces occurs above 800°C. It is
facilitated by the reflow of the silicon oxide layer taking
place at this temperature range. Hydrogen is lost from
the interface region by diffusion into the silicon bulk.
Infrared spectroscopy indicates formation of strained
Si–O–Si bonds after annealing at 1100°C, and suggests
that annealing to 1200°C and above allows relaxation of
the strained bonds.
Infrared spectroscopy showed that the same mecha­
nisms are generally applicable in the bonding interface
between two thermally oxidized silicon wafers [39].
The bonded SiO2/SiO2 interface is typically annealed at
a higher temperature, 1200°C, to reach the final bond­
ing strength.
In large-series SOI wafer production the qual­
ity of the bonded interface is routinely checked using
scanning acoustic microscopy (SAM). It has the ability
to detect very narrow planar gaps in the bonded inter­
face on the basis of reflection of the focused acoustic
wave. Typically a pulse-echo image is created by ana­
lyzing the echo that returns when ultrasonic pulse is
launched at the bonded wafer pair, and the same trans­
ducer is used for sending and receiving. In case of an
air gap practically all acoustic energy is reflected from
the buried solid-air interface. The elapsed time before
the return indicates depth, and a data gate can be set
to analyze only the echoes from the bonded interface.
The intensity of the reflected energy is recorded at each
measuring point during the scan across the wafer area,
and a defect map is created. The technique is totally
equivalent to acoustic inspection of plastic encapsu­
lated microelectronics devices (e.g., for failure analy­
sis). The ultrasonic frequency that is used in bonded
wafer inspection is typically from 100 MHz to a maxi­
mum of few hundred MHz. The smallest detectable
defect size in a bonded wafer pair is from 5 to 10 μm.
In routine process control measurements the minimum
size of void that is detected is significantly larger, and
it is mainly limited by the scan resolution to have the
required throughput in a production environment. As an
example, Figure 7.12 summarizes the SAM inspection
of bonded wafers taken from medium- and large-series
production of thick-film SOI wafers. The processes
for wafer cleaning and direct bonding were essentially
similar to those described above. In more than 90% of
the wafers SAM cannot detect any voids larger than
20–30 μm. The average number of voids corresponds
to the void density per unit surface area that is signifi­
cantly smaller than 0.01 cm2. The total area of voids in
a wafer is typically much less than 1 mm2.
119
PA R T I
Silicon as MEMS Material
(a)
1 mm
(b)
Figure 7.12 Voids of different sizes are detected by SAM in
bonded SOI wafers. The smallest detectable defect size limited
by the scan resolution was 20–30 μm. The sample is taken from
large-series wafer production and includes more than 1000
bonded wafers. Wafer diameter is 150 mm.
●
Noncontacting areas in the bonded interface are gen­
erally caused by particles and organic contamination
due to poor wafer cleaning procedures and poor wafer
surface condition. At the present stage of thick-film
SOI technology voids are not a fundamental issue, but
they remain one of the yield-determining factors in the
wafer manufacturing environment. Voids become criti­
cal when extremely low failure rates are required and
no defects larger than a given critical defect size are
allowed in the bonding interface. Sensor elements that
require hermetic sealing and that cannot be fully tested
for very low leakage rates for some critical automotive
applications provide a good example.
In wafer production the most common way of speci­
fying the voids in thick-film SOI wafers makes use of
transmission of infrared light. Both IR light transmis­
sion and SAM offer nondestructive quick scans but are
unable to detect microscopic voids. Another technique
that is used in MEMS for inspection of defects beneath
the surface that can be used for bonded SOI wafer
inspection is infrared light microscopy. IR-GFP provides
another angle to trapped particle detection in the bond­
ing interface (Figure 7.13). Trapped particles and mac­
roscale defects associated with particles can be found
by imaging the residual stress-fields around the defects.
The residual stress at the particle locations is typically
from less than 1 MPa to several MPa [40].
The different methods to determine the bond
strength and their limitations were reviewed by Vallin
et al. in Chapter 19 of this book and in Ref. [41]. The
most commonly applied methods include the double
cantilever beam (DCB) measurement, the tensile test,
the Chevron test, and the blister test methods. Until
now any nondestructive methods have not evolved.
Of the different methods the DCB measurement, also
referred to as the crack opening method, is frequently
120
“a”
“b”
“c”
“d”
Figure 7.13 ● Magnified IR-GFP images: (a) IR-transmission
image, (b) shear stress image. Figure 7.13b shows a macroscale
defect, where a single particle “a” has generated a noncontacted
area, and several other particles are tapped in the bonding
interface. The maximum residual stress is present at
location “d” [40].
used and is the only method that is easily suited to
wafer production. In DCB measurement a thin blade is
inserted into the bonded interface to open a crack, and
the length of the crack is measured. The bond strength
is derived considering the structure as a system of two
cantilever beams that are bent. The crack that is opened
is atomically sharp allowing quantification of the frac­
ture toughness. The repeatability of the measurement
in measured crack length was estimated to be less than
5%, implying a relative standard deviation in fracture
toughness of 20%. To get reproducible results the crack
opening should be automated and the measurement
should be performed in an inert environment to avoid
stress corrosion that is typical of cracks in brittle mate­
rials. It is related to breaking of the strained bonds at
the crack tip by interaction with water, and leads to the
crack growth during the crack length measurement of
wafer bonds [42]. A major drawback is that it is difficult
to insert a blade between two strongly bonded wafers,
and direct bonded silicon wafers annealed at 1000°C or
above tend to break. The method is therefore mostly
limited to low bond strengths.
In the Chevron test the load is applied to a specimen
with a chevron-shaped notch, and an atomically sharp
Thick-Film SOI Wafers: Preparation and Properties
crack is formed at the tip of the chevron. Successful
measurements have been demonstrated on very small
test specimen in millimeter size (micro-Chevron tests).
It can be used to measure both strong and weak bonds.
With blister testing, internal cavities sealed by wafer
bonding are pressurized to apply load on the bond­
ing interface. The bond strength is estimated from the
pressure required to initiate the fracture. Both methods
can produce good repeatability and reproducibility, and
using the micro-Chevron test structure is being devel­
oped as a standardized method for measuring wafer
bond strength.
The methods listed have been used in optimization
of direct wafer bonding schemes. It is not clear to what
extent they are in use to control the bond strength in
production environments. The methods are all purely
mechanical and destructive, and only sampling-type
testing is possible. The DCB measurement does not
require sample preparation and is straightforward to
implement. The drawback of the method is that it has
proven difficult to open the crack between the wafers in
case of a permanent chemical bond with a full strength
of the bond without breaking the wafers, which is the
condition in SOI wafer production. Tensile measure­
ments require considerable preprocessing of samples
and the relatively large scatter would probably limit this
method’s use in quality control in wafer production.
The other two methods, the Chevron test and the blis­
ter method, require processing of the test structures in
the wafers before direct bonding, and therefore dummy
work pieces with test structures are needed. This
requirement means the methods are not well suited to
the fabrication of standard unstructured bonded SOI
wafers.
In applications where the buried oxide is used as a
sacrificial layer to release mechanical sensor elements, a
well-defined oxide etch rate is critical. Evaluation using
hydrofluoric acid (HF) etching of the buried oxide has
been used to test the bond quality. Hydrofluoric acid
etches the buried oxide faster in the area of low bond
strength and can signal differences in bonding in the
region of high mechanical bond strength. Comparison of
normal high-temperature bonding and plasma-activated
bonding indicates that even if the mechanical strengths
are identical, the etch rate of the plasma-activated
bonding interface can be several times higher [43].
In HF etching of the buried oxide film both the etch
rate and the profile of the etching front are character­
istic of the bond quality. For full strength of the bond
the etched oxide edge is nearly straight and the bonding
interface is identical with the thermally oxidized silicon
interface (Figure 7.14). If HF etching proceeds faster
along the bonding interface, a notch is formed and the
oxide starts to etch also in the vertical direction, resulting
in an increase of the effective etch rate. For hydrophilic
CHAPTER 7
Figure 7.14 ● Characterization of bond quality based on etch
rate of the buried oxide in HF etching for optimization of bonding
schemes. (a) Top view of the SOI wafer after HF etching showing
the 20-μm wide trenches etched through the SOI layer to the
buried oxide layer and approximately 20-μm distance of buried
oxide etching on both sides of the trenches. (b) (SEM) shows
a cross-section of an SOI wafer after HF etching of the buried
oxide. The original join is between the upper silicon wafer and the
thermal oxide.
silicon–oxide bonds the recorded values for the etch
rate in 50% HF for a large number of different types
of bonded SOI wafers over an extended period of time
range from 1.40 to 1.60 μm/min, indicating that the vari­
ation of the etch rate is well within /10%. A similar
test using vapor phase HF etching showed that the vari­
ation of the etch rate across an SOI wafer corresponding
to an average etching distance of 4.9 μm was approxi­
mately 6% ( 3σ). The weak preferential HF etch­
ing along the original bonding interface that can be seen
after 1100°C annealing (Figure 7.14) has been associ­
ated to strained Si–O–Si bonds between the two wafers.
Preferential etching can be explained by the fact that
the strained Si–O–Si bond is ruptured by an adsorbed
water molecule and two OH-groups are formed. Infrared
absorption data indicates that relaxation of the strained
bonds occurs in annealing to higher temperatures sug­
gesting a further reduction of the etch rate [38].
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Silicon as MEMS Material
7.4.2 Thinning by Grinding
and Polishing
The brute-force mechanical thinning of the bonded device
wafer employs the grinding and precision chemical–
mechanical polishing processes (Figure 7.9). These proc­
ess steps define the thickness and the TTV of the SOI
layer as well as the properties and quality of the wafer
surface. In the conventional wafering process lapping
and double-side polishing can produce very good thick­
ness uniformity, with the TTV across the wafer smaller
than 0.5 μm. Those manufacturing processes can pro­
vide the required wafer form and surface finish control,
but they have no precise thickness target. Therefore,
surface grinding technology has been quite universally
applied in mechanical thinning of thick-film SOI wafers.
The most attractive feature of the high-precision sur­
face grinding process is that it allows accurate control of
both the absolute thickness of the wafer and the thick­
ness uniformity across the wafer. Another advantage is
the minimal mechanical crystal damage it produces. The
handle silicon wafer is in most cases double-side polished.
It allows two-sided processing of the SOI wafer, but
also provides the minimum TTV that is critical for the
final thickness variation of the SOI layer.
The grinding process is designed to minimize brittle
fracture of silicon in grinding, to assure very high surface
finish, wafer form accuracy requirements, and minimal
surface and near surface damage. For a high-precision
grinding process of silicon the total grinding tool sys­
tem needs to be considered. The fundamental grinding
tool design requirements include vibration free and rigid
grinding tool, very high stiffness between the tool and the
silicon wafer, high-resolution motion control, micrometersize abrasive media bonded as a rigid grinding wheel,
thermal stability, high-precision metrology system inte­
grated into the grinding tool, and clean controlled envi­
ronment [44]. Vertical-spindle type grinding tools with
the rotational in-feed grinding configuration are most
frequently used. In principle the simple geometry assures
flatness of the wafer as the axes of rotation of the spin­
dle and the wafer are aligned. In practice the grinding
tool is not infinitely stiff and the shape of the wafer is
controlled by fine adjustment of the angle between the
axis of rotation of the wheel and the axis of rotation of
the wafer. Pregrinding and fine grinding are usually car­
ried out in two different grinding stations with diamond
cup grinding wheels of different grit size. Fine grinding of
silicon wafers refers to grinding with 2000 mesh or finer
diamond wheels, corresponding to 3–6-μm grit size.
In the SOI wafer grinding sequence the device wafer
thickness is reduced very close to the final silicon film
thickness. In volume production of thick-film SOI
wafers an average TTV across the wafer of 0.5 μm or
122
less and tolerance for the final wafer thickness better
than 0.5 μm are routinely achieved.
Surface and subsurface damage is easily created dur­
ing grinding of single crystalline silicon which is hard
and brittle. Ductile and brittle modes of deformation
can occur in a brittle material such as silicon. Brittle and
partial ductile chips can be found simultaneously on
the surface of a silicon wafer. The diamond particle size
specification has the most significant effect on surface
quality and depth of subsurface damage, and the duc­
tile mode process is associated with small depth of cut.
Under optimal grinding conditions a more ductile or
partial ductile mode surface can be obtained. For mini­
mum mechanical subsurface damage from the grinding
step, the size of diamond abrasives should be as small
as possible. In grinding a self-conditioning state of the
grinding wheel must be obtained, implying use of softer
bond materials with less wear resistance.
The polishing method for silicon is optical chemical–
mechanical polishing based on silica slurries. The polish­
ing step is designed to remove the mechanical crystal
damage and to make the mirror surface. The polish­
ing method and the processes are basically the same as
those used for prime grade silicon wafer polishing, and a
similar quality of the surface is achieved. Polishing com­
bines mechanical action with chemical etching using
abrasive alkaline polishing slurry with colloidal or fumed
silica particles and polyurethane pads. One can reach
the required accuracy of the polishing process by using
CMP polishing tools that were developed for chemical
mechanical planarization of wafers in mainstream semi­
conductor manufacturing. Most of the CMP machines
that are in use are based on rotary polishing tables, but
other basic designs such as linear systems are employed
as well. The process is typically a single-wafer process.
The many options for tool designs, primary tool param­
eters, and the key elements of the CMP process are
reviewed in Ref. [45].
The CMP step has to remove approximately 1.0
to 2.0 μm of silicon to totally remove the mechanical
damage created in the fine grinding step. An arche­
typical polishing method then utilizes a two-step pol­
ishing process with specific properties of the polishing
pads and slurries. The primary polish which is used to
remove most of the silicon material is followed by a
step of final polishing to produce the smooth surface.
Typical values of the polishing removal rates for the
stock removal and final polishing steps are from 0.5 to
1.5 μm/min and 10 nm/min, respectively.
Two critical issues specific to thinning of the thickfilm SOI layer are the control of the final layer thick­
ness (the end-point of polishing), and the uniformity of
the silicon film. Accurate control of the end-point and
the thickness uniformity require the use of a singlewafer CMP polisher, and automated process control for
Thick-Film SOI Wafers: Preparation and Properties
CMP provides the necessary manufacturability, stabil­
ity, and predictive process results. In the CMP technol­
ogy different techniques for the end-point detection
were developed. Indirect methods of measuring the
motor current changes or direct monitoring of changes
in the frictional forces to identify the point where the
polishing meets the interface between two material lay­
ers cannot be utilized in SOI wafer polishing. Optical
reflectometry for in-situ measurement of film thickness
requires extensive hardware modifications, and its use
is limited by the very thick silicon layers in thick-film
SOI wafers for mechanical systems. As a result, the inline thickness measurement system integrated with the
CMP tool is probably the most extensively used tech­
nique for the end-point detection. The data from thick­
ness measurement are used for changing the process
time (or any other process parameter) using run-to-run
control methods for compensating for changes in the
polishing removal rate. Thickness control of the SOI
layer better than 0.1 μm ( 3σ) is achieved in the pro­
duction environment.
One possible embodiment of the thinning process
showing the step-wise reduction of the device wafer
thickness and the typical thickness tolerance and thick­
ness uniformity at each step is given in Table 7.1.
Controlling the thickness uniformity of the SOI
film can be further improved by local plasma-assisted
chemical etching (PACE). In PACE technology [46]
the chemical etching area is confined under a small
electrode where plasma is generated. Starting with
the map of SOI film thickness, SOI wafers are etched
locally by controlling the position of the wafers and the
dwell time for etching. The whole process consists of
SOI substrate fabrication (as described above), PACE
CHAPTER 7
which includes the measurement of the SOI film thick­
ness map, local plasma etching, film thickness measure­
ment after etching, and touch polish and final cleaning
of the wafers. A short touch-polishing step is necessary
since the surface quality is degraded during the plasmaetching process. The technique has been primarily con­
sidered for fabrication of SOI layers in the range of
0.1–1 μm as an alternative approach to the layer trans­
fer methods. Typical volume of material removed in the
local plasma-etching step is 1–3 μm, and the thickness
uniformity of 1.5 nm (rms) for 0.1-μm-thick SOI films
was reported [47]. The technique has been demon­
strated also for thick-film SOI wafers with active layer
thickness up to 30 μm. A similar technique was applied
to demonstrate extremely thin and uniform 8-in. SOI
wafers [48]. Commercial tools based on local plasma
etching exist in the market at least for large-diameter
silicon wafer flattening. With the metrology system for
SOI film thickness measurement they are in principle
suited for SOI layer thinning, but volume production of
SOI wafers based on the PACE process has rarely been
assessed in published papers.
The capability of the mechanical thinning process
based on conventional back-grinding and CMP proc­
esses in medium- or large-series wafer production is
demonstrated as follows. The SOI layer thickness is
most commonly measured on the basis of a Fourier
transform infrared (FTIR) technique using a Michelson
interferometer. The technique is the same as for sili­
con epitaxial layer thickness measurement, which is
an ASTM-approved method to measure epitaxial film
thickness, and the same tools are used. There are two
implementations of the measurement, one based on the
interferogram and one based on spectroscopic analysis.
Table 7.1 Example of possible application of the back-grinding and CMP polishing processes in thinning of 150- or 200-mm diameter thick-film
SOI wafers
Process step
Si film
thickness(μm)
Device Si wafer
300–400
Handle Si wafer
Thickness
tolerance (μm)
Total thickness
variation (μm)
Damage
depth (μm)
5
Not critical
None
N.A.
0.5
0.5
None
Rough grinding
25
1
2
15–20
Fine grinding
2
0.5
0.5
1.0
CMP polishing
0.5
0.2
0.5
0
CMP final polishing
0.0
0.1 ( 3σ)
0.5
None
Typical silicon film thickness, thickness tolerance, thickness uniformity (TTV) control, and characteristic crystal damage depth after each unit process step are given. Silicon
film thickness is calculated from the target film thickness.
123
Silicon as MEMS Material
124
is critical as it becomes the reference for the control
of the thickness of the SOI layer and directly contrib­
utes to the final thickness uniformity of the SOI film. A
rather typical specification limit for the thick-film SOI
wafer thickness uniformity is 0.50 μm, including the
thickness variation from wafer to wafer and the TTV
across the wafer. The thinning process has been refined
to control the SOI layer thickness uniformity more
accurately within 0.30 μm based only on the improve­
ment of the accuracy of the mechanical thinning process
(Figures 7.15 and 7.16); the mechanical thinning process
Figure 7.15 ● Thickness variation (μm) of the SOI layer across a
150-mm-diameter wafer demonstrating the process capability of
the mechanical thinning process in large-series wafer production.
The target thickness of the SOI layer was 2.5 μm.
(a) 13.0
SOI thickness (μm)
The interferogram-based technique relies on the time
domain to extract the film thickness. An abrupt inter­
face with no transition layer is assumed. It does not take
into account the finite width of the interface between
the epitaxial silicon layer and the substrate, but it is a
good approximation for the silicon-oxide interface of a
bonded structure. In the spectroscopic, model-based
approach, the instrument measures the reflectance
of the sample over a wide spectral range, and a calcu­
lated reflectance spectrum is fitted to the measured
spectrum. In epi layer thickness measurement, layer
thickness, transition layer width, and substrate carrier
concentration can be extracted, but for the silicon–
oxide interface the first principle models to calculate
the reflectance spectrum are not broadly implemented.
The interferogram-based approach is a single-beam
measurement. The repeatability of the measurement
(≤10 nm) is good compared to typical thickness varia­
tion of thick-film SOI layers, but to correlate the meas­
urements in a long term for variation in the light source
or in the environmental conditions some corrections
may be necessary. Also, because the method relies on
a single optical beam, there is some variation between
the tools, and calibration to some other method is nor­
mally made. For very thin films the interferogram side
bursts generated by reflection from the interface merge
with the center burst, and reference wafers are required
to separate the two to extract the SOI layer thickness.
Such merging starts to occur when the film thickness is
2 μm, and it does not seriously limit the measurement
of thick-film SOI layers. The upper limit for the thick­
ness measurement depends on the carrier concentration
in the device silicon layer. In lightly doped silicon 200­
μm-thick layers and above can be measured. In lowresistivity material another complication besides the
absorption of infrared light is the index of refraction of
silicon, which becomes a function of the carrier concen­
tration and the light wavelength. With these limitations
the interferogram-based FTIR technique has been used
successfully in thick-film bonded SOI wafer produc­
tion with a full range of specifications for the SOI layer
thickness and resistivity.
In large-series SOI wafer production the uniform­
ity of the silicon film is driven by two parameters, the
wafer-to-wafer variation of the mean layer thickness
and the thickness variation across the wafer (TTV of
the SOI layer). Final thickness of the silicon film is con­
trolled in the CMP polishing step using the end-point
detection or in-line thickness measurement system inte­
grated with the CMP tool. Within-wafer thickness varia­
tion is defined by the back-grinding and CMP processes,
and equally by the TTV of the handle silicon wafer. The
surface grinding process only controls the total thick­
ness of the wafers using the back surface of the wafer as
the reference plane. Minimal TTV of the handle wafer
Mean thickness
Mean + 3σ
Upper limit
Lower limit
Mean -3σ
12.5
12.0
11.5
11.0
70
90
110
130
Wafer number
(b) 101.0
SOI thickness (μm)
PA R T I
Mean thickness
Upper limit
Mean - 3σ
Lower limit
Mean + 3σ
100.5
100.0
99.5
99.0
0
20
40
60
Wafer number
Figure 7.16 ● Thickness uniformity for thick-film bonded SOI
wafers. Examples were taken from large-series SOI wafer
production. The target silicon film thickness was 12.0 μm (a) and
100.0 μm (b). Wafer diameter is 150 mm.
Thick-Film SOI Wafers: Preparation and Properties
has greatly benefitted from significant engineering to
develop sophisticated fine grinding wheels for silicon
grinding with an exceedingly small depth of the crystal
damage from the grinding step.
Figure 7.16 shows an example of the wafer-to-wafer
variation of the film thickness taken from SOI wafer
production. The error bars in the figure correspond to
the 3σ values from the 9-point FTIR-measurement
of the SOI layer thickness. With the in-line thickness
measurement system the average film thickness can be
routinely controlled within 0.1 μm ( 3σ). The over­
all uniformity for all wafers and all sites calculated at
3σ level is 0.40 μm. Thickness variation is independ­
ent of the silicon film thickness which is a characteristic
feature of the thinning process based on back-grinding
and CMP polishing. The distribution of SOI thickness
values for all wafers and all sites shows that more than
97% of the surface area is within 0.2 μm of the target
thickness (Figure 7.17).
A typical SOI wafer specification for the back-grinding
and polishing process is given in Table 7.2. It represents
standard products, and wafer suppliers typically offer
tighter specification for some of the parameters.
7.4.3 Properties of Thick Bonded SOI
Wafers
7.4.3.1 Stress and Wafer Bow
The presence of the buried silicon oxide film signifi­
cantly alters the thermal and mechanical behavior of the
SOI structure compared with processing of standard
Figure 7.17 ● Thickness of bonded SOI wafers including all
sites of all wafers from a 9-point FTIR thickness measurement.
Total number of wafers is over 300. Thickness is calculated
as the difference from the target thickness. Wafer diameter is
150 mm.
CHAPTER 7
bulk silicon wafers. The thermo-elastic properties of
thermal oxide are clearly different from those of silicon,
and the buried oxide has a significant impact on the
room-temperature bow of the SOI wafer and the stress
in the active device layer. The most important sources
of strain are the differential thermal expansion of sili­
con and thermal silicon dioxide, and the intrinsic stress
of the SiO2 layer. In bonded SOI wafers the strain is
accommodated elastically by the build-up of in-plane
stresses. When the device wafer is thinned down it
results in bending of the structure, and the deformation
can be described in terms of a bending radius of cur­
vature or bow of the wafer. Larger strains induced by
processing of SOI wafers can in extreme cases lead to
plastic deformation or even delaminating of the silicon
film.
In a bonded wafer the compressive stress in the bur­
ied thermal SiO2 film at room temperature induces
bow and a convex shape to the SOI wafer. The intrinsic
stresses that occur during the oxide growth depend on
the growth temperature and are related to the volume
expansion in the oxidation process of silicon. At low
oxidation temperature (950°C and below) the lack of
free volume typically leads to compressive stress in the
growing oxide film. At higher temperatures (1000°C)
relatively small intrinsic stress exists in thick (100 nm)
thermal SiO2 films. Viscous flow of the thermal oxide has
been used to explain the relaxation of the internal stress.
The stresses in thermal SiO2 at room temperature are
for the most part due to the differences in the thermal
expansion coefficients between silicon (2.6 106 1/K)
and SiO2 (5 107 1/K). The stress is compressive
and the reported values for the overall mechanical
stress including both the internal stress and the ther­
mal stress vary from 200 to 400 MPa [49]. The stress
distribution depends on many parameters such as
SiO2 film thickness, the oxide growth conditions, pos­
sible heat treatments after oxidation, and the crystal
orientation.
The bending of the SOI wafer can be characterized
by wafer bow (deflection of the center point of the
wafer from a reference plane defined by three points
taken at the edge of the wafer). For SOI layers that are
less than 10 μm thick the ratio of SOI layer thickness to
the total thickness is small and the silicon film has prac­
tically no contribution to the bending of the wafer. In
this range the wafer bow is defined by the combination
of the thicknesses of the handle silicon wafer and the
buried oxide film. Data on 380-μm-thick 150 mm-diam­
eter wafers in Figure 7.18 illustrate the bow in bonded
SOI wafers comparing the bow values in the handle
silicon wafers and in the SOI wafers with 0.5-μm-thick
BOX layer. The wafer bow increases from 15 to 15 μm
in silicon wafers to 65 to 95 μm in SOI wafers. The bow
value can be quite systematically predicted for different
125
PA R T I
Silicon as MEMS Material
Table 7.2 Example of a thick-film bonded SOI wafer specification for microelectromechanical systems
Overall wafer
SOI wafer parameter
Typical
Crystal pulling method
Wafer diameter, mm
Handle wafer thickness, μm
Handle wafer thickness tolerance, μm
Total thickness variation, μm
Bow/warp
Czochralski
150 and 200
380–725
/15
2
Depends strongly on the thickness
of handle wafer, BOX, and SOI layer
Polished or lapped/etched
Handle wafer backside
Silicon film
Buried oxide
Available
SOI film thickness, μm
Thickness tolerance, μm
Resistivity, Ohm-cm
P-type (Boron)
N-type (Phosphorus)
N-type (Antimony)
Crystal orientation
Crystal orientation accuracy
2
/0.5 or
Buried oxide type
Buried oxide thickness, μm
Thermal SiO2
0.2–4.0; formed on handle or device
wafer or both wafers
/5
Buried oxide uniformity, %
/1.0
0.00550
0.130
0.010–0.020
100
0.5°
300 (150 mm)
/5
Max / 30 μm if oxide allowed
to remain on back surface
/0.3
1000
500
111, 110
0.2°
Specification represents typical capability of thinning of wafers by grinding and CMP. Since the mechanical material is originally from a bulk silicon wafer its properties are
equivalent to that of Czochralski silicon. Polishing and wafer cleaning processes are basically similar to those for prime silicon wafers, and similar surface quality can be
achieved.
types of wafers starting from Stoney’s equation [50],
which has been—and still is—widely used to relate
the bending of the wafer to the average stress in ther­
mal oxide. The radius of curvature R increases approxi­
mately as the square of the handle wafer thickness. The
wafer bow, which is proportional to 1/R, then depends
on the layer thicknesses as tBOX/tSi2 where tBOX and tSi
are the BOX and handle wafer thicknesses. For a given
value of strain defined by the thermal oxide, increasing
the handle wafer thickness provides an effective way of
reducing the bending of the wafer. However, in MEMS
applications rather thin handle silicon wafers are often
preferred to assist processing of wafers from both sides
or to reduce the overall thickness of the sensor ele­
ments. At the same time the design considerations of
the sensor elements or the requirement of robust proc­
esses usually set some lower limit for the buried oxide
film thickness. Therefore, bending of the wafers easily
becomes an issue, and thick-film SOI wafers typically
have significantly higher bow values than those in prime
silicon wafers.
One method that is commonly used to reduce the
wafer bow is to retain a thermal oxide layer on the
126
back surface of the SOI wafer (Figure 7.18). The bow
of the SOI wafer then depends on the relative thick­
nesses of the buried oxide and the backside oxide, but
in practice the wafer bow can be very close to that of
the handle silicon wafer. Another way to reduce the
bow of wafers is to add a thin silicon nitride layer into a
composite buried insulator to balance the compressive
stress of thermal oxide. The concept, which requires
direct bonding of silicon nitride, has been demon­
strated but is probably not in common use in SOI wafer
fabrication.
When the active silicon layer is thick (10 μm), it
directly changes the total bow of the SOI wafer (Figure
7.19). The bending moment of the silicon film is oppo­
site that of the substrate wafer reducing the overall bow
of the wafer. The magnitude of the wafer bow reduction
as a function of the SOI layer thickness also depends
on the details of the SOI wafer fabrication process and,
for example, forming the buried oxide initially on the
device wafer or the handle wafer was seen to produce
systematically different behavior. Simulations indicate
that the residual intrinsic stress in the SOI layer has a
pronounced effect on variation of the overall wafer bow,
Normalized wafer bow
Thick-Film SOI Wafers: Preparation and Properties
CHAPTER 7
1.00
0.75
0.50
0.25
0.00
–0.25
Figure 7.18 ● Bow of bonded SOI wafers with thin device layer
(approximately 10 μm or smaller). Handle silicon wafer thickness
was 380 μm and the buried oxide thickness was 500 nm. Effect
of a balancing oxide with nominal thickness equal to the buried
oxide thickness on back surface of the wafer is also shown. The
values given are for a 3-point reference plane (reference points on
edge of the wafer).
and that even low values of residual stress can signifi­
cantly influence the wafer shape [51].
7.4.3.2 Crystal Defects
Film quality and crystalline perfection of SOI layers
obtained by direct bonding and mechanical grinding
and polishing techniques are virtually identical to those
of device grade bulk silicon wafers. If the polishing is
performed to prime grade standards, the crystalline per­
fection of the initial bulk Si wafer can be retained. In
thick-film bonded SOI wafers the device silicon wafer
directly defines the crystal material of the SOI film.
Accordingly, the crystal quality and defects are corre­
lated to the control of the crystal pulling techniques.
Because of the thick silicon layers, control of the crys­
tal defects associated with precipitation of oxygen in
the bulk of the device wafer needs consideration when
deciding upon the silicon material. In the bonded SOI
process the device silicon wafer is heat-treated at 1100–
1200°C to form a permanent chemical bond and reach
the final bond strength; two high-temperature proc­
ess steps are necessary when thermal oxide is grown
on the device wafer to form the buried oxide. In such
high-temperature annealing, oxygen incorporated into
Czochralski-silicon precipitates, leading to formation
of oxygen precipitates in the bulk of the device silicon
wafer. In high-oxygen silicon, a denuded zone free of
precipitates can form near the silicon oxide interface. If
the SOI layer is thin (10 μm) it is in the region of the
denuded zone where precipitation of oxygen is greatly
reduced, and low concentration of crystal defects in the
silicon film can be achieved. In thick SOI layers oxygen
precipitation in the bulk of the device silicon wafer actu­
ally defines the concentration of oxygen-related crystal
0
50
100
SOI layer thickness (μm)
150
Figure 7.19 ● Variation of wafer bow as a function of the SOI
layer thickness. The measured values of bow are divided by the
value estimated for thin SOI layer (thickness 10 μm) assuming
300 MPa compressive stress in the buried oxide using Stoney’s
equation to enable comparison of wafers with different handle
wafer and buried oxide thicknesses. The values are lot averages
of 150-mm-diameter SOI wafers.
defects in the SOI film. Stacking faults then grow on the
oxygen precipitates during thermal oxidation of the SOI
layer. For oxygen concentration of 14 ppma or higher,
the stacking fault density induced by thermal oxidation
strongly depends on the actual oxygen concentration in
the crystal and the silicon film thickness.
The choice of crystal material is critical to control
oxygen precipitation and thereby, for example, the for­
mation of oxidation-induced stacking faults (OISF) in a
thick device layer. Basically one can use float-zone silicon
material with inherently low oxygen concentration, or
epitaxial silicon wafers. However, it is also possible to use
Czochralski (CZ) silicon with reduced oxygen con­
centration. Figure 7.20 shows the number of OISF as
a function of the oxygen concentration in the crystal
material of the device wafers. It summarizes data from
different types of CZ crystals including weakly doped
n- and p-type and highly doped p-type material. The
device layer thickness in the wafers is from 8 to 50 μm.
In SOI wafers in which the oxygen concentration in
the device wafer is 11 ppma or less there is very little
or no oxygen precipitation that would lead to the for­
mation of stacking faults. The OISF density is from
0 to 2 cm2 independent of the type of crystal material
or the SOI film thickness. Similar OISF densities are
typically measured from prime quality polished silicon
wafers indicating that the defect density is related to the
overall crystal quality rather than the SOI fabrication
process. At higher oxygen concentrations from 11 to
13 ppma, OISF start to appear although there is quite
a lot of variation according to the type of crystal, layer
thickness, and formation of buried oxide, either on the
127
PA R T I
Silicon as MEMS Material
device wafer or the handle silicon wafer. Finally, when the
oxygen concentration is around 15 ppma very high OISF
concentrations of 1 105 cm2 or higher can be found.
For reference, IC requirements for the oxygen concen­
tration in polished silicon wafers to control oxygen precip­
itation for internal gettering of metal impurities are most
commonly in the range of 12–16 ppma. In thick-film SOI
wafers designed for MEMS applications crystal material
with lower oxygen concentration is advantageous.
7.5 BESOI Process
An alternative method to make thick-film bonded SOI
wafer is the BESOI. It is basically a layer transfer proc­
ess which makes use of selective chemical etching for
the final thinning step of the SOI layer. Heavily borondoped p
type silicon exhibits much lower etch rate
than lightly doped n- or p-type silicon in alkaline etching
solutions such as ethylenediamine-pyrocatechol-water
(EDP), tetramethyl ammonium hydroxide (TMAH),
or KOH, and a thin boron-doped layer is the most fre­
quently used etch stop. In this approach a p
layer is
first formed on the seed wafer, and a lightly doped nor p-type epitaxial silicon layer that later becomes the
SOI film is grown on top of the p
layer. The layer
is transferred to a second silicon wafer by direct bond­
ing and subsequent chemical etch-back of the device
wafer. The isotropic fast-etching step or mechanical
thinning of the device layer is followed by a selective
etching step that stops at the p
region. The bur­
ied etch-stop layer can be formed either by implant­
ing a high dose of boron to produce a p
type layer
and growing an epitaxial layer on top of a boron-doped
OISF density (cm–2)
40
30
20
10
0
5
6
7
8
9
10
11
Oxygen content (ppma)
12
13
Figure 7.20 ● Thermal oxidation induces stacking faults in thickfilm SOI wafers. Thermal oxidation was carried out at 1100°C for
2 hours (wet oxidation). Device wafer properties vary including
n-type, p-type, and highly p-type silicon. SOI layer thickness
varies from 8 to 50 μm. The buried oxide thickness varies from
400 nm to 2 μm, and it was initially formed either on the device
wafer or the handle silicon wafer by thermal oxidation.
128
surface layer or by the two-layer epitaxial process to
form the p
and the lightly doped active layers.
Compared with the direct mechanical grinding and pol­
ishing techniques, introduction of the etch stop extends
the wafer bonding technique to thin films and strin­
gent thickness uniformity requirements. Another major
difference is the fact that the presence of the highly
boron-doped layer represents the key factor in the
defect-generating mechanisms which result from the
bonding and thinning process steps.
A schematic process flow of BESOI is outlined in
Figure 7.21. As a specific example, a process based on
epitaxial etch-stop layer is briefly described. In this
process the first epitaxial p
silicon layer is grown
on a silicon wafer to a boron concentration in excess of
1 1020 cm3, typically using a single wafer atmospheric
pressure epi reactor. Thickness of the boron etch-stop
layer is in the range of 1–2 μm. Due to the small covalent
radius of the boron atom, the equilibrium lattice constant
of the highly boron-doped layer is smaller, which causes
significant lattice contraction of the p
layer. The lat­
tice mismatch induces strain and, when the critical epi­
taxial film thickness is exceeded, the strain is released
by plastic deformation in the form of misfit dislocations
along the interface. To compensate for the strain the
boron-doped layer is codoped with germanium. It is elec­
trically inactive, has a covalent radius that is larger than
that of a silicon atom, and has high solubility in silicon.
The strain compensation prevents the propagation of
dislocations into the device layer. For full compensation
of the stress the amount of germanium in the crystal is
approximately six times that of boron [52]. The second
lightly doped p- or n-type epitaxial layer is grown on top
of the highly boron doped B/Ge etch-stop layer to form a
two-layer epi structure. Low temperature epi processes at
1000°C have been used to obtain epi layers with sharp
transitions between the epi layers to achieve the required
thickness control in selective etching, and to avoid p-type
background doping of the device layer. In order to have
the interface with thermal SiO2 in the final SOI struc­
ture, a thin thermal oxide is grown on the seed wafer.
The device wafer is bonded to the handle silicon
wafer with a thermal oxide by joining the wafers at
room temperature and annealing the bonded wafer pair.
The device wafer is thinned by first grinding or rapidly
etching in isotropic etching solution to remove most of
the device wafer. In the second step, an alkaline aqueous
solution such as KOH or TMAH is employed to etch off
the remaining silicon until the etching stops at the peak
of the boron concentration in the p
layer. The etchstop layer can be removed by another selective etching
step, or in some cases also by short nonselective etching
or reactive ion etching. The chemical etching process
that is designed to stop at the transition from p to the
lightly doped layer is based on HF–NHO3–CH3COOH
Thick-Film SOI Wafers: Preparation and Properties
chemistry [53]. The SOI wafer undergoes a final touch
polish. The touch polish process is designed to minimize
degradation of the SOI layer uniformity while achiev­
ing surface roughness typical of a prime quality polished
silicon wafer. It also removes the tail of the boron diffu­
sion from the p
etch stop layer.
The process described above uses a double etch-stop
approach. The selectivity of alkaline etching of highly
boron-doped silicon is from 1:10 to 1:100 depending
CHAPTER 7
on the type of etching solution and the actual peak con­
centration of boron. The overall etch selectivity of the
combination of the two selective etching steps can be
as high as 104:1. Therefore, the final thickness variation
of the device layer is determined mainly by the toler­
ances of the epi process and the final touch polish step.
Thickness uniformity that is better than 10 nm has
been reported for thin BESOI layers. In case of thick
SOI layers typical of MEMS applications, the thickness
Blank device wafer
Handle silicon wafer
SOI film is originally part of the bulk silicon wafer.
Cleaning to eliminate particle and surface
contaminants.
Serves as a substrate for the SOI wafer. Final cleaning
of wafers.
p++ epi
Thermal oxidation
Epitaxial growth of in-situ B-doped epitaxial layer
20
codoped with Ge. Boron concentration ≥1×10 cm–3,
and epi layer thickness from 1 to 2 μm.
Thermal oxidation to form an insulating layer that
later becomes the buried oxide of the SOI structure.
Second epitaxial layer
Epitaxial growth of second lightly doped n- or p-type
epitaxial layer over the p++ etch stop layer.
Thermal oxidation
Thermal oxidation to form thin thermal oxide over the
double epi layer. Thickness 40–50 nm.
Direct bonding and annealing
Cleaning, mechanical alignment, and contacting of the
wafer pair. High-temperature annealing of the bonded
wafer pair.
Device wafer thinning
Back-grinding of the device silicon wafer or isotropic
etching to rapidly remove >90% of the device wafer.
Etch-back
Etch-back to p++ etch-stop layer using alkaline
etching solution (KOH, TMAH, or EDP).
Remove etch-stop layer
Removal of p++ layer by selective etching,
non-selective etching, or reactive ion etching.
Touch polishing and final cleaning
Figure 7.21 ● The sequence of steps required to make thick-film bonded SOI wafer by wafer bonding and etch-back, according
to Ref. [54].
129
PA R T I
Silicon as MEMS Material
uniformity is predominantly due to the thickness vari­
ation that is introduced by the epitaxial growth of the
device silicon layer.
In BESOI process the crucial step is the formation
of the highly doped p
etch-stop layer. With ion
implantation it is difficult to provide a dislocation-free
substrate for subsequent epitaxial silicon growth, and
the threading dislocations propagate freely into the
epitaxial device film formed on the implanted surface
layer [54]. The selective etch solution sets the lower
limit for the concentration of implanted boron which
in practice is around 1 1020 cm3. Such a high boron
dose causes considerable recoil and displacement dam­
age but is not able to produce an amorphous silicon film
that could recover almost totally by reconstruction of
the amorphous silicon layer. In addition, the thermal
anneal times and process temperatures for the oxidation
and bonding steps have to be minimized throughout the
process in order to keep the implanted transition layer
sharp and to prevent the out-diffusion of boron to the
top epitaxial silicon layer. What is left is ion implanta­
tion damage in the form of large residual dislocation
loops that are mostly located at the projected range of
boron ions and that are impossible to get rid of. The
residual defect density can be reduced to the range of
1 104 or 1 105 cm2.
The residual defect problem has been overcome by
the double epitaxial process described above [54]. With
Ge-doping for strain compensation complete absence of
misfit dislocations has been demonstrated, and essen­
tially bulk crystalline quality of silicon can be retained.
Besides the propagation of misfit dislocations into the
device layer unless the strain in the heavily boron doped
layer is compensated, another issue related to p
etchstop layers is out-diffusion of boron. Low-temperature
epi processes have been used to obtain sharp transition of
the doping profile in the boron-doped etch-stop layer. It
is necessary to have accurate control of the layer thick­
ness and a low p-type background doping of the device
layer. To maintain a sharp etch-stop layer, the maximum
temperature in direct wafer bonding is also limited to
below 1000°C until the etch-back step in the process.
Yet another defect-generation mode that is characteris­
tic of silicon epitaxy is related to pyramids and spikes
on the surface of the epitaxial layer. If the surface con­
tains spikes from epi growth they invariably cause local
noncontacted areas in the bonded interface similar to
those induced by large surface particles. It is one of the
major yield-determining factors in large-series produc­
tion of BESOI wafers. Slip dislocation networks have
been observed in such regions, indicating that during
thermal annealing the stress at the site of the spike can
exceed the critical stress for plastic deformation [54].
A much larger area than the noncontacted region can be
affected.
130
An example of BESOI wafer specification is outlined
in Table 7.3. The double epitaxial etch-stop technique can
meet the requirements for SOI film quality and crystal­
line perfection as well as the need for accurate control of
the SOI film thickness in the manufacturing environment.
It is possible to consistently achieve dislocation-free
SOI films and retain the quality of epitaxial silicon
crystal. In the lower end of the thickness range the
thickness uniformity is related to the selectivity of the
etching processes and the sharpness of the transition
layers as well as the final polishing step. For thicker lay­
ers, the thickness control of the silicon epitaxy process
becomes dominant.
7.6 Techniques Based on Thin-Film
SOI and Silicon Epitaxy
There are several thin-film SOI manufacturing technolo­
gies. A short description of the most important technolo­
gies follows.
7.6.1 Smart Cut Process
The Smart Cut technology is first and foremost applied
in large-scale manufacturing of thin-film SOI wafers for
CMOS applications. With the Smart Cut process the
maximum SOI layer thickness is limited to 1.0–1.5 μm.
Combined with epitaxial growth of silicon to increase
the SOI layer thickness, the technique can be used to
manufacture thick-film SOI wafers. The process is
Table 7.3 A part of a commercial specification for large-series
production of BESOI wafers
SOI wafer parameter
Target values
SOI film thickness
0.05–20 μm
Thickness tolerance ( )
0.05–1 μm
The larger of 2%
or 200 Å
1–2 μm
2.0%
2–20 μm
0.5 μm
Wafer diameter
100–200 mm
Stacking faults
10 cm2
Buried oxide thickness
Oxide pinhole density
0–3.0 μm
1 per wafer
Thick-Film SOI Wafers: Preparation and Properties
briefly described below; for more detailed presentation
the reader is referred to the review article [55] and the
references therein.
The Smart Cut process combines hydrogen implan­
tation and direct wafer bonding. With this method the
thinning steps in grind-back and polish SOI or BESOI
processes are circumvented by implantation of the seed
wafer with hydrogen prior to direct bonding of the
wafer. Hydrogen implantation causes splitting of the
entire wafer at a depth corresponding to the projected
range of hydrogen upon annealing in the temperature
range of 400–600°C. Implantation enables a very pre­
cise control of the top silicon layer thickness from about
20 nm to about 1.5 μm. The SOI layer uniformity can
be /50 Å or even better for the lowest film thick­
ness range, with perfectly controllable layer thickness
across large-diameter wafers. The wafer bonding proc­
ess is designed to preserve the original silicon crystal
quality and to prevent the blistering or flaking effects
that would occur in unconstrained (nonbonded) hydro­
gen implanted silicon.
The key unit process steps of the Smart Cut proc­
ess include (i) thermal oxidation of the seed wafer,
(ii) hydrogen implantation through the oxide into silicon,
(iii) cleaning and direct bonding of the seed wafer to the
handle silicon wafer, (iv) heat treatment of the bonded
wafer pair in the temperature range 400–600°C lead­
ing to splitting of the seed wafer, (v) high-temperature
annealing to form a permanent chemical bond, and (vi) a
final polishing step to reduce the surface roughness. The
key to this process is to provide a mechanical support in
the form of the handle wafer bonded to the hydrogenimplanted seed wafer to prevent blistering or flaking.
A thermal oxide is grown on the seed wafer, and this
oxide later becomes the buried oxide of the bonded
SOI wafer. The oxide film is effective in reducing the
channeling of the hydrogen ions during implantation.
Thermal oxidation contributes to the final uniform­
ity of the silicon layer, and therefore optimization of
the oxidation conditions is critical. Splitting occurs at a
depth corresponding to the projected range of hydrogen
ions, and the implantation energy primarily determines
the SOI film thickness. Typically the smallest hydro­
gen dose needed for the splitting to occur is from 2 to
5 1016 H /cm2, and higher doses than 2 1017 H /
cm2 would lead to blistering already during the hydro­
gen implantation step. Splitting occurs if the hydrogen
dose is over a threshold value, and therefore the thick­
ness uniformity is not sensitive to the local variation of
the dose across the wafer.
Bonding of wafers basically follows the process for
direct bonding described in Section 7.4. To provide
the mechanical support and to suppress the tendency
towards blistering, the interfacial bond strength must
be sufficient at the temperature at which the splitting
CHAPTER 7
occurs. This is achieved by designing the cleaning and
annealing parameters to produce strongly hydrophilic
OH-terminated surfaces and to enforce reactions
between the OH-groups linked with hydrogen-bridging
bonds to form Si-O-Si bonds. Blistering can take place
also in local areas if there is no mechanical support due
to noncontacted areas that are induced (e.g., by sur­
face particles). It leads to macroscopic defects where
no silicon film is transferred. Low-temperature anneal­
ing in the temperature range of 400–600°C enforces the
splitting of the wafers along the hydrogen implanted
zone, and a thin silicon film on an oxide layer bonded
to the handle silicon wafer leads to the SOI structure.
A second annealing step is carried out to form a perma­
nent chemical bond, and annealing parameters (anneal­
ing temperature 1100–1200°C) commonly used in
hydrophilic wafer bonding are applied.
The exfoliated silicon surface is rough compared
with silicon surfaces polished to electronic grade stand­
ards. A short polishing step is needed to reduce the sur­
face roughness of the as-split wafer to correspond to a
standard polished silicon surface. Because of the polish­
ing step the thickness uniformity and the final surface
roughness are interrelated. In the new process genera­
tions of Smart Cut wafers with silicon layer thickness
in the range of 200–500 Å and below, it appears that the
differences derive from the steps used to reduce the
roughness of the silicon surface [55].
Splitting of the surface layer occurs by interaction
between the microscopic cavities in the implanted layer.
Hydrogen implantation produces fine disk-shaped cavi­
ties that are confined around the maximum hydrogen
concentration located at the projected range of hydrogen,
with the density of platelets increasing with the hydro­
gen dose. The hydrogen-induced exfoliation strongly
depends on the chemical interaction that is intrinsic of
the H–Si system. The detailed picture of the splitting
mechanism was obtained on the basis of a combination
of microscopic and spectroscopic techniques including
TEM, infrared absorption spectroscopy which provides
information on the chemical state of hydrogen on ther­
mal evaluation of implanted silicon, forward recoil scat­
tering to measure the total amount of hydrogen, and
mass spectrometry [55, 56]. The essential microscopic
mechanisms behind the splitting process include hydro­
gen implantation induced damage and formation of point
defects, formation of agglomerated defects and internal
surfaces upon annealing, build-up of pressure inside the
cavities by increasing amount of H2 released into the
platelets, and the restoring force provided by the handle
wafer that drives lateral crack propagation.
Hydrogen implantation induced splitting occurs
in different crystal orientations [57]. The kinetics are
orientation dependent, the (100) orientation having
the highest rate of blistering. The crystal orientation
131
PA R T I
Silicon as MEMS Material
dependence was correlated with the atomic densities
in different crystal planes, but the underlying blistering
mechanisms and the activation energies for splitting are
similar for (100), (110), and (111) orientations. The
time for onset of splitting is shortest for the (100) ori­
entation and longest for the (110) orientation at a given
temperature. This is consistent with the atomic density
in different crystal planes, and the number of bonds
that need to be broken for splitting to occur is lowest
for the (100) plane and highest for the (110) plane.
The Smart Cut process is implemented in large-series
production of SOI wafers with very thin silicon films,
mainly for advanced CMOS applications. The target of
such development is towards thinner and more uniform
SOI films. When moving to 65-nm device generations
and below, the silicon film thickness also needs to scale
down. Currently available silicon film thicknesses are in
the range of 20–50 nm; the energy of hydrogen implanta­
tion is then in the range of 5–10 keV. The buried oxide
also needs to scale down, and currently the oxide thick­
ness is 100 nm. The uniformity of the silicon film is
from 2.5% to 5% (6σ level, including all thickness
variation). The thickness of the transferred SOI layer is
defined by the hydrogen implantation energy, and it can
be adjusted in a wide range. In the highest thickness range
the silicon film thicknesses up to 1.0–1.5 μm are possible.
The buried oxide thickness can also be adjusted in a wide
range from about 10 nm to several micrometers.
Standard bulk silicon wafers are used as the start­
ing material for the silicon film in the final SOI wafer,
and the quality of the crystal material is defined by the
quality of the silicon wafers. Compared to SIMOX the
initial damage to silicon is greatly reduced, due to lower
damage caused by each implanted atom and the lower
dose. For CMOS applications the seed wafer is typically
made of silicon material that is free of COP defects
(crystal originated particle) that are formed by agglom­
eration of vacancies during crystal pulling.
7.6.2 ELTRAN Process
ELTRAN is another method to manufacture SOI wafers
that was originally developed by Canon. ELTRAN wafers
are basically BESOI wafers that are formed by wafer
bonding and etching porous silicon. In its original form
the process involved epitaxial growth of the active sili­
con layer on porous silicon in a seed wafer, and the etchback of the device wafer was based on the extremely
high etch rate of porous silicon [58]. Later the tech­
nique was developed to include mechanical splitting at
the porous silicon layer to transfer the epitaxial layer
on the handle silicon wafer and basically to allow the
reuse of the seed wafer. The ELTRAN process is briefly
described below. For more detailed presentation the
132
reader is referred to the recent review article [59]
and references therein.
Several special properties of porous silicon are used
in the process. One key to the process is to grow a
device quality epitaxial silicon layer on top of porous
silicon. Annealing in a hydrogen atmosphere seals the
surface pores and smoothes the surface of a porous
silicon film, allowing the growth of high-quality epitax­
ial silicon on top of it. Second, the porous layer has a
large surface area that contributes to its extremely high
etching rate. Compared to single crystalline silicon, the
selectivity for etching porous silicon can be as high as
105:1. Another special feature is that the bonded wafer
can be split within the porous silicon layer by control­
ling the internal stress to define the splitting plane.
A schematic ELTRAN manufacturing process based
on mechanical grinding [58] starts with forming a porous
silicon layer on the seed wafer. A porous silicon layer is
formed by anodizing in a solution of HF and ethanol. With
the single crystal silicon wafer as the anode, microscopic
pores with a diameter of a few nanometers are formed
on the surface. A typical density of the pores is about
1 1011 cm2. The thickness of the porous layer around
10μm is sufficient to stop the grinding inside the porous
layer. The structure of the porous silicon can be controlled
by the concentration of the solution and the current den­
sity, and it also depends on the resistivity of silicon wafer.
By a low-temperature (400°C) dry oxidation of porous Si
a thin 1–3 nm oxide is formed on the inner walls of the
pores. A thin oxide layer preserves the porous structure in
subsequent high-temperature processing.
Next the wafers are baked at 1000–1100°C in hydro­
gen ambient in a CVD epitaxial reactor. Baking in hydro­
gen makes the surface silicon atoms migrate toward
the pores to reduce the surface energy. During the prebake the density of the pores on the surface is radically
reduced to less than 1 104 1/cm2. During the hydrogen
prebaking a small amount of silicon is provided from the
gas phase to increase the number of available silicon atoms
and to close all of the surface pores. Single crystal silicon
film is epitaxially grown on the H2 prebaked porous sili­
con by conventional silicon epitaxy. The epitaxial layer
will form the silicon film in the SOI wafer. In case of thin
SOI layers a thermal oxide is grown on the epi layer, and
the oxide film becomes the buried oxide layer.
The seed wafer containing the porous silicon layer,
the epitaxial silicon layer and the thermal oxide film is
bonded to a second silicon wafer. The direct bonding
process of the wafers is basically identical with the proc­
ess described previously (Section 7.4). The device wafer
is removed by surface grinding, leaving a porous silicon
layer on the surface. The porous silicon layer is removed
by etching, using a solution containing a mixture of HF
and hydrogen peroxide. Because of the extremely high
selectivity of etching it does not cause any significant
Thick-Film SOI Wafers: Preparation and Properties
degradation of the thickness uniformity of the underly­
ing epitaxial silicon film. The high etch rate is explained
by penetration of HF/H2O2 into the pores by capillary
forces and etching of the walls sideways until the porous
structure collapses. The effective thickness of silicon
that must be etched is on the order of the thickness of
the wall between the pores, which is only around 10 nm.
The etch rate of crystalline silicon in HF/H2O2 is actu­
ally very low due to the low reactivity of H2O2. Similar
selectivity cannot be reached with etching solutions such
as HF–HNO3–CH3COOH that react strongly with sili­
con. After etching the surface is microscopically rough
with surface roughness around 10 nm. An atomically flat
surface is achieved by means of annealing in hydrogen.
Annealing in hydrogen ambient at 1000°C reduces the
surface roughness to about 0.1 nm which is similar to the
surface roughness of polished silicon wafers. With the
hydrogen annealing process to reduce the surface rough­
ness any degradation of the thickness uniformity related
to the polishing processes is avoided.
The technique was further developed to include
reproducible mechanical splitting within the porous Si
layer by means of a water jet. Mechanical splitting is
based on a porous layer that has two layers of different
pore structure. The first porous silicon layer on the sur­
face must have a small pore size to make possible the
growth of epitaxial silicon layer. The second porous layer
is optimized to form a double layer structure with differ­
ent pore sizes to define the splitting plane. The porous
structure is controlled by varying the current density
during the anodization process, and it is also affected
by the porosity and the thickness of the first layer. In
mechanical splitting the maximum stress is formed
in the second layer close to the interface between the
two layers. It is possible to consistently split the wafers
precisely along the region of maximum stress and to
restrict the splitting plane inside the porous silicon
layer [59].
With ELTRAN process the SOI layer is formed by
epitaxial silicon growth and the buried oxide is formed
by thermal oxidation. Therefore, the thicknesses of the
silicon layer and the buried oxide layer can be control­
led independent of each other, and the thickness of the
layers can be varied over a wide range. The thickness
uniformity of the SOI film is defined by the selectiv­
ity of porous silicon etching, silicon epitaxy, and silicon
etching during the hydrogen annealing to reduce the
surface roughness, and can be better than /5% also
in very thin SOI wafers. The crystal properties of the
active layer are based on epitaxial silicon, and low levels
of HF defects (0.05 cm2) and density of Secco etch
defects in the range of a few hundred per cm2 have
been reached. A minority carrier lifetime of a few hun­
dred microseconds has been obtained, indicating a high
crystal quality of the thin SOI layer [59].
CHAPTER 7
7.6.3 Comparison of Different Methods
for Thick-Film SOI Wafer Manufacturing
for MEMS
There are presently several different approaches to SOI
wafer manufacturing. Most of them are primarily designed
for thin-film SOI wafer manufacturing. The approach based
on mechanical thinning is distinct from the other meth­
ods as it is characteristically a thick-film SOI technology.
However, in all bonded wafers as well as in SIMOX technol­
ogy, growing thick epitaxial silicon layers is a feasible means
of increasing the layer thickness. SIMOX technology has an
additional limitation of a maximum buried oxide thickness
400nm, which is very thin for most MEMS applications.
The different bonded SOI technologies are briefly discussed
as follows, focusing on requirements and specification range
in typical MEMS applications and distinguishing between
the approach that relies on mechanical grinding followed by
chemical–mechanical optical precision polishing for the final
thinning and the thin-film techniques.
SOI film quality and the defect-generating mecha­
nisms in SOI wafers depend to a large extent on the
fabrication method used. In the bond, grind-back, and
polish approach the SOI device layer is originally from a
bulk silicon crystal. The critical parameter contributing
to the defect formation is precipitation of oxygen. The seed
wafer is heat-treated two times at a high temperature lead­
ing to precipitation of oxygen in silicon crystal and to OISF
in later thermal oxidation processes unless the silicon crys­
tal material is picked properly. In all other bonded wafers
the resulting thick-film SOI device layer is epitaxial silicon.
In BESOI wafers the defect-generating mechanisms are
related to formation of misfit dislocations because of the
high boron concentration in the etch-stop layer. Another
mechanism for defect generation is surface defects from
epitaxial silicon growth, which cause noncontacted areas
in wafer bonding with associated local strain fields. In the
ELTRAN process silicon epitaxy on top of porous silicon
surface generates crystal defects (e.g., those seen as Secco
etch defects). However, with proper defect engineering
all aforementioned techniques including SIMOX are able
to provide good-quality SOI films. The critical processing
parameters that contribute to defect generation in the SOI
film have been identified and the processes have advanced
to the point of consistently achieving very low defect den­
sities retaining essentially bulk quality.
Like the defect-generating mechanisms, SOI film thick­
ness and thickness uniformity depend on the fabrication
method of the wafers. In the bond, grind-back, and polish
type of approach the process can directly produce any
SOI layer thickness from 2 to 100μm. Another charac­
teristic feature of this approach is that the thickness uni­
formity is totally independent of the silicon film thickness.
The capabilities of today’s silicon grinding and polishing
133
PA R T I
Silicon as MEMS Material
techniques set the lower limit for the SOI film thickness
and thickness uniformity control around 0.3μm. It is
this thickness nonuniformity which in practice sets the
lower limit also to the SOI film thickness for this tech­
nology. In all other approaches, in the thick-film range
typical of MEMS applications (thickness 2μm), silicon
epitaxy defines the SOI film thickness. Apart from the
lowest thickness range, thickness uniformity of the SOI
film is also defined simply by the epi process. In ambient
pressure high-temperature single wafer epi reactors the
overall thickness uniformity in production environment is
typically 2% of the layer thickness. Different techniques
and mechanical thinning of the SOI layer and those using
silicon epitaxy produce similar TTV of the SOI layer in
the range of 15–20 μm thick layers. Smaller thickness
variation can be obtained by starting with a thin-film
SOI wafer and then growing a layer of epitaxial silicon
if the target SOI layer thickness is below 10μm. In the
higher thickness range, latest above 20μm, the situation
is reversed and direct mechanical thinning yields smaller
thickness variation than any of the other methods.
The key process steps of the different methods for
manufacturing BSOI wafers are summarized in Table 7.4.
The approach that relies on mechanical grinding and
chemical–mechanical optical precision polishing for the
final thinning of the wafer is a straightforward one. It
does not require etch-stop layer formation or ion implan­
tation steps. There is no additional step of growing a
layer of epitaxial silicon to increase the SOI film thick­
ness either. Also, it can start from two prime grade pol­
ished silicon wafers with no additional processing steps
other than thermal oxidation prior to wafer bonding,
and the process has a smaller number of critical steps
that could interfere with the wafer bonding process
even if the process for direct bonding is basically identi­
cal in the different bonded SOI approaches.
Also in MEMS the productivity enhancement has
been achieved by migrating to the larger diameter wafers.
The transfer from 150 to 200-mm wafer size has already
occurred in a number of MEMS manufactures. Bonded
wafers are all scaled to 200-mm wafer size. In largediameter wafers the approach that starts from Smart Cut
SOI and uses epi process to increase the SOI film thick­
ness could have a greater advantage from the fact that
reclaiming of the seed wafer in the process is possible.
7.7 Conclusion
Direct wafer bonding associated with mechanical thin­
ning of the SOI layer is a generic technology that enables
the fabrication of thick-film SOI wafers. It is perfectly
adapted to the range of SOI layer thicknesses that are
commonly used in MEMS applications. The selection of
wafer type is based strongly on the performance versus
134
Table 7.4 Critical unit process steps for the different methods of
bonded SOI wafer manufacturing
Method for bonded
SOI manufacturing
Key process steps
Bonding, grinding and
chemical–mechanical
polishing
Cleaning of wafers
Thermal oxidation
Direct bonding
Back-grinding
CMP polishing
BESOI
Silicon epitaxy to form etch-stop and
active layers
Cleaning of wafers
Direct bonding
Back-grinding/isotropic etching
Selective etching step(s)
Touch polishing
Smart Cut
Thermal oxidation of seed wafer
Hydrogen implantation
Cleaning of wafers
Direct bonding at RT
Annealing to split the wafers
(400–600°C)
High temperature anneal
Touch polishing
ELTRAN
Anodization to form porous silicon
Prebake (CVD epi reactor)
Silicon epitaxy
Thermal oxidation
Cleaning of wafers
Direct bonding
Mechanical splitting of the bonded
wafer
Selective etching to remove porous
Si layer
Annealing in hydrogen
The approach relying on bonding, grinding and chemical–mechanical polishing can
directly produce any SOI layer thickness 2 μm. In all other techniques growing a
layer of epitaxial silicon to increase the SOI layer thickness would be needed.
overall cost per die and should include all aspects
for consideration, not just the starting wafer price.
Therefore, the choice of material depends strongly on
the application and optimization of the cost and perform­
ance. The prospect of bonded SOI wafers to be used in
large-volume applications is being driven by several fac­
tors. Especially when combined with DRIE, it reduces
the size of the sensor elements, enables unique device
configurations, and also reduces steps in the fabrication
processes of sensor elements. Enhanced device perform­
ance affords a further opportunity for SOI in MEMS.
Thick-Film SOI Wafers: Preparation and Properties
CHAPTER 7
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8
Chapter Eight
Silicon Dioxides
Simo Eränen
VTT Micro and Nanoelectronics, Espoo, Finland
8.1 Introduction
Silicon dioxide is definitely the most common insulator
material in IC technology and in the other fields of silicon
device fabrication technology. The success of silicon diox­
ide in device applications stems from its chemical stabil­
ity and today thoroughly known properties. In the early
days of microelectronics silicon had to find its way against
germanium. The natural thermal oxide of silicon was one
of the factors in its success. Germanium oxide is water
soluble and decomposes at temperatures above 800°C.
In device fabrication silicon dioxides enter and are
produced in several different ways. For instance, silicon
dioxide can be thermally grown on the silicon surface
at elevated temperatures utilizing oxygen or water con­
taining ambient. In this case the growth is based on the
chemical reaction between the silicon atoms and mole­
cules with the oxygen content. On the other hand silicon
dioxides can be deposited on various material surfaces
in microelectronics from usually silane (SiH4) and oxy­
gen gas phases utilizing very diverse deposition chemis­
tries and equipment. As a consequence the rich variety
of growth methods for silicon dioxides appear with the
spans of, e.g., densities, porosities, stoichiometries, film
stresses, refractive indices, electrical breakdown proper­
ties, doping elements, impurities, and etch rates.
In modern integrated circuit technology silicon diox­
ides serve a large number of different functions for the
fabrication and final device structures. From the fabrica­
tion point of view the most essential tasks are diffusion,
etching, ion implantation masking, silicon surface passi­
vation, and ion implantation screening. As to the device
functions the silicon dioxides serve as the capacitor
dielectrics, the isolations dielectrics for, e.g., the multi­
level metallization systems, and the final passivation lay­
ers for the finished devices. For the MEMS fabrica­
tion and devices silicon dioxides are utilized as for the
integrated circuits, but usually the layer thicknesses are
larger and in some applications the optical properties
must be considered. MEMS applications do not need
ultrathin layers like the MOS gate oxides. On the other
hand the nearly conformal growth of thermal oxides is
beneficial for the three-dimensional structures that are
commonplace in the MEMS. However, the relatively
high stress of the thermal oxide prevents utilization for
the MEMS structure layers in some cases, and, con­
sequently, for these layers chemical vapor deposition
(CVD) oxides are rather the materials of choice.
In this chapter the words silicon dioxide and oxide
are used interchangeably.
For microelectronics devices the desirable thicknesses of
the oxides vary over a huge span of several orders of mag­
nitude. On one hand the film thicknesses in the nanom­
eter scale are required in the leading-edge digital circuits.
At the other extreme, today we see emerging MEMS
application with oxide layers of even ten micrometers.
Figure 8.1 shows an example of the utilization of dif­
ferent kinds of silicon dioxides for various purposes in
the fabrication of MEMS devices.
8.2 Growth Methods of
Silicon Dioxide
The following paragraphs describe common oxidation
processes found in MEMS manufacturing.
137
PA R T I
Silicon as MEMS Material
Fig. 8.1 ● Example of utilization of different oxides in MEMS fabrication.
8.2.1 Thermal Oxidation
oxidation on silicon
1,00E+01
W <111> 1100ºC
8.2.1.1 Thermal Oxidation Processes
●
●
●
Oxidizing species are transported from the ambient
to the surface, where the oxide is growing.
Oxidizing species must diffuse through the oxide
onto the silicon–oxide interface.
Oxidizing species react with the silicon atoms at the
silicon–dioxide interface.
138
D <111> 1200ºC
1,00E+00
oxide thickness (microns)
When a silicon wafer experiences an oxidizing ambient at
the elevated temperatures the silicon dioxide is chemi­
cally grown on the surface. The oxidizing ambient is usu­
ally steam, and the process is known as wet oxidation.
If pure oxygen gas is employed, the process is called dry
oxidation.
The basic oxidation kinetics has been dealt in sev­
eral textbooks on silicon technology [1]. The model for
oxide growth was proposed in 1965 by Deal and Grove
[2]. Their model is also known as the linear–parabolic
model and it remains the most important description of
oxide growth. The name stems from the fact that for thin
oxides the film thickness increases linearly with time, but
for prolonged processes the thickness varies as the square
root of time. The model gives a reasonable representa­
tion of the oxide growth on Si over a wide range of thick­
nesses, temperatures and oxidant partial pressures. The
Deal–Grove approach is based on three basic mechanisms
that govern the oxide growth:
W <100> 1100ºC
1,00E-01
1,00E-02
W <111> 900ºC
1,00E-03
0,10
W <100> 900ºC
D <100> 900ºC
1,00
oxidation time (hours)
10,00
Fig. 8.2 ● Dry and wet oxide growth rates (see text for details) on
silicon.
Figure 8.2 shows the growth rates of thermal dry
and wet oxides as a function of temperature and silicon
crystal orientation. The oxidation rate clearly increases
with the temperature. Further, at low temperatures the
growth rate has pronounced dependence on the crystal
orientation of the surface to be oxidized. In addition,
Silicon Dioxides
CHAPTER 8
2250
2000
tox
2000ppm H2O in O2
1750
Oxide
Original silicon surface
0.44*tox
d(Å)
1500
<Ippm H2O in O2
1250
Substrate silicon
H2O– O2 off
1000
750
980ºC <100> Si
H2O– O2 on
500
Fig. 8.4 ● Consumption of Si during the oxide growth.
250
0
0
50
100 150 200 250
300 350
400 450
1 (min)
Fig. 8.3 ● Influence of moisture on the dry oxide growth rate.
Source: Reprinted with permission from ECS—The Electrochemical Society.
the process in steam is 5–10 times faster than in dry
oxidation. These observations are the essential parts of
the linear–parabolic model and rest on the nature of the
basic mechanisms. All the processes involved speed up
with the increasing temperature. For thin oxides the
growth is controlled by the surface reaction of the sili­
con atoms with the oxidizing species. The reaction rate
depends on the number of the reaction sites and is,
consequently, a function of the crystal orientation. For
thick oxides the diffusion transport from the ambient to
the oxide–silicon interface becomes dominant. For the
water molecules the transport seems to be much more
fluent than for the oxygen molecules.
In Figure 8.2 the text boxes for each oxidation curve
indicates the Si surface crystal orientation [(100) or
(111)], the oxidation mode (wet W or dry D), and
the process temperature. The curves have been calcu­
lated using the rate coefficients given by S.M. Sze [3].
Of course, wet and dry oxidation are not well-defined
concepts, since to some extent water vapor exists every­
where. It has been shown that even small amounts of
water vapor in the oxygen can have drastic influence on
the linear and parabolic oxidation rate constant. This is
shown in Figure 8.3 [4].
8.2.1.2 Consumption of Si During Oxidation
As described in the Deal–Grove model the oxidation reac­
tion takes place at the silicon–oxide interface. Thus, when
the oxide grows, silicon is consumed and the interface
moves into the silicon. Based on the densities and molecu­
lar weights of Si and SiO2 it is observed that the thickness
of the consumed silicon layer is 44% of the total oxide
thickness. This is illustrated in Figure 8.4.
8.2.1.3 Dopant Effects
The doping elements like boron, phosphorus, and
arsenic are inevitably present in the oxidation processes
of the silicon devices as the oxide growth consumes
silicon material. This fact has influences on the oxide
growth and on the other hand on the element concen­
tration distribution.
Let us first consider the doping element redistribution
effects. The important parameters here are the element
diffusion coefficients in the silicon and the oxide and the
segregation coefficient on the oxide–silicon interface.
The diffusion coefficient describes the rapidity of the
element movement to find its thermodynamical equilib­
rium position. On the other hand, the segregation coeffi­
cient m (ratio of the dopant concentration on the silicon
side to the same dopant concentration on the oxide side
of the interface) determines the concentrations of the
impurities near the interface of the adjacent phases.
For instance, if m 1 the doping elements like to
reside on the oxide side. Furthermore, if the diffusion
in the oxide is low, a high concentration of dopants will
be inside the oxide layer. On the other hand, if the dif­
fusion of the dopant elements is fast through the oxide,
the dopants may have a tendency to escape from the
oxide into the gaseous ambient. The latter case leads to
a low dopant concentration in the oxide and further to
the depletion of the silicon surface. In the opposite case
m 1 and the oxide rejects the dopants. If now the dif­
fusion through the oxide is slow, the dopants will pile up
on the silicon side. However, if for m 1 the diffusion
is fast, the dopants again can escape into the ambient,
which results in the silicon depletion of the dopants.
The four cases above are schematically described in
Figure 8.5 [5]. Here the case A is valid for boron in the
oxidizing environment, whereas the case B is for boron
in the H2 atmosphere, where the diffusion constant of
boron in the oxide rapidly increases. Case C applies for
phosphorus and arsenic, and case D for gallium.
The presence of a high concentration of the common
doping elements is known to enhance the oxide growth.
139
Silicon as MEMS Material
PA R T I
Case 1: Oxide takes up impurity (m < 1)
Oxide
10–2
Oxide
Silicon
Silicon
CB
CB
10–3
B/A(μ/min)
A
10–4
B
(A) Diffusion in oxide slow
B(μ2/min)
(B) Diffusion in oxide fast
Case 2: Oxide rejects impurity (m > 1)
Oxide
1018
1020
1021
CBC(cm–3)
Oxide
Silicon
1019
Silicon
CB
Fig. 8.6 ● Influence of the phosphorus doping on the oxidation
rate constants.
CB
Source: Reprinted with permission from ECS–The Electrochemical Society.
for the linear rate constant above the P concentration of
4 1019cm3.
C
D
8.2.1.4 Chlorine Effects
(A) Diffusion in oxide slow
(B) Diffusion in oxide fast
Fig. 8.5 ● Dopant redistribution in oxide and silicon during hightemperature processing.
Source: Reprinted with permission from Journal of Applied Physics.
Copyright 1964, American Institute of Physics.
The mechanisms of growth enhancement however, are
not the same for all the dopants. For instance, the segre­
gation coefficient of boron in the silicon–oxide interface
is clearly less than unity and the boron atoms tend to
pile up into the growing oxide. In practice the concentra­
tion of boron atoms is a factor of ten larger on the oxide
side than on the silicon surface. In the oxide the boron
atoms influence the silica structure, increasing the diffu­
sion coefficient of the oxidizing species. However, for the
effect to be observable the boron concentration in the
oxide must be larger than 1020cm3. The other p-type
dopants (i.e., Al and Ga) that have high diffusion coef­
ficients in the oxide do not cause the same effect [6].
For the high surface concentrations of the group V
dopant elements P and As the oxide growth rate enhance­
ment is observed as well. However, the mechanism is dif­
ferent. Since the oxide rejects the dopants in this case,
the growth enhancement is expected in the linear growth
regime. Again, for the effect to be visible the dopant
surface concentration must be larger than 1019cm3.
Figure 8.6 shows the dependence of the oxidation rate
constants on the phosphorus doping level of the silicon
substrate [7]. Clearly a marked enhancement is observed
140
Most of the modern oxidation furnace tubes are equipped
with chlorine chemistry for the cleaning of the quartz
ware at high temperatures. The conventional chlorine
compounds were Cl2 and HCl, but today organic Cl
compounds have gained the dominant role. The chlorine
reacts with the metallic impurities creating volatile reac­
tion products that are swept away to the exhaust from the
oxidation tube. It has also been found that the addition of
chlorine into oxygen flow in the dry oxidation process has
beneficial effects on the oxide quality. For instance, chlo­
rine improves the dielectric strength, improves the carrier
lifetime in silicon, and reduces the oxidation defects and
the oxide charges.
In addition, in the dry oxidation process chlorine
increases the oxide growth rate. Figure 8.7 shows an exam­
ple of the dry oxide thickness for various O2/HCl mixtures
at 1000°C on the 100 and 111 substrates [8]. It is
easily seen that the chlorine addition has an influence on
the thin and thick oxides.
8.2.1.5 Pressure Effects—HIPOX
The high-pressure oxidation (HIPOX) technique is
employed when it is desirable to increase the oxide
growth (e.g., for the growth of thick oxides). The other
alternative is the wish to maintain the normal growth
rate at decreased temperatures. The HIPOX process is
usually run in vertical furnaces in the temperature range
from 600°C to 1200°C. The operating pressure can be
as high as 25 atm.
Silicon Dioxides
A
1.0
B
1.0
(100) Si orientation
Oxide thickness (μm)
(111) Si orientation
Oxide thickness (μm)
CHAPTER 8
0.1
= 10% HCl
= 5% HCl
= 1% HCl
= 0% HCl
0.1
= 10% HCl
= 5% HCl
= 1% HCl
= 0% HCl
0.01
0.01
0.1
1.0
10.0
100.0
Oxidation time (h)
0.1
1.0
10.0
100.0
Oxidation time (h)
Fig. 8.7 ● Influence of chlorine on dry oxide growth rate.
Source: Reprinted with permission from ECS—The Electrochemical Society.
The rate constants in the Deal–Grove model depend
on partial pressure of the oxidizing species. The linear
rate constant depends linearly on the partial pressure,
whereas the dependence of the parabolic constant fol­
lows the law P0.6…0.8 depending on the temperature
range and the ambient. For instance, Lie et al. [9] stud­
ied the dry oxidation of the 100 and 111 silicon
in the temperature range of 800–1000°C and pressure
range of 1–20 atm. For the linear rate coefficient they
found the linear pressure dependence and for the para­
bolic rate coefficient the P0.7 law. Altogether the oxide
thickness has a sublinear dependence on the oxygen par­
tial pressure, but at 20 atm the gain on the oxide growth
rate is of the order of a factor of ten.
8.2.1.6 Oxidation of Polysilicon
The polycrystalline silicon—like crystalline Si—forms
an oxide layer in the oxidizing atmosphere. This oxide is
an important device layer for, e.g., DRAM cells and sev­
eral surface micromachined devices. The oxidation rate
of polysilicon is very much case dependent, but as a rule
of thumb, the first approximation of the oxidation rate
is that of the crystalline silicon with the equivalent proc­
ess and doping conditions. The other influencing factors
are the grain size and the accompanying stress, dopant
type and concentration, and the grain orientation [1].
Probably due to the stress induced by the grain bounda­
ries the oxidation rate of the polysilicon is initially faster
than for the crystalline silicon. However, for the thicker
oxides the kinematic rates become equal, because the
growth is governed by the diffusion of the oxidizing spe­
cies through the oxide. Further considerations on the oxi­
dation of the undoped and phosphorus-doped polysilicon
layer can be found, e.g., in Wang et al. [10].
Figure 8.8 shows an oxide layer grown on a borondoped thick polysilicon layer. In this case the polysili­
con has been grown utilizing a fast deposition process
(40 nm/min) at 680°C. Here the oxidation rate is well
Si substrate
Polycrystalline
silicon
Oxide
Fig. 8.8 ● A SEM on 300-nm oxide on thick polysilicon.
in accord with the rate of the crystalline silicon with a
moderate doping level.
8.2.1.7 Stress in Silicon Dioxide
There are two sources of oxide stress in the thermal
oxidation processes of silicon surfaces. The first one is
the so called residual stress that stems from the differ­
ent thermal expansion coefficients of silicon and oxide. The
thermal expansion of silicon is about five times higher
than that of oxide. Thus, during the cool-down period
from the process temperature to the room temperature
silicon contracts more, which creates a compressive
stress on the order of 100 MPa into the oxide layer.
The second source of stress is due to the oxide growth
mechanism at the silicon–oxide interface. The SiO2
molecules that are formed during the growth have about
twice the volume of the original silicon atoms. This
causes compressive stress on the order of 700 MPa into
the oxide layer. Experiments have shown that this stress
component disappears when the temperature is raised
141
PA R T I
Silicon as MEMS Material
above 965°C. This is interpreted in a way that the oxide
layer can perform a viscous flow above that temperature,
thus relaxing the stress inside the film [1, 11].
Temperature (°C)
1250
80
1200
1150
1100
60
8.2.2 CVD Oxide Growth Methods
In semiconductor fabrication various kinds of insulating,
semiconducting, and metallic thin films are deposited on
the substrates via CVD methods. Usually the CVD films
are amorphous or polycrystalline. In the CVD growth
the gases that contain the desired species for the film for­
mation are reacted in the growth chamber and form the
target film on the substrate. Unlike in the case of the
thermal oxide, the CVD films do not usually react with
substrate. Thus the film growth does not consume the
substrate and the films can be deposited on several kinds
of materials.
For CVD a large variety of systems that must exhibit
economical ways to produce high-quality films in terms
of, e.g., uniformity, purity, electrical properties, step
142
50
0.5
0.69 eV
40
30
Size of stacking faults (μm)
Like all the high-temperature processing steps, oxidation
tends to introduce defects into the silicon crystal. The
crystallographic defects in silicon are usually quite mobile
at high temperatures and thus their density, distribution,
and type will vary due to the subsequent processing steps.
Stacking faults are the most important area defects
that degrade the performance of the integrated devices.
Oxidation-induced stacking faults (OISFs) have been
found to be of the extrinsic type, which suggests that
the extra lattice plane is formed by the injection of self­
interstitials into the lattice during the oxidation [1].
Since stacking faults are surrounded by dislocations, the
fast-diffusing (metallic) impurities can be trapped by
these dislocations. This is an extra mechanism for the
device degradation, since the trapped impurities tend to
increase, e.g., the leakage currents.
During the oxidation the OISFs can grow as the proc­
ess proceeds, but under certain conditions the OISFs
can be made to shrink as well. Figure 8.9 [12] shows
that above the temperature of 1150°C the growth of the
stacking faults during dry oxidation stops and the alreadygenerated defects start to dissolve. In addition, the pres­
ence of the chlorine compounds during the oxidation is
shown to reduce the growth of the OISFs. This is due to
the vacancies introduced by chlorine. The vacancies serve
as the annihilation sites for the excess silicon atoms and
thus partly prevent defect formation [13].
The well-known textbook by Ravi [14] displays a rich
variety of the OISFs revealed by the preferential etching
and microscopy. The same reference gives an in-depth
discussion on the growth mechanisms and dynamics of
OISFs.
0.4
x
Oxide
thickness
|100|
0.3
x
20
0.2
x
15
2.3 eV
0.1
10
8
Oxide thickness (μm)
8.2.1.8 Oxidation-Induced Defects in Silicon
6
5
4
|100|
|111|
5° Off |100|
0.68
0.70
3
2
0.64
0.66
3
0.72
0.74
–1
10 / T(°K )
Fig. 8.9 ● Dynamics of OISF growth.
Source: Reprinted with permission from Journal of Applied Physics.
Copyright 1975, American Institute of Physics.
coverage, and adhesion are employed. The science and
technology of CVD includes special knowledge in sev­
eral fields of science and engineering like chemistry,
thermodynamics, plasmas, gas dynamics, RF aspects,
vacuum technology, and mechanical design.
In 1966 Grove developed a simplified model for the
deposition of the CVD films [15]. The model includes
aspects that are similar to those of the Deal–Grove model
for thermal oxidation, like the diffusion transport of the
reactant species over the boundary layer from the gas
phase to the substrate surface. In the CVD case the reac­
tants form precursors—sometimes called adatoms—that
undergo surface migration to the surface sites, where the
film growth takes place. After the reaction the byprod­
ucts are transported away from the site to the outlet of
the process chamber. Usually the low-pressure CVD
(LPCVD) processes run under the surface reaction lim­
ited mode, where the surface reaction has the Arrhenius­
type temperature dependence exp(–Ea/kT), Ea being the
activation energy. In order to guarantee the uniform film
growth, it is essential to ensure a uniform temperature
over all the substrate surface. Then the arrival rate of the
reactant species at the wafer surfaces is not as important,
Silicon Dioxides
CHAPTER 8
CVD processes
Low pressure
Atmospheric
Tube
reactor (LPCVD)
Showerhead
reactor (SACVD)
ALD reactor
Plasma reactor
(PECVD)
ALD
Plasma
ALD
Tube
(batch)
Epitaxial
reactor
Single
wafer
Tube reactor
Planar reactor
Barrel
(Batch)
Pancake
(batch)
Single
wafer
Pancake
(batch)
Pancake
(minibatch)
Fig. 8.10 ● Types of CVD reactors.
since usually the reactor design can guarantee sufficient
gas feed at all the important locations of the chamber. For
the atmospheric pressure CVD (APCVD) processes the
reverse is true. In the mass-transport limited processes
like APCVD the temperature control is not so critical.
All the reactant species arriving at the substrate surface
will take part in the film-forming reaction [1].
CVD reactors come in several different designs.
The reactors can be of the cold or hot wall type, which
means that the reactor walls are either at a lower tem­
perature than, or at the same temperature as, the wafers.
Secondly, the reactor can work at the atmospheric pres­
sure range (APCVD) or at reduced pressure on the order
of 10 mtorr to 1 torr. And, finally, for the LPCVD systems
the energy for the growth reaction is either purely thermal
or enhanced with a plasma source. The latter type of reac­
tor is called a plasma-enhanced CVD (PECVD) system.
Figure 8.10 summarizes the types of CVD reactors.
8.2.2.1 CVD Oxides
The Chemical Vapour Deposition (CVD) of the sili­
con dioxides takes several approaches in silicon device
manufacturing, where these films are utilized to accom­
plish a large number of different functions. For MEMS
devices the most important ones are cavity liners, deep
silicon etch masking, trench and hole filling, sacrificial
layers, passivation, and optical tuning layers.
One of the most popular oxide CVD processes is the
so-called low-temperature oxide (LTO). This process
is based on the reaction of silane (SiH4) and oxygen in
order to form an oxide layer at relatively low tempera­
tures. The process temperatures can vary over a con­
siderable span from 200°C to 450°C depending on the
reactor type, since this deposition process may be per­
formed in the APCVD, LPCVD, or PECVD systems.
An alternative chemistry for the CVD oxide deposi­
tion is offered by the TEOS systems. TEOS—also known
as tetraethyl orthosilicate Si(OC2H5)4—is a liquid com­
pound that is usually delivered into LPCVD equipment
using the nitrogen bubbler. The reaction temperature is
higher than for the LTO (around 700°C), but the ben­
efit is more conformal films than in silane chemistry. An
extra benefit is the added safety of the processing.
The TEOS processes are employed in the PECVD reac­
tors, as well. In this case the deposition temperatures are
below 450°C and the conformality of the films is superior
compared with that of the silane-based processes. A fur­
ther approach utilizing the TEOS process is to add ozone
(O3) into the TEOS vapor in the APCVD processes.
As shown in Table 8.1 one of the aspects of CVD dep­
osition of the oxides is the possibility of doping the grow­
ing oxide with network-forming elements (see paragraph
8.3) like boron and phosphorus. For this phosphine and
diborane are the most common source gases. The addition
of phosphorus into the CVD oxide forms phosphosilicate
143
Silicon as MEMS Material
PA R T I
Table 8.1 Deposition conditions for several CVD oxides
Growth temperature (°C)
Growth rate
Reactants
LPCVD TEOS
680–730
25 nm/min
TEOS
APCVD
250–450
1 μm/min
SiH4 and O2
PH3/B2H6
PECVD
200–400
SiH4 and N2O/NO
SiH4 and O2
PH3/B2H6
PECVD TEOS
250–425
800 nm/min
TEOS
TMP/TMB
LPCVD
400–500
300 nm/min
SiH4 and O2
PH3/B2H6
Ozone TEOS
300–400
200 nm/min
TEOS and O3
TEOP/TMB
AP-PECVD
300–500
20 nm/min
HMDSO and O2
glass (PSG). The dopant concentrations are usually rela­
tively high, reaching a few weight percentages. This
results, e.g., in reduced stress and improved step coverage
(see paragraph 2.3). An important feature of PSG is the
opportunity to flow the material at elevated temperatures
(above 1000°C), which leads to the improved surface
topography. Adding boron into the PSG will form boro­
phosphosilicate glass (BPSG) with a lower flow tempera­
ture than for PSG.
The comparison table above summarizes the growth
parameters of the various CVD oxides.
8.2.3 Multidimensional Effects
So far the oxidation effects on planar surfaces have been
considered. In the silicon technology there are, however,
a vast number of cases where the oxide layers must be
formed on the vertical walls and over the convex or con­
cave corners in the device structures, where the two- and
three-dimensional phenomena become effective. These
are common in a huge number of MEMS structures and
also in IC devices, including, e.g., the trench capacitors
of memory devices and the shallow trench isolation tech­
nology. A well-known example of the multidimensional
effects is the formation of the “bird’s peak” during the
LOCOS isolation in CMOS processing. Here the active
area of the transistor is protected by a nitride layer during
the growth of the thick field oxide [16]. The nitride layer
effectively stops the diffusion of oxygen species through
the film, thus preventing oxide growth on the active
area. The oxygen can, however, diffuse sideways around
the edge of the nitride pattern and form a tapered oxide
layer under the outer rim of the nitride.
The growth of the thermal oxide on the vertical and
horizontal surface is generally understood to take place in
144
Doping
a similar fashion. Consider for instance a thermal oxida­
tion process on a cavity with vertical walls that has been
etched into the silicon substrate. After the process the
oxide thickness is equivalent on the horizontal and ver­
tical surfaces, if the crystal orientations are identical.
At the corners, however, the situation is different. The
oxidation species have different opportunities to diffuse
through the oxide layer in order to react with fresh silicon
depending on whether the corner is convex or concave.
Consequently, it is expected that the oxide thickness at
the concave corners is thinner than at the convex corners.
In fact, the situation is more complicated with aniso­
tropic stress and temperature-dependent oxidation rates.
So if the oxide thickness is critical for the device opera­
tion, each case should be studied three-dimensionally on
an individual basis (Figure 8.11) [17, 21].
For CVD oxide films the conformality on the surface
topography is an important figure of merit, as well. In
practice, people speak about the “step coverage”, which
means the ratio of the film thicknesses on the vertical
and horizontal surfaces. The step coverage of the CVD
films depends on the interplay of several factors like the
arrival angle of the reactants on the specific point of the
substrate surface, the sticking coefficient, and the sur­
face transport of the precursors on the surface [1].
8.3 Structure and Properties of
Silicon Dioxides
The thermally grown silicon dioxide on silicon is amor­
phous (i.e., noncrystalline). The noncrystalline phase
likes to develop towards the thermodynamic equilib­
rium structure (i.e., the crystalline quartz). This proc­
ess is known as the devitrification, and the speed of the
Silicon Dioxides
CHAPTER 8
Fig. 8.11 ● Thermal oxide on convex
and concave corners.
process is temperature dependent—approaching zero
below 1000°C. In several cases the devitrification is a
problem, for instance for the furnace hardware, but it is
not usually observed in the device fabrication, because
in these cases the high-temperature treatments are
much shorter than for the furnace hardware.
The structural models for the amorphous silicon dioxide
have been explained, e.g., by Revesz [18]. The basic struc­
tural unit of the silicon dioxide is a tetrahedron formed by
a silicon atom and four oxygen atoms. The silicon atom sits
in the center of the structure and is chemically bonded to
the oxygen atoms in the four corners of the tetrahedron.
The oxygen atom has two valence electrons, and thus it
has a possibility to form a bond to the silicon atom of the
neighboring tetrahedron. Since the oxide is amorphous,
all of the oxygen atoms do not form bonds between the
adjacent structural units. Consequently, depending on the
bonding state of the oxygen atoms, they are referred to as
bridging or nonbridging oxygen. The amorphous structure
forms a more open network and thus the density of the
oxide is less than the crystalline form (i.e., the quartz).
Figure 8.12 shows the basic, two-dimensional model
of the silicon dioxide as described by Revesz [18]. The
structural unit is shown as a triangle. In addition, the
picture shows several possible defects in the structure.
Further, structural defects (impurities)—substitutional
or interstitial—can be present. In modern technology
the most important substitutional impurities are boron
and phosphorus replacing silicon atoms. These impu­
rities can be the core of glassy structures and are thus
named as the network formers.
Table 8.2 gives an indication of the basic physical prop­
erties of silicon dioxide. These values apply to the ther­
mally grown oxides. With the various CVD oxides the
situation becomes more complicated, since these may
depend on the growth conditions and the subsequent
thermal history of the layer. For instance, the CVD oxides
deposited at low temperatures have lower density and
varying indices of refraction, stoichiometry, and stress.
In addition, the etch rates may increase in the standard
processing conditions. However, as a rule of thumb the
properties of the CVD oxides approach those of the ther­
mal oxides, when the post-growth annealing tempera­
tures are approaching the values of the thermal oxidation.
Moreover, the PECVD deposition processes may result in
additional impurities like hydrogen in the oxide layers.
8.4 Processing of Silicon
Dioxides
The preceding sections have concentrated on the various
aspects of the growth and deposition of silicon dioxides.
The present section touches on topics of oxide process­
ing, cleaning and etching.
8.4.1 Cleaning
Usually in microelectronics fabrication the wafercleaning steps are performed before the high-temperature,
layer deposition and/or lithography process steps. The
145
Silicon as MEMS Material
PA R T I
Legend:
Si network former
Acceptor type network former or intermediate
Donor type network former or intermediate
Bridging oxygen
Non-bridging oxygen
Bridging oxygen vacancy (vob)
~
Individual non-bridging oxygen vacancy (vo )
nb
~
~
Non-bridging oxygen interstitial
(associated with the network) (oi,a)
Individual interstitial oxygen
(not associated with the network) (oi)
Univalent anion (e.g., OH– ) in the position of
non-bridging oxygen
Interstitial cation (network modifier or
+
intermediate), e.g., Na
Interstitial cation (network modifier or
intermediate), e.g., Ba++
Fig. 8.12 ● A basic two-dimensional model of the silicon dioxide as described by Revesz [18]. The basic tetrahedrons are shown as triangles.
Source: Reprinted with permission from IEEE Transactions of Electron Devices, Copyright 1965 IEEE.
Table 8.2 Properties of silicon dioxide
Dielectric constant
3.9
Thermal conductivity (W/cm2 °C)
0.014
Breakdown field (MV/cm)
6
Thermal expansion coefficient (ppm/°C)
0.05
Density (g/cm3)
2.27
Melting point (°C)
1700
DC resistivity (ohm/cm)
1016
Molecules/cm3
2.3 1023
Energy gap (eV)
9
Refractive index
1.46
intention of the cleaning is to remove particles and pho­
toresistant residues, metallic impurities, and organic
contamination.
Usually, in the course of growing fresh oxides or
depositing oxide layers on nonmetallic films (oxide, polysilicon, silicon nitride), a so-called standard clean (SC)
sequence is employed. This consists of three steps usu­
ally named as SC1, DHF, and SC2. The alkaline SC1
bath is a mixture of hydrogen peroxide and ammonium
hydroxide diluted in the DI water. The classical blend
is 1:1:5 (NH4OH:H2O2:H2O), but many other blends,
especially towards the decreasing reactant concentra­
tions, have been employed. Here, however, the balance
between H2O2 and NH4OH has to be maintained in
order to avoid increasing surface roughness of the sili­
con surface [19]. Normally, the SC1 bath temperature
is between 40°C and 80°C. The aim of the SC1 steps
is to attack the particles and organic contamination.
The DHF (dilute hydrofluoric acid) step is applied in
order to remove the chemical oxide that grows in the
146
SC1 bath. Here the wafers are immersed into a diluted,
room-temperature HF solution for a short time. The
last SC2 process targets at the metallic impurities. The
bath is a water mixture of HCl and H2O2 at an elevated
temperature. The SC2 is important for many active
devices like transistors, because the metallic impurities
tend to degrade the device performance. However, for
MEMS devices, where the metallic impurity contamina­
tion can be tolerated, the DHF and SC2 can be skipped
in several occasions.
Another acidic clean that is effective against organic
contaminants and metallic impurities is the so-called
Piranha solution. The bath consists of a hot (110°C)
mixture of H2SO4 and H2O2, and the most frequent
use is against the badly damaged photoresists after the
plasma etching or ion implantation.
When metallic layers—usually aluminum—have been
deposited and patterned on the wafers, the aggressive
alkaline or acidic baths can no longer be applied. In sev­
eral fabrication processes, however, the PECVD layers
Silicon Dioxides
or LTO oxidations are needed on the metallization. In
these cases usually solvent cleanings using IPA or ace­
tone are employed.
8.4.2 Etching
Etching is a method for the material removal in many
industrial processes. In microelectronics fabrication there
must exist processes to selectively etch practically all the
materials involved in the fabrication flow. That is, there
must be a masking material that is relatively insensitive
to the etching process. This material covers the chip sites
that should not be etched. In addition, the etching proc­
ess should not be too aggressive for the materials that
lie under the layer to be etched. The etching of silicon
dioxide has traditionally been done using wet chemicals
like HF or BHF/BOE (buffered hydrofluoric acid/buff­
ered oxide etch). In most cases the photoresist serves as
the masking material, but for the very thick oxide layers
(2 μm) the silicon nitride is preferable.
Usually, the oxide wet etching is done employing
near-room-temperature processing. For HF etching the
etch rate depends on the concentration of the etchant
in the water. In order to form the buffered solution,
ammonium fluoride (NH4F) is added to the HF bath in
order to reduce the attack against the photoresist mask­
ing layer. NH4F particularly helps to avoid the delamina­
tion of the photoresist mask on the oxide surface, which
decreases the etch undercut below the masking layer.
In practice the concentration of HF varies in a large
range from 1% to 49% in DIW. The high concentra­
tions are employed in order to achieve high etch rates
(1 μm/min), but the disadvantage is the photoresist
delamination. On the other hand, diluted HF baths are
for the native oxide removal and silicon surface treat­
ments. The BOE baths can provide moderate etch­
ing rates that depend on the ratio of the NH4F to HF
concentrations. For instance, the ratio (NH4F:HF) 7:1
at room temperature results in an etching rate of about
100 nm/min.
Etching with the HF or BHF solutions stops at the Si–
SiO2 interface, and usually there is no risk of the increased
Si surface microroughness. However, if the etchant
solution is contaminated with metallic ions with a high
CHAPTER 8
electronegativity, like copper, there is a chance that the
silicon surface will experience pitting corrosion [19].
Due to the amorphous structure of the silicon diox­
ide the wet etching is isotropic (i.e., the etching pro­
ceeds in each direction at the equivalent rate). Thus the
etching influences the dimensions of the layer under
the masking material, too. This may create a problem
when the size of the etch patterns are shrinking. When
the thickness of the film to be etched becomes close to
the size of the lateral dimension of the film pattern, the
undercutting due to the isotropic wet etching cannot be
accepted. This means that below the feature size of a
few microns wet etching calls for an alternative process­
ing scheme. This anisotropic mode is offered by socalled dry etching that is based on the plasma physics at
reduced pressures in the RF-powered reactors.
For dry etching in wafer fabrication the reaction cham­
bers vary a lot in the geometrical configuration, pressure
range, materials, RF-coupling mode and etchants that are
fed into the chamber in the gaseous phase [1]. For dry
etching of silicon dioxide, fluorine-containing molecules
such as CF4, SF6, NF3, and CHF3 are normally employed.
Other gases like O2, Ar, and He can be added, e.g., for
heat transfer, plasma, stabilization, and enhanced ioniza­
tion. Typical etch rates for the oxides are in the range of
several hundred nanometers per minute. Contrary to the
wet etching several additional aspects must be consid­
ered for the dry process. These include the selectivities
or etch rates of the etching process to the masking layer
(photoresist) and to the materials underlying the oxide
film. Typical values are 10:1, meaning that the oxide
layer is consumed ten times faster than the other materi­
als. Further, the degree of the anisotropy or the lateral
etch rate and the side wall profile must be taken into
account. In several cases the etch rate depends on the
area to be etched. This is the so-called loading effect.
A recommended introduction to these effects can be
found in a book by Wolf and Tauber [1].
A recently developed alternative for the oxide etching
is HF vapor etching, which is especially suitable for the
dry, stiction-free release processes of MEMS structures.
This process combines anhydrous HF gas-phase etching
with alcohol vapor at reduced pressure [20]. The spe­
cial feature of the process is the selectivity against other
common materials, including aluminum.
References
1. S. Wolf, RN. Tauber, Silicon Processing
for the VLSI ERA, second ed., Lattice
Press, 2000.
2. B.E. Deal, A.S. Grove, General
relationship for the thermal oxidation
of silicon, J. Appl. Phys. 36 (1965)
3770.
3. S.M. Sze, Semiconductor Devices.
Physics and Technology, John Wiley &
Sons, 1985.
4. E.A. Irene, R. Ghez H.R. Huff, E. Sirtl
(Eds.), Semiconductor Silicon, The
Electrochemical Society, 1977,
p. 313.
5. A.S. Grove, O. Leistiko Jr., CT. Sah,
Redistribution of acceptor and donor
impurities during thermal oxidation of
silicon, J. Appl. Phys. 35 (1964) 2695.
6. B.E. Deal, M. Sklar, Thermal oxidation
of heavily doped silicon, J. Electrochem.
Soc. 112 (1965) 430.
147
PA R T I
Silicon as MEMS Material
7. C.P. Ho, J.D. Plummer, J.D. Meindl,
B.E. Deal, Thermal oxidation of
heavily phosphorus-doped silicon,
J. Electrochem. Soc. 125 (1977) 665.
8. D.W. Hess, B.E. Deal, Kinetics of the
thermal oxidation of silicon in O2/HCl
mixtures, J. Electrochem. Soc. 124
(1977) 735.
9. L.N. Lie, R.R. Razouk, B.E. Deal,
High pressure oxidation of silicon in
dry oxygen, J. Electrochem. Soc. 129
(1982) 2828.
10. Y. Wang, J. Tao, S. Tong, T. Sun,
A. Zhang, S. Feng, The oxidation kinetics
of thin polycrystalline silicon films,
J. Electrochem. Soc. 138 (1991) 214.
11. E.P. EerNisse, Stress in thermal SiO2
during growth, Appl. Phys. Lett. 35
(1979) 8.
148
12. SM. Hu, Anomalous temperature
effect of oxidation stacking faults in
silicon, Appl. Phys. Lett. 17 (1975)
165.
13. C.W. Pearce, V.C. Kannan, Saucer pits
in silicon, in: Defects in Silicon, The
Electrochemical Society, Pennington,
NJ, 1983, p. 396.
14. K.V. Ravi, Imperfection and Impurities
in Semiconductor Silicon, John Wiley
& Sons, Inc., 1981.
15. A.S. Grove, Mass transfer in
semiconductor technology, Ind. Eng.
Chem. 58 (7) (1966) 48.
16. J.L. Fay, J. Beluch, B. Despax,
G. Sarrabayrouse, Feasibility of an
isolation by local oxidation of silicon
without field implant, Solid State
Electron. 45 (2001) 1257.
17. D-B. Kao, J-P. McVittie, W.D. Nix, K.
C. Saraswat, Two-dimensional thermal
oxidation of silicon-II, modeling stress
effects in wet oxides, IEEE Trans.
Electron Devices ED-35 (1988) 25.
18. A.G. Revesz, The defect structure of
grown silicon dioxide films, IEEE Trans.
Electron Devices ED-12 (1965) 97.
19. T. FutatsukiT. Hattori (Ed.),
Ultraclean Surface Processing of
Silicon Wafers, Springer, 1988.
20. W.I. Jang, C.A. Choi, M.L. Lee,
C.H. Jun, Y.T. Kim, Fabrication of
MEMS devices by using anhydrous
HF gas-phase etching with alcoholic
vapor, J. Micromech. Microeng. 12
(2002) 297.
21. M. Radi, http://www.iue.tuwien.ac.at/
phd/radi/
9
Chapter Nine
Multiscale Modeling Methods
Teruaki Motooka
Kyushu University, Fukuoka, Japan
9.1 Macroscopic and Microscopic
Equations
In order to analyze the characteristics of MEMS devices,
it is usually good enough to use macroscopic or classical
equations. For example, mechanical and electromagnetic
properties can be respectively described by the Navier’s
equation
d
∂2 u
∂t 2
∇× c∇u F
(9.1)
and the Maxwell’s equations
∇× D ρ
(9.2)
∂B
∇ ×E ∂t
∇× B = 0
(9.3)
(9.4)
and
∇× H = j +
∂D
∂t
(9.5)
Here, in the Navier’s equation u is the displacement
vector, (∂/∂r in the Cartesian coordinate system)
represents the nabla operator, F is a body force, d and
c are the material parameters; density and elastic con­
stant (generally tensor), respectively. In the Maxwell’s
equations, D is the electric displacement vector, E is the
electric field vector, B is the magnetic flux density, H is
the magnetic field intensity, ρ and j are the charge den­
sity and current density, respectively. These vectors are
related with the material parameters (dielectric con­
stant), μ (magnetic permeability), and σ (electric con­
ductivity) as follows: D E, B μH, and j σE. In
these classical equations, the physical quantities can be
definitely determined as a function of space r and time t.
Materials are made by huge numbers of atoms com­
posed of nuclei and electrons. Electron is one of the
most important elementary particles and its motion
is governed by the Schrödinger equation which is the
basic equation in the microscopic or quantum mechani­
cal world. For example, the Schrödinger equation of an
atom with the atomic number Z can be written as
⎤
⎡
2 Z ⎛
2⎞
Z
e2 ⎥
⎢ �
⎜⎜∇2 Ze ⎟⎟
⎥
⎢
⎟⎟ ∑
∑
i
⎜
ri ⎠ i j ri rj ⎥
⎢ 2m i1 ⎜⎝
⎣
⎦
× Ψ(rr1 ,r2 ,…,rZ ) EΨ (r1 ,r2 ,…,rZ )
(9.6)
where m and e are the electron mass and charge, respec­
tively, h indicates the Dirac constant, �i is the nabla
operator on the i-th electron at the position ri. This is
the typical eigenvalue problem. In the left-hand side,
the Hamiltonian operator composed of the kinetic
energy, attractive potential energy with the nucleus
positioned at the center, and repulsive potential energy
of the electron system operates on the wavefunction
Ψ(r1, r2,…, rz) as the eigenfunction. In the right-hand
side, E represents the energy of the atom as the eigen­
value of the Hamiltonian operator. It should be noted
that, in the microscopic world, all physical quantities are
operators operating on wavefunctions and the observed
values are the eigenvalues of these operators. Since the
151
Modeling in MEMS
PA R T I I
wavefunction is generally superposed by various eigen­
functions corresponding to each operator, the physical
quantity is, unlike that in the macroscopic or classical
world, not deterministic, but probabilistic depending on
the wavefunction at the time of observation.
It is sometimes necessary to analyze MEMS charac­
teristics not only in the macroscopic scale (typically m
size) but also in the microscopic scale (typically nm size).
A typical example is the analysis of the I-V characteris­
tic of a nanopore device for DNA molecular sensing [1].
Figure 9.1 shows a schematic diagram of this device
which is generally operated by measuring the reduc­
tion of K and Cl ionic currents through a nanopore
in a solid-state membrane separating two Teflon cham­
bers containing solutions of electrolyte and DNA. DNA
molecules are driven from the cis to trans sides through
the nanopore by an applied voltage between two elec­
trodes set apart at a macroscopic distance, typically mm
scale. On the other hand, the current reduction is due
to DNA translocations at the nanopore. Thus, in order
to theoretically obtain the I-V characteristic, it is neces­
sary to solve appropriate equations in both macroscopic
and microscopic scales. One of the basic equations is
the Poisson equation,
∇× ε∇ϕ(r ) ρ(r )
where ϕ(r) is the electrostatic potential (ESP) defined
as the potential energy of a test unit charge at the posi­
tion r. Equation 9.7 is deduced from Eq. 9.2 by using
the relations E �ϕ and D E ( is generally ten­
sor and depending on r.) If is a scalar constant, Eq. 9.7
is reduced to a more familiar form, �2ϕ –ρ/.
In the classical theory, the potential energy of a sin­
gle electron at the position r can be expressed as –eϕ(r)
by using ESP. However, in the microscopic theory, Eq.
9.7 is only an approximation. For example, the electron
potential energy in a many-particle system such as in
the atom described earlier is not only a function of r but
also depends on the coordinates of the Z-electrons
V(r,r1 , r2 ,… ,rZ ) Ze2
r
Z
i1
K
Cl
+
K
Cl–
Cl–
SiO2
A
Si
ssDNA–
Teflon
trans side
V
K+
Cl–
Cl–
Fig 9.1 ● Schematic diagram of a DNA microscope. A singlestranded DNA (ssDNA) is translocated through a nanopore.
152
ι
(9.8)
In order to solve Eq. 9.7, the electron poten­
tial described in Eq. 9.8 is averaged over the electron
motions with the coordinates r1, r2, …, rz. This can
be performed in the framework of the quasi-classical
approximation [2] based on the one-electron model in
which each electron independently moves in an aver­
aged potential field made by the other electrons. After
rather lengthy mathematical manipulations including
the determination of the electron charge density ρ(r) by
using one-electron wavefunctions, this approach results
in the Thomas-Fermi equation
(9.9)
+
–
cis side
e2
∑ rr
∇2ϕ(r ) C[ϕ(r )]3 / 2
K+
(9.7)
where C is a constant and excellent results are known to
be obtained for heavy atoms. A less accurate but more
practical approach is usually taken to solve the multiscale problem illustrated in Figure 9.1. For example,
M.E. Gracheva et al. [3] treated the DNA transloca­
tion through the nanopore by using molecular dynamics
(MD) simulations, while the Poisson Eq. 9.7 was solved
classically but self-consistently by taking account of
charge variation in the electrolytic solution due to the
existence of the DNA in the nanopore region.
Finally, it would be interesting to compare macro­
scopic and microscopic capacitors. The electrostatic
energy stored in a macroscopic capacitance C is Q2/2C
(Q: stored charge), while it becomes e2/C for charging
single electron (e: electron charge) on a microscopic
capacitor such as a quantum dot. In the macroscopic
case, charge Q can be stored in capacitance C through
an integration of infinitesimally small amount of charge
dQ, which gives rise to the factor 1/2. On the other
hand, in the microscopic case, the charging process
must be discrete in the unit of “quantum of charge”,
that is, electron charge e. Exact quantum mechanical
Multiscale Modeling Methods
analysis for putting multiple electrons in a quantum dot
is very difficult due to the interactions between many
electrons and an appropriate approximation such as the
independent-electron model is usually employed for
practical calculations.
CHAPTER 9
of linear equations can be written in matrix form if we
number the two-dimensional grid points (j,k) in a single
one-dimensional sequence by defining
i j(K
k for j 0,1,…,K and k 0,1,… , M
1)
(9.14)
and introducing vectors Ui and Bi made from ϕj,k and
ρj,k, respectively. Now, Eq. 9.13 can be transformed into
9.2 Computational Methods
Macroscopic or classical equations described earlier are
partial differential equations (PDEs). Practically, PDEs
can be classified into the boundary- and initial-value prob­
lems and are numerically solved by using digital comput­
ers. Here, only the basic ideas for numerical calculations
of PDEs are described. More details can be seen in the
standard text books, for example, Numerical Recipes:
The Art of Scientific Computing (Press, 2007) [4].
First of all, an appropriate discretization of all continu­
ous variables r and t as well as the dependent variables
must be performed for the numerical treatment. As an
example of boundary-value problems, let us consider
the two-dimensional Poisson equation in the Cartesian
coordinate system
∂ 2ϕ( x, y )
∂ 2ϕ( x, y )
2
∂y 2
∂x
ρ( x, y )
ε
(9.10)
Assuming a rectangular region 0≤x≤Lx and 0≤y≤Ly,
the dependent variable ϕ(x,y) is represented by the val­
ues at the discrete set of points
x j jΔ,
j 0,1, 2,… ,K
(9.11)
U i M 1 + U i( M 1)
U i 1 + U i1 − 4U i = Bi
(9.15)
which gives rise to a matrix equation
AU B
(9.16)
where the matrix A is known and generally called “trig­
onal with fringes” and the vector B is also known includ­
ing the given boundary values. The unknown vector U is
formally written by A1B and can be numerically calcu­
lated by using various computer routines.
As an example of initial-value problems, let us con­
sider the one-dimensional wave equation with propaga­
tion velocity v along the x-axis:
∂ 2 u( x, t )
∂t 2
v2
∂ 2 u( x, t )
∂x 2
The independent variables 0≤x≤L and 0≤t can be
discretized as
x j jΔx,
j 0,1, 2,… ,K
t n nΔt, n 0,1, 2,…
and
y k kΔ, k 0,1, 2,… ,M
(9.12)
where is the grid spacing (K Lx and M Ly ).
Based on the finite-difference method for the secondorder derivatives of function ϕ(x,y), Eq. 9.10 can be
reduced into the system of linear equations:
ϕ j 1,k ϕu j,k
Δ2
ρ
j ,k
ϕ j1,k
ϕ j,k 1 ϕu j,k
ϕ j,k1
(9.17)
(9.18)
(9.19)
where Δx (KΔx L) and Δt are the space and time
steps, respectively. Based on the finite-difference
method for the second-order derivatives, a system of
linear equations similar to Eq. 9.13 is obtained:
u nj 1 2u nj
(Δt)2
u n1
j
v
2
u nj 1 2u nj
u nj1
(Δx)2
(9.20)
Δ2
ε
(9.13)
where ϕj,k ϕ(xj, yk) and ρj,k ρ(xj, yk).
In addition to the linear Eq. 9.13 for ϕj,k, the bound­
ary conditions must be taken into account. For exam­
ple, in the Dirichlet boundary condition, ϕj,k has been
specified at the boundary points defined by j 0, j K,
k 0, and k M. Thus, the unknown values of ϕj,k are
for j 1, 2, …, K–1 and k 1, 2, …, M–1. This system
where ujn u(xj,tn). A similar matrix equation like
Eq. 9.16 for boundary-value problems can be deduced
from Eq. 9.17 and B includes the given initial values
for initial-value problems. Especially, for numerically
solving the time-dependent Maxwell equations, the finite­
difference time-domain (FDTD) method is useful.
Various free software programs are available, for example,
at http://ab-initio.mit.edu/wiki/index.php/Meep [5].
In the FDTD method, the leapfrog scheme is usually
used to simulate time evolution. This scheme is widely
used for numerical calculations of many-particle systems.
153
Modeling in MEMS
PA R T I I
In order to show the basic idea of the leapfrog scheme,
let us consider the Newton equation describing the
movement of the planets [6].
d 2ri (t )
dt
2
G∑ m j
i≠ j
ri (t ) rj (t )
ri (t ) rj (t )
3
(9.21)
where ri(t) and mi are the position vector at t and mass
of the i-th planet, respectively, and G is the universal
gravitational constant. The movement of the i-th planet
can be numerically calculated in the leapfrog scheme as
follows:
ai (tn ) G∑ m j
i≠ j
vi (tn
ri (tn
ri (tn ) rj (tn )
ri (tn ) rj (tn )
Δt2) vi (tn Δt2)
Δt) ri (tn )
vi (tn
3
(9.22)
ai (tn )Δt
(9.23)
Δt2)Δt
(9.24)
As illustrated in Figure 9.2, the position vector
at tn 1(tn Δt) is calculated by that at tn and the
velocity vi at tn Δt/2 which is determined by that at
tn Δt/2 and the acceleration ai at tn.
Besides the finite-difference method described ear­
lier, the finite element method (FEM) is also very popu­
lar for solving PDEs. In the FEM, discretization is first
performed by the following process: (1) The continu­
ous space region of the problem is divided by a set of
elements such as triangles and curvilinear polygons.
(2) Appropriate basis functions such as piecewise lin­
ear and polynomial functions are chosen in these ele­
ments. Then the dependent variables are expanded by
these basis functions which results in a matrix equa­
tion for the expansion coefficients. More information
including a commercial package for FEM simulations is
available, for example, at http://www.femlab.com/ [7].
Figure 9.3 shows the ESP and electrostatic energy den­
sity calculated by the FEM for the DNA sensing device
illustrated in Figure 9.1. FEMLAB [7] was employed
for solving an electrostatic problem based on the macro­
scopic Maxwell equations described in Section 9.1.
The idea of the basis-function expansion is widely
used in microscopic or quantum mechanical calcula­
tions. One of the very popular software packages is
Gaussian [8] in which Gaussian-type functions are
tn – Δt/2
tn + Δt/2
x
x
tn–1
Fig 9.2 ● The leapfrog scheme.
154
tn
t
tn+1
employed to expand electronic wavefunctions for atoms
and molecules. The column vector C made by the
expansion coefficients can be determined by solving the
matrix equation in the Hartree–Fock–Roothaan method
HC ESC
(9.25)
where H is the Hamiltonian matrix, S is the overlap
matrix, and E is the energy eigenvalue. As an applica­
tion of the Gaussian03 program for the analysis of a
nanopore DNA microscope described in Figure 9.1, the
calculated molecular orbital energies of the adenosine,
a construction unit of DNA molecules and its dimer
dApA made by using a phosphate and terminating at
the sites of 5 and 3 are shown in Figure 9.4 [9]. This
dimer has odd-number electrons and thus spin-polarized
or open-shell calculations were carried out. There exist
two kinds of molecular orbitals: that is, α or up-spin
Fig 9.3 ● Calculated ESP ϕ and electrostatic energy density We.
It is assumed that the device (see Figure 9.1) is axial-symmetric
and the cell is filled with water ( 78.4). The top and bottom
electrodes are set at –1 and 1 V, respectively. In this model,
the Si part in the middle is considered to be also an electrode
and the voltage is set at 0 V. Both the contour map of ϕ (1 to
–1 V) and color map of (1.44 108–1.92 1017 Joule/m2)
indicate that the electric field is strongly concentrated in the
region near the nanopore. (This figure can be viewed in colour on
the book’s companion website (http://www.elsevierdirect.com/
companions/9780815515944)
Multiscale Modeling Methods
and β or down-spin orbitals. For these relatively large
molecules, the geometry optimization was at first per­
formed by using the Hartree–Fock method with the
3-21G* base set. Then, the MO energy levels were cal­
culated by using the 6-31G(d) Gaussian basis functions
and Becke’s three-parameter density-functional formu­
lation (B3LYP) for the optimized structure.
Quantum mechanical calculations described earlier
are practically impossible to apply for MEMS systems
where a huge number of atoms are involved. One of the
most popular methods to simulate atomic-scale behav­
iors of many-atom systems is MD simulations. In the
MD method, atomic or molecular motions are analyzed
CHAPTER 9
by solving the Newton equation. Let us consider, as
an example, the system composed of N Si atoms. The
classical motions of these atoms are described by the
position vectors r1(t), r2(t),…, rN(t) at t and these are
determined by solving the N Newton equations
m
d 2ri (t )
dt 2
Fi (r1(t), r2(t),… , rN (t))
(9.26)
here m is the mass of the Si atom, 4.66 1026 Kg and Fi
is the force working on the i-th atom. In the first-principle
MD method, Fi is calculated by solving the Schrödinger
equation for electrons in the Si atoms, but this approach
Fig 9.4 ● Molecular orbital energies of deoxyadenosine and
its dimer dApA. It is noted that the gap between the highest
occupied molecular orbital (HOMO) and lowest unoccupied
molecular orbital (LUMO) becomes much smaller upon
dimerization. Source: Taken from Ref. [9]. Also in colour on companion
website.
Fig 9.5 ● Snapshots of atomic
configurations during nucleation and
crystal growth under a symmetric
temperature gradient as shown in the
top panel: (a) t 0 ns, (b) t 15 ns,
(c) t 21 ns, and (d) t 24 ns. These
snapshots were obtained by projecting
the atomic coordinates in the central
10-Å thick region including the diagonal
(110) plane of the MD cell on the (110)
plane. Bottom panel shows a magnified
view of the enclosed region in the top
panel: (a) t 15 ns, (b) t 17 ns, (c)
t 19 ns, and (d) t 21 ns. Source:
Adapted from Ref. [13].
155
PA R T I I
Modeling in MEMS
is only possible for small systems with at most 1000 Si
atoms. For larger systems composed of more than 1000
atoms, Si empirical potentials V(r1(t), r2(t),…, rN(t))
such as the Tersoff [10] and Stillinger-Weber [11] poten­
tials can be employed and Fi is calculated as
Fi ∂V(r1(t), r2(t),…, rN (t))∂ri
(9.27)
Note that the existence of electrons is neglected
and the force is completely determined by the posi­
tions of atoms or more exactly nuclei in these empirical
potentials.
Since MEMS devices are working under a certain
temperature and pressure condition, it is better to carry
out MD simulations under the same temperature and
pressure conditions. The details of these techniques can
be seen, for example, in the standard text book [12]. An
example of MD simulations of crystallization processes
of supercooled liquid Si under a certain temperature
condition using the Tersoff potential is shown in the top
panel in Figure 9.5 [13]. Although the Tersoff potential
gives rise to high melting temperature near 2550 K, it
can well reproduce crystallization processes in solid and
liquid Si. Thus, it is considered to be useful to describe
nucleation and crystallization processes in Si. A rectan­
gular MD cell with size of 48.9 48.9 97.8 Å3 includ­
ing 8192 Si atoms was first melted completely at 3000 K
for 10 ns (Figure 9.5a). Nucleation first occurs at the
lower temperature region (Figure 9.5b) and then crys­
tallization proceeds toward the high-temperature region
(Figure 9.5c). The crystalline front-end hits the bottom
of the MD cell and then crystallization continues to the
top region (Figure 9.5d) due to the periodic bound­
ary condition. It is remarkable that the (111) surface
of the crystallite is predominantly parallel to the z-axis
or direction of the temperature gradient. This can be
attributed to (1) the trend that the solid/liquid Si inter­
face is stabilized by forming {111} facets and (2) tem­
perature dependence of the crystallization velocity.
References
1. C. Dekker, Solid-state nanopores,
Nat. Nanotechnol. 2 (2007)
209–215.
2. A.B. Migdal, translated by
Leggett, A.J., Qualitative Methods
in Quantum Theory, W.A. Benjamin,
Inc., 1977.
3. M.E. Gracheva, A. Xiong,
A. Aksimentiev, K. Schulten, G. Timp,
J.-P. Leburton, Simulation of the
electric response of DNA translocation
through a semiconductor nanopore–
capacitor, Nanotechnology 17 (3)
(2006)622–633.
4. W.H. Press, S.A. Teukolsty, W.T.
Vetterling, B.P. Flannery, Numerical
Recipes: The Art of Scientific
Computing, third ed., Cambridge
University Press, 2007.
156
5. MIT Electromagnetic Equation
Propagation, http://ab-initio.mit.edu/
wiki/index.php/Meep
6. Department of Computer Science,
Princeton University, http://www.
cs.princeton.edu/introcs/94diffeq/
7. COMSOL, http://www.femlab.com/
8. M.J. Frisch, G.W. Trucks, H.B.
Schlegel et al. Gaussian 03, Revision
D.01, Gaussian, Inc., Wallingford CT,
2004. http://www.gaussian.com/ .
9. T. Motooka, H. Ueda, K. Harada, M.
Fukuda, Electronic structures of DNA
molecules and their alignment control
on Si(100) substrates with onedimensional lattices, Sci. Technol. Adv.
Mater. 7 (2006) 705.
10. J. Tersoff, Empirical interatomic
potential for silicon with improved
elastic properties, Phys. Rev. B 38
(1988) 9902.
11. F. Stillinger, T. Weber, Computer
simulation of local order in condensed
phases of silicon, Phys. Rev. B 31
(1985) 5262.
12. D. Frenkel, B. Smith, Understanding
Molecular Simulation, Academic
Press, 2002.
13. T. Motooka, S. Munetoh, Moleculardynamics simulations of nucleation
and crystallization in supercooled
liquid silicon: temperature-gradient
effects, Phys. Rev. B 69 (2004)
073307.
10
Chapter Ten
Manufacture and Processing
of MEMS Structures
Miguel A. Gosálvez
Laboratory of Physics, Helsinki University of Technology, Espoo, Finland
10.1 Introduction
The manufacture and processing of MEMS structures
is generally referred to as micromachining. It consists
of the sequential realization of material deposition,
patterning and etching processes that incrementally
modify the substrate and/or a multilayer structure on it
in order to realize three-dimensional shapes with spe­
cific electromechanical functionalities, as discussed in
Chapters 22 through 29 of Part IV of this book.
Through the years, the set of micromachining proc­
esses has grown into a mature toolbox offering numer­
ous alternatives depending on the application and
material requirements. In surface micromachining, as
an example, the growth of different layers of silicon
nitride, oxide, and carbide; metals such as aluminum,
copper, titanium, and tungsten; or polymers such as
photoresist and polyimide, can be achieved by several
methods, including epitaxial growth, thermal oxida­
tion, sputtering, evaporation, chemical vapor deposition
(CVD), low-pressure CVD (LPCVD), plasma-enhanced
CVD (PECVD), spin-on deposition and/or sol-gel dep­
osition. Some of the films are deposited as structural
layers, becoming an integral part of the micromachined
structure with specific mechanical, electrical, optical,
or thermal properties. Others, however, are sacrificial,
eventually removed after serving their purpose tempo­
rally. Anodic bonding, silicon bonding, and silicon fusion
can be used to bring two different substrates together,
serving as extreme examples of material deposition
before or after other processing steps. Similarly, par­
tial or total removal of the grown films and/or material
from the substrate can be achieved by several methods,
including isotropic and anisotropic wet etching as well
as dry etching, typically in the form of plasma etching,
reactive ion etching (RIE), and deep reactive ion etching
(DRIE, also known as the Bosch process). For the reali­
zation of both growth and etching, selective masking is
routinely performed, restricting the material deposi­
tion and/or removal to carefully chosen regions of the
substrate and/or the multilayer structure. This is done
by using various patterning techniques, such as optical,
X-ray, and electron beam lithography.
Although the general concept of modeling the pre­
vious variety of deposition, patterning, and etching
processes has been discussed already almost 20 years
ago in the OYSTER, MEMCAD, and other projects
[1–4], the realistic simulation of the micromachining
of MEMS structures has become progressively pos­
sible only during the last 10 years [5, 6]. Currently,
major software companies such as Coventor Inc. [7]
and IntelliSense Software Corp. [8] offer products that
enable the micromachining of MEMS structures almost
completely virtually in a personal computer. By simply
providing a list of the required mask layouts and cor­
responding lithography processes together with the list
of the different material deposition and etching steps,
these programs will automatically generate the resulting
MEMS structure using a database of material properties
and process parameters. Furthermore, the programs can
perform a complete thermal, optical, and/or electro­
mechanical finite element analysis (FEA) of the result­
ing MEMS structure, enabling the characterization and
comparison of different versions of a device even before
stepping into a clean room. Other companies, such
as SoftMEMS [9], are trying to position themselves
in the MEMS design market, while some projects,
such as BICEPS3 [10, 11] or the nationwide Japanese
157
PA R T I I
Modeling in MEMS
MemsONE [12], are trying to provide competing—yet
affordable—toolboxes for the modeling of microfab­
rication and multiphysics analysis of the constructed
MEMS structures.
In this chapter we are concerned with the simulation
of micromachining, while the finite element analysis of
the MEMS structures is considered in other chapters.
We will present an overview of the currently available
simulators, centering mostly on the modeling of aniso­
tropic etching due to the special challenges posed by
this technique as well as its overall importance and gen­
eralizability, as described below. We will describe the
major features of the simulation methods first, proceed­
ing then to present the simulators themselves, including
commercial and free tools.
10.2 Requirements for Modeling
Micromachining
10.2.1 Database
The simulation of the different micromachining proc­
esses is possible only if a comprehensive database of
different material properties and process parameters
is available. As an example, the purely vertical deposi­
tion of a desired thickness of a material layer on a flat
substrate is a simple computational mask, requiring only
the addition of a corresponding number of rows to a
computational array. However, assigning realistic elec­
tromechanical properties to the layer—also computa­
tionally straightforward—can only be done if a database
can be used. Companies focused on the modeling of
MEMS, such as Coventor and IntelliSense [7, 8], need
to provide extensive micromachining databases to ena­
ble a realistic representation of each modeled layer and,
thus, their complex combination to produce MEMS
devices. The need for a comprehensive database is
shared by many research groups, and open organizations
such as the MEMS and Nanotechnology Clearinghouse
[13] provide an open material database which can be
completed and/or modified by the members.
10.2.2 Anisotropy
When the material is deposited on a non-flat multilayer
structure, the propagation of the micromachined sur­
face may significantly depart from vertical growth only.
Depending on the actual growth method, the amount of
(i) conformal deposition over the vertical and horizontal
features of the interface and (ii) shadowing effects by
the vertical features may become relevant. As an exam­
ple, metal deposition by evaporation is known to suf­
fer from poor step coverage, while sputtering typically
158
results in a more conformal film growth, although some
thinning is observed at the steps.
The realistic propagation of the micromachined sur­
face becomes especially complex for those micromachin­
ing processes whose evolution rate depends strongly on
the direction of propagation. As an example, wet etching
of silicon in alkaline solutions can be strongly anisotropic,
as discussed in Chapter 24 of this book. This means that
the etch front propagates vertically with a different rate
than horizontally and, in fact, the etch rate is different
for any pair of directions. As a result, fast etch planes
appear at the convex corners of the masking patterns
and slow etching planes appear at the concave features.
The propagation of the etch front in the presence of a
mask becomes highly nontrivial even for a completely
flat initial substrate, making anisotropic etching difficult
to grasp intuitively. Often regarded as one of the biggest
challenges in the modeling of micromachining—even
bordering on the black arts—the complexity has led to
the development in many companies of secretly kept
etch recipes after numerous trial and error tests.
Due to the challenges associated with the modeling
of etching and its widespread use—grossly accounting
for one third of the main micromachining technologies
of deposition, patterning, and etching—this chapter will
focus mainly on the description of the simulation meth­
ods for wet etching. In principle, the vertical, conformal,
and/or shadowed deposition of material layers can be
realized using similar methods.
10.2.3 Morphology
An additional ingredient for the modeling of microma­
chining is the description of the changes induced in the
surface morphology during deposition and etching. As an
example, the deep vertical walls realized by the Bosch
process are typically characterized by scalloping profiles.
Similarly, anisotropic etching can lead to rugged, stepped
morphologies due to the misalignment between the mask
and the silicon wafer. And other defects such as pyrami­
dal and trapezoidal hillocks; zigzag patterns; and round,
triangular, or hexagonal pits can appear on the etched
surfaces, affecting the electromechanical functional­
ity of the structure. Thus, being able to simulate these
features simultaneously to the overall propagation of the
etch front has become a requirement for the realistic
simulation of a MEMS structure. As described later, the
simulation and understanding of many of these features
has been enabled by the use of atomistic simulators.
10.2.4 Compatibility
Since MEMS devices are built to perform certain opti­
cal, thermal, and/or electromechanical functions, it
Manufacture and Processing of MEMS Structures
is desirable to enable the analysis of these properties
already at an early stage when only the computational
model of a MEMS structure exists. The analysis is typi­
cally done using finite element methods (FEM)—or
finite element analysis (FEA)—numerically solving the
corresponding coupled thermal, electromagnetic, and
electromechanical differential equations. Thus, the com­
putational model of the micromachined structure needs
to be as compatible as possible with the FEM model
to avoid possible feature loss during conversion. In this
respect, the use of atomistic unit-cell-based methods
during the modeling of micromachining provides certain
advantages as the cell-nodes can be directly used for the
volume and surface creation of the FEM meshes.
10.3 Micromachining As a Front
Propagation Problem
From the point of view of performing simulations, the
previous deposition, patterning, and etching processes
share a fundamental feature, namely, that each microma­
chining process results in the three-dimensional propaga­
tion of the material surface and/or interface. As a result,
the evolving surface may be thought as a complex
propagating front, with constituent parts that may split
and/or join during one or several stages of the microma­
chining sequence and typically featuring a multi-valued
height profile.
Traditionally, the propagation of such fronts is modeled
by placing markers (or nodes) along the boundary region
and advancing each node in the normal direction accord­
ing to the local value of the propagation rate, for example,
the deposition or etching rate, available from experi­
ments, interpolations, or physical models [14, 15]. The
major drawback of the marker method is that the nodes
need to be added, removed, and redistributed along the
boundary periodically in order to handle the splitting and
joining of the separate parts of the front, resulting in a
computationally time-consuming procedure—especially
for surface fronts in three dimensions—that is also char­
acteristically complex from a programming perspective.
An alternative to the use of markers is the Level Set
method [15]. A typical deposition/etch front in threedimensional space is considered as the zero isosurface of
a hypervolume in 4D. More generally, an n-dimensional
front is represented as the zero-level set of points of an
(n 1)-dimensional function, known as the Level Set
function, ϕ. Typically, the extra dimension of ϕ is cho­
sen to describe the signed distance from any point in the
n-dimensional space to the front [14]. The idea is to prop­
agate the Level Set function in time and to recover the
front by extracting the zero level set of points at every
time step. Thus,
the evolving front is defined as the set
�
�
of points {r } such that φ(r(t ), t ) = 0. Using the chain
CHAPTER 10
rule, this expression is rewritten in differential form as
the Level Set equation [14]: (∂φ /∂t) + R |∇φ|= 0,
where R is the propagation rate in the normal direction
of the front. This partial differential equation can be
numerically solved using finite difference methods [14,
16]. The most valued feature of the Level Set method
is the ability to describe natively the splitting and join­
ing of different parts of the front by avoiding an explicit
treatment of the boundary, which is the problem of
the marker methods. However, the Level Set method
features a strong dependence on the full knowledge
of the propagation rate R at any point and direction in
n-dimensional space, requiring the use of an extensive
database for the simulations or, alternatively, a suitable
physical model to determine the values—or at least
an interpolation scheme that makes use of a reduced
number of data points to calculate the rest. Although
the Level Set approach has been used for the simulation
of deposition, etching, and lithography processes [15]
and has been applied to the complex case of anisotropic
etching [16], much work is still needed to demonstrate
that it can rival the geometric and atomistic methods
presented in Sections 10.4 and 10.5.
Another alternative for the propagation of an inter­
face is the Phase Field method [17, 18], where the
markers and their dynamics are substituted by a par­
tial differential equation for an auxiliary field known as
the Phase Field, reminiscent of an order parameter that
takes different values in each phase (e.g., 1 and 1)
and changes smoothly across the interface, which is
modeled to have a finite (nonzero) width. Different
terms can be used in the equation in order to reproduce
the interfacial dynamics of the simulated system, typi­
cally including surface and/or bulk diffusion, concen­
tration and temperature gradients, viscous terms, etc.,
and occasionally involving additional equations for some
of the observables. The resulting Phase Field equations
are typically solved numerically using finite differ­
ence discretizations and integrated in time using either
explicit or implicit algorithms. As with the Level Set
method, the Phase Field models also provide a suitable
approach to describing the splitting and joining of the
different parts of the interface. Although the method
has been successfully applied to solidification and frac­
ture dynamics in metals and alloys, it has not been used
to address the propagation of the processed interface
in micromachining, remaining unclear whether its use
would be practical.
For the particularly complex case of anisotropic etch­
ing the etch front is characteristically facetted and the
use of a marker method will result in groups of nodes
being placed on the same facet plane, consequently
following the same displacement for each time incre­
ment. This makes it possible to focus on the propagation
of the facets themselves instead of the markers, justifying
159
PA R T I I
Modeling in MEMS
the introduction of the so-called geometrical method
[19–23]. Although described thoroughly in Section 10.4,
the essential idea is to abstract the facetted etch front
as a set of two fundamental polygons—the upper and
lower contours of the front—propagating the upper
contour segments horizontally along their normal direc­
tions while advancing the lower contour segments
according to a combination of the motion of the evolv­
ing floor and the side-wall facets. The difficult task in
this approach is to compute the change in the geometry
at each contour corner where two consecutive segments
meet, requiring the use of the Wulff-Jaccodine method
described in Section 10.4. Although the appearance and
disappearance of new/old side-wall facets can be suc­
cessfully monitored if the time increments are small
enough, the results are typically compromised in sys­
tems where the etching facets can intersect in compli­
cated ways, which is the same problem faced by any
marker-based method.
As an alternative to the geometrical, Level Set, and
Phase Field methods, one can use a fundamentally dif­
ferent approach based on an atomistic description of the
propagating front. Presented in Section 10.5, the idea
of the atomistic methods is to represent the surface by
a collection of atoms or cells, similar in spirit to the use
of markers but fundamentally different from these in
two ways: (i) The surface atoms in the front are part
of a larger structure, namely, the bulk of the material,
also made of atoms. This is contrary to the markers,
whose introduction defines an isolated region represent­
ing the front. As a result, the atomistic methods enable
a natural description of the splitting and joining of dif­
ferent parts of the propagating front, also allowing the
formation of multi-valued height profiles natively. (ii)
The surface atoms are not displaced in order to propa­
gate the front but, instead, the surface sites are (gradu­
ally) filled or emptied to represent the advancement
of the interface. This is again contrary to the markers,
which are themselves propagated in space according to
specific equations of motion. Correspondingly, the nec­
essary complete knowledge of the propagation rate and
direction required to displace the markers is replaced
by local growth and/or etch rates for the surface sites,
thus reducing the number of data points needed in
order to calibrate the atomistic simulations. In addition,
the atomistic methods can be seen as particular reali­
zations of the Phase Field and Level Set methods. As
an example, when the filling and emptying of the sur­
face sites is performed gradually, the atomistic method
represents effectively a phase field model whose field
value changes smoothly between the two extreme val­
ues across the interface (i.e., empty versus full). In this
way, the atomistic methods have positioned themselves
as the most suitable alternative for the accurate descrip­
tion of micromachining as a front propagation problem.
160
10.4 Anisotropic Etching:
Geometrical Simulators
Many tools have been developed for the simulation and
understanding of anisotropic etching. Traditionally, a
distinction is made between the geometric (or macro­
scopic) and atomistic (or microscopic) simulators. The
geometrical simulators have primordially focused on the
prediction of the propagation of the etch front in silicon
micromachining applications. In addition to the descrip­
tion of the three-dimensional etch front, the atomistic
simulators have also focused on the understanding of
the changes in the etched surface morphology.
The geometrical simulators [19–23] are based on the
assumption of an underlying velocity field that deter­
mines the amount and direction of motion for each
point on the surface. Since many points belong typically
to the same plane (or facet), they can be simultane­
ously treated by describing the etch front as a collec­
tion of facets. The idea is to discretize time into small
time steps and to propagate each facet along its normal,
according to the experimentally measured etch rate.
As it turns out, the reduction from points to facets can
be further simplified to two fundamental polygons, as
shown in Figure 10.1: (i) the upper contour, contain­
ing the upper edges of the side walls in contact with
the masking layer (i.e., the contour of underetching),
and (ii) the lower contour, corresponding to the lower
edges of the side walls in contact with the etched floor.
Additionally, one or several cross-section contours may
be considered. The upper and lower contours—also
referred to as polygons—are completely horizontal
while the cross-section polygons are completely vertical.
For the upper contour, each side of the polygon
is identified with a crystallographic plane {hkl}, cor­
responding to a side wall making an angle α{hkl} with
the horizontal plane. Each polygon side is advanced
horizontally along its normal direction by an amount
Δt ⋅ R{hkl} cosα{hkl}, where Δt is the time increment
and R{hkl} cosα{hkl} is the projection of the etch rate of
{hkl} on the horizontal plane. The change in geometry at
each polygon corner is more complicated than a simple
intersection of the propagated sides. It is determined
using the Wulff–Jaccodine method, which minimizes the
surface energy by minimizing the contour perimeter. At
each corner, one considers the set of tentative displace­
ment vectors corresponding to the etch rates (multiplied
by Δt) for all horizontal directions between the polygon
sides that share the corner, as shown in Figure 10.1c.
Each displacement vector is associated with an infinite
straight line perpendicular to the displacement vector
and passing through the end point of the displacement
vector. The new polygon is determined as the set of
straight lines and their intersections, which minimizes
Manufacture and Processing of MEMS Structures
(b)
(a)
CHAPTER 10
Upper contour
Mask outline
Lower contour
C’
C
C’’
[–
10
0]
B’
A
B
00
[1–10]
]
(c)
[001]
[0
10
]
[110]
]
10
[0
A
[001]
[1
B’’
(d)
B
B’’
B’
[–100]
(e)
C
C’
C’’
[110]
B
[1–10]
C
[00–1]
(f)
[00–1]
[010]
(g)
Fig 10.1 ● (a, b) Upper and lower contours used in the geometrical method, showing two cross-sections (B’B’’ and C’C’’). (c) WulffJaccodine method applied to point A (horizontal propagation of upper contour). (d, e) Side view of cross-sections B’B’’ and C’C’’. (f, g)
Wulff-Jaccodine method applied to points B and C (propagation in vertical plane). Source: After [19, 23].
the perimeter of the polygon. In this way, some planes
may appear while others disappear. In order to monitor
the changes in the facets and maintain the accuracy of
the simulation, small time steps and depth increments
are used (typically, Δt 30 s and Δh = 1μm ).
A similar propagation method is applied to the lower
polygon, with the exception that the advancement
of each polygon side is generally a combination of the
etch rates of the floor and the lower facet of the corre­
sponding side wall. Once the upper and lower polygons
have been propagated, the side wall facets are calcu­
lated from the available top and bottom polygon sides.
If the time increments are small enough, this allows for
monitoring of the appearance or disappearance of side
wall facets. The same method can be applied for verti­
cal cross-sections, taking into account that some of the
polygon sides are effectively pinned if they are parallel
to and in contact with a mask. Examples are shown in
Figures 10.1d–g.
In order to obtain the possible displacement vec­
tors correctly, it is important to select the proper set
of crystallographic directions and corresponding etch
rates (multiplied by Δt) in the proper crystallographic
zone. As an example, Figure 10.1f displays the relevant
Δt-scaled etch rates for the ⟨010⟩ crystallographic
zone, while Figure 10.1g shows the relevant rates for
the ⟨110⟩ zone. Note that the propagation of the crosssection polygons is not used as an aid for improving
or modifying the propagation of the overall etch front
given by the upper and lower contours, but as an addi­
tional analysis tool.
The geometric simulators can successfully describe
the propagation of the etch front in complicated
geometries. Examples of commercially available simu­
lators are SIMODE from Amtec GmbH, Germany
[24], originally developed by Frühauf and co-workers
at the University of Chemnitz, Germany [19]; and
FabMeister-ES from Mizuho Information & Research
161
PA R T I I
Modeling in MEMS
Institute, Inc., Japan [25], formerly known as
MICROCAD, originally developed by Koide and co­
workers at Hitachi Ltd. [22], Asaumi, and co-workers
at Fuji Corp. [23], and Sato and co-workers at Nagoya
University [26, 27], Japan. These programs can typically
produce simulation results within seconds or minutes,
depending on the mask layout, number of time steps,
and computer architecture. However, their perform­
ance is compromised in complex undercut geometries
such as those for closely spaced mask windows, where
the etch fronts may intersect in a complicated manner.
In addition, etching of both top and bottom sides of the
wafer poses a difficult challenge as the advancement of
the upper and lower polygons becomes nontrivial.
The major drawback of the geometric simulators is
the need for a full orientation-dependent etch rate data­
base [26–28]. This is required in order to extract the
relevant rates for applying the Wulff–Jaccodine method,
depending on the crystallographic zone and the involved
polygon sides, as depicted in Figure 10.1. The larger
the number of measured etch rates for different sur­
face orientations, the more displacement vectors can be
used, improving the accuracy of the simulations. Even
if the propagation of the etch front is, wisely, reduced
to the propagation of the upper and lower contours,
the geometrical method can be described as some kind
of “brute force” approach due to the use of hundreds
or even thousands of etching rates. In the atomistic
methods, however, the emphasis is placed on reducing
the amount of required experimental information to a
handful of etch rates.
10.5 Anisotropic Etching:
Atomistic Simulators
There are two types of atomistic simulator, depend­
ing on the actual method used for advancing time. The
Cellular Automata (CA) methods provide a determin­
istic, mean-field propagation of the interface. They
are characterized by a Constant Time Step (CTS) dis­
cretization of time and a Decide and Perform (D&P)
updating scheme consisting of two system-complete
evaluation loops inside each time step. In the first pass,
the algorithm decides which processes need to be real­
ized and, in the second, the selected processes are
performed—effectively realizing them simultaneously
(or in parallel). This is shown in Figure 10.2a. On the
other hand, the Kinetic Monte Carlo (KMC) methods
provide a completely sequential, always stochastic prop­
agation of the interface. They are based on the use of a
single evaluation loop that performs each event as soon
as it is decided (Figure 10.2b).
In both KMC and CA implementations the atoms of
the surface are visited one by one and their neighborhoods
162
are inspected in order to determine the removal rate,
deciding whether the atom is removed or remains
attached. The essential difference between the methods
is that KMC removes each atom as soon as its removal
has been decided, while CA first determines all the
atoms that need to be removed and then removes them
simultaneously. Thus, in KMC there is always a small
time interval (Δt/N) between two consecutive proc­
esses, while in CA many processes can take place simul­
taneously and the time interval is between different
groups of processes. In a way, KMC is more atomistic
than CA. As a result, KMC is more suitable for under­
standing the development of morphologic features, such
as hillocks, pits, or meandering steps, while CA is more
suitable for mean-field descriptions, such as the propa­
gation of the etch front in the wet micromachining of
a MEMS structure, where the atomistic nature is less
important than the overall average behavior.
10.5.1 Cellular Automata
A cellular automaton is a discrete model of the physi­
cal system consisting of an n-dimensional lattice whose
nodes, cells, sites, or atoms can be present in one of
many states, where “many” can also be infinite. Based
on the current state and number of neighboring sites,
the state of each site changes after every time step by
applying the same set of rules to all sites simultaneously.
A simple example is given in Figure 10.2a.
For the simulation of etching one distinguishes
between the Discrete Cellular Automata (DCA) and
the Continuous Cellular Automata (CCA). They dif­
fer in the number of states available for each atom site.
In DCA the sites have only two states, either occupied
(1) or empty (0). For CCA the sites can be partially
occupied, leading to infinite occupation values in the
continuous range [0,1]. Correspondingly, the atomistic
removal rates are either 1 or 0 for the DCA method,
but they can take any value in the range [0,1] for
CCA. The continuous range of values for the occupa­
tion of the sites and the removal rates makes possible
an improved representation of smooth variations along
the direction perpendicular to the surface, enabling the
description of continuous motion of the interface in the
CCA method. In this respect, the CCA method is very
similar to a Phase Field model of the interface, with the
continuous occupation of the sites assuming the role of
the phase field.
There is a third type of CA, which can be referred
to as a Stochastic Cellular Automaton (SCA). As for
DCA, the sites are either occupied or empty, with no
other intermediate state. However, the simultaneous
removal of identical surface atoms is decided stochas­
tically according to removal rates that can take any
Manufacture and Processing of MEMS Structures
(a)
CHAPTER 10
CA
t + Δt
t
Probe N processes
Visiting the cells
randomly or sequentially
is equivalent
Side view
:
e) d
id n
a
ec s es
(d e n
p ess d o
d
oo c te ted pte
t l ro p
rs p ce cep cce
Fi N c
a
Ac ot
st l a
te be
N
la
re Se
al co
ize n
d
ac lo
ce op
pt (p
ed e
R
Ac em
pr rfo
o c rm
N ce ov
ot p e
es ):
ac te d
se
ce d
s
pt
ed
Top view
(b)
KMC
t
Probe N processes
t + Δt
Must visit the cells
randomly
Accepted and removed
Not accepted
Fig 10.2 ● (a) Decide and Perform loops inside each time step of a CA simulation. (b) Single loop for each time step of a KMC simulation
(simple Metropolis version). At time t a stepped surface with a pit is depicted. The processes considered are cell removals. A simple rule
is applied consisting of the removal of step cells only.
value in the range [0,1], as for CCA. In a way, SCA is
a hybrid between DCA and CCA, having also features
that resemble the KMC method. For this reason, the
SCA method will be presented after the KMC methods
at the end of Section 10.5.2.
Discrete Cellular Automaton (DCA, or
BCA Basic Cellular Automaton)
The orientation dependence of the etch rate of silicon
can be described by a Discrete Cellular Automaton
(DCA) that uses a simple choice of atomistic rates, as
introduced by Than and Büttgenbach [29]: The removal
rate of any surface atom is 1, except for the atoms with
three bulk neighbors—characteristic of the stable {111}
surface—for which the removal rate is 0. This describes
anisotropic etching as a sequence of collective removals
where all the current surface atoms are removed simulta­
neously in each time step—except for the {111} atoms.
The method is graphically described in Chapter 24,
Section 24.2.4.1 of this book. DCA is also referred to
as the Basic CA method or BCA.
Due to the geometrical differences between the dif­
ferent crystallographic planes at the atomistic scale, the
previous rule (i.e., removing every atom except the 111
terrace atoms) results in a different etch rate for each
surface. Taking the unit of time as 1 and a as the lattice
parameter of the conventional unit cell of silicon, one
gets (Section 24.2.4.1): R111 0 , R110 a/(2 2 ),
R100 a/4 , R311 a/ 11 , R211 a/(2 6), and
similarly for other orientations. The general trend in the
dependence of these etch rates with orientation happens
to be in good qualitative agreement with some experi­
ments, such as etching in potassium hydroxide (KOH)
at medium concentration, as shown in Figure 10.3a.
The BCA method captures the global and local minima
and maxima at {111}, {110}, {100}, and {311}, respec­
tively. However, it cannot describe other etchants, such
as the case where R110 R100 , since BCA is limited to
the fixed value of R110 /R100 2 . In fact, the rates of
163
Modeling in MEMS
PA R T I I
any one pair of orientations are fixed by the underlying
geometry and the given rule, and their relative values can­
not be tuned to match an experiment. It is only possible
to shift up or down the whole set of etch rates for cali­
bration purposes, typically matching the rate of {100}.
In anisotropic etching it is well known that the crystal
facets appearing on the etched structures correspond to
the slowest etching planes for concave geometries, such
as cavities or trenches enforced by using masks, and the
observed facets correspond to the fastest etched orien­
tations for convex shapes, such as the convex corners of
square – island masking patterns or the overall surface of
a spherical specimen. Due to this feature and the fact that
the DCA method reproduces approximately the orienta­
tion dependence of the minima and maxima in the etch
rate, the use of this method can provide a rather realistic
picture of the propagated etch front, as shown in Figure
10.3b, c. The micro-needles in Figure 10.3b serve as an
example of the etching of convex geometries, while the
suspended micro-channels depict the behavior for con­
cave geometries. The good match to the experiment is
limited to etchants that roughly behave as 30–40 wt%
KOH and Si{100} wafers. Even in this case examples of
disagreement can be found, as shown in Figure 10.3d–f,
where etching of the fast planes at the convex corners has
advanced more in the experiment than in the BCA simula­
tion. This is directly due to the rate of {311} being much
lower for BCA than in the experiment (see Figure 10.3a).
Continuous Cellular Automaton (CCA)
The Continuous Cellular Automaton (CCA) was intro­
duced by Zhu and Liu [34]. In this method the atoms
are associated with removal rates of any value—not
restricted to 1 or 0—and the surface sites can be par­
tially occupied. The propagation of the surface consists
of gradually decreasing the occupation of each surface
site by an amount equal to the current removal rate of
the occupying atom, whose value dynamically changes
with the neighborhood. The evolution can be pictured
as nonuniform, site-dependent erosion. The use of the
D&P double loop ensures simultaneous removal of iden­
tical sites. For stepped surfaces, this provides an aver­
age surface propagation mode consisting of the gradual
removal of entire atom rows located at the steps,
accompanied by a slower continuous “erosion” of the
terrace regions. In most cases, the removed rows alter­
nate according to a predictable sequence.
(b)
160
BCA
Micro-needles
(100)
140
120
100
Exp
(311)
BCA
Exp
40
(110)
Suspended micro-channels
(c)
20
0
(d)
(111)
80
60
0
20 40 60 80 100 120 140 160 180
Angle, degrees
Exp
(e)
CPU time:371 s
BCA
(g)
Depth: 225.82 um
Time: 205.64 min
225 um
200 min
BCA
225.82 um
189.49 min
CPU time: 4404 s
Exp
1146 um, 375 cells
Etch rate, microns per hour
(a) 180
Another feature that makes the DCA method suitable
for prototyping is the relative speed of the simulations.
Compared to the CCA method (see Section 10.5.1), a
DCA simulation is typically 4–20 times faster, the rea­
son being the high total removal rate for DCA as most
atomistic rates get the value 1. In spite of this, owing
to the D&P double loop, a DCA simulation is typically
slower than a KMC simulation (see Section 10.5.2).
(f)
1563 um, 512 cells
CCA
Fig 10.3 ● (a) Etch rate dependence on orientation for the DCA method ( BCA) and comparison to a typical experiment (37 wt%
KOH at 90 °C [30]). (b, c) DCA simulations compared to experiments for the manufacture of micro-needles [31] and suspended microchannels [32]. (d–g) Comparison of etching results for DCA method, experimental result (30wt% KOH at 80 °C [33]), mask layout with
system dimensions [33], and CCA method. Source: (b) and (c) reproduced with permission by IOP (Fig. 4(e) in Ref. [31]) and Elsevier
(Fig. 10(b) in Ref. [32]), respectively. (e) reproduced with permission by Amtec GmbH, Germany (bottom figure on p. 41 of Ref. [33]).
164
Manufacture and Processing of MEMS Structures
As an example, Figures 10.4a–h show the changes
observed in the occupation of different surface sites
during a sequence of events consisting of the removal
of atoms A and B in alternation. The occupation is
described by the size and color of the occupying
atoms, with the larger, darker spheres corresponding
to a larger occupation and the smaller, lighter spheres
being closer to the empty state. The bulk sites, with
ETA
T
AR-T
(a)
A
(d)
(b)
B
(e)
A
(h)
BR-T
occupation 1, are represented by white spheres. The
figure shows seven generic atoms: the terrace atoms
(T), two step atoms (A and B), the corresponding ter­
race atoms at the upper edge of the steps (Edge Terrace
at A, ETA; and Edge Terrace at B, ETB), and the cor­
responding terrace atoms restricted by the presence of
the step (A-Restricted Terrace, AR-T; and B-restricted
Terrace, BR-T).
T
180
Co-terrace
A
(f)
BR-T
T
ETB
d
B
(a)-(b): A is removed, B emerges
(b)-(f): Occupation of B decreases
(f)-(g): B is removed, ETB becomes A
(g)-(h): Occupation of A decreases
KOH 50 w/v 90 C
(511)
(311)
(211)
3473 um, 512 cells
Etch rate, microns per hour
(i) 200
B
α B
(c)
B
d
ETA
T
ETB
Terrace
β
AR-T
(g)
CHAPTER 10
(k)
160
(100)
140
120
(111)
100
80
166 um
150 min
(l)
BCA
(911)
60
3473 um, 512 cells
CCA
40
(110)
Exp
20
Fit
0
0
20
(111)
(j)
40
60 80 100 120 140 160 180
(111)
Angle, degrees
Activation energies (eV) for calibrated atomistic rates
100
Atomistic removal rate, A /ms
L, 0.00
H, 0.57
V, 0.60
KR(1)-EMK, 0.47
M, 0.57
ETM, 0.66
ETH, 0.62
K, 0.59
D, 0.57
EMK, 79
EDA, 0.58
10–1
10–2
10–3
CPU time: 206 s
Exp
(n)
165 um
(m)
CCA
165 um
A, 0.83
10–4
T, 0.57
10–5
2.7 2.8
CPU time: 2122 s
2.9
3
3.1
3.2
1/ T, K–1
3.3
3.4 3.5
×10–3
Fig 10.4 ● (a–h) Typical time evolution for the CCA method. Average height decreases and time increases from (a) to (b), (c) to (d), and
(e) to (f). (i) Example of etch rate dependence on orientation for the CCA method and comparison to the experiment. CCA has been
calibrated using the surface orientations marked as “Fit.” (j–m) Comparison of etching results for BCA, experimental result (30 wt% KOH
at 80 °C [33]), mask layout with system dimensions [33], and CCA. (n) Atomistic removal rates calibrated at three different temperatures:
determination of atomistic activation energies. Source: (k) and (n) reproduced with permission by Amtec GmbH, Germany (figures on
p. 93 and 99 of Ref. [33]).
165
PA R T I I
Modeling in MEMS
In the same way as the etch rates of the different
surfaces can be written down exactly for DCA, this
can also be done for CCA. In this case, however, the
expressions are more complicated, incorporating not
only the geometry (through the numerical coefficients
and parameter a) but also the relative kinetics; that is,
the actual atomisitc removal rates are different from 1
and 0 in general [35].
Considering the generic orientation shown
in Figure 10.4a–h, the etch rate is written as
R Δh/Δt (Δh A ΔhB )/(Δt A ΔtB ), where Δhj
(j A, B) is the change in the average height of the
surface when the atoms of type j are removed, which
depends on the miscut angle, and Δt j is the corresponding
time increment. For this figure, Δh A d cosα/N and
ΔhB d cos β/N, where d 3a/4 is the Si-Si dis­
tance, N 7 is the number of periodically repeated
surface atoms, α is the angle between the normal to
the surface and the normal to the “co-terrace” (see
Figure 10.4h), and β is the angle between the normal to
the surface and the normal to the “terrace” (see Figure
10.4e). Thus, one gets Δh Δh A
ΔhB a/ 123 .
Since at each time step the occupation of each surface
site is decreased by an amount equal to the current
removal rate of the occupying atom multiplied by the
current time step, the time increments satisfy the fol­
lowing two equations:
⎡ rART
⎢
⎢
⎣
2rT rETA + rA
0
rBRT
2rT
rB
⎡1⎤
rETB ⎤ ⎡ΔtA ⎤
⎥⎢
⎥⎢⎥
⎥ ⎢ ΔtB ⎥
⎢1⎥
⎣⎦
⎦⎣
⎦
(10.1)
where (rART 2rT rETA rA )Δt A (rBRT 2rT
rETB )ΔtB 1, or the equivalent, rART Δt A rBRT ΔtB
2rT Δt A 2rT ΔtB rETA Δt A rETBΔtB rA Δt A 1, is
the total reduction in the occupation of site A until
atom A is removed. Note that the reduction in the
occupation sums up necessarily to 1 (right-hand side).
In other words, {rART ,rBRT ,(rT ,) 4,rETA ,rETB ,rA }
is the full site-type history of atom A, exposed to the
etchant during alternating time intervals of duration
Δt A and ΔtB . In a similar manner, the second row of
the matrix equation describes the total site-type his­
tory for atom B. In this case it is very simple, since B is
removed right after it emerges to the surface. Solving
the matrix Eq. 10.1 for Δt A and ΔtB , and using the
previous value for Δh, one gets:
R
a
59 rB
rB (rART 2rT rETA rA )
rART
rETA rA rBRT rETB
(10.2)
Similarly, one obtains the equations for other surface
orientations. As a result, a system of nonlinear equations
166
is obtained, which links the experimental etch rates for
the planes to the removal rates for the atoms:
R100 R110 a
rD
4
a
rM
2 2
a rT rL( T )
R111 3 rT rL( T )
rH (2rT rV )
a
R211 rV rETH
2 6 rH rT
rH (rT rV )
a
R311 11 rH rT rV rA
a (rD rEDAA )(rETH rV ) rA rH (10.3)
R511 3 3 rD rEDA rETH rV rA rH
2
a (rT rETM )(rM rL(ETM) ) rM
R331 rT rETM rL(ETM) rM
19
a
R210 (rM rEMK rK )
4 5
a
R310 (rKR(1)EMK rK )
2 10
Equation 10.3 uses 14 site-specific rates correspond­
ing to the most essential terrace, step, kink, and adatom
sites [35], including edge-terrace sites, which are located
at the upper edge of the steps. There are 7 basic sites
(T, M, D, H, V, K, and A, appearing as {111}-Terraces,
{110}-Monohydrides, {100}-Dihydrides, {h 2 h h}­
Horizontal dihydrides, {h 2 h h}-Vertical dihydrides,
{h 2 h 0}-Kinks, and {h 1 1}-Alternative-dihydrides,
respectively, with h being an integer), 4 edge sites (Edge
Terraces at M and H steps, or ETM and ETH, Edge
Monohydrides at K steps, or EMK, and Edge Dihydrides
at A steps, or EDA), 2 adatom sites or Lollies (L(T)
and L(ETM), obtained when removing the 111-Terrace
and {h 2 h 2 h}-ETM atoms, respectively) and 1
restricted site, KR(1)-EMK-, appearing on {h 2 h 0}.
The actual form of the equations depends on the rela­
tive values of the removal rates for the step and edgeterrace sites. See Ref. [35] for further details.
Calibration of CCA
It is possible to solve the system of equations (Eq. 10.3)
for the site-specific rates in terms of the experimental
face-specific etch rates. A calibration procedure is con­
sidered, consisting of finding proper values for the 14
atomistic rates (the unknowns) given the values of the 9
face-specific rates (the equations) [35, 36]. This is done
by minimizing the global error between the experimen­
tal and calculated etch rates, numerically solving the sys­
tem. The 9 equations correspond to 7 surfaces from the
[110] crystallographic zone, e.g., {111}, {211}, {311},
Manufacture and Processing of MEMS Structures
{911}, {100}, {551} and {110}, and {2} orientations
from the [100] zone, e.g., {210} and {310}. Depending
on the particular etch rate anisotropy, {551} may be
replaced by {331}, {311} by {411}, or {911} by {511},
as some examples. Although there exist additional equa­
tions for other surface orientations, the number of facespecific rates containing nonredundant independent
information is limited, and incorporating more equations
would make the system mathematically over-deter­
mined. The limited number of equations is not a major
drawback for the successful realization of the calibration.
As a matter of fact, it is of benefit as it reduces to less
than ten the number of experimental etch rates needed
for calibration. This is a dramatic decrease as compared
to the geometrical methods, which require hundreds and
even thousands of etch rates to perform the simulations.
Furthermore, the same calibration procedure can be
performed consistently at different temperatures for
the same etchant at a fixed concentration, thus allowing
the extraction of atomistic activation energies [37]. The
atomistic removal rates of the fourteen surface sites
are calibrated at three different temperatures, and the
obtained rate values are plotted on an Arrhenius diagram
(rate vs. inverse temperature), as shown in Figure 10.4j.
The atomistic activation energy for each surface site is
obtained by extracting the slope of a linear fit. The fact
that a linear fit can be used underlines the consistency
of the calibration method throughout the different tem­
peratures. The extraction of atomistic activation ener­
gies enables performing simulations at any temperature
for the chosen etchant concentration.
DCA vs. CCA
Figure 10.4i shows a typical comparison between the
experimental etch rates for the surface orientations in the
[110] crystallographic zone and the etch rates obtained
with the CCA method after calibration. The experi­
mental etch rates used for calibration are shown as “Fit,”
except for {210} and {310} of the [100] zone, which are
not shown. In comparison to BCA in Figure 10.3a, CCA
reproduces not only qualitatively but also quantitatively
the anisotropic features of the etch rate, including the
locations and values of the global and local minima and
maxima, as well as the discontinuity in the etch rate at
{551}. The comparison of the etched shapes in Figure
10.3d–g shows that CCA describes better than BCA
the fast etching planes at the convex corners. While the
advancement of these orientations is too slow for BCA, for
CCA the planes lag behind the experiment only a small
amount. Similarly, Figure 10.4k–n shows a comparison of
the etched shapes for a different system, demonstrating
the improved accuracy obtained when using CCA.
As compared to DCA, a well calibrated CCA simula­
tor is able to reproduce quantitatively the local and global
CHAPTER 10
maxima and minima of the etch rate dependence on the
orientation and is not limited to 30–40 wt% KOH and
Si100 wafers. This is shown in Figs 24.4e–h of this book,
demonstrating that different etchants can be described
well by the CCA method. Generally speaking, CCA is
a more accurate method than DCA for the simulation of
three-dimensional etch profiles of interest in engineering
applications. As shown in Figures 10.3d–g and 10.4k–n,
the improved accuracy for CCA comes at the expense
of longer simulation times (see the quoted CPU times,
i.e., the time required for a simulation to be finished in a
computer). Typically CCA is slower than DCA by a fac­
tor between 4 and 20 times, depending on the system.
This is due to the fact that most rates have value 1 for
DCA while many rates take rather low values in CCA.
Constant and Variable Time Stepping
In its simplest form a CCA simulation proceeds by
using a CTS implementation. This simply consists
of choosing the size of the time step (typically 1) and
performing the double D&P loop inside each step
(Section 10.5). In the first loop, the occupation of every
site is reduced according to the current value of the
removal rate of the occupying atom multiplied by the
time step. The atoms at the sites reaching zero (or nega­
tive) occupation are marked for removal. In the second
loop, the marked atoms are removed and the state and
rate of their neighbors are updated. After this, a new
time increment can be performed.
It is possible to use an alternative Variable Time
Stepping (VTS) procedure, characterized by advancing
time just the exact amount required to remove the next
atom or group of atoms. To do this one proceeds as fol­
lows: during the first loop the minimum time to remove
one surface atom (or a group of atoms having the same
time increment) is determined and, in the second loop,
only those atoms with this time increment are removed.
Note that for the DCA method there is no actual dif­
ference between the VTS and CTS implementations.
Correspondingly, it only makes sense to use CTS when
considering the DCA method.
Time Compensation
The CCA simulations can be performed using either
the CTS or VTS implementations. VTS is suitable for
deriving and verifying the analytical equations for the
etch rates of the different surface orientations, while
CTS is suitable for simulating and developing MEMS
engineering applications. Although VTS represents an
exact propagation method, CTS is only approximate
in nature due to the following: (i) The occupation of
one or several sites can become negative just before the
removal of the corresponding atom, and (ii) the method
enables the simultaneous removal of different groups
167
PA R T I I
Modeling in MEMS
of atoms that should occur sequentially (according
to the exact evolution provided by VTS). This occurs
since the time step can be larger than the two small­
est time increments to remove the next two scheduled
groups of atoms. As a result, both groups are removed
simultaneously, which can be conflictive as the removal
of the first group can sometimes lead to the formation
of very active surface atoms which should be removed
next instead of the second group. A standard time com­
pensation (TC) procedure [34] and an alternative back­
ward TC method [38] can be used to resolve the first
problem. However, neither of the two methods can
eliminate the second problem, its being possible only to
minimize it by using small time increments.
Stochastic Cellular Automaton
The third type of CA method, the SCA, is discussed
after the KMC methods at the end of Section 10.5.2.
10.5.2 Kinetic Monte Carlo
Monte Carlo (MC) methods refer to any computational
calculation that makes use of random numbers. Kinetic
MC (KMC) refers to the description of the time evo­
lution of a system by considering the kinetics of the
different processes, i.e., their rates. New states are
sequentially generated by realizing one process per time
step, paying special attention to the correct determina­
tion of the time increment between consecutive proc­
esses. This is in contrast with the Thermodynamic MC
(TMC) method where the measure of time is irrelevant,
as the principal objective is the determination of equilib­
rium properties consisting typically of ensemble averages
of the internal energy and other thermodynamic quanti­
ties. KMC enables the analysis of the evolution of both
equilibrium and nonequilibrium systems and, in particu­
lar, the transient behavior from any given initial state to a
completely different state, a problem that is of particular
interest in the micromachining of MEMS structures.
Metropolis KMC
In its simplest form a KMC simulation proceeds as
follows: In each time increment a random number is
chosen ( 0 q 1) in order to pick up an atom i, as
shown in Figure 10.5a. A removal decision is made by
comparing the neighborhood-dependent removal rate
ri ,
ri and a second random number 0 e 1 . If e
the atom is removed. The change in the atom types for
the surface neighbors and the emergence to the surface
of the bulk neighbors leads to a new state of the system.
If e is larger, the previous state remains. Irrespective
of the atom removal or stay, time is incremented as
the inverse of the total number of surface atoms,
168
Δt 1/M. After this, a new time increment can be per­
formed. This simple procedure is known as Metropolis
KMC [38]. It is also regarded as the CTS KMC method
because the number of processes M is a constant in
many applications, leading to constant time steps.
Fast KMC Simulations
Although the outlined method can be easily imple­
mented, there are typically alternative procedures that
can speed up the simulations. If most atomistic removal
rates are low, many processes need to be tried before a
success is observed when comparing ri and e. To speed
up such simulations one may sample the processes
according to the removal rates instead of picking up the
processes randomly. While performing random pick-ups
ensures that the most abundant processes are chosen
more often, sampling the rates ensures that the most
probable processes—with higher rates—are chosen
more frequently. In practice, for each time step, sam­
pling the rates corresponds to choosing the first proc­
i1
M
∑ ij1 rj , where e
ess i for which ∑ j1 rj e ∑ j1 rj
is a random number (see Figure 10.5b). This is similar
to performing a random pick-up, where one chooses the
i1
M
i
first atom i that satisfies ∑ j1 1 q ∑ j1 1 ∑ j1 1 , or
i (see Figure 10.5a).
equivalently, i 1 qM
For a given random number e, the determination of
the next process i requires visiting the set of all removal
rates until the cumulative sum ∑ ij1 rj satisfies the
previous condition. By considering all the rates as the
components of a one-dimensional array, as described
in Figures 10.5c–e, finding the next event consists of
searching for the index whose cumulative sum equals or
M
surpasses the length e ∑ j1 rj (see Figure 10.5f). Since
on average the time cost of finding the event increases
linearly with the number of surface atoms M, the
method is known as a Linear Search. In the same man­
ner as the time increment between random pick-ups is
the inverse of the total number of current surface atoms
( Δt 1/M 1/ ∑ M
j1 1), when sampling the removal
rates the time increment is the inverse of the current
total removal rate ( i.e., the sum of all the current ato­
mistic rates, Δt 1/R 1/ ∑ M
j1 rj ).
Several alternative methods can be used to perform
fast KMC simulations based on efficiently sampling the
removal rates [38, 39]. Typically, this is done by group­
ing the rates. Each group (or bin) contains several rates
and is assigned a rate that is the sum of the contained
rates. The bins themselves are subsequently grouped
into larger bins, assigning them the corresponding sum of
the rates inside each. Grouping is continued for increas­
ingly larger bins until a single bin eventually contains the
sum of all the rates in the system. The procedure leads
to a tree structure where the root corresponds to the
largest bin and each branch represents a bin containing
Manufacture and Processing of MEMS Structures
(a)
Random pick-up
i-1
M
i
1≤ Σ 1
Σ 1 < q· Σ
Choose first i that satisfies: j=1
j=1
j=1
Reactive steps, unreactive terraces
(g)
(b)
CHAPTER 10
Linear search
i-1
M
i
j=1
j=1
j=1
Choose first i that satisfies: Σ rj < e· Σ rj ≤ Σ rj
Removal rates
Metropolis KMC
Choose atom i
randomly
Choose random
number e
Accept if e ≤ r_{i}
Δt= I/M (cons.)
Fast KMC
Choose rate ri
randomly
Always accept
Δt = I/R (var.)
(c)
Tree search (TS)
Leaves level
Detail of
removal rates
n+I
n
(d)
Row n
Root level
Partial sums
Row n+I
Rates
arranged
as ID array
Random number
(f)
Linear search (LS)
(e)
Equivalent representation of rates as ID array
Removal rates
Fig 10.5 ● (a) Metropolis KMC method (CTS). (b) Alternative, faster KMC method (variable time step). (c–e) Representation of the
removal rates as a one-dimensional array for use in a Linear Search. (f) Linear Search. (g) Tree Search (binary tree).
several bins from the immediately higher level—until
reaching the leaves, which correspond to the original
rates (see Figure 10.5g). The long linear search between
all the rates at the leaf level (Figure 10.5f) is replaced
by several short linear searches, each of them inside a
bin at a different level (Figure 10.5g). The computa­
tional cost to find the next rate is reduced from O(M)
to O(gloggM), where g is the bin size (assumed constant
throughout the levels). This can be orders of magnitude
faster than the long linear search at the leaf level.
As an example, one can use a binary tree with
two rates per bin (see Figure 10.5g). In this case, the
time to find the next rate is O(log 2 M) . Another fast
method is K-Level Search (KLS) [40], whose time cost
is O( M1/K ) , where K log g M is the number of levels.
KLS stands as the most general tree-search method,
containing many methods as particular cases, such as
the binary, quaternary, and octal trees; the linear search;
Maksym’s binning method; etc. [38, 39, 41]. If the
number of different processes (N) is small, the Bortz–
Kalos–Lebowitz (BKL) or N-fold method can be used
[42, 43], having a time cost O(N) independent of
M. BKL uses a modified tree structure with only two
levels. The first level is the list of the atom rates.
Grouping in the second level is based on the actual val­
ues of the rates, in such a manner that the processes
gathered into each bin have the same rate. Although
BKL typically performs fewer searches than KLS, a
larger bookkeeping effort is required since the rates
of the neighboring atoms are typically modified and,
thus, they need to be moved from one bin to another.
Correspondingly, BKL becomes inefficient if second
and third neighbors are included and/or if the number
of different rates is larger than 10–15, which are typical
situations for the simulation of anisotropic etching. This
justifies the use of KLS. In practice, the even bin sizes
for KLS (g 2, 4, 8,…) ultimately provide the fastest
search times as they enable bit-shift implementations of
multiplication and division operations used to find the
location of the atoms in the tree structure [44].
Calibration of KMC
The dependence of the process rates on the local envi­
ronment can be considered as an explicit function of
the number of neighbors, e.g., the number of nearest
and next-nearest neighbors, n1 and n2. One may assume
the existence of a function r(n1,n2) describing the
169
Modeling in MEMS
PA R T I I
removal rate (or, when normalized, the removal prob­
ability) of an atom in the different configurations. For
instance, it has been shown that anisotropic etching in
KOH at medium concentration (e.g., 30–40 wt%) can
be described by a Removal Probability Function (RPF):
1
r( n1 , n2 ) 1
βε n 0
1 1
e
βε (n n 0 )
e 1 1 1 1
βε n 0
2 2
1
e
e
βε (n n 0 )
2 2
2
(10.4)
where β 1kBT , kB is the Boltzmann constant and
T is the temperature. This particular analytical form
is based on geometrical arguments and visual fitting
of simulated and experimental etched profiles for a
set of mask designs [45]. The use of the RPF reduces
the number of adjustable variables from 48 removal
rates to 4 physically meaningful parameters ( ε1 , ε2 ,
n10 , n20 ). As an example, Figure 10.6a shows simula­
tion results for the KMC method using the RPF model
with ε1 0.35 , ε2 0.16 , n10 2.84 , n20 7.0
and T 348K (75°C). Comparison with column (b) of
the same figure shows that the RPF model provides a
good description of the etching results for 30 wt% KOH
at 80 °C [33]. Mimicking other etchants using the RPF
model, however, is not guaranteed to work. In a sense,
the RPF model is similar to the BCA method, limited
to describe 30–40 wt% KOH in practice.
In most cases the dependence on the neighborhood
is not treated as a parameterized function but rather as
an adjustable matrix (or table) where the process rates
rn1 ,n2 can be manually fitted by matching simulations
and experiments. This can be based on the comparison
of (i) the simulated and experimental surface morpholo­
gies, (ii) the etch rates of different surface orientations,
and (iii) the shape of the etching profile in the engineer­
ing applications. As an example, this approach has been
used in [46–48] by comparing detailed STM images
and KMC simulations of the surface morphologies of
stepped {111} surfaces and in [49] by simultaneously
matching experimental and simulated morphologies of
a wide range of surface orientations (see Figure 10.7).
Typically, these calibrations are performed by first set­
ting the rates of the slowest processes, gradually intro­
ducing changes in the more active rates by isolating and
reproducing characteristic morphologic features such
as straight, polygonal, or curved steps; triangular, hex­
agonal or round pits; different types of hillocks; or even
macroscopic features such as the resulting shape in the
undercutting of masked convex corners.
The derivation of a system of equations for KMC
similar to that in Eq. 10.3 for CCA linking the experi­
mental etch rates to the atomistic removal rates is an
open, unsolved problem. The difficulty is that the
expression for the etch rate of any surface orientation
depends in a complicated manner on the values of the
atomistic removal rates, changing as the atomistic rates
are modified [50]. In principle, only a complex itera­
tive fitting procedure may succeed in solving this prob­
lem in the future. As a result, presently the calibration
of the KMC removal rates for the simulation of aniso­
tropically etched MEMS structures cannot be routinely
performed as it requires an experienced user capable of
isolating, understanding, and reproducing the particular
features of the evolving front.
Fig 10.6 ● (a–d) Comparison of simulations and experiment: Octree search KMC method (column (a)), experiment (column (b), 30 wt%
KOH at 80 °C [33]), BCA method (column (c)) and CCA method (column (d)). Source: Masking pattern and system dimensions (in microns,
column (b)) from Ref. [33]. (b) reproduced with permission by Amtec GmbH, Germany (figs on p. 31–37 of Ref. [33]).
170
Manufacture and Processing of MEMS Structures
Stochastic Cellular Automata
The SCA was introduced by Than and Büttgenbach
[29]. The surface sites have only two occupation
states, namely, fully occupied (1) and empty (0).
However, the removal rates of the atoms can take any
value in the range [0,1]. The inner structure of a time
step is as follows: In the first loop, a removal deci­
sion is made for every surface atom by comparing the
neighborhood-dependent removal rate r and a random
r , the atom is marked to
number 0 e 1 . If e
be removed. The random number e can be kept equal
for all equivalent atoms—stressing the parallelism and
simultaneity—or can be chosen different for each atom.
Once all decisions have been taken, the marked atoms
are removed in the second loop, and the state and rate
of their neighbors are updated. At this point, time is
incremented by one unit and the system is ready for a
new time step. This procedure corresponds to a CTS
implementation. The method is reminiscent of the
Metropolis KMC scheme of Section 10.5.2. The dif­
ference is that SCA operates on the surface atoms syn­
chronously using the double D&P loop characteristic
of the CA simulations while Metropolis KMC operates
purely sequentially.
Calibration of SCA
The derivation of a system of equations for SCA similar
to that in Eq. 10.3 for CCA linking the experimental
CHAPTER 10
etch rates to the atomistic removal rates is an open
problem. Refs. [10, 29] consider only the case of the
main orientations {100}, {110}, and {111}. However,
incorporating more surface orientations is a complex
task. Although the face-specific etch rates of 100 and
110 can be simply assigned to the site-specific rates
for a particular type of atom in each case, the same is
not true for other orientations, including {111}. The
removal of the terrace atoms on the {111} surface leads
to a full layer of addatoms (or lollies), and the actual
value of their removal rate will affect the overall etch
rate for this surface. As a result, the etch rate of {111}
depends on the removal rates of two atoms. Although
in this case the dependence is simple, the etch rates for
other surface orientations become complex functions of
several (probably, many) atomistic rates. The form of
these functions has not been determined yet.
KMC vs. CA
When comparing KMC and CA simulations, the latter
are characterized by an average behavior following exactly
the same pattern in equivalent regions of the microma­
chined system. On the contrary, KMC is stochastic by
construction, leading to random features in the etch
front, including the formation of round edges between
the fast etching planes. For shape comparisons between
the etch fronts it is recommended to use the KMC
method in systems containing twice the number of unit
cells as compared with the DCA and/or CCA systems.
Fig 10.7 ● (a–i) Some typical surface morphologies for different surface orientations using the KMC method. After calibration has been
performed, the same atomistic rates are used to simulate the surface morphology of the different surface orientations [49]. Source: (f),
(g), (h), and (i) are from Fig. 1(f), 1(c), 1(e), and 1(a) in [49], respectively. Reproduced with permission by IOP.
171
PA R T I I
Modeling in MEMS
This reduces the relative importance of the stochastic
features of the KMC front. Simulation results concern­
ing the use of CCA and KMC for etching applications
such as microneedles, microfluidics, and other complex
processes can be found in Refs [35, 36, 44]. Figure 10.6
offers a comparison of the three simulation methods
against the experiment for an etchant (30 wt% KOH
at 80 °C [33]) that is particularly suitable for the KMC
method using the RPF model and the BCA method.
Computationally, KMC is typically faster than
either DCA or CCA (see the CPU time values quoted
in Figure 10.6). Although the numbers depend on the
simulated system and the size of the atomistic neighbor­
hood as well as on the computer architecture, the com­
putational cost is typically about 10–40 and 2–4 times
slower for the CCA and DCA simulations, respectively.
The reason can be found in the two D&P loops of the
CA method (see Section 10.5), which have a large
impact on the efficiency. Considering the CA methods,
DCA is faster and can typically finish a given task within
a few tens of seconds up to several minutes, depending
on the computer speed, the size of the system held in
the computer memory, and the duration of the simu­
lated etch process. CCA is slower, taking typically from
a few minutes to a few hours. Thus, for MEMS applica­
tions KMC and DCA can be used for fast prototyping
and CCA for more accurate simulations.
10.5.3 Atomistic vs. Geometric
Simulators
Although the calibration of the geometrical simulators
is simpler, as they can directly use the measured etch
rates while the atomisitic simulators need to convert
the face-specific etch rates into site-specific removal
rates, there are several reasons to favor the use of the
atomistic simulations:
■
■
■
Rather straightforward compatibility with the
Finite Element Analysis (FEA) tools for the
determination of electromechanical, thermal, and/or
optical properties. The whole domain is already
conveniently discretized, including convex and
concave regions and/or protrusions.
A realistic description of the surface morphology and its
origin is included, enabling an improved understanding
of the interplay between the microscopic phenomena
and the macroscopic features. The underlying
atomistic process can be visualized, and the simulated
macroscopic system can be understood better.
A reduction in the number of experimentally
required parameters is obtained. As an example,
the use of CCA significantly reduces the number of
experimental parameters to just nine as compared
172
with hundreds or thousands of etch rates required by
the Wulff-Jaccodine method.
■
■
■
The correctness of the underlying atomistic
processes is tested, serving as a screening method for
different possible mechanisms.
The boundary conditions are greatly simplified,
allowing the use of complex mask designs.
Multi-valued surface fronts containing parts which
may split and/or join are handled natively without
any need for special procedures or geometrical
analysis. In this respect, the geometric simulators are
not always able to describe wafer perforation e.g.,
during double-side etching.
10.6 A Survey of Etching
Simulators
The following is a list of various commercial and non­
commercial simulators for modeling anisotropic etch­
ing, listed in alphabetical order. Table 10.1 compares the
major features offered by the simulators. This includes
the type of simulator (geometric or atomistic), the sup­
ported substrates (Si, GaAS, etc.), wafer orientations
(e.g., Si{100}, Si{110}, etc.), etching conditions (aniso­
tropic and isotropic etchants, concentrations and temper­
atures), mask layout tools, support for multiple masking
and etching processes (simultaneous use of different
masking materials, sequential patterning with different
masks, sequential processing by wet and dry techniques,
etc.), support for RIE/DRIE, visualization tools, export
options, operating system requirements, etc.
10.6.1 ACES
ACES stands for Anisotropic Crystalline Etch
Simulation. This simulator was released during 1998–
2001 by the Micro Actuators, Sensors and Systems
Group (MASS) at the University of Illinois at UrbanaChampaign, Urbana, USA, under a free license policy.
Although ACES is no longer an active project, the latest
version from 2001 can be downloaded [51]. ACES is an
atomistic simulator using a CCA. The time evolution
is implemented using CTS and TC for the elimination
of negative occupation (see Section 10.5.1). It uses the
dynamic method for data storage, which allocates and
deallocates memory according to the size of the active
slab region [38]. ACES is based on Refs [52, 53].
10.6.2 AnisE
The AnisE simulator was marketed in 1997–2008 by
IntelliSense Sofware Corp., from Boston, Massachusetts,
Manufacture and Processing of MEMS Structures
CHAPTER 10
Table 10.1 Wet etching simulators
VisualTAPAS1 SEAES
IntelliEtch
MICROCAD2
SIMODE/
Qsimode
ACES
AnisE/SUZANA Etch3D
UI UrbanaChampaign
TU
Coventor, Inc. Helsinki UT,
Braunschweig
Nagoya U
Southeast Fuji Res. Inst. Chemnitz UT
U
Corp.
Commercialized by
Free, OTM
UIUC3
IntelliSense/
Academic4
Free/
IntelliSense1
Academic4
Mizuho Inf.
&Res.
Imtec
Availability
1998–2001,
2001
1997–mid2008/ 2005–2007
1994
2007–/
mid-2008–1
2007–
1998–
1998–
Simulator
Atomistic
Atomistic
Atomistic
Atomistic
Atomistic
Geometric
Geometric
Type
CCA
DCA, SCA
Metropolis KMC KMC, DCA, CCA
CCA
Wulff–Jaccodine Wulff–Jaccodine
TimeStepping
CTS
CTS
CTS
VTS, CTS
CTS
DataStorage
dynamic
dynamic
dynamic
Octree
dynamic
Points/Segments Points/Segments
Substrate
Si, GaAs
Si
Si
Si
Si
Si, quartz
Si, quartz
Orientation
(100), (110),
(111)
(100), (110)
3main
vicinal any (hkl), incl.
vicinal
(100)
any (hkl)
(100), (110)
SOI wafer
No
No
No
Yes
No
No
No
Anisotr. Etch
KOH, TMAH,
EDP
KOH, TMAH, EDP KOH, TMAH
KOH, TMAH,
KOH:IPA
KOH, TMAH
KOH, TMAH
KOH, TMAH, KOH:
IPA
Conc.s/Temp.s
Various
Various
Limited
Various
Various
Wide range
Various
Database
Limited
Limited
Limited
Limited
Limited
Extensive
Limited
Isotr. Etch
Yes
Yes
Extra module
Yes
Yes
?
Yes(estimation)
User-defined rates
Yes
Yes
Yes (difficult)
Yes
Yes
Needs full pattern Needs full pattern
Etch control by…
time, doping
time, frames,
time
time, depth
removed atoms
time, depth,
frames,
removed atoms
time, depth
etch stop
time,
multipleetch
stops
Etch top/bott/both
Yes/?/?
Yes/Yes/Yes
Yes/Yes/Yes
Yes/Yes/Yes
Yes/Yes/No
Yes/?/?
Yes/Qsimode/
Qsimode
Mask layout
Arbitrary
Arbitrary
Arbitrary
Arbitrary
Arbitrary
Arbitrary
Arbitrary
Mask editor
Integrated
External
(IntelliMask)
External
External
External
(L-Edit)
Integrated
External (EMaDe)
Maks files
DXF, GDSII, CIF, DXF, GDSII
GIF, BMP
?
DXF, GDSII, BMP CIF
?
DXF, GDSII, ASCII,
GIF
Points
Points, surf,
cubes, atoms
OpenGL
surf
Outline, facets
Outline, facets
Yes
No
Yes
Using Qsimode
Developed at
TC
Integrated 3D viewer Points, facets
Points, surface
OpenGL
Cross sections
?
Coventor
Surf→ext.
viewer
Yes
Yes
TC
TC
CTS
CTS
OpenGL
(Continued )
173
PA R T I I
Modeling in MEMS
Table 10.1 Continued
ACES
AnisE/SUZANA Etch3D
VisualTAPAS1 SEAES
MICROCAD2
SIMODE/
Qsimode
Measure distances
?
Yes
No
Yes
?
Indirectly
RIE
wetetch
Yes
Extra module/Yes Extra module
Yes
No
No
No
Many masks/etches
Yes
Yes
?
Yes
No
?
Only in Qsimode
FEA export
?
For IntelliSuite
For CoventorWare C3D8R (ABAQUS) No
?
ADPL, DirectX
Other exports
VRML, AVImovie VRML, DXF
?
VRML, XYZ, JPG
No
IGES, AVS
DXF, IGES, GDSII
OS
Windows
Windows
Windows
Windows
Windows
Unix
Windows
References
[52, 53]
[55]/[10, 29, 54] [45]
[35, 36, 38, 44,
45]
[57,58]
[22,23,27]
[19]
?
Notes:
? not known (information is not available)
1
Commercial version: IntelliEtch [61].
2
Presently marketed as FabMeister-ES.
3
Office of Tech. Management at U. Illinois Urbana-Champaign [51].
4
Academic collaboration only.
USA, as part of the IntelliSuite family of MEMS design
tools [8]. The tool is an atomistic simulator based on
the methods DCA and SCA using CTS. AnisE is based
on SUZANA (see Section 10.6.8) and Refs [29, 54,
55]. AnisE was replaced during 2008 by a new simula­
tor IntelliEtch, a licensed version of VisualTAPAS (see
Section 10.6.9).
10.6.3 Etch3D
The Etch3D simulator was marketed in 2005–2007
by Coventor Inc., with headquarters in Cary, North
Carolina, USA, as part of the CoventorWare package
for MEMS design [7]. Etch3D is a simulator using the
Metropolis KMC method, i.e., the CTS implementa­
tion of KMC (see Section 10.5.2). Etch3D is suitable
for the simulation of anisotropic etching in 30–40 wt%
KOH at 70–90 °C. In addition, it can qualitatively simu­
late etching in low, medium, and high concentration
of both KOH and TMAH. It is based on Ref. [45] and
general theoretical arguments about the concentration
and orientation dependence of the etch rate of a generic
etchant [56].
10.6.4 MICROCAD (presently
FabMeister-ES)
FabMeister-ES has been marketed since 2005 by
Mizuho Information & Research Institute, Inc. [25].
The program is traditionally known as MICROCAD,
which was released in 1997 by Fuji Research Institute
174
Corp., Japan, with a focus mainly on the domestic
Japanese market. MICROCAD is a geometrical simu­
lator based on the Wulff-Jaccodine method and using
CTS. The program makes use of ODETTE, one of
the widest etch rate databases for anisotropic etching.
MICROCAD is based on Refs. [22, 23, 27].
10.6.5 SEAES
SEAES stands for South East Anisotropic Etching
Simulator. This academic simulator from the Key
Laboratory of MEMS of the Ministry of Education,
Southeast University, Nanjing, China, is only available by
directly contacting the main developers, Dr. Zai-Fa Zhou
(zhouzaifa@yahoo.com.cn) and Prof. Qing-an Huang
(hqa@seu.edu.cn). SEAES has been developed since
2005 and is currently under active development. The
simulator implements the CCA method and uses CTS
with standard TC (see Section 10.5.1), according to our
analysis of the original publications [57, 58]. Although
there are many similarities between SEAES and the
CCA engine in VisualTAPAS (see Section 10.6.9),
data storage is different, with SEAES being based on
the dynamic method [38]. More information about
SEAES can be found in Refs [57, 58].
10.6.6 SEGS
Directed Segments, or SEGS, was released under a
free license policy during 1996–1998 by the California
Institute of Technology, California, USA. SEGS is no
Manufacture and Processing of MEMS Structures
longer an active project. The program provided online
3-D isotropic and anisotropic etch simulations based on
a hybrid geometrical-cellular method. A description of
SEGS is provided in Ref. [59].
CHAPTER 10
available. In the last few years SUZANA has undergone
new active developments, including the modeling of
DRIE [11]. SUZANA is based on Refs [10, 29, 54].
10.6.9 VisualTAPAS
10.6.7 SIMODE/QSimode
SIMODE was developed during 1993–1999 by Frühauf
and co-workers at Chemnitz University of Technology,
Chemnitz, Germany. Initially, the program was mar­
keted by Gemac GmbH, Chemnitz. Since 2003, it
has been traded by Amtec GmbH, Chemnitz [24].
SIMODE is a software package consisting of a mask
design tool (EMaDe), two engines (SIMODE, for the
simulation of the etched relief based on the propaga­
tion of the upper and lower contours, and QSimode,
for the simulation of vertical cross-section etches), and
the 3D-Viewer. SIMODE itself is a geometric simulator
based on the Wulff-Jaccodine method using Constant
Time Stepping. For Si100 wafers, simulations can be
performed in KOH (30% and 40% at 60 °C and 80 °C),
TMAH (25% at 70 °C, 80 °C, and 90 °C), and KOH:IPA
(27% at 70 °C). For Si110, simulations are possible for
30% KOH:H2O at 80 °C. Other conditions are provided
on request. The program is based on Ref. [19].
10.6.8 SUZANA
SUZANA was developed during 1994–1996 by Than
and Büttgenbach at the Institute for Microtechnology,
Technical University of Braunschweig, Braunschweig,
Germany [29, 54]. The program is an atomistic simulator
based on the Discrete Cellular Automaton (DCA) and
the SCA, using CTS (see Section 10.5.1). For the SCA
method, it is not clear whether the random number e
is kept constant or is different for equivalent surface
atoms (see Section 10.5.2). This program has been the
basis for the commercial simulator AnisE since 1997
(see Section 10.6.2). SUZANA itself is not publicly
VisualTAPAS stands for Visual Three-dimensional
Anisotropic Processing at All Scales. Inheriting many fea­
tures from a previous simulator (TAPAS) developed by
Gosálvez at Helsinki University of Technology, Helsinki,
Finland, VisualTAPAS was further developed by Xing
and Gosálvez at Nagoya University, Nagoya, Japan. The
program was released in February 2007 and is currently
under active development [60]. VisualTAPAS is an atom­
istic simulator that uses both KMC and CA time-evolution
algorithms. This includes a fast Octree Search KLS
method for the KMC simulations, and both DCA and
CCA for the CA simulations. Variable and CTS are
available for both KMC and CA. Standard and Backward
TC methods can be used in the CCA simulations. Data
storage is based on an octal tree representation of the
substrate [38], enabling the simulation of etching for
any surface orientation—not limited to {100}, {110},
and {111}—and masking by silicon oxide and/or nitride
for the top and/or bottom sides simultaneously. At the
time of writing VisualTAPAS has been calibrated to sim­
ulate KOH (30 wt% at 70 °C and 80 °C; 11 wt%, 40 wt%,
and 50 wt% at 70 °C; and 37 wt% at 30 °C, 50 °C, 70 °C,
and 90 °C), TMAH (20 wt% at 80 °C), and KOH:IPA
(11 wt% and 37 wt% at 70 °C), with more calibrations
under work. VisualTAPAS includes the modeling of
DRIE. VisualTAPAS is offered as a fully operational, free
trial version which expires after starting the program
several times (typically 10). A commercial, non-expiring
version is available under the name of IntelliEtch [61]
from IntelliSense Software Corp. [8]. Academic groups
can choose between a free IntelliEtch copy with­
out support or full support for a modest license fee.
VisualTAPAS is based on Refs [35, 36, 38, 44, 45].
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February 1990, pp. 44–49.
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model of a microfabricated structure,
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Actuator Workshop, June 1990,
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M.A. Shulman, J.K. White, A
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computer-aided design, in: Proc.
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6. N. Finch, J. Marchetti, A. Swiecki,
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18.09.2009).
10. U. Triltsch, S. BŸttgenbach, Next
generation of TCAD environments for
MEMS design, in: Proc. Symposium
on Design, Test, Integration and
Packaging of MEMS/MOEMS-DTIP
2008, Nice, France, April 9–11, 2008.
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Microsystems): http://www.imt.tu­
bs.de/imt/en/institut/mitarb/boese/
projekte/design (visited 28.10.2008).
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IMT, TU Braunschweig): http://www.
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set approach to a unified model for
etching, deposition and lithography
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diffusion and complex simulations,
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16. B. Radjenović , M. RadmilovićRadjenović , M. Mitrić , Appl. Phys.
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19. J. Frühauf, K. Trautman, J. Wittig,
D. Zielke, A simulation tool for
orientation dependent etching,
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20. C.H. Sequin, Computer simulation
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21. G. Li, T. Hubbard, E.K. Antonsson,
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and Simulation of Microsystems
(MSM 98), Santa Clara, California,
USA, April 6–8, 1998, pp. 356–361.
22. A. Koide, K. Sato, S. Tanaka,
Simulation of two-dimensional etch
profile of silicon during orientationdependent, Proc. of MEMS-91
(1991) 216.
23. K. Asaumi, Y. Iriye, K. Sato,
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January 26–30, 1997, pp. 412–417.
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MEMS materials: measurement of
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Seventh International Symposium,
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27. K. Sato, M. Shikida, Y. Matsushima,
T. Yamashiro, K. Asaumi, Y. Iriye,
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28. FabMeister-ES (formerly
MICROCAD) includes the etching
simulator and a database (ODETTE).
Mizuho Information & Research
Institute, Inc. (http://www.mizuho­
ir.co.jp/english/solution/microcad/
index.html (visited 18.09.2009)).
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of anisotropic chemical etching of
crystalline silicon using a cellular
automata model, Sens. Actuators A 45
(1994) 85–89.
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Hines, Orientation-resolved chemical
kinetics: using microfabrication to
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KOH/Si etching, J. Phys. Chem. B
106 (2002) 1557–1569.
31. M. Shikida, M. Ando, Y. Ishihara,
T. Ando, K. Sato, K. Asaumi, Nonphotolithographic pattern transfer for
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cellular automata method,
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35. M. Gosálvez, Y. Xing, K. Sato,
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cellular automaton for anisotropic
etching, J. Microelectromech. Syst. 17
(2008) 410–431.
36. Y. Xing, M. Gosálvez, K. Sato, Step
flow based cellular automaton for the
simulation of anisotropic etching of
complex MEMS structures, New J.
Phys. 9 (2007) 436.
37. M. Gosálvez, Y. Xing, K. Sato, R.M.
Nieminen, Discrete and continuous
cellular automata for the simulation of
propagating surfaces, Sens. Actuators
A: Phys. (2009), doi 10.1016/j.sna
2009.08.012.
38. M.A. Gosálvez, Y. Xing, K. Sato,
R.M. Nieminen, Atomistic methods
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simulation of crystal growth, J. Phys.:
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40. J.L. Blue, I. Beichl, F. Sullivan, Faster
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42. A.B. Bortz, M.H. Kalos, J.L. Lebowitz,
A new algorithm for Monte Carlo
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Comput. Phys. 17 (1975) 10–18.
43. T.P. Schulze, Kinetic Monte Carlo
simulations with minimal searching,
Phys. Rev. E., 65, 036704.
44. Y. Xing, M. Gosálvez, K. Sato,
Octree-search kinetic Monte Carlo
for the simulation of complex 3D
MEMS structures, in: Proc. of MEMS
2008, The 21st IEEE International
Conference on Micro Electro
Mechanical Systems, Tucson, Arizona,
USA, January 13–17, 2008,
p. 323–326.
45. M.A. Gosálvez, P. Kilpinen,
E. Haimi, R.M. Nieminen, V. Lindroos,
Anisotropic wet chemical etching of
crystalline silicon: atomistic MonteCarlo simulations and experiments’,
Appl. Surf. Sci. 178 (2001) 7–26.
46. J. Flidr, Y.C. Huang, T.A. Newton,
M.A. Hines, An atomistic mechanism
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surfaces, J. Chem. Phys. 108 (1998)
5542–5553.
47. T.A. Newton, Y.-C. Huang, L.A.
Lepak, M.A. Hines, The site-specific
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Understanding the pH dependence
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of dissolved oxygen in buffered HF
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49. M. Gosálvez, R.M. Nieminen, Surface
morphology during anisotropic wet
chemical etching of crystalline silicon,
New J. Phys. 5 (2003) 100.
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evolution by step formation and flow,
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52. Z. Zhu, C. Liu, Simulation of
anisotropic crystalline etching using
a continuous cellular automata
algorithm, J. Comput. Modeling Eng.
Sci. 1 (2000) 11–19.
53. Z. Zhu, C. Liu, Micromachining
process simulation using a continuous
cellular automata method,
J. Microelectromech. Syst. 9 (2000)
252–261.
54. S. Büttgenbach, O. Than, SUZANA:
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55. J. Marchetti, Y. He, O. Than,
S. Akkaraju, Efficient process
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using cellular automata simulation
techniques, in: SPIEÕs 1998
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Microfabrication, Micromachined
Devices and Components, Santa Clara,
CA, USA, September 20–22, 1998.
56. M.A. Gosálvez, K. Sato, A.S. Foster,
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(2007) S1–S26.
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CHAPTER 10
simulator for silicon anisotropic
etching processes considering high
index planes, J. Micromech. Microeng.
17 (2007) S38–S49.
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60. http://tfy.tkk.fi/~mag/VisualTAPAS/
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177
11
Chapter Eleven
Mechanical Properties of
Silicon Microstructures
Maria Ganchenkova and Risto M. Nieminen
COMP/Department of Applied Physics, Helsinki University of
Technology, Espoo, Finland
11.1 Basic Structural Properties of
Crystalline Silicon
11.1.1 Silicon Structure Ground State:
Lattice Parameter
At ordinary pressure silicon crystallizes in a diamond
structure that consists of a face-centered cubic lattice
with a basis of two atoms. Each atom constituting this
structure is tetrahedrally coordinated and manifests sp3
hybridization. However, at higher pressures there exist
a number of high-pressure phases with different struc­
tures, as we discuss later (Figure 11.1).
Lattice parameter is one of the most fundamental
characteristics of a crystal. There exist lattice parameter
a
Fig 11.1 ● The diamond structure. Lattice parameter is denoted
as a.
measurement methods that give its absolute value with
an accuracy of the order of 10�7, namely the Bond
method [1] and simultaneous X-ray and optical inter­
ferometry (XROI) [2].
XROI measurements performed for pure silicon
at 22.5°C under vacuum independently by different
groups [3–5] gave results that were consistent within
estimated errors (Table 11.1) and only slightly higher
than those obtained by Cohen [6]).
Other measurements reported besides XROI give a
broader value range, which is, however, still quite nar­
row (3 � 10�6 Nm) [8].
All the theoretical calculations using force-field
methods correctly describe bulk silicon in its diamond
structure ground state, giving a value for the lattice
parameter that is close to the value that is experimen­
tally observed (Table 11.2). This is, however, natural,
because all the semiempirical potentials, including tightbinding (TB) ones, are constructed so as to provide a
correct description of the silicon ground state and use
the correct lattice constant as a fitting parameter. The
potentials are also fitted so as to accurately describe
the energy needed to create small displacements from
equilibrium, elastic constants, and phonon frequencies
(see the next section). More accurate ab initio calcula­
tions also reproduce the experimental lattice parameter
Table 11.1 The lattice parameter measured by XROI method (in Å)
[4]
[3]
[7]
[6]
5.427
5.44
5.41
5.38
179
Modeling in MEMS
PA R T I I
Table 11.2 The lattice parameter value (in Å) calculated using different methods
Lenosky
TB [9]
Kwon
TB [10]
Wang
TB [11]
Sockboro
TB [12]
Tersoff
[13]
SW
[14]
EDIP
[15]
DFT (Ganchenkova)
LDA
GGA [328]
5.427
5.44
5.41
5.38
5.432
5.431
5.430
5.395
reasonably well (Table 11.2). However, as seen in the
table, DFT (density functional theory) calculations
with the use of the LDA (local density approximation)
approximation slightly underestimate this value, whereas
those using the GGA (generalized gradient approxima­
tion) approximation lead to the overestimation of it.
The temperature dependence of the lattice param­
eter has been measured by different groups (see for
example Refs. [16, 17]. Okada and Tokamuru [17],
on the basis of their measurements of the silicon lat­
tice parameter in the temperature range from 120 to
1500 K, have proposed the following phenomenological
relation for the linear thermal expansion coefficient:
5.456
Table 11.3 Coefficient β estimated for different impurities (in
cm3/atom)
Impurity
β
O
(4.4 � 0.2) � 10�24
measured
[18]
C
(�6.9 � 0.5) � 10�24
measured
[18]
B
�5.46 � 10�24
from �4.5 � 10�24 to
�5.6 � 10�24
�2.3 � 10�24
calculated
measured
[19]
[22–24]
measured
[20]
Reference
α(T ) � (3.725 1 � exp ⎡⎢�5.88 � 10�3(T � 124)⎤⎥
⎣
⎦
�5.548 � 10�4 T) � 10�66 K�1
(11.1)
P
�0.77 � 10�24
�0.72 � 10�24
�1.0 � 10�24
�1.8 � 10�24
calculated
measured
measured
measured
[20]
[20]
[24]
[22]
where T is the absolute temperature (in K). This rela­
tion is accurate within 2 � 10�7 K�1.
The lattice parameter is expressed in terms of the
thermal expansion coefficient as
Sb
2.8 � 10�24
2.8 � 10�24
calculated
measured
[21]
[21]
{
}
⎤
⎡
a(T ) � a0 ⎢⎢ ∫ α(T )dT � 1⎥⎥
⎥⎦
⎢⎣ 295.7
T
(11.2)
where a0 is the lattice parameter at 295.7 K, and α(T)
varies from 0 to 4.5 � 10�6 K�1 when T changes from
130 to 1400 K.
In addition to the temperature, the silicon lattice
parameter can be sensitive to the presence of impurities, which can lead to both lattice contraction and
expansion, depending on the impurity atom size. This
lattice contraction/expansion, Δa/a, is proportional to
the impurity concentration, CI, and can be expressed as
Δa
� βCI
a
(11.3)
where β is called the expansion coefficient.
There are both wanted and undesirable impurities
in silicon. Oxygen and carbon are the most frequent
impurities and are unwanted. Some X-ray diffractom­
eter measurements were done for these kinds of impuri­
ties [18] and expansion coefficients β were determined
(Table 11.3). The desired impurities (such as P, B, Sb,
etc.) are introduced to the crystal in a controlled way
180
and often in concentrations below the level that is
detectable by the lattice parameter measurement tech­
niques. For cases where it is important to estimate the
lattice expansion/contraction due to dopants (e.g., when
one has to evaluate residual stresses in diffused wafers
and devices), an analytical formula has been proposed [8]:
⎡ r � rSi ⎤ 1
⎥
β�⎢ i
⎢ r
⎥
⎣ Si ⎦ NSi
(11.4)
where ri and rSi are the tetrahedral covalent radii of
the dopant and silicon atoms, respectively, and NSi is
the number of silicon atoms per cm3. This formula has
been applied for the estimates of the expansion coef­
ficient for a number of dopants, such as P [19], B [20],
and [21]. The expansion coefficient calculated using
Equation 11.4 agrees well with most of those estimated
experimentally.
11.1.2 Silicon Structure Ground State:
Elastic Constants and Moduli
The elastic constants provide a description of the elas­
tic response of a solid [25–27]. For single crystals, the
second-order elastic constants describe the linear elastic
Mechanical Properties of Silicon Microstructures
stress–strain response. Higher order elastic constants
reflect the nonlinear elasticity of the material [26].
11.1.2.1 Harmonic Approximation and Room
Temperatures
The elastic constants are the system energy second
derivatives with respect to the strains, defined as
εij �
∂u j ⎞⎟
1 ⎛⎜ ∂ui
⎟⎟
⎜⎜
�
2 ⎝⎜ ∂x j
∂xi ⎟⎠⎟
(11.5)
where u is the elastic displacement. Indeed, when the
strains are sufficiently low, one can approximate the elas­
tic energy ΔE stored in a uniformly strained crystal as
ΔE �
V
Cij εi ε j
2
C11 �
1 ∂2 E
V ∂ε12
1 ∂2 E
C11 � C12 �
, ε � ε1 � ε2
2V ∂ε2
C44 �
B�
The elastic constants allow one to calculate the compo­
nents of the elastic stress from the known elastic strain
according to Hooke’s law:
C11 � 2C12
3
1
μ � C44 � (2C44 � C12 � C11 )
5
(11.10)
1
C12 � (2C44 � C12 � C11 )
5
ν �
⎡
⎤
2
2 ⎢C12 � C44 � (2C44 � C12 � C11 )⎥
5
⎣⎢
⎦⎥
(11.11)
and
E � 2(1 � ν )μ
(11.8)
(Note that here the stress and strain components are
not in the Voigt but in the standard notation.)
The usual way for measuring the elastic constants is
the monitoring of ultrasonic velocities as a function of
the external static pressure [28]. The first measured
values of silicon elastic constants were reported by
McSkimin and coworkers [29, 30]. Later these constants
were defined more accurately by Hall [31] (Table 11.4).
There exist several theoretical techniques for the cal­
culation of elastic constants, including molecular stat­
ics (MS), molecular dynamics (MD), and Monte-Carlo
(11.9)
and the reverse value—compressibility, K � 1/B, can
be determined by imposing hydrostatic loading scheme
(that is, ε1 � ε2 � ε3). The experimentally measured
values of B and K for crystalline silicon are 97.84 GPa
and 1.02 GPa�1, respectively [31], whereas the calcu­
lated values for B vary within 90–110 GPa.
For practical characterization of material elastic prop­
erties we often use other parameters, such as the shear
modulus, μ, Poisson’s ratio, ν, and Young’s modulus, E,
which can be expressed in terms of the elastic constant
tensor components (in Voigt’s notation) as
(11.7)
1 ∂2 E
V ∂ε42
σii � C11εii � C12(ε jj � εkk )
σij � 2C44 εij ,(i � j)
(MC). The interactions between silicon atoms are
described either with empirical interatomic potential
(the best-known potentials are those of Stillinger-Weber
(SW) [13, 14], and Lenosky [35], as well as the modified
embedded atom method (MEAM) potential of Baskes
[36] and the environment-dependent (EDIP) potential
[37] or in the framework of TB and ab initio formula­
tions. Typically, the elastic constants are determined as
strain derivatives of the calculated stresses or energy. By
now, quite a number of theoretical calculations of these
values have been reported [9–12, 32–34] (Table 11.4).
The calculated elastic constants are sensitive to the
choice of the interatomic interaction law, but most of
them reproduce the experimental data reasonably well.
The crystal bulk modulus B, defined as
(11.6)
where Cij is the tensor of elastic constants, V is the
crystal volume, the Einstein summation rule over the
repeated subscripts is implied, and Voigt’s notation for
the strains is used. The quadratic dependence of elastic
energy on strains is usually called harmonic approxima­
tion. The total number of independent components of
the elastic constant tensor depends on the symmetry
of the crystal. In particular, crystalline silicon has cubic
symmetry, which is fully characterized by only three
independent constants:
CHAPTER 11
(11.12)
The deviation of the crystal elastic properties from full
isotropy is characterized by either the anisotropy ratio,
A, or anisotropy factor, H:
2C44
C11 � C12
H � 2C44 � C12 � C11
A�
(11.13)
which in silicon are measured to be 1.56 and 574 GPa,
respectively.
The Voigt formulation is always appropriate for
monocrystalline materials. However, for polycrystalline
materials it can be used only when the grains of different
181
PA R T I I
Modeling in MEMS
Table 11.4 Comparison of theoretical and experimental values for second-order elastic constants for
crystalline silicon (in GPa)
Method
Potential
Ref
C11
C12
C44
υ
μ
B
Y
Theoretical calculations
MD
SW
Tersoff
Lenosky
SWmod
Baskes
[32]
161
141
164
161
161
80.5
74.0
83.0
80.5
63.3
60.2
68.9
70.5
80.4
76.9
0.291
0.261
0.274
0.250
0.221
46.9
45.3
50.5
53.6
58.2
108
98.1
110
108
97.6
138
138
151
161
164
MS
EDIP
TB
[33]
[9]
[10]
[11]
[12]
172
167
150
154
128
64.7
66.5
56.3
69.9
75.3
72.8
75.4
89.0
69.0
0.233
0.232
0.177
0.252
65.1
65.4
72.2
58.3
100.5
100.1
87.6
98.1
93.0
161
161
170
146
LDA
[32]
[34]
159
162
67.3
63.5
80.0
77.3
0.224
0.221
57.2
66.1
97.9
96.4
140
161
GGA
[32]
151
60.6
79.2
0.209
56.5
90.6
137
T � 300 K
[29,30] 165.64 63.94
79.51
0.218
68
97.84
T � 300 K
[31]
165.70 63.9
79.6
0.218
60.5
97.8
T � below 100 K
[28]
167.72 64.98
80.36
Experimental measurements
orientations have the same stress. Otherwise, when the
grains have the same state of strain or when long-range
internal stress fields are involved, the Reuss formulation
operates better [8].
11.1.2.2 Effect of Pressure
At high-elastic strains the harmonic approximation
becomes insufficient to correctly describe the elastic
energy. This was demonstrated for the first time by
McSkimin [29], who measured the Cij as a function of
the applied hydrostatic pressure up to 8 GPa. He found
some deviation of the Cij from the constant values
already at some hundreds of MPa.
There exist several ways to improve the energy descrip­
tion. One of these is to assume that the elastic constants
themselves are the functions of the applied loads. Several
calculations and measurements of the pressure depend­
ence of the second-order elastic constants have been
reported in the literature (e.g., Table 11.5). However,
the linear pressure dependence of the second-order
elastic constants remains reasonable only up to some
stress limit.
182
99.23
Table 11.5 The pressure derivatives of the second-order elastic
constants for crystalline silicon
Reference
dC 11/dP
dC 12 /dP
dC 44 /dP
Calculated [38]
4.9
4.9
2.1
Measured [30]
4.2
4.2
2.7
An alternative way to treat the nonlinearity effects
is to include the higher than second-order terms in the
formal expansion of the elastic energy in strains. The
coefficients in these expansion terms are referred to as
higher order elastic constants. Cubic crystals have six
independent third-order elastic constants Cijk. They
are usually described using the Lagrangian form (see for
example Ref. [39]. The alternative form is the Eulerian
form, where the basic difference lies in the coordinate
system being fixed or following the solid under defor­
mation. These constants have been measured using the
ultrasonic method by McSkimin [29] and Hall [31]
(Table 11.6).
Mechanical Properties of Silicon Microstructures
CHAPTER 11
Table 11.6 Comparison of theoretical and experimental values for third-order elastic constants for crystalline silicon
(in GPa)
Method
C111
C112
C123
C144 � 2C166
C456
[39]
�750
�480
~0
�580
�80
[34]
�810
�422
�61
�555
�61
[31]
�795 � 10
�445 � 10
�75 � 5
�605 � 10
�86 � 5
[30]
�825 � 10
�451 � 5
�64 � 10
�608 � 10
�64 � 5
Reference
Theoretical calculations
DFT/LDA
Experimental data
T � 298 K
One of the methods used for calculation of the
higher order elastic constant was introduced by Nielsen
and Martin [39]. It implied the use of the stress theo­
rem within density-functional theory and exploited
the method of homogenous deformation. Later Zhao
et al. [34] slightly modified the methods in a way that
allowed their use for complex crystal lattices. The elas­
tic constant values calculated with these methods repro­
duce the measured values within 20 GPa, except for the
C123 value calculated by Nielsen and Martin [39], which
is almost zero (Table 11.6).
There are two different expressions for the relation­
ship between the volume and pressure. The first is the
Murnaghan equation, which assumes the bulk modulus
varies linearly with the pressure:
P�
�B�
⎛
⎞⎟
B ⎜⎜⎛⎜ V ⎞⎟
⎟
⎜⎜⎜⎜ ⎟⎟ � 1⎟⎟
⎟⎟
B� ⎝⎜⎝⎜ V0 ⎠⎟
⎠
(11.14)
�B�
⎛
⎞⎟
B ⎜⎜⎛⎜ V ⎞⎟
⎟⎟
⎟
�
1
⎜⎜ ⎟
⎟⎟
B� ⎜⎝⎜⎜⎜⎝ V0 ⎟⎠
⎠⎟
(11.15)
Another relation is found by relating the first two
terms in the Eulerian stress–strain relation, the Birch
equation:
P�
�7 /3
⎛
⎛ V ⎞�5 /3 ⎞⎟⎟
3 ⎜⎜⎜⎛ V ⎟⎞
⎟⎟
B⎜⎜⎜ ⎟⎟
� ⎜⎜⎜ ⎟⎟⎟
⎟⎟
⎜⎝ V0 ⎟⎠
2 ⎝⎜⎜⎜⎝ V0 ⎟⎠
⎠
⎧⎪
⎛⎛ ⎞�2 /3
⎞⎟⎪⎫
⎪⎪
⎪
⎜⎜⎜ V ⎟
3
⎟
* ⎨1 � (B� � 4)⎜⎜⎜ ⎟
� 1⎟⎟⎟⎪⎬
⎜
⎟
⎟
⎪
⎪
⎜
4
⎝⎜⎝ V0 ⎠
⎠⎟⎪⎪⎭
⎪⎩⎪
c � 6c112 � 2c123
B� � 4 � � 111
9B
(11.17)
The Birch equation gives significantly better fit than
Murnaghan’s one, and in fact no higher order terms are
required for describing the PV results within the cal­
culational accuracy. The calculated values of B� is 3.99
[34], which correlates reasonably well with the value of
4.11, measured at 298 K [31].
In engineering practice one often meets anisotropic
(nonhydrostatic) loading schemes. For example, biax­
ial strain in the (001) plane can arise during the growth
of a thin silicon film on a (001) substrate with a differ­
ent lattice constant. In this case the strain tensor can be
decomposed into hydrostatic, εh, and shear, εs, parts as
2(1 � 2C12 /C11 )
εxx
3
(1 � 2C12 /C11 )
εs � �
εxx �
3
where
(as � a f )
εxx �
af
εh � �
where the bulk modulus derivative in Lagrangian theory
is expressed as
P�
where the bulk modulus derivative in Eulerian theory is
expressed as
(11.18)
The hydrostatic component of the strain affects only the
interatomic bond length, while the shear part changes
only the angles between interatomic covalent bonds. In
the case of the biaxial strain applied in the (111) plane
the elements of the strain tensor are
2C44
ε||
2C44 � C11 � 2C12
C11 � 2C12
εs �
ε||
2C44 � C11 � 2C12
εh �
(11.16)
(11.19)
where � is the in-plane lattice mismatch strain.
183
Modeling in MEMS
PA R T I I
11.1.2.3 Effect of Temperature, Doping and
Defects
A number of measurements of the elastic constant tem­
perature dependence have been reported [29, 31, 40, 41].
For instance, McSkimin [29] scanned the temperature
range of 77–300 K, Hall [31] that of 4.2–310) K, and
Burenkov et al. [40] up to 1273 K. The data for the tem­
peratures up to 1477 K are compiled in [41]. According
to all the experimental measurements, below 100 K the
second order constants remain practically the same as
those extrapolated at 0 K (Figure 11.2), as discussed in
Section 11.1.2.1 (Table 11.4). At higher temperatures
Cij increases linearly with temperature (Figure 11.2) at
the rates specified in Table 11.7. The linear elastic con­
stant change with temperature is confirmed by theoretical
calculations (Table 11.7) [42, 43], where the considered
temperature interval was 888–1417 K. The calculated
elastic constants and their ratios for different tempera­
tures are summarized in Table 11.8. Unfortunately,
quantitative agreement between the calculated and exper­
imentally measured values is poor (Tables 11.7 and 11.8).
The reason is that the calculations used SW potential,
16.8
C11
16.7
16.6
16.5
16.4
Elastic moduli (GPa)
16.3
C44
8.1
8.0
7.8
5.2
5.1
5.0
4.9
(C11 – C12)/2
4.8
50
100
150
200
250
300
Temperature (K)
Fig 11.2 ● The temperature dependence of the second order
elastic constants for pure and n-type doped silicon. The samples
of silicon are doped with ~2 � 1019 (P atoms)/cm3.
Source: Data from [31].
184
11.1.3 High-Pressure Silicon Structures
The silicon ground state structure has been shown to be
stable up to the melting point [8]. However, pressureinduced phase transformations have been experimentally
observed at high pressures. Twelve different high-pressure
phases have been identified so far (Table 11.10). The con­
ditions for the phase transformation are different. Some
of the phases are thermodynamically stable when pres­
sure exceeds some critical values and form directly from
the cubic phase. The others transform from high-pressure
phases. For example, Cannon [47], using X-ray diffraction
with synchrotron sources, has shown that the transforma­
tion sequence with the increase of the pressure is
7.9
0
which is not well fitted to the experimentally measured
elastic constants at the ambient temperature (Table 11.4).
It has been shown that the temperature dependence
of elastic constants in silicon is strongly affected by the
doping [31, 45]. This effect has been investigated for
the cases of both heavily doped n-type silicon with the
carrier concentrations of 2.0 � 1019 cm�3 (phosphorus
doping) [31] and 4.8 � 1019 cm�3 (arsenic doping) [45],
and for the case of heavily doped p-type silicon with the
dopant concentrations of 5 � 1017 cm�3 (boron) and
3 � 1019 cm�3 (gallium) [46]. Quantitatively, doping
modifies elastic constants within 1–3%, but qualitatively
the temperature dependence can be changed completely
(see, for example, Figure 11.2).
In addition to doping, silicon elastic constants are
affected by the presence of intrinsic point defects. This
was investigated theoretically by Allred et al. [33], where
they considered interstitials, vacancies, and Frenkel pairs
(FPs) using MS method with EDIP potential. For all
these kinds of defect, the dependence of the elastic con­
stants and bulk modulus on defect fractions is found to
be linear (see Table 11.9). The different elastic constants
change most isotropically by vacancies: The increase of
vacancy concentration leads to the softening of the elas­
tic constants within 1.51–1.74%. In contrast, the increase
of interstitial concentration leads to the decrease of C44,
the increase of C12 and no change of C11 (Table 11.9).
A similar situation is found for FPs. The elastic con­
stants vary between �0.12–3.25% and �1.92–1.70%
for interstitials and FPs, respectively. The effect of the
point defect concentration on the temperature depend­
ence of the elastic constants can also be expected, even
though we could not find the information about this kind
of experimental measurements in the literature.
I – II – XI – V – VI – VII – X
This sequence is characterized by the smooth transition
from one phase to another, so that phase pairs coexist over
a wide range of pressure. When the high-pressure phase
is already formed and the decompression experiment is
Mechanical Properties of Silicon Microstructures
performed for this phase, the transformation sequence
can be different from the “compression” one and depends
on the pressure release condition. Thus, the sequence
observed in [64] is V – XI – II – XII – III.
CHAPTER 11
The formation of some high-pressure phases requires
also some heating [57] or plastic deformation at moderate temperatures (670–970 K) [59]. An example is
the phase Si-IV, which is formed from the metastable
Table 11.7 The temperature dependence rates of the elastic constants, *10�5
Reference Method
Potential
⎛ 1 ⎟⎞ dC
⎜⎜ ⎟ 11 �1
⎜⎜⎝ C ⎟⎟⎠ dT , K
⎛ 1 ⎟⎞ dC
⎜⎜ ⎟ 12 �1
⎜⎜⎝ C ⎟⎟⎠ dT , K
⎛ 1 ⎟⎞ dC
⎜⎜ ⎟ 44 �1
⎜⎜⎝ C ⎟⎟⎠ dT , K
11
12
44
Theoretical calculations
[157]
MC
SW
�7.89
�2.36
�16.1
[267]
MD
SW
�6.65
�3.35
�30.4
[41]
�9.66
�14.5
�6.41
[44]
�9.4
�9.8
�8.3
[40]
�9.3
Experimental studies
�10.0
Table 11.8 The temperature dependence of the elastic constants and their ratios (in GPa)
Reference
Method
Potential
T, K
C11
C12
C44
υ
μ
B
Y
[42]
MC
SW
888
1164
1477
141.28
136.96
133.76
75.20
74.56
74.08
51.20
47.36
45.44
0.304
0.312
0.317
43.94
40.90
39.20
97.23
95.36
93.97
114.55
107.34
103.24
[43]
MD
SW
888
1164
1477
139.20
137.12
132.96
75.20
74.24
73.60
52.80
45.60
41.92
0.300
0.316
0.325
44.48
39.94
37.02
96.53
95.20
93.39
115.67
105.11
98.11
[41]
Exp.
888
157.28
60.48
75.20
0.218
64.48
92.75
157.05
1164
1477
152.32
147.84
58.88
57.44
73.12
69.76
0.218
0.221
62.56
59.94
90.03
87.57
152.38
146.41
Table 11.9 The elastic constant and bulk modulus dependence on the point defect fraction (data from [33]). The point defects considered
are vacancy (V), interstitials (I), and Frenkel pairs (FP)
Defect
Elastic constant change within the defect fraction
interval of 0–0.3%
The defect fraction rate of the elastic constants
ΔC11
ΔC12
ΔC44
ΔB, %
⎛ 1 ⎞⎟ dC
⎜⎜ ⎟ 11
⎜⎜⎝ C ⎟⎟⎠ d η
⎛ 1 ⎞⎟ dC
⎜⎜ ⎟ 12
⎜⎜⎝ C ⎟⎟⎠ d η
⎛ 1 ⎞⎟ dC
⎜⎜ ⎟ 44
⎜⎜⎝ C ⎟⎟⎠ d η
44
⎛ 1 ⎞⎟ dB
⎜⎜ ⎟
⎜⎝ B ⎟⎠ d η
V
�1.74
�1.55
�1.51
�1.69
�0.06
�0.05
�0.05
�0.06
I
�0.12
3.25
�1.79
1.29
0.00
0.11
�0.06
0.04
FP
�1.92
1.70
�3.30
�0.40
�0.06
0.06
�0.11
�0.01
11
12
185
PA R T I I
Modeling in MEMS
Table 11.10 Crystalline phases of silicon
Structural parameters
Notation
Structure
Pressure
region
Reference
Si-I
Diamond cubic
0–12.5
[47,48]
Si-II
Body-centered tetragonal (β-Sn)
8.8–16
[48–53]
Pressure
regions
Lattice
parameters
11.2
a � 0.469
c � 0.258
a � 0.469
c � 0.259
a � 0.467
c � 0.257
12.5
10.3
Si-III (BC8)
Body-centered tetragonal (basis of 8 atoms)
2.1–0
[48–50,54]
0
2
Si-IV
Si-V
Diamond hexagonal
Primitive hexagonal
–
14–35
[56–61]
[48,53]
16
16
18
36
Si-VI
Unidentified
34–40
[53,62]
Si-VII
Hexagonal close packed
40–78.3
[50,53,63]
41–42
43
Si-VIII
Tetragonal (30 atoms per unit cell)
14.8–0
[64]
Reference
[48]
[51]
[52]
a � 0.575
α � 109.47°
a � 0.575
α � 109.47°
[55]
a � 0.38
[57]
c � 0.628
a � 0.386
c � 0.631
[58,59]
a � 0.255
c � 0.239
a � 0.253
c � 0.237
a � 0.254
c � 0.238
a � 0.246
c � 0.631
[55]
[48,50]
[53]
[52]
[62]
a � 0.252
c � 0.414
a � 0.244
c � 0.415
[50]
a � 0.863
[64]
[53]
c � 0.750
Si-IX
Tetragonal (12 atoms per unit cell)
12–0
a � 0.775
[334]
[64]
c � 0.389
Si-X
Face-centered cubic
78.3–230
[62,63]
87 � 7
a � 0.467
[62]
Si-XI (Imma)
Body-centered orthorhombic
13–15
[52]
~13
a � 0.474
b � 0.450
c � 0.255
[52]
Si-XII (R8)
Trigonal (8 atoms per unit cell)
12–2.0
[55,65,66]
8.2
a � 0.562
α � 110.07°
a � 0.571
[55]
2
186
[55]
Mechanical Properties of Silicon Microstructures
Si-III. In [56, 60] Si-I transformation to Si-IV has been
described as martensitic transformation after secondary
twinning, like that related to deformation twinning.
Many theoretical calculations have addressed this
problem. All the calculations are based on the calcula­
tions of the total energies of different structures at zero
temperature. Most of the calculations are performed
within the ab initio approaches, such as the densityfunctional theory with LDA [67, 68] and GGA [69],
or linear muffin-tin-orbitals (LMTO) [69]. In some of
the works the full sequence of transformations has been
considered [68, 70, 71]. These calculations show good
agreement with experimental observations.
11.2 Dislocations in Silicon
Extended defects could be classified with respect
to their dimensionality: Dislocations are 1D (linear)
defects, grain boundaries and stacking faults are typi­
cally 2D (planar) defects, and secondary phase pre­
cipitates are defects of 3D (volume) type. Extended
defect effects on the device functionality can be both
detrimental (for instance, the degradation of electronic
properties of semiconductors) and beneficial (e.g., when
their presence enhances the efficiency of a chemical
reaction or some other process that reduces nonradia­
tive recombination centers in semiconductors).
It is technologically very difficult to grow singlecrystal semiconductor samples for microelectronic and
optoelectronic applications that would be totally devoid
of extended defects, or, at least, of dislocations. In this
sense silicon is nearly the unique exception. It is rela­
tively easy to grow high-purity silicon single crystals
with vanishing dislocation content, which makes silicon
an ideal benchmark material for experiment, theory,
(a)
CHAPTER 11
and modeling. Unfortunately, in practical applications
it is often impossible to avoid the conditions (such as
temperature gradients during the bulk crystal growth,
or lattice misfit in heteroepitaxial growth) that promote
the nucleation of dislocations.
Dislocations, stacking faults, twins, and internal sur­
faces are nonequilibrium defects and their density must
not depend on temperature according to the Arrhenius
exp(�E/kT) law. Their presence adds some contribu­
tion to the internal energy of the material that depends
on the nature of a particular defect and on its linear or
surface energy density. The fact that extended defects
introduce an excess of internal energy into the crystal
raises, in particular, the question of their interaction
with atomic defects and impurities.
11.2.1 General Remarks
Plastic strain of a crystal in response to shear stress
application results from multiple displacements along
the crystallographic slip planes. Dislocations are line
defects representing the boundary between the region
where the slip has already occurred and a still-perfect
region of the crystal. Therefore a dislocation line can­
not terminate in a perfect region of the crystal, but
either forms a closed loop or terminates at an internal
or external surface or at another dislocation. Away from
the dislocation line the crystal is locally only negligibly
different from the perfect crystal.
One of the basic parameters characterizing a disloca­
tion is its Burgers vector b, which defines the amount of
slip caused by the dislocation (Figure 11.3). Dislocations
with Burgers vector equal to a lattice vector are called
perfect; otherwise they are referred to as partial dislo­
cations. The partial dislocations are always associated
(b)
1
1
2
2
S
S
F
3
F
t2
b
t1
Fig 11.3 ● Comparison of a lattice plane of a faulted crystal containing an edge dislocation (a) and of a perfect crystal (b). When we use
a Burgers loop procedure (see text) from S to F both on the perfect and in the faulted crystal, we must perform an extra step to close
the loop in the perfect crystal.
187
PA R T I I
Modeling in MEMS
with stacking faults. In many materials the stacking
fault energies are too high for partial dislocations to
exist. However, in some special structures, such as FCC
(face centered crystal) lattice, there exists a restricted
number of planes with low stacking fault energies.
The most energetically stable perfect dislocations
in the diamond type lattice have Burgers vectors of
½ �110� type, which correspond to the shortest
primitive lattice vectors in silicon. The preferable glide
planes are {111}-planes. These two factors define the
operative Burgers vectors and slip planes, so that the
preferable slip systems in diamond-cubic crystals are
1/2[110](111), the same as in FCC metals.
It is well known that the diamond structure can be
interpreted in terms of two interpenetrating FCC lat­
tices, one of which is displaced by (1/4, 1/4, 1/4) with
respect to the other. Due to the coexistence of two FCC
sublattices, there exist two different sets of (111) planes,
such as, for example, b and B in Figure 11.4. Thus the
silicon structure can be considered as a periodic stack­
ing of three pairs of {111} layers … aA bB cC aA …
In this structure, low-energy stacking faults involve the
insertion or removal of the pairs of planes aA, bB, or cC.
Correspondingly, two types of stacking fault exist:
a. cC aA bB | aA bB cC… , called intrinsic stacking
fault (ISF), corresponds to the removal of one
double layer (cC in this example). Another
formation of this stacking fault is a shear of the
upper half of the crystal by a/6 �112� , which puts
the cC layer into aA position.
b. cC aA bB | aA | cC aA bB cC… , called extrinsic
stacking faults (ESF), corresponds to the insertion
of one extra double layer (aA in this example).
These stacking faults are created, for example,
when an experimental treatment (such as silicon
wafer oxidation) produces excess of interstitials that
condense into dislocation loops.
The low energy of these stacking faults is a consequence
of their atomic structure, where nearest and second
Fig 11.4 ● Preferred dislocation line directions in silicon.
188
nearest neighbor distances and angles between atoms
remain unchanged compared with the perfect silicon
lattice. Most of the binding energy resides in nearest
neighbor covalent bonds, and the energy of the crystal
changes only slightly when SF is formed.
The double-layer stacking of {111} planes in the
diamond structure allows us to distinguish two sets of
planes that one could call narrow-spaced planes and
widely spaced planes [72, 73]. Following this classifica­
tion, one can define two sets of dislocations formed by
shear between either the narrow-spaced planes, such
as B|c (“glide set dislocations”) or the widely spaced
planes, such as b|B (“shuffle set dislocations”) [72, 73].
The fundamental difference between these two sets is
that narrow-spaced planes are connected by three times
more covalent bonds than widely spaced planes. Thus,
generally speaking, a low-energy stacking fault can only
be created between widely spaced planes. However, it is
now commonly accepted that dislocations usually belong
to the “glide set” [74], though the local transformations
to the “shuffle set” can occur in some circumstances, for
example when the dislocation absorbs or emits single
point defects—vacancies or self-interstitials [75].
Dislocations are often characterized also by the angle
β between the dislocation line direction and the Burgers
vector. There exist two fundamental types of straight dis­
locations: edge dislocations, where the Burgers vector b is
perpendicular to the dislocation line (β � 90°), and screw
dislocations, with b directed parallel to the dislocation
line (β � 0°). The edge dislocation in crystalline lattice
looks like a line of unsaturated lattice atoms that termi­
nates an extra lattice half-plane. When β is neither zero
nor an integral multiple of /2, the dislocation has a mixed
character (combining both edge and screw counterparts).
Two types of dislocation in silicon are of special inter­
est: screw dislocations and 60° dislocations for which
β � 60°. These preferred orientations correspond to
lower core energies. In terms of the Peierls–Nabarro
model of dislocation core [73], these types of disloca­
tions lie in the valleys of Peierls potential.
Mechanical Properties of Silicon Microstructures
The elastic energy per unit dislocation length, which
is confined within a cylinder of radius R around a gen­
eral straight dislocation, is defined as [73]
W
μb2 ⎛⎜ 2
sin2 β ⎞⎟⎟ αR
⎜cos
�
β
�
⎟ ln
L
4π ⎝⎜⎜
b
(1 � ν)⎟⎠
(11.20)
where μ is the shear modulus of the bulk material, ν is
the Poisson’s ratio, and α is a parameter representing the
core energy of the dislocation. As follows from Equation
11.20, the most stable dislocations are those with the
shortest Burger’s vectors b. On the basis of this consider­
ation, the so-called Frank criterion for the dislocation dis­
sociation can be formulated. Namely, the dissociation of a
dislocation with Burgers vector b1 into a complex system
consisting of two partial dislocations (called Shockley
partials) with Burgers vectors b2 and b3 occurs if
b12 � b22 � b32
(11.21)
An immediate consequence is that a dissociated dislo­
cation is unstable when the interaction force between
partial dislocations is attractive and stable when the
interaction is repulsive. The resulting partial disloca­
tions have different core structures or different Burgers
vector orientation and are connected with a low-energy
stacking fault. The dissociation decreases the excess
internal energy of undissociated defect, which is due
mostly to elastic strain. The stacking fault contribu­
tion to the internal energy of the system is negligible
in comparison with the internal energy decrease due to
the formation of partials, provided their interaction is
repulsive. It should be noted, however, that dislocations
lying in the shuffle set cannot directly dissociate in par­
tials, because this process is accompanied by the forma­
tion of a high-energy stacking fault.
In order to make dislocations change their positions,
one needs to apply external elastic stress above a cer­
tain threshold. In general, the minimum stress required
to move a dislocation is a function of temperature and
the time over which dislocation motion is observed.
However, the minimum stress for which dislocation
starts to move at zero absolute temperature, which
is also referred to as the Peierls stress, is a materialdependent parameter, which can be determined by
numerical simulations for each particular dislocation
type by molecular-static geometry optimizations. On
the other hand, the Peierls stress can be obtained exper­
imentally from the measurements of the yield stress at
vanishingly low temperatures [74]. Thus, the Peierls
stress as a measure of intrinsic lattice resistance to dis­
location motion can be used, in particular, as a means to
correlate experiments and simulations.
On the atomistic scale, the conservative dislocation
motion (or glide) involves local atomic displacements
CHAPTER 11
that proceed through switching one or a few interatomic
bonds at a time. Hence, this kind of motion is sensitive
to the energetics of bond switching required for dislo­
cation translation by a unit atomic distance in the glide
plane and thus is defined by the core structure of the
moving dislocation, because the relative displacement
of the core atoms contributes most to the energetics of
dislocation motion. From the purely geometrical con­
siderations, the shuffle-set should be energetically more
favorable for dislocation gliding than glide-set. Indeed, it
was demonstrated by computer simulations (see Refs in
[74]) that the shuffle-set gliding of the dislocation
implies the breaking of the least number of bonds during
the dislocation movement, and the glide-set is the set of
planes on which dislocations move.
Gliding is not the unique mode of dislocation move­
ment. Another mode, named climb, is a dislocation
movement due to building up or eating out of the dis­
location extra-plane, so that the dislocation crosses
its glide planes. Evidently, climb requires addition or
removal of atoms and is non-mass-conservative, in con­
trast with glide, which, as mentioned above, is a mass
conservative movement. Due to the necessity for mass
transfer, climb contribution to dislocation mobility and
plastic deformation is important only in quite special
conditions (such as fast particle irradiation), which pro­
vide a noticeable excess of intrinsic point defects.
11.2.2 Dislocations in Silicon: Simulation
Approaches
Silicon has been a favorite material for theoretical and
experimental investigations of dislocation nature and
mobility. However, many issues still remain unresolved.
Atomistic modeling coupled with experimental observa­
tions should be able to resolve these issues.
The early dislocation modeling treated the crystal
as an isotropic elastic medium. The models belonging
to the continuum approach allowed simulations of dis­
location movement taking into account the long-range
interactions between dislocations and the interaction
of impurities with dislocations, which were considered
impurity sinks or heterogeneous catalysts for precipita­
tion. Therefore this approach is also called Dislocation
Dynamics. However, as early as the 1960s it was real­
ized that a refinement of these models would only be
possible when detailed information about the intera­
tomic forces was available [76].
Indeed, while the crystal outside the dislocation core
region is distorted only slightly and, therefore, is well
described within a linear elastic framework, the large
lattice distortions inside the core region require atom­
istic treatment. Because the core structure is the basic
fundamental property of the dislocation, which largely
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PA R T I I
Modeling in MEMS
defines the dislocation behavior (see e.g., Refs. [77,
78]), one of the central problems of dislocation mod­
eling is the development of realistic atomistic models of
the core. In general, core contribution to the line energy
can be evaluated for different dislocation types using
interatomic potentials, TB models, and first principles
methods.
During the last few decades there were several
attempts to address this problem using semiempirical
and ab initio calculations (see Ref. [74] and references
therein). In these attempts the core structure was deter­
mined via the MS geometry optimization, where the
total energy was minimized with respect to the atomic
positions at zero temperature. The difference between
the computational approaches is in the way of descrip­
tion of interatomic interactions. The simplest approach
is to use the so-called valence force-field potential, as
that proposed by Keating [79], which emphasizes the
sp3 bonding picture and adds bond-bending terms of
the correct symmetry to a bonding pair potential. The
ideology of these potentials stems from the existence of
covalent bonds among neighboring atoms with the fixed
four-fold atomic coordination. In order to treat atoms
with lower coordinations the concept of dangling bonds
was introduced. Correspondingly, two parameters were
introduced, one for the harmonic bond stretching term,
and one for the harmonic bond bending term, which is a
function of the scalar product between the vectors con­
necting the atom to its covalently bonded neighbors.
The Kitting potential ideology in various versions
and with different parameterizations has been widely
used to study the elastic and static properties of cova­
lent semiconductors [80, 81]. The interatomic range
covered by proposed potentials varied from close near­
est-neighbor distance [14, 79, 80, 82, 83] up to several
neighbor shells [84, 85].
Though simple semiempirical potentials are able
to reproduce both the elastic constants and the pho­
non spectra of silicon, they cannot take into account
the excess electronic energy of the dangling and overcoordinated bonds, which, according to different esti­
mates, varies from 0.5 to 2 eV [86–88], [327]. In
order to extend the potential validity range away from
near-tetrahedral coordination, an ab initio data-fitted
EDIP has been proposed, which is able to reproduce
quantum mechanical-based dislocation results for the
90° and 30° partials [15]. However, even the best avail­
able potentials are unable to reproduce all experimental
situations.
For instance, the screw dislocation mobility, which
depends critically on the subtle details of the core struc­
ture, is poorly described by the existing interatomic
potentials. Also, none of the semiempirical potentials
can tackle problems related to the charge effects. The
fact that defects in silicon can be charged is important
190
for the proper understanding of interactions between
intrinsic point defects and the dislocation core, because
point defects often act as the controlling factor for dis­
location motion. The latter effect of electromechanical
coupling is expected to result in promising technological
applications. All such problems are the subject of the
first principles calculations.
Ab initio density functional theory calculations are
considered nowadays to be the most accurate approach
among those currently in use. Unfortunately they also
have strong limitations, though the situation is expected
to improve with the increasing current capabilities of
the DFT methods in combination with the development
of more powerful computers and better algorithms. In
particular, they suffer from the artifacts of boundary
conditions in small computational cells.
There exist two main approaches to deal with the
fact that in any computational approach only a small
piece of the crystal (simulation cell) with only a finite
number of atoms is simulated. These are usually
referred to as “supercell” and “cluster” methods. The
first approach implies periodic repetition of a simula­
tion cell (or supercell), which evidently results in an
infinite superlattice of defects. The advantage of this
approach is that simulated defects are embedded in an
infinite elastic medium. However, where dislocations
are involved, the approach faces a number of problems.
First of all, the sum of the Burgers vectors in the simu­
lation cell must be zero in order to avoid the divergence
of the elastic strain energy of the crystal. This means
that the simulation cell must contain at least two dis­
locations. Second, due to the periodicity of boundary
conditions, dislocations in the supercell can interact
with an infinite number of “mirror” dislocations. When
the supercell is not sufficiently large, these interactions
can affect the atomic and electronic structure of the
simulated dislocation. Finally, due to the fact that the
introduction of a dislocation into a material destroys
the translational symmetry of the lattice in a plane
orthogonal to the dislocation line, there appear prob­
lems with lattice mismatch at the cell boundaries. As
a possible way to cope with this problem, it has been
proposed to distort some of the bond lengths and angles
at the boundary of the cell in order to create a periodic
structure [86, 89, 90]. Another possible solution, which
was extensively used, is a dislocation quadruple method,
where a lattice of dislocation quadruples is introduced
in the crystal [91].
The second approach is the so-called cluster method,
where a finite cluster surrounding the defect is con­
structed. In contrast to the supercell approach, this
technique allows us to treat an isolated dislocation.
However, the cluster method is also not an ideal choice.
First of all, the cluster should in any case be sufficiently
large in order to reasonably reproduce the long-range
Mechanical Properties of Silicon Microstructures
dislocation elastic field and minimize the effects of lat­
tice structure distortions at the cluster surface. Second,
one has to care about a proper way of the cluster sur­
face termination, because the surface atoms are asso­
ciated with dangling bonds that affect the calculated
electronic properties of the cluster. In order to avoid
these dangling bonds, they are usually passivated with
hydrogen atoms, but, unfortunately, even that does not
solve the problem, because the hydrogen atoms inter­
act with electronic states at the valence and conduction
band edges [8].
Thus, all individual dislocation simulation techniques
have their shortcomings. In order to compensate for
these shortcomings, the modern trend is to combine
different methods and approximations. During the
last decade, the combination of atomistic and con­
tinuum approaches became a common approach [92].
Namely, important parameters describing the disloca­
tion behavior, including their mobility and interactions,
are defined from atomistic simulations and then used as
input for continuum approach techniques. In principle,
such a multiscale approach, covering the broad range of
time and length scales, can be used for computational
prediction of overall crystal plasticity behavior from the
underlying physics of dislocation motion.
11.2.3 Dislocations in Silicon:
Dislocation Core Structures
Since the dislocation core was found to have a sig­
nificant effect on crystal plasticity (M.S. Duesbery,
review), much effort has been dedicated to quantitative
analysis of the dislocation core structure and its effects
on the dislocation mobility.
Dislocation core can exist in several metastable modi­
fications, which differ from each other by in-core atomic
bonding topology. The difference between the core
structures manifests itself in the difference of the core
free energies, which, in turn, determine the stability of a
particular core modification. Atomistic simulation tools
are currently the main approach for the investigation
of dislocation core structure. Experiments are usually
unable to provide precise information on the core ener­
gies. However, constantly evolving capabilities of highresolution electron microscopy (HREM) improve the
situation with direct observations of the dislocation struc­
ture [93], thus opening new possibilities for the mutual
verification of computational and experimental data.
For a long time static core properties were analyzed
using semiempirical interatomic potentials (see Ref.
[8]). At the same time a number of semiempirical TB
calculation results of the dislocation core structure were
reported [94]. The emergence of new capabilities for
accurate first-principles electronic structure calculation
CHAPTER 11
allows us to analyze the dislocation core in silicon and
other semiconductors using density functional theory
(see for example, Ref. [95]).
Silicon is an exceptionally “friendly” material for
DFT calculations, because its relatively low plane-wave
cut-off energy allows quite large supercells to be used
for calculations. In combination with a specific property
of dislocations in silicon—that is, narrow dislocation
cores—this allows us to incorporate two dislocations
into a supercell of reasonable size without overlapping
their cores. The resulted DFT total energy is a combi­
nation of core and elastic energies and its partitioning
into these two contributions depends on the choice of
the core cutoff parameter (or core reference radius).
Therefore, comparing calculated core energies of various
metastable core structures, one should be careful to use
the same core cutoff parameter for all considered struc­
tures in order for such comparisons to be meaningful.
As already noted, under moderate stress and tem­
perature conditions the �110� aligned dislocations in
silicon dissociate into Shockley partials connected by
an ISF. For the predominant perfect dislocations of 60°
and screw types, the partials can be of 30° or 90° char­
acter (Figure 11.5), and the dissociation reaction could
be written as
1 / 2[110] � 1/6[121] � 1/6[211]
However, in the case of high strains the dissociation of
edge dislocations into two 60° partials is also observed.
Most of the theoretical studies have concentrated on
the glide set dislocations, which dissociate in a straight­
forward way and on the resulting partial dislocations.
The disagreement between experimental measurements
of dislocations [72, 96–99] and theoretically predicted
dangling bond (unpaired electrons) density led to the
conclusion that purely geometrical description of dislo­
cations as periodic arrays of dangling bonds in the core
is not acceptable. On the basis of the TB calculations of
band energy as a function of core structure, Jones [100,
101] and Marklund [87, 102] concluded that cores of
both 30 and 60° partial dislocations can be partially or
totally reconstructed. Later the core reconstruction was
confirmed by other atomistic calculations that used a
number of different empirical potentials [8, 103–106].
Some examples of the proposed core reconstruc­
tion are presented in Figure 11.6. As one can see in this
figure, the unreconstructed cores of dislocation lines,
which separate the SF from the perfect crystal, contain
dangling bonds. This can result in a total energy of the
partials that is higher than the energy of their perfect
nondissociated counterpart. However, the additional
lattice distortions resulting in the pairing of the dan­
gling bonds (reconstruction) leads to a significant energy
191
PA R T I I
Modeling in MEMS
Fig 11.5 ● (a) Perfect diamond lattice. Two layers of atoms, immediately above (white) and immediately below (dark) the glide-set (111)
plane are shown. Each atom has four bonds, but the fourth bonds are out of the plane and are not shown. Stacking fault can be formed
by dark atoms slipping into adjacent centers of the white triangular lattice in three ways. (b) The core of a 30º partial (unreconstructed),
as an interface between the stacking fault and the perfect lattice. (c) The core of a 90º partial (unreconstructed).
Fig 11.6 ● Reconstructed core structures of partial dislocations in silicon. (a) DP core of 30º partial. (b) SP core of 90º partial. (c) DP core
of 90º partial.
reduction. This model is consistent with the experi­
mental observations, indicating the observation that less
than 3% of the atomic sites in partial dislocation cores
have unpaired electrons [107].
As can be observed in Figure 11.6, the reconstruction
of 90° and 30° partials occurs by formation of dimeric
units oriented across or along the dislocation line,
respectively. As a result, in the case of 30° partial dis­
location the repeat distance along the dislocation core
changes from b � 1/2[108] to 2b. This type of recon­
struction is called double-period (DP) reconstruction.
The reconstruction energy (defined as the energy gain
per unit dislocation length for the transition from the
unreconstructed to the reconstructed configuration) has
been estimated in many theoretical works (Table 11.11).
As follows from the reconstruction energy values pre­
sented in Table 11.11, all the calculations confirm that
DP reconstruction of 30° partial reduces its core energy
quite significantly (by 1.02 eV per dimer [109]). The
semiempirical calculations with Tersoff [82] and EDIP
potentials give the energy values close to that calculated
with DFT approach.
In contrast with 30° partials, 90° partial dislocation
can reconstruct in two different ways (Figure 11.6b, c):
by single-period (SP) and DP reconstructions. In the case
of the SP reconstruction, the repeat distance along the
dislocation is b, but there is no more mirror symmetry
192
Table 11.11 Core reconstruction energy (in eV/B � 3123456) of
3011partials from different calculations. The energy of DP core of
(DP) core of 9012 partial is given relative to that of the SP, E
Potential
Reference
30°
SW
(Bualtov 1995)
0.81
Tersoff
[103]
0.54
0.46
EDIP
[110]
0.45
0.80
TB
[111,112]
[108]
[112]
1.38
0.69
0.69
[113]
~[109]
[109]
[114]
[112]
[115]
0.53
0.52
0.44
DFT
90° SP
90° DP
ESP – 0.21
0.42
0.88
ESP – 0.19
ESP – 0.26
ESP – 0.042
with respect to the plane perpendicular to the dislo­
cation line (Figure. 11.6b). The DP reconstruction is
characterized by the break of both mirror and transla­
tional symmetries (Figure 11.6c). The reconstruction
Mechanical Properties of Silicon Microstructures
(a)
CHAPTER 11
(b)
Fig 11.7 ● Core structures of shuffle-set screw dislocation in silicon. The high-energy core atoms are shown in dark color. (a) Core A
resides in a hexagonal ring. (b) Core B resides at the boundary between two hexagonal rings.
energy calculations for the 90° partial dislocation have
not provided results as consistent as for 30° partials
(Table 11.11). Depending on calculation approach the
SP reconstruction energy varies from 0.42 to 0.88 eV/b
(Table 11.11). However, all the calculations indicate
that SP reconstruction energy is slightly higher than that
for DP. The reported difference between the SP and DP
reconstructions is less sensitive to calculation conditions
and is about 0.22 eV/b, except for one DFT calculation
[115] where this value was estimated to be ~0.04 eV/b,
which would mean the coexistence of these two vari­
ants at the room temperature.
The 60° partials are much less studied than 30° and
90° partials. This is the result of the fact that these par­
tials are formed only as an edge dissociation product,
while the edge dislocation is predominant only in strongly
compressed crystals [116]. The structure of the unrecon­
structed 60° partial dislocation can be considered to consist
of two segments (30° and 90° segments) and involves three
dangling bonds per repeat distance, which are roughly at
an angle of 60° to the dislocation line. Two reconstruction
modes are usually considered to be those leading to mini­
mal cores. The first one implies the reconstruction of two
dangling bonds from neighboring 30° and 90° segments,
leaving one dangling bond per repeat distance uncompen­
sated. The second reconstruction mode leaves two dan­
gling bonds in every second 90° segment, which can be
reconstructed later as in the usual 90° partial.
The shuffle-set dislocations have not been considered
to the same degree as the glide-set ones. However, the
shuffle-set perfect screw dislocations can play the pre­
dominant role in low-temperature deformation. This
is a commonly accepted interpretation of some experi­
ments [8, 117], which demonstrate the change of the
deformation mechanism in silicon with temperature
decrease (T � 450° C), as manifested in the bend­
ing of the yield stress temperature dependence curve.
Another indication of this is also a change in the dislo­
cation microstructure [118].
Two different core structures for the perfect screw
dislocations on the shuffle-set plane in silicon have
been proposed, that is—core A [119] and core B [105]
(Figure 11.7). Core A is centered at the intersection of
two shuffle-set planes, whereas core B is at the inter­
section of a glide-set with a shuffle-set of planes. The
features of the core A and B structures define their
behavior during the low temperature–high stress experi­
ments: While dislocations with core A are likely to be
involved in cross-slip, the dislocations with core B can
dissociate into glide partials.
Indeed, the results of ab initio calculations show that
core B is a metastable configuration whose energy exceeds
the energy of the core A ground state by 0.32–0.38 eV/b
[105, 120]. The earlier, less accurate calculations with
semiempirical SW potential [14] predicted a lower
energy difference of 0.14 eV/b [105]. It has also been
demonstrated that core B is likely to be unstable at finite
temperatures with respect to dissociation into glide par­
tials, whereas core A may be reasonably stable at lower
temperatures and can contribute to plastic response.
11.2.4 Dislocations in Silicon:
Core Defects
The dislocation core can hardly exist as perfect and
defect-free. In reality, secondary point-like defects
are possible in the dislocation core. Moreover, “recon­
struction defects” (RD) are introduced during recon­
struction, such as anti-phase defect (APD), topological
solitons, kinks and soliton-kink complexes. Among all
the known defects the most important core defects are
considered to be kinks, which control the mobility of
dislocations at finite temperatures.
Nowadays the major source of the information about
the structure and energetics of core defects is computer
simulations, whereas experimental evidences are still
scarce and limited by the current HREM resolution.
193
Modeling in MEMS
PA R T I I
(a)
S1
D
A1
A2
(b)
C
Fig 11.8 ● A solitonic defect in a reconstructed 30° partial
dislocation in silicon {111} plane. The dangling bonds are
oriented along the dislocation line in the �011� direction. Two
possible configurations (Al and A2) of the three-coordinated
silicon atoms are possible (after [124]).
So far all the reported theoretical calculations were con­
centrated on core defects in the glide-set partial disloca­
tions, leaving aside the shuffle-set perfect dislocations,
which play an important role in low-temperature defor­
mation. Unfortunately, despite the effort spent, even
for glide-set dislocations the energetics of core defects
remain unclear. This is the main obstacle for the predic­
tive capabilities of dislocation mobility modeling.
(c)
(d)
11.2.4.1 Reconstruction Defects or Solitons
During the process of dislocation core reconstruction
irregularities in the reconstruction pairing of dangling
bonds can be formed. In the case of the 30° partial recon­
struction each of the atoms belonging to the dislocation
line can choose between two neighbors to bond with
(Figure 11.8). As a result, there are two variants of recon­
struction, which are energetically degenerate and related
to each other precisely by the broken-symmetry opera­
tion, namely translation by b. The soliton is a boundary
that separates two perfectly reconstructed domains of
opposite phase and is characterized by an isolated dan­
gling bond carrying atoms in the core.
While the soliton on 30° partials is formed by break­
ing the mirror symmetry along the dislocation line, the
symmetry for 90° partials is broken normally to the dis­
location line. The APD defect on 90° partial has several
modifications: one for SP core and two for DP core,
one of which is related to the translational symmetry,
while another one is related to the mirror symmetry
(Figure 11.9). The “translational” APD of DP core
can be considered to consist of short segments of the
SP core, the energy of which has been calculated to
be ~0.4 eV [121]. Two more RDs have been considered
in [121] (Figure 11.9) using the TB method, but were
found to have higher energy of about 0.65 eV.
194
(e)
Fig 11.9 ● RD in the partial dislocation cores in silicon, indicated
by vertical dashed lines. (a) RDs on 30º partial. (b) RDs on SP 90º
partial. (c) RDs connecting DP 90º partial cores that are related
by translation symmetry. (d) RDs connecting DP 90º partial cores
that are related by mirror symmetry. (e) Combination of RDs in
(f) with interstitial and vacancy. The ground state of the DP core is
four-fold degenerate.
The values calculated using different approaches for
both reconstruction energy and APD formation energy
are compared in Table 11.12. As follows from the table,
the results depend on the potential used for the calcula­
tions. However, EDIP gives the energies in close agree­
ment with ab initio data.
11.2.4.2 Core Vacancies and Interstitials
One of the most powerful experimental techniques for the
defect identification in semiconductors is a combination
Mechanical Properties of Silicon Microstructures
CHAPTER 11
Table 11.12 Reconstruction energy (in eV/bond) and ADP
formation energies (eV) (data from [110])
Table 11.13 Kink formation energies (in eV) in 30 partial
dislocations in silicon (after [74])
Partial type
EDIP
SW
Tersoff
ab initio
Potential
Reference:
LK
SW
[77]
1.2
SW
(Bulatov 1995)
SW
30°
rec
APD
0.45
0.49
0.81
0.82
�0
�0
0.43
90°
rec
APD
0.40
0.65
�0
�0
0.37
0.44
of electron paramagnetic resonance (EPR) with electron
dipole spin resonance (EDSR). This method applied to
silicon samples after plastic deformation has shown several
line centers in the spectrum, three of which were ascribed
to vacancies inside the dislocation core, because they are
not observed for all crystallographically equivalent orienta­
tions [122]. Kinks were excluded, when Lehto and Öberg
demonstrated that these defects are fully reconstructed
and possess only shallow levels [115]. Additional analysis
of the orientation symmetry of the EPR signal and energy
spectrum has shown that the three observed line centers
could be ascribed to different vacancy configurations along
the 30º partial [123, 124]. These three configurations are
believed to be a vacancy with three neighboring atoms
(V3c), vacancy with four neighboring atoms (V4c), and a
linear chain of V3c defects [124]. The annealing experi­
ments show that the EPR signals associated with these
defects disappear at temperatures higher than 800ºC.
Justo et al. (Justo, 2000) via ab initio calculations
showed that due to the positive binding energy of a
vacancy and dislocation, vacancies in silicon tend to
agglomerate in dislocation core. Indeed, while a bulk
vacancy has the formation energy of ~3.6 eV, the energies
of V3c, V4c, and V3c chain are significantly lower, having
values of 0.9 eV, 2.4 eV, and 1.9 eV per vacancy, respec­
tively, that clearly define the driving force for the vacancy
redistribution towards dislocations. Moreover, HREM
observations of the 30º partial dislocations show a density
of core atoms of 0.5–1.5 per core site, suggesting the for­
mation of vacancy and interstitial segments in the core.
In contrast, the same observations of 90ºC partial disloca­
tions show a perfectly reconstructed core structure with
low concentration of vacancy and interstitial defects [75].
11.2.4.3 Kinks
Ideally, dislocations are straight and at zero tempera­
ture occupy the �110� valleys, the low-energy “Peierls
valleys” of the crystal. However, with, for example, the
temperature increase a dislocation can arbitrarily choose
the direction in the glide plane and climb from one
glide plane to another one. Such dislocation consists of
segments lying in neighboring parallel Peierls valleys in
the same glide plane and of segments crossing a Peierls
RK
LC
RC
~0.82
0.82~
1.12
~0.79
[109]
0.98
0.65
1.29
0.79
EDIP
[110]
0.65
0.39
~0.90~ 0.83
TB
[111, 112]
0.35
1.24
0.88
HREM
[93]
0.80
TEM
[126]
0.90
IL
[127]
0.62
2.15
Experiment
Table 11.14 Kink formation and migration energies (in eV) in 90
partial dislocation in silicon (data from [54])
Potential
E eV
Em,eV
Reference
LR/R
LL
RR
LR/R
EDIP
[110]
0.70
0.84
1.24
0.62
Tersoff
[103]
0.12
Tersoff
[77]
0.50
TB
[128]
0.12
1.74.
2.04
1.87
TB
[111,112]
0.12
1.62
DFT
[129]
0.1
1.80
DFT
[130]
0.4
1.09
TEM
[131]
�0.4
�1.2
HREM
[93]
0.74
1.55
Experiment
hill. The dislocation segment where the dislocation line
jumps over the Peierls barrier is called kink [73].
Kinks are the most extensively studied dislocation
core defects, because their nucleation and migration
along the dislocation line are the primary mechanisms
of dislocation motion at finite temperatures [73]. The
data on kink formation energy in 30° and 90° partials
obtained both experimentally and via theoretical cal­
culations are summarized in Tables 11.13 and 11.14,
195
Modeling in MEMS
PA R T I I
respectively. As noted above, computational experi­
ments nowadays give the main contribution to the
understanding of the core defect properties, allowing us,
in particular, to distinguish between particular defect
configurations, which is impossible to do in experi­
ments, where effective kink energies are obtained.
Unfortunately, there is a poor agreement between the
values reported by different groups (see Tables 11.13
and 11.14). This is a consequence of the fact that all
the values have been calculated using different semiem­
pirical potentials and, probably, different calculation
conditions (in particular—different treatment of the
boundary conditions). Unfortunately the most accurate
DFT calculations have not been widely applied to kink
problems so far. Even those that are available produce
results that are sometimes less accurate than semiem­
pirical type calculations [125].
The kinks denoted in Tables 11.13 and 11.14 as
LK and RK are two different orientations of the kink,
namely left (like BC in Figure 11.10) and right (like DE
in Figure 11.10) kinks, respectively. It should be noted
that the atomic configurations of LK and RK are differ­
ent from each other [74]. Other kink types, denoted in
the table as LC and RC, are combinations of LK and RK
with APDs, respectively. It has been found that over­
lap of the kink core and APD results in the significant
decrease of the energy. According to the SW potential
calculations (Bulatov, 1995), the LK 1 APD � LC and
RK 1 APD � RC reactions give the energy gain of 0.51 eV
and 0.84 eV, respectively. However, TB calculations [111]
give different values, namely 0.80 eV and 0.42 eV, where
C
the LC reaction gains more energy than RC. Based on the
SW potential calculations (Bulatov, 1995) it has been sug­
gested that kink reactions with APD defects can affect
the kink migration, increasing or lowering, depending on
the reaction type and its activation barrier.
Taking into account that 90º partials have two com­
peting core reconstructions (SP and DP), a much more
extended family of kink species can be imagined. The
possible kink configurations are presented in Figure 11.11,
where the different types of kinks are labeled according
to their geometric characteristics [111].
For SP core four different types of kinks can be con­
sidered, labeled as LR, RL, LL, and RR in Figure 11.11a,
b. However, according to the TB calculations [111] two
of them, namely LL and RR, are unstable and spontane­
ously dissociate into LR and RL kinks emitting RD.
For DP core of the 90° partial five different species
of RD and eight topologically different species of kinks
have been qualitatively described [109]. However, there
has been little quantitative study of these defects, pro­
viding, at present, no information that could be used for
the prediction of the 90° partial’s motion. Despite that,
some suggestion has been made from the indirect data
indicating the energy reduction due to the kink disso­
ciation [109]. Thus it has been proposed that kink dis­
sociation could make more kinks available for the 90°
partial dislocation motion. Moreover, the existence of
two types of Peierls valleys can also be the reason for
the more pronounced mobility of 90° partials in con­
trast with 30° partial dislocations (Table 11.15).
Unfortunately, nowadays it is very difficult or prac­
tically, impossible to check experimentally the detailed
theoretical predictions. The direct observation of kinks
has been reported using a special HREM technique
[93] that allowed a “plane-on” view of stacking faults
using forbidden reflections. However, even this tech­
nique does not allow the imaging of the detailed atomic
arrangements in the core of kinks and partial disloca­
tions; it provides only information about kinks, spacing.
D
B
E
A
Fig 11.10 ● Schematic representation of kinks on a dislocation line.
(a)
LR
(b)
RR
RL
LL
(c)
(d)
LK
LK1
DP
196
LK2
SP
Fig 11.11 ● Kinks in 90º
partial. (a) Kink pair LR and RL
in a SP 90º partial. (b) Kink pair
RR and LL on (SP) 90º partial.
(c) A kink pair on DP 90º
partial. (d) Dissociation of kinks
shown in (c) into partial kinks
bounding short segments of
SP core (after [74]).
RK
RK1
DP
RK2
SP
DP
Mechanical Properties of Silicon Microstructures
Table 11.15 Kink migration energies (in eV) in 30 partial
dislocations in silicon (based on data from [54])
Potential
Reference
LK
RK
LC
RC
SW
(Bulatov 1995)
0.82
0.74
0.22
1.04
EDIP
[110]
1.46
0.89
TB
[111, 112]
1.53
2.10
HREM
[93]
1.55
TEM
[126]
1.30
IL
[127]
1.58
Experiment
Nevertheless, this information is useful for direct com­
parison with theoretical predictions.
11.2.5 Dislocations in Silicon: Mobility
There are two fundamental measures of the lattice
resistance to the dislocation motion, namely Peierls
stress and Peierls barrier. Both are related to the usually
assumed mechanism of the dislocation transfer from
a Peierls valley to a neighboring one (called Peierls–
Nabarro mechanism [132]), which involves the nuclea­
tion of kink pairs and their subsequent propagation
along the dislocation line until they either recombine
or run away from each other, completing translation
of the whole dislocation. When the stress is vanishing,
the barriers for the kink forward and backward motion
are equal. This balance becomes broken, however,
when the shear stress in the dislocation glide plane is
nonzero. In this case, one of the barriers decreases and
the other increases, leading to the directed dislocation
motion (glide). The condition, when one of the barriers
vanishes completely, implies the reaching of the Peierls
stress. Closely related to the Peierls stress is the Peierls
barrier, which is the energy barrier that a straight dislo­
cation must surmount in order to shift to a neighboring
Peierls valley. The Peierls barrier is defined as energy per
unit length of the dislocation line [72, 73, 96].
In the framework of the Peierls–Nabarro mecha­
nism the dislocation motion is a stochastic sequence of
thermally activated, random kink-pair nucleation and
migration events. Thus the dislocation velocity, V, is
determined by the balance of kink-pair nucleation and
migration rates under stress and can be expressed as [73]
V � νD
⎛ E � Em ⎞⎟
τabh2
⎟⎟
exp ⎜⎜⎜� k
kBT
kBT ⎠⎟
⎝⎜
(11.22)
CHAPTER 11
where νD is the Debye frequency; τ is the resolved
shear stress on the dislocation; a, b, and h are the dis­
location period, Burgers vector value, and kink height,
respectively; and Ek and Em are the kink nucleation and
migration energies, respectively. This model is very suc­
cessful for the description of the dislocation mobility in
silicon and is widely used [74]. Some estimates, both
theoretical and experimental, for Ek and Em for partials
are summarized in Tables 11.13–11.15. When the tem­
perature is high enough, the Peierls barrier can totally
vanish, which means that kink mechanisms play no or
little role. In this case the dislocation mobility is con­
trolled by the viscous friction, which is defined by the
interaction between moving dislocations and phonons
and electrons.
The Peierls stress, as discussed above, is directly
related to the yield stress (i.e., the macroscopic stress
above which the crystal deforms plastically). Indeed,
being defined as the minimum stress for dislocations to
move at zero temperature, the Peierls stress corresponds
to experimental measurements of the yield stress at
vanishingly low temperatures. The yield stress, τly , is, in
turn, temperature dependent and over a wide range of
temperatures (T � 700–1200 K) can be expressed as
⎛ Q ⎟⎞
⎟
τ ly � Cly ε� n exp ⎜⎜⎜
⎜⎝ nkBT ⎟⎟⎠
(11.23)
where Cly and n are temperature independent con­
stants, ε� is the strain rate, and Q is an activation energy
of about 2 eV [72, 96], thus suggesting that plastic
deformation or, in other words, dislocation motion is a
thermally activated process. It should be noted, how­
ever, that beyond this temperature range there is a cer­
tain deviation from the Arrhenian behavior. At higher
temperatures an increase of the activation energy is
observed, which is explained either by the change of
the self-diffusion mechanism [75, 133, 134] or by the
effect of dislocation–dislocation interactions [135]. At
lower temperatures both activation energy and yield
stress become lower than predicted by Equation 11.23.
The core reconstruction has been shown to have a
strong influence on Peierls stress and, hence, on the dis­
location mobility [110]. It is commonly believed now
that the low dislocation mobility in silicon and its brit­
tleness at low temperatures (T � 0.6Tmelt, where Tmelt
is the melting temperature) is due to the high Peierls
stress (tens of GPa) for the glide-set partials [8]. Gally
et al. [136], in particular, suggested that dislocation
nucleation and propagation are insufficient to relieve
the stress concentration at the crack tip, resulting in
the brittle behavior of silicon. Several attempts to cal­
culate the Peierls stress have been performed using both
semiempirical potentials [137] and ab initio [138, 139].
All of them confirmed the high values of the Peierls
197
PA R T I I
Modeling in MEMS
stress for the glide-set partials. Moreover, Justo et al.
[138, 139] have shown a strong relationship between
the strength of partial reconstruction and the experi­
mentally measured activation energy Q of dislocation
mobility.
Using the SW potential, Ren et al. [137] estimated
the Peierls stress of a perfect shuffle-set screw dislo­
cation to be ~5 GPa, but this seems to be an overesti­
mation [74]. Later ab initio calculations of the Peierls
stress for shuffle-set screw dislocation gave the value of
about 3.3 � 0.2 GPa, which agrees much better with
the experimental data on the low temperature shear
stress, which give the value of 3.4 GPa [140]. These
results are also consistent with the low temperature
yield stress measurements, which approach 1 GPa at
300 K [117, 118].
One should remember, however, that the Peierls–
Nabarro mechanism is a simplification that ignores the
fact that dislocations in silicon are dissociated and the
partials can strongly interact with each other and move
together. This is not a problem in the case when, for
instance, due to the large applied stress the partials
behave relatively independent of each other. However,
when the stress is small and the coupling between
partials significantly affects the dislocation mobility,
that, in particular, has been suggested as an explana­
tion of the reported low-stress anomalies in dislocation
mobility [97].
An attempt to take into account the effect of cou­
pling between partials has been undertaken by Möller
[141], who assumed that below some threshold stress
the kink pairs nucleate simultaneously on both par­
tials, making this event rarer than in the model by
Hirth and Lothe. However, this model was not success­
ful in explaining the experimental data and has been
discarded.
As an alternative mechanism for dislocation mobility
in silicon, it has been proposed that point defects rather
than kinks control the lattice resistance to dislocation
motion [142, 143]. In order to explain the low stress
dislocation mobility, an idea of “weak obstacles” was
introduced [72, 96, 144], but that has also been dis­
carded due to the low concentration of extrinsic defects
in silicon [145].
It should be noted, however, that the results pro­
vided by different experiments represent a consider­
able scattering that makes their theoretical explanation
by means of a single theoretical model problematic.
Indeed, a number of measurements for the dislocation
velocity within the same temperature and stress range
using different experimental techniques (such as selec­
tive etching, X-ray topography, and transmission elec­
tron microscopy) have been reported ([86, 97, 131,
146–149], Alexander, 1987) giving absolute values of
the velocities that differ by about a factor of two [150].
198
11.2.6 Dislocations in Silicon: Interaction
with Defects and Impurities
Dislocations and point defects (including both intrinsic
point defects and impurity atoms) can significantly affect
each other’s behavior. On the one hand, dislocations pro­
mote spatial redistribution of point defects in a crystal.
On the other hand, point defects can control various
kinds of activities of dislocations, for example, immo­
bilizing them. This, in turn, can alter the electrical and
optical properties of the material as well as lead to the
mechanical strengthening of the crystal by suppressing
the generation of dislocations on the macroscopic level.
In order to characterize the interaction of point and
extended defects, one has to take into account specific
properties of both the extended defects (such as their
local topology, charge state, anisotropic strain, and elec­
trostatic fields) and point defects. The probability, p, of
the occurrence of a certain dislocation–defect reaction
leading to the formation of a new state, characterized
by the reaction energy gain Ei, depends on temperature
and can be approximately expressed as [151]
1
p�
1�
⎛ E ⎞⎟
1
⎜
i ⎟
exp⎜�
⎜⎜ k T ⎟⎟
C0
⎝ B ⎠
(11.24)
where C0 is the mean atomic fraction of point defects
in the crystal. According to this equation, the com­
bination of sufficiently high concentration of defects
and a noticeable value of the dislocation–defect inter­
action energy can lead to the point defect concentra­
tion enrichment around a dislocation, which is called
Cottrell atmosphere. The temperature dependencies of
the dislocation–defect reaction probability, as predicted
by Equation 11.24, are shown in Figure 11.12 for dif­
ferent point defect concentrations. As follows from this
figure, in order for the defects present in the crystal at
concentration of, e.g., 10�6 to be gettered at the dislo­
cations at temperatures above 900 K, their interaction
energy should exceed 1.5 eV.
The determination of the defect–dislocation interac­
tion energy requires accurate microscopic calculations
that take into consideration the features of the disloca­
tion atomic structure. There exist a number of studies
on the interaction of intrinsic point defects and different
impurities with partial dislocations in silicon. The calcu­
lation techniques used range from simple valence force
field potentials to ab initio density functional meth­
ods. Some calculated values of the vacancy–dislocation
binding energies are summarized in Table 11.16. As seen
in this table, these energies markedly scatter, showing
no agreement even concerning the relation between
binding strengths to 30° and 90° partials. While the
Mechanical Properties of Silicon Microstructures
CHAPTER 11
1.2
Ei = 0.5 eV
1.0
p
0.8
A
B
C
D
E
3
0.6
4
0.4
7
6
5
8
0.2
Fig 11.13 ● Atomic configuration of a (111) glide plane with a 30°
partial dislocation lying along (110) direction. The black circles
represent the atoms of the dislocation core (after [139]).
0.0
C0 = 10−6
1.0
2.0
p
0.8
1.5
0.6
0.4
1.0
0.2
0.5
0.2
0
200
400
600
800 1000 1200 1400
Temperature (K)
Fig 11.12 ● (a) The temperature dependence of p for the inter­
action energy of 0.5 eV and different impurity atom concentrations
10�n atom�1, where n � 3–8. (b) The temperature dependence
of the probability p of the occurrence of the dislocation–impurity
atom reaction leading to the formation of Cottrell atmosphere
for the impurity concentration of 1 ppma and several interaction
energies.
Table 11.16 Binding energies of vacancies and different glide-set
partials
Potential
Reference
30°
90°
SW
[77]
2.62
3.0
Tersoff
[77]
2.67
1.69
Kaxiras-Pandey
[329]
0.58
0.94
LCAO
[154]
1.9
DFT
[152]
0.9
2.0
ab initio cluster method calculation by Lehto and Öberg
[152] gave the difference between 90° and 30° partials
of about 1.1 eV, the semiempirical potential calculations
vary from �0.98 to 0.398 eV, depending on the poten­
tial used. However, all the theoretical works agree on
the positive binding energies between vacancies and
dislocations in silicon, implying that vacancies in sili­
con should be captured by dislocation cores. This effect
is indeed confirmed experimentally, as discussed in
Section 11.2.4 where the core defects are considered.
It should be remembered, however, that no calculations
did consider so far the possible effects of different
charge states of the defects and dislocations, which can
probably have a significant effect on all the discussed
values. The information about self-interstitial interac­
tions with dislocations in silicon is scarcely presented in
the literature. The work by Justo et al. [139] identified,
in particular, three possible sites for an interstitial in the
core of a 30° glide partial dislocation: I1-bridging atoms
in the same reconstructed dimer (interstitial between
atoms A and B in Figure 11.13), I2-bridging atoms of
different reconstructed dimers (between atoms B and C
in Figure 11.13), and I3-sharing an APD site (atomic
site E in Figure 11.13). Their ab initio supercell calcula­
tions show that the energy of the interstitial atom in the
dislocation core is about 1 eV below that of the lowest
energy interstitial in the silicon bulk [153]. The energy
of the interstitial in the shuffle-set dislocation has been
estimated to be 1.59 eV, that is lower than for the glideset dislocation case [139]. Combining the ab initio cal­
culations with Monte-Carlo and MD simulations, Justo
et al. [139] showed that even though the concentration
of vacancies and self-interstitials in the dislocation cores
is considerably larger than in the bulk, it is still too small
to allow the formation of shuffle dislocation segments.
Similar to intrinsic point defects, some impurities also
strongly interact with dislocations with a positive interac­
tion energy (see Table 11.17). Sumino [155] has proposed
two mechanisms of impurity gettering at high tempera­
tures. In the first one, when impurities are supersaturated,
dislocations act as preferential sites for precipitation. The
second mechanism involves reactions incorporating an
impurity atom in the dislocation core. Such precipitates
and/or defect complexes in the dislocation core can serve
as pinning centers that immobilize dislocations.
Impurity atoms that are gettered by a dislocation are
usually not distributed continuously but discretely along
the dislocation line, as, for example, in silicon doped by
[151]. Assuming that the interaction between the dislo­
cation and a pinning particle is of a short-range nature,
the dislocation release rate Γ from the pinning particles
under the action of stress τ in the temperature range,
199
PA R T I I
Modeling in MEMS
Table 11.17 The interaction energies of neutral impurities on the
90 partial. B, N, P, As are substitutional, while O is a bond-centered
impurity
Impurity
Reaction
Off-core
O
O–O
O2–O2
2O–O2
0.3 [335]
B
P
In core
Solitonic
state
2.5 [156]
4.5 [156]
High
purity Si
0.4 [157]
0.9 [157]
0.6 [157]
2.5 [157]
P–P
0.4 [157]
0 [158]
1.1 [157]
1.7 [157]
2.3 [158]
2.3 [157]
N
N–N
N2–N2
2N–N2
0.6 [157]
1.5 [157]
2.6 [157]
0.6 [157]
3.4 [157]
As
As–As
As2–As2
2As–As2
0.7 [157]
0.6 [157]
2.1 [157]
0.7 [157]
2.5 [157]
where the unpinned part of the dislocation is easily
mobile, can be written as
⎡ E* � τb2 ⎤
⎥
Γ � LN*ν * exp ⎢⎢�
⎥
*
⎣⎢ N kBT ⎦⎥
(11.25)
where L is the length of the dislocation, N* is the parti­
cle line density, E* is the interaction energy, ν* is the fre­
quency of the dislocation vibration, and b is the Burgers
vector of the dislocation. The release stress is expressed as
⎡
LN*ν * ⎤⎥ 2
τ R � N* ⎢⎢ E* � kBT ln
b
Γ ⎥⎥⎦
⎢⎣
(11.26)
The process of dislocation release from impurity atoms/
complexes governs the dislocation mobility in the
low stress range. Indeed, it has been experimentally
observed that in the low-stress range in crystals doped
with a certain kind of impurity the dislocation veloci­
ties are zero and increase rapidly toward those found in
undoped crystal with increasing stress. In contrast, in
the high-stress range the dislocation mobility is limited
by the effects of impurities dispersed within the crystal.
200
Screw
Dopant
60° partials
dislocations
concentration,
cm�3
υ0, m/s Q, eV υ0, m/s Q, eV
1.2 [335]
B–B
B2–B2
2B–B2
P2–P2
2P–P2
Table 11.18 Magnitudes of Q and υ0 for different dislocation types
in undoped and doped silicon under a shear stress of 20 MPa
(after [151])
1.0 � 104 2.20
3.5 � 104 2.35
P
6.2 � 1018
3.3 � 101 1.66
7.0 � 101 1.74
P
1.5 � 1019
1.7 � 101 1.58
9.5
1.57
Only certain types of impurity atoms are found to
have a strong effect on dislocation mobility. So, in the
high strain range the light impurities, such as C, O,
and N, which are electrically inactive, do not affect
the motion of 60° and screw dislocations. The meas­
ured dislocation velocities in crystals doped with these
impurities have been the same as in high-purity silicon
under the same stress [151]. In contrast, donor impuri­
ties, such as P, As, and Sb, enhance the velocity of both
60° and screw dislocations under high stress [97, 146,
149, 159], decreasing the magnitudes of both activa­
tion energy Q and prefactor υ0 (Table 11.18). Acceptor
impurities, such as B, affect the dislocation velocity very
little (Table 11.18). The magnitudes of Q for disloca­
tions in B-doped silicon are only slightly smaller than in
high purity silicon.
However, in situ X-ray topography experiments
[149, 160] show that such impurity atoms as nitrogen,
oxygen, phosphorus, and boron tend to immobilize dis­
locations at stresses below some critical value of ~3–
5 MPa, depending on impurity type and concentration.
For example, in O-doped silicon the dislocation veloc­
ity decreases more rapidly than in the undoped silicon
when the stress is close to a critical stress below which
dislocations become immobile, while dislocation mor­
phology changes from the well-defined �110� straight
lines to irregular ones [149].
It should be remembered that all the conclusions
about the impurity effects on dislocation mobility should
be taken with a certain caution, because it is always dif­
ficult to ensure that there is only one type of impurity
in the sample. Moreover, when constructing models
describing the impurity effect on dislocation mobility,
one should take into account the charge effect on the
dislocation velocity. So Patel et al. [161] have proposed
a model in which dislocation velocity is proportional
to line charge of the dislocation, in order to explain
the enhancement of dislocation velocity due to dop­
ing with donor impurities observed in silicon, assuming
Mechanical Properties of Silicon Microstructures
that the dislocation causes an acceptor level within
the band gap. However, on the basis of the model by
Haasen [162], called the dislocation charge model, one
could argue that a charged dislocation is unstable against
the double kink formation, which turned out to be also
incorrect to explain the experimental observations.
Later Hirsch [116] proposed a model in which the
dislocation velocity is proportional to the kink density
along it. According to this model, the density of kinks is
higher in a donor-doped silicon than in an intrinsic crys­
tal, if kinks provide acceptor levels at the lower part of
the band gap. The same holds for acceptor-doped sili­
con, when kinks provide donor levels at the upper part
of the band gap. In these cases, the dislocation velocity
is enhanced in comparison with the intrinsic case.
While the pinning effect of impurity atoms is expected,
the effect of intrinsic point defects on dislocation mobil­
ity in pure silicon remains unclear. It was found that
climbing 60° dislocations may become unstable during
motion (i.e., some segments move faster than others and
the dislocation line becomes ragged) [163]. It was postu­
lated that this is due to vacancy absorption or emission
by a dislocation, which in turn modifies the dislocation
core. However, detailed atomistic mechanism is lacking.
Double cross-slip of screw dislocations also has been pro­
posed as a mechanism for dislocation point defect interac­
tion [142]. The motion of screw dislocations after double
cross-slip requires jog dragging, which depends on the rate
of emission or absorption of point defects. Interaction
with intrinsic point defect and climb also seem to be nec­
essary to explain the forward–backward asymmetry of
dislocation mobility observed in [164].
11.3 Physical Mechanisms of
Fracture in Silicon
11.3.1 General Remarks
Solids are typically classified as brittle or ductile,
according to how they respond to external loads. Silicon
belongs to the class of intrinsically brittle solids. In
practice, though silicon single crystal manifests a tensile
yield strength (6.9 � l0l0 dyne/cm2 or l06 psi), which
is three times higher than that for stainless-steel wires
[165, 166], it can yield by fracturing at room tempera­
ture, while metals usually yield by deforming inelasti­
cally. In order to explain specific features of the fracture
processes a number of factors, which span many dif­
ferent length scales, must be properly accounted for.
Firstly, the fracture initiation and propagation are dic­
tated by the microstructure of materials, which, in turn,
is controlled by processes occurring at a broad range of
scales from atomic to mesoscale. Secondly, the intensity
CHAPTER 11
of stress concentration at the crack tip is mostly deter­
mined by the macroscopic parameters. Thus a number
of factors, such as crystallographic orientation and
geometry, the number and size of surface, edge, and
bulk imperfections, and the stresses induced and accu­
mulated during growth, polishing, and subsequent
processing are of great concern for the resulting strength
of a mechanical component or device.
Though monocrystalline silicon is known to be a brit­
tle material, at temperatures above 0.5Tm (Tm is the
melting temperature) limited plasticity under complex
loading, such as indentation [167, 168], scratching [169–
171], turning [172–174], grinding, and polishing [175–
177], is observed. This change of the fracture mode is
called “ductile-to-brittle transition” (DBT) and has a very
sharp character for silicon [178–181], where it often
reflects the phase transformation of cubic diamond phase
to amorphous or metastable crystalline R8/BC8 phases.
The fundamental features lying in the basis of the dif­
ferences between brittle and ductile modes are of atomic
nature. In the brittle mode the crack tip remains atomi­
cally sharp [182, 183], while the stress concentration at
the tip causes bond-breaking and cleavage. In contrast to
this, in the case of the ductile fracture the stress at the
crack tip is relieved by generation and motion of dislo­
cations, which cause the crack tip blunting and prevent
the bond from breaking. In other words, the dominance
of the brittle or ductile fracture mode is defined by the
preferable mechanism of the stress concentration relief
at the crack tip, which depends, in turn, on the relative
ease of (i) dislocation generation, (ii) dislocation motion,
and (iii) dislocation accumulation at and near the crack
tip. In silicon, which has very sluggish dislocation mobil­
ity, the transition of fracture from brittle-to-ductile
mode is limited by the dislocation motion away from
the crack tip rather than by nucleation at it.
Given the modern trend for the reduction in size of
critical components of advanced electrical and mechani­
cal devices, a clear understanding of the brittle and
ductile fracture mechanisms becomes increasingly
important. The classical theory of the brittle fracture,
as proposed in the 1920s by Griffith [184], is based on
continuum thermodynamics. According to this theory, a
static crack can be considered to be a reversible thermo­
dynamic system. The central concept of the theory is
that crack growth is energetically favorable if the poten­
tial energy release rate (during an incremental crack
growth), G, equals (or exceeds) the energy absorbed by
the fracture process, GIc, which leads to the so-called
Griffith criterion for the crack instability,
G � GIc
In the case of an ideally brittle material, the energy
absorbed by the fracture process is the same as the
201
PA R T I I
Modeling in MEMS
Table 11.19 Surface free energies of silicon single crystal
planes [119]
Fig 11.14 ● The schematic representation of the low index planes
{001}, {110} and {111} in silicon.
energy required to create the new crack surfaces.
Correspondingly, crack extension takes place when the
crack is supplied with a driving force larger than the
specific energy 2γ (where γ is a free surface energy).
The Griffith criterion of a balance between the crack
propagation driving force and the material resistance
against fracture provides a necessary condition for
unstable fracture onset, but cannot explain why and how
fracture proceeds. The details of a fracture mechanism are
the subject of an atomistic consideration. Nevertheless,
the Griffith criterion leads to an important conclusion that
a brittle crack in a crystal could be expected to choose a
cleavage plane with low surface energy and to propagate
on this plane with equal ease in all directions.
Indeed, it is well known that while the amorphous
and polycrystalline brittle solids behave isotropically,
brittle single crystals manifest mostly anisotropic behav­
ior. In the latter case, the combined anisotropy of sur­
face energy, elastic constants, and plastic deformation
leads to the crack path dependence on the variations
of the elastic energy release rate and the surface energy
with orientation [185]. This results in the existence of
a family of favored crystallographic planes along which
the crystal can potentially cleave. In general, these
planes are those that have the highest atomic density
and maximal interplane separation. In particular, for the
silicon single crystal the fracture anisotropy has been
reported with reference to the low index plane, such
as {001}, {110}, and {111} shown in Figure 11.14 (see
for example Ref. [185]); these low index planes, accord­
ing to the atomic bonding analysis [186], have the sur­
face free energies, γ, as specified in Table 11.19. This,
in turn, leads to the dependence of the fracture tough­
ness, whose measure is the critical stress intensity factor
KIc on the crystallographic orientation. The investigation
of the effect of crystallographic orientation on fracture
toughness and the fracture path of silicon single crystal
using Vickers microhardness indentation tests [187] has
shown that the fracture toughness variation follows the
202
Crystal
plane
γ, J/m2 Crystal
plane
γ, J/m2
Crystal
plane
γ, J/m2
(100)
1.99
(110)
1.41
(111)
1.15
(210)
1.78
(310)
1.89
(410)
1.94
(211)
1.63
(311)
1.80
(411)
1.94
(221)
2.00
(331)
1.72
(320)
1.80
(322)
1.65
(433)
1.45
(522)
1.46
symmetry of the indentation axis with no distinct cor­
relation with the elastic constants. On the basis of these
observations Ebrahim and Kalwani [187] suggested
that the fracture path and toughness are significantly
affected by the inclination angle of cleavage planes rela­
tive to the indent plane (Figure 11.15). The following
relationship was proposed in [188] for the estimation of
the fracture toughness:
�
3
2
1
KIc � 0.129(c/a ) 2 (ϕ E[hkl] /H)5 ( Ha 2 /ϕ )
where c is the crack length, a is the indent size, ϕ is a
plastic constraint factor (~3), E is the Young’s modu­
lus along the [hkl] direction, and (hkl) is the “indented”
fracture plane. It should be noted that this equation can
be applied to median cracks with c/a � 2.0.
The obvious anisotropy in fracture toughness has
been shown also by many other experiments (see Table
11.20, which summarizes the estimated values of frac­
ture toughness for different fracture planes). Thus,
Chen and Leipold [189] measured the fracture tough­
ness of single-crystal silicon using the controlled surface
fracture method, and reported the values of 0.82, 0.90
and 0.95 Mpa m1/2 for the {111}, {110} and {100} ori­
entations, respectively (Table 11.20). Later, Li et al.
[190] used a uniaxial tensile test with single-edge­
notched tension specimen (Figure 11.16) and the fol­
lowing formula to estimate KIc as a function of fracture
tensile stress, σf, notch length a, and the geometry of
the specimen:
KIc � Yσ f a
where Y is a factor related to crack configuration as
Y � 1.99 � 0.41λ � 18.70λ2 � 38.48λ3 � 53.85λ 4
λ � a/W
where W is the width of the specimen, as shown in
Figure 11.16. In contrast to the experimental techniques
Mechanical Properties of Silicon Microstructures
(a)
1.4
(b)
CHAPTER 11
(c)
(111)
KIC(MPA m1/2)
(001)
1.2
(111)
(001)
(110)
(110)
(112)
1.0
(112)
(112)
(010) (110)
0.8
(110)
(011)
(110)
(100)
(211) (112)
(121)
(101)
0.6
0
30
60
90
120 150 180
Orientation angle
0
30
60
90
120 150 180
0
30
Orientation angle
60
90
120 150 180
Orientation angle
Fig 11.15 ● The critical stress intensity factor, KIc, versus orientation for the (a) (110), (b) (001), and (c) (1 11) indent plane measured in
Vickers microhardness indentation tests.
Source: Data from [187].
Table 11.20 The fracture toughness values for the {110}, {100}, and (111) fracture planes (data from
[187])
Method
KIc, MPa m½
[193]
Double cantilever beam
0.71
Fitzgerald (2000)
Double cantilever beam
0.96–1.65
Reference
Indent plane
{110} Fracture plane
[194]
{100}
{110}
Indentation/four-point bend
1.19
1.05
[195]
{100}
Indentation/four-point bend
0.90
[196]
{110}
{100}
{111}
{100}
Vickers indentation fracture
1.18
1.07
1.14
1.12
{110}
{100}
{111}
Vickers indentation fracture
0.83
1.01
0.81
Uniaxial tensile test
1.00
Double cantilever beam
0.75
[187]
[190]
Indentation/four-point bend
{100} Fracture plane
[193]
[195]
{100}
Indentation/four-point bend
0.95
[196]
{100}
{110}
{110}
Indentation/four-point bend
1.13
0.82
1.15
{110}
{100}
Vickers indentation fracture
1.25
0.86
Uniaxial tensile test
2.00
[187]
[190]
Vickers indentation fracture
(Continued )
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Modeling in MEMS
Table 11.20 Continued
Method
KIc, MPa m½
[197]
Double cantilever beam
0.62
[193]
Double cantilever beam
0.617
Indentation/four-point bend
0.82
Notched/four-point bend
1.34–2.85
Reference
Indent plane
{111} fracture plane
[195]
{112}
[198]
[181]
{110}
Double cantilever beam
0.93
[196]
{110}
Indentation/four-point bend
1.18
[187]
{110}
{110}
Vickers indentation fracture
Vickers indentation fracture
1.14
1.22
below cR, and the dynamic fracture energy, (υ), can be
expressed as
B
σ
W
σ
a
L/2
L/2
Fig 11.16 ● Single-edge notched tension specimen model
(after [190]).
used in [189, 191, 192], which are performed with
a bending mode that applied nonuniform stress, the
uniaxial tensile test is the most direct measurement
method for mechanical properties of MEMS devices.
Nonetheless, this experiment completely confirmed the
anisotropy of fracture toughness in microscale singlecrystal silicon observed earlier. Moreover, Li et al. [190]
also demonstrated an anisotropy of the fracture path in
single-crystal silicon, where cracks propagate predomi­
nantly on {111} and {110} low index planes. At the
same time they have shown that fracture paths never
occur on the (001) cleavage plane.
For the crack propagation stage, Freund [7] within
the continuum mechanical considerations proposed
the criterion for a crack moving at a temporal velocity.
According to this criterion the crack velocity asymp­
totically reaches an upper bound that is equal to the
Rayleigh wave velocity cR, the velocity of acoustic
surface waves. The continuum mechanical approach,
however, implies the consideration of only the specific
case of a crack propagating along a straight path [7].
In this case, a straight crack propagating at a velocity υ
204
⎛
ν ⎞
Γ(ν ) � G(l,σ)⎜⎜⎜1 � ⎟⎟⎟
⎜⎝
cR ⎟⎠
All the known experimental and numerical studies show
that the crack velocity in silicon never attains cR and lies
within the range of (0.7–0.9)cR [199–201]. This is inde­
pendent of the strain energy release rate, where a very
high driving force leads to a path instability which splits
the initially continuous crack front and results in the
propagation of multiple cracks [199].
Unfortunately, both Griffith’s and Freund’s crite­
ria are insufficient to predict the cleavage propagation
plane. In reality, cleavage is related not only to a certain
plane, but to both the cleavage plane and the cleavage
direction. Indeed, the fracture process at the atomistic
level can be described as a sequence of single stretchto-rupture and relaxation events with associated energy
barriers [183, 202–206]. Since the atomic distribution
in many cleavage planes is different for different direc­
tions, the energy barriers are different, too. This phe­
nomenon was called “molecular crack arrest” or “lattice
barrier” and believed to be the source of directional ani­
sotropy, previously discussed.
Thus, as it was already postulated, the nature of the
fracture process is ultimately determined by events on
the atomic scale. Consequently, the fracture characteri­
zation requires atomic-scale characterization tools. Even
though the growing ability to fabricate and mechanically
test high-quality microscale and nanoscale specimens
leads to the convergence of computational tools and
experimental measurements of mechanical properties to
Mechanical Properties of Silicon Microstructures
the same length scale, the atomistic computer simula­
tion at present remains the main atomistic scale tool for
the fundamental characteristics of the fracture behav­
ior. Understanding of these processes at the atomistic
level connected with the knowledge of the macroscopic
behavior of real materials could provide a new level of
control in the design of modern applications.
11.3.2 Simulation Approaches Applied
to the Fracture
From the atomistic modeling point of view there exist
several fundamental open questions, such as (i) how pre­
dictive atomistic simulations of the fracture are and (ii)
would it be possible to develop a practical tool for engi­
neers based on atomistic considerations? One thing that
can be safely said is that atomistic modeling will play an
increasingly important role in the next decades, espe­
cially as a part of the multiscale methods, where con­
tinuum methods will incorporate atomistic information.
Many atomistic-based studies have been conducted
for cracked or notched specimens to investigate fracture
behavior (see, for example, Refs. [200, 207–222]). The
first atomistic studies of fracture were performed in the
early 1970s by Thomson and coworkers [204]. In their
simulations they used the so-called “lattice theory”,
which exploits the one- or two-dimensional lattice
model, where atoms at the lattice sites are connected
to nearest neighbors with Hooke’s springs. On the basis
of these calculations, Thomson et al. [204] introduced
the “lattice-trapping” effect, which means the inability
of a crack to advance/heal until loads somewhat larger/
smaller than the Griffith load are reached. Later in the
1980s Leonid Slepyan [223] proposed a completely
analytically solvable strip lattice model, in which atoms
remain associated with particular points on a lattice, for
the study of the dynamic cracks. This model answered
four conditions: (1) for moderate strains, dynamic cracks
are attracted to steady states; (2) at steady state, there
is an intimate connection between the speed of the
crack and the wave properties of the medium; (3)
there is a minimum velocity below which a crack will
not propagate; (4) the crack becomes unstable when
the fracture energy reaches some threshold. The lat­
ter property concerning crack instability reflects the
inability of cracks to reach the Rayleigh wave that is
well-established experimentally for silicon [199–201].
For example, Marder and Gross [201] used the Slepyan
technique to calculate a velocity gap and transverse
instability during dynamic crack propagation.
Unfortunately, in reality fracture phenomena are diffi­
cult to handle in an analytically tractable way. First of all,
because there exists no two-dimensional material with
snapping Hooke springs between nearest neighbor atoms,
CHAPTER 11
taking into consideration three-dimensionality and a real
interatomic interaction is a must. This, together with
the fact that a large number of atoms are driven far from
equilibrium when a crack propagates, bifurcating and
changing direction, makes the real dynamic fracture ana­
lytically intractable. Thus it requires more realistic largescale atomistic simulations with an adequate description
of interatomic interactions.
Atomistic studies are often associated with MD that
is potentially an important part of multiscale methods
describing very complex fracture processes. Indeed, MD
analysis has been very actively exploited for the inves­
tigation, in particular, of dislocation nucleation [156,
218, 219, 224–226] and crack propagation [218, 219,
224, 227]. For single-crystal silicon, MD simulation was
carried out for evaluation of deformation and fracture
behavior [36, 205, 228–233]. The critical point of these
studies is the accuracy in treatment of the atomic inter­
actions as required for a proper description of fracture.
Atomistic modeling of cracks is a rather complicated
problem because it requires a correct description of both
the long-range elastic interactions and the short-range
chemical interactions. This means that one has to use
a large atomistic model or embed the atomistic region
into a flexible surrounding. Thus one should find a rea­
sonable compromise between the accuracy of the atomic
interaction treatment and time expenses in force calcu­
lations. For a long time fracture has been studied using
empirical interaction models (see for example, Refs.
[209–211, 222, 228]). However, the obtained results
have been found to be interatomic potential-dependent
and do not always agree with experiments even quali­
tatively. So, the first attempts to model fracture
in silicon were done using the classical Tersoff and
Stillinger–Weber [14]) potentials. Later on, EDIP
potential [234] was developed and used. However, all
these potentials failed due to an incorrect description
of the bond-breaking process [223]. For example, even
though SW potential properly describes elastic prop­
erties of silicon and captures well the nonlinear phys­
ics involved in heating and melting, it does not give a
fracture along the experimentally preferred fracture
planes (111) and (110) [223]. Furthermore, Holland
and Marder [223] and later Kang and Cai [32] showed
that at low or moderate strains cracks propagated
in a ductile manner due to the large lattice trapping
(Table 11.21), when two dislocations open up at the
crack tip, blunting it and preventing its propagation.
At the same time it has been proven experimentally
that silicon manifests brittle behavior and atomically
sharp crack tip for fracture along (111) [183, 235].
At very high strains, the crack tip region melts [223].
Furthermore, SW potential simulations evidence for
fracture along (100), that is contradictory to the experi­
mental observations [190] indicating additional potential
205
PA R T I I
Modeling in MEMS
Table 11.21 Fracture strength and Young’s moduli of silicon calculated using different interatomic
potentials. Young’s moduli presented are for nanowires (NW) at T � 300 K and bulk silicon at zero
temperature (in GPa)
Potential
Fracture
strength
NW Young’s Bulk Young’s
modulus
modulus
Fracture
behavior
Reference
SW
14.6
123
138
ductile
[32]
Tersoff
26.3
128
138
ductile
[32]
Lenosky
10.2
102
151
ductile
[32]
SWmod
22.7
165
161
brittle
[32]
Baskes
13.2
139
164
brittle
[32]
SW
-
--
114
ductile
[223]
SWmod
-
--
172
brittle
[223]
SW
-
--
151
ductile
[223]
SWmod
-
--
201
brittle
[223]
�110� direction
�100� direction
�111� direction
shortcomings. In order to make cracks in silicon behave
in a brittle manner along (111) and (110), the SW
potential was modified (SWmod in Table 11.21) in a
way that increased the restoring forces between pairs
of bonds. However, this modification leads to the rise
of the melting temperature up to 3500 K (the experi­
mental Tm � 1685 K) and the Young’s modulus also gets
shifted (see Table 11.21).
Despite the fact that EDIP potential [15] is believed
to be much more sophisticated for silicon, it reproduces
dynamic fracture even more poorly than SW does the
crack tip behavior.
Baskes and coworkers developed an MEAM poten­
tial [36, 229], which was used for simulation of a crack
motion in silicon [222]. This MEAM potential was also
used later by Bailey et al. [228] to investigate a critical
value of the stress intensity factor for the crack initiation
of various crystal orientations and notch shapes. MEAM
potential reproduces well the brittle character of the frac­
ture in silicon (Table 11.21). However, it does not succeed
in describing silicon atom interaction with impurities,
such as oxygen, for example. Thus, the most sophisticated
description of the interatomic interactions for the simula­
tion of the dynamics of materials fracture is expected to
be given by accurate quantum mechanical formulations.
This point has been demonstrated by Gumbsch and cow­
orkers [202, 205, 232, 236], which analyzed the cleavage
206
fracture processes by ab initio calculations. They showed,
in particular, that the bond breaking processes at crack tip
are dependent on the fracture planes, a phenomenon that
is well documented experimentally, though it cannot be
well reproduced by semiempirical calculations.
Though classical mechanics may be inadequate for
describing the most fundamental aspects of fracture
[237], the quantum mechanical approaches also have
their own shortcomings. First of all, these methods are
very time consuming and require the use of powerful
computer facilities, especially, taking into account that
for an adequate crack simulation the use of large com­
putational cells is a must. Secondly, the choice of the
pseudopotential approximation should be done carefully.
For example, Pérez and Gumbsch [202, 205, 232, 236]
used the approximation, which precludes relaxation of
core electron states. However, in the case when atomic
separations undergo the large changes characteristic
for fracture, the validity of this approximation needs
to be accurately verified. A few more ab initio calcu­
lations have addressed the investigation of the fracture
features. Thus, Be’ery et al. [238] demonstrated that
cracks propagate at very low velocities under control­
led conditions in silicon. Later the same group studying
the crack deflection from the (110) to the (111) cleav­
age plane in single-crystal silicon as a function of crack
tip velocity explained this as evidence of phenomena
Mechanical Properties of Silicon Microstructures
associated with atomistic irreversible energy dissipation
mechanisms [239]. Shilo et al. [240], using a combi­
nation of experimental and theoretical ab initio tools,
suggested an importance of a crack interaction with
microstructural defects (dislocations) and ramifications
for the stability of the crack front.
A number of attempts to incorporate the atomistic
data into the continuum methods have been under­
taken. The most widespread method is to divide the
simulation cell into few regions that are treated on dif­
ferent scales depending on the distance from the crack
tip. Some of these multiscale methods, such as a vir­
tual internal bond (VIB) [241–244] and FEAt [245],
treat the crack tip region with MD, whereas the elastic
medium around the crack is described by randomized
cohesive interactions between material particles and
finite elements. Other methods are the quasi-continuum
method [246] and the MAAD method [210, 211]. The
latter method couples quantum mechanical description
of the crack tip region with empirical potentials used
for the outer region.
11.3.3 Lattice Trapping and Cleavage
Anisotropy in Silicon
As already discussed in Section 11.2.1, silicon has two
principal cleavage planes: {111} planes, usually the easy
cleavage planes, and {110} planes [179, 190, 247].
Measurements have shown that {110} planes have a
slightly lower surface energy, that is, ~2.3 J/m2, than
{111} planes, ~2.7 J/m2. The theoretical calculations
significantly underestimate these values. For example,
the fracture toughness calculated using atomic bonding
analysis [186] gave the values of 1.41 J/m2 and 1.15 J/m2
for {110} and {111}, respectively. Even the most accu­
rate density functional theory-based quantum mechani­
cal methods give values that are closer to those obtained
from the atomic bonding analysis than to the experi­
mental data (~1.73 J/m2 for {110} and ~1.44 J/m2
for {111}) [202, 205].
For both cleavage planes the propagation direction
anisotropy is observed. This anisotropy manifests itself
in a preferential crack propagation direction, that is,
the �110� direction for both {110} and {111} planes
[179, 247]. The cleavage on the {110} plane demon­
strates a much more pronounced propagation anisotropy
than on the {111} plane, where it is minimal.
According to the Griffith theory [248], a perfectly
brittle crack in a crystal is expected to choose a cleavage
plane with low surface energy and to propagate on this
plane with equal ease in all directions. However, from
the atomistic point of view the situation is somewhat dif­
ferent. Thomson et al. [204] and Sinclair et al. [203])
in the 1970s introduced the so-called lattice trapping
CHAPTER 11
effect, which causes the crack to remain stable and not
to propagate until the load is less than the Griffith load.
Later the semiempirical MD calculations ([245], Riedle,
1996) showed that lattice trapping may also depend on
the direction in which the crack tip bonds are broken and
may therefore be different for crack propagation along
different crystallographic directions on one cleavage
plane. This has been confirmed and extended recently
by ab initio calculations, where the anisotropy in frac­
ture behavior with respect to the propagation direction
on {110} plane was also explained as a consequence of
a difference in lattice trapping for the different propa­
gation directions [202, 205]. Pérez and Gumbsch [202,
205] have shown, in particular, that crack propagation in
the �110� direction, which is preferable according to
the experimental observations [179, 247], takes place via
continuous opening of the bonds at the crack tip and leads
to a relatively small lattice trapping. In contrast, a crack
driven in the �001� direction on the {110} plane mani­
fests a discontinuous bond breaking, leading to a larger
lattice trapping range [202, 205]. Moreover, attempts to
achieve propagation in the �001� direction, perpendicu­
lar to the preferred direction, have always resulted in the
deflection of the crack plane onto the {111} or {112}
planes [202], in full agreement with the experimental
observations made by Cramer et al. [199]. The transition
from the {110} to the {111} cleavage plane as a func­
tion of the load-to-fracture has lately also been observed
by Muhlstein et al. [249, 250] in fatigue cracks in singlecrystal silicon MEMS specimens. The destabilization of
the {110} crack propagation in the �001� direction
against deflection onto an inclined {111} cleavage plane
was interpreted as being a result of the high molecular
crack arrest as predicted for the {110}– �001� system
by ab initio calculations [199, 202].
11.3.4 Dynamic Crack Propagation
At some scale, any fracture is dynamic. For a crack that
is already propagating (after initiation), we may say that
dynamic effects are important when the crack tip speed
is small compared with the stress wave velocities [237].
But even when the crack at the macroscopic scale
advances quasi-statically, at the atomic scale the inertia
of individual atoms must be accounted for in depicting
their separation from one another. Bond rupture is a
dynamic process.
Measurements and modeling of fracture surface rough­
ness under dynamic and static loading has led to new
insights into the conditions for crack propagation. First,
Ramanathan et al. [251, 252] suggested that the rough­
ness is defined only by dynamic conditions near the crack
tip, which, in turn, are affected by the dynamic stress
transfer. Then, based on this suggestion, the crack front
207
PA R T I I
Modeling in MEMS
waves were assumed to be responsible for the small-scale,
self-affine fracture surface roughness found experimen­
tally in both dynamic and (macroscopically) static loading
[253]. However, this crack front wave theory was found
to be inadequate in predictions of the observed exponent
of scale dependence. Therefore an alternative model has
been suggested, where the roughness originates in multi­
ple voiding and void coalescence ahead of the main crack,
that provides the correct exponent [253].
There have been few attempts to experimentally
verify crack front waves [254, 255]. Sharon et al. [255]
claim that they observed solitary waves, which may, in
fact, be crack front waves. However, Bonamy and RaviChandar [254] argue that the observed solitary waves
may be due to an interaction between shear waves and
the propagating crack front.
Next, the effect of microcracking as an impor­
tant dissipation mechanism has been widely discussed
[256–258]. Microcracks can act as nuclei for macro­
scopic crack branching leading to the crack roughening
and increasing the fracture toughness with crack veloc­
ity [259–265]. This has also been shown to predict an
upper bound for the crack velocity that lies far below
the Rayleigh wave speed [260, 261, 263, 264]. At the
same time, if microcracks form a cloud, the effective
wave speed and therefore the crack speed through the
damaged material are reduced [266] and the macro­
scopic fracture toughness increases.
One of the fundamental problems for fracture
mechanics is the correct way of stating the criterion for
static crack propagation. One of the criteria, widely used
in many engineering applications, is based on energy
release rate or critical stress intensity factors as discussed
in the previous sections. However, sometimes for the
case of quasi-static loading, this criterion leads to the
prediction of the wrong crack path and fundamentally
unrealistic crack-tip conditions. The ultimate answer to
the quasi-static fracture criterion may not be approach­
able by calculations of static behavior alone but may lie
in essentially dynamic phenomena [237]. In particular,
Ravi-Chandar and Knauss [267], using deeply notched
thin sheets of Homalite loaded in mode I by the electro­
magnetic method showed strong correlation between the
onset of crack propagation and the crack-tip stress inten­
sity factor. Thus for engineering applications, the idea of a
dynamic initiation toughness arises in analogy to the frac­
ture toughness used in quasi-static fracture, where the
critical toughness might be a material constant that could
be measured in a simple standard experiment [237].
The propagation of dynamically moving cracks has
been addressed by a number of the atomistic calcula­
tions. Most of them were directed towards understand­
ing of the steady-state propagation, crack speed, and the
onset of dynamic instabilities. Both analytical [201] and
MD [268] approaches have been applied to this problem.
208
In particular, the analytical calculations that considered
one- and two-dimensional structures showed that a
dynamically propagating crack can only access a limited
velocity of about 20% of the Rayleigh wave velocity.
When the crack tip speed reaches half of the Rayleigh
wave velocity, the crack manifests a branching instabil­
ity [201]. MD simulations [268] essentially confirm the
analytic results, giving the same estimate for the lower
band of forbidden velocities for the straight crack and
also revealing an upper critical velocity. Gumbsch et al.
[268] also showed that the upper critical velocity for
the mode I crack strongly depends on the nonlinearity
of the atomic interaction. Thus one should be accurate
choosing the form of the atomic interaction description
(see also Section 11.2.2).
Furthermore, according to MD simulations, the type
of crack instability above the critical velocity depends
on the crystallographic orientation of the crack and on
the crystal structure ([200, 268], Mikkula, 1998). The
generation of cleavage steps and dislocation emission
are usually observed at lower overloads, while crack
bifurcation was only observed at the highest overloads.
Dislocation emission usually leads to a pronounced
change in crack propagation direction.
11.3.5 Brittle-to-Ductile Transition
As discussed in Section 11.3.1, the particular fracture
mode, brittle or ductile, is defined by the competition
between two processes. These are the extension of the
crack by creation of two new surfaces (brittle response)
or stress relaxation by the generation of dislocations that
blunt the crack tip (ductile response). Silicon under­
goes a transition between brittle and ductile response at
T ~ 873 K. This transition is very sharp function of tem­
perature and takes place within the temperature range
of only 2 K!
According to the Griffith criterion (see Section 11.2.1),
the energy required for an incremental advance of the
brittle crack front is 2γ. The ductile fracture is a more
complex process and its description requires a proper
account of dislocation nucleation and motion in the
neighborhood of the crack tip. The first attempt to
rationalize the distinction between brittle and ductile
behavior was made by Kelly et al. [269]. They postu­
lated that a material would be ductile if the crack tip
stress exceeded the theoretical shear stress before the
theoretical tensile stress was reached. Later Rice and
Thomson [270] defined a ductile behavior as spontane­
ous emission of dislocations at the crack tip. According
to their criterion, dislocations are considered to be
nucleated when they move a distance exceeding some
critical distance ac from the crack tip. Then, if ac is
smaller than the dislocation core radius, the material
Mechanical Properties of Silicon Microstructures
is considered to be ductile at all temperatures; oth­
erwise the material is brittle at low temperatures.
Unfortunately this criterion predicts a DBT temperature
that is much higher than that observed experimentally.
A more recent DBT criterion [271, 272], which
is the further development of the Rice and Thomson
model [270], exploits the unstable stacking fault energy
γus, a measure of the nucleation energy for a dislocation
of Burgers vector b on the (hkl) plane. According to this
criterion, sometimes called the Rice model, dislocation
nucleation at the crack tip and therefore ductility is
reached when
G � αγ us
where α is a constant of the order unity, which depends
on the geometry of the crack.
As an alternative model of the DBT, Hirsch and
Roberts [180] postulate that ductility is defined by the
motion, rather than the nucleation of dislocations. This
model connects the DBT with dislocation mobility and
scales with the unstable stacking fault energy γus.
Thus, according to the ductility criteria considered,
the conditions for both brittle fracture and the nuclea­
tion and motion of dislocations can be expressed in
terms of features of the γ-surface. On the basis of this
concept and adopting the view that dislocation nuclea­
tion is a necessary precursor to dislocation motion,
Kaxiras and coworkers [273] proposed a ductility con­
dition that depends only on two energies, γ and γus, and
defined a “disembrittlement parameter” determining to
which class a solid belongs:
D�
γ
γ us
The difficulty with using this criterion is that values for
γ and γus have to be established from accurate micro­
scopic calculations. Even then, it is not clear for which
slip system or for which cleavage plane these quantities
must be evaluated [273].
Kaxiras and Duesbery [274] calculated the general­
ized stacking fault (GSF) energy surface for both shuffle
and glide planes in silicon (for the definition of the shuf­
fle and glide planes in the diamond structure see Section
11.2.1 using first-principles calculations in the DFT/LDA
framework. They found that GSF energy, γus, has a
value of about 1.81 J/m2 and 2.02 J/m2 for shuffle and
glide planes, respectively. They also showed that atomic
relaxation affects the glide plane energetics more than
the shuffle plane, indicating that at zero tempera­
ture the sessile mode will be favored. However, it was
found that because of the high entropy the glide plane
“under the proper thermodynamic conditions” can have
a lower energy than the shuffle plane. This led Kaxiras
and Duesbery [274] to the conclusion that as the
CHAPTER 11
temperature is increased beyond a critical point, a tran­
sition from sessile shuffle mode to glissile glide mode
can occur that can be related to the DBT in silicon.
While Rice’s criterion for ductile versus brittle behavior
addresses the issue of dislocation nucleation and motion,
it does not include any information about the surfaces
created due to dislocation emission at the crack tip. Juan,
Sun, and Kaxiras [275] found that the energy associated
with ledge surface creation is approximately 60% of the
energy of the free surface. Assuming an evanescent force
law, they incorporated the ledge effects into Rice’s origi­
nal theory within continuum mechanics and showed that
the increase in the necessary loading for dislocation emis­
sion due to surface traction can be up to 20%.
Despite this result, increasing experimental evidence
([162, 276]) seems to indicate that BDT in BCC (body
centered cubic) metals is controlled by the mobility of
dislocations away from the crack tip. One distinguishing
difference between BCC metals and covalent solids such
as silicon in terms of the BDT is that the activation energy
of the BDT in BCC metals is in general much lower (by
an order of magnitude) than the activation energy of bulk
slip [277–279], while for covalent solids, the BDT activa­
tion energy is comparable to activation energy of bulk slip
[180, 280]. The much lower BDT activation energy in
BCC metals could be interpreted in terms of the strong
stress-dependence of the activation energy of slip in the
vicinity of the highly stressed crack tip. However, recent
discrete dislocation dynamics simulation [281] has shown
that the effective activation energy of crack tip plasticity—
even with stress-dependent activation energy—is only
marginally reduced from the activation energy of bulk slip.
This must be interpreted to clearly rule out the mobility
of screw dislocations as the only decisive factor and the
rate-limiting step for crack tip plasticity and the BDT.
It rather suggests that other factors such as the blunting
edge dislocations [279, 281], or the crack tip enhance­
ment of the dislocation emission process itself [282, 283],
may play an important role. However, there remain many
unknown facts amongst which the role of the initial dis­
location density of the material and the nature of the dis­
location sources near the crack tip are the most-needed
ones. More experiments, dislocation dynamics simula­
tions, and in particular more specific atomistic simulations
are required to clarify these questions.
Later Kang and Wei [32] similar to the previous
models also proposed that fracture behavior is the result
of competition between two different failure modes,
cleavage on the (110) plane and slip on the (111) plane.
On the basis of this proposal they introduced another
criterion for the brittle-to-ductile transition defining a
“ductility parameter”:
A
Sσ c
τc
209
PA R T I I
Modeling in MEMS
where σc is the ideal tensile strength, which is the meas­
ure of resistance against the cleavage on the (110) plane;
τc is shear strength, which measures the resistance against
slip on the (111) plane; S is the Schmidt factor, the
resolved shear stress on the slip system (slip plane and
slip direction) per unit tensile strain, and is defined as
S � cosϕ cosλ
where ϕ is the angle between the tensile axis and slip
plane normal and λ is the angle between the tensile axis
and slip direction. According to this criterion [32], if
“ductility parameter” A � 1, then ductile fracture can be
predicted, otherwise when A � 1 the fracture is brittle.
The “ductility parameter” has been calculated using
different computational approaches [32] (Table 11.22).
Unfortunately, it has been found that the resulting
value is dependent on the approximation used. So, the
MD calculations with SW, Tersoff, and Lenosky empiri­
cal potentials predict A � 1 and, thus, ductile behavior,
whereas MEAM, SWmod and DFT calculations predict
A � 1 and brittle behavior.
11.4 Physical Mechanisms of
Fatigue of Silicon
Table 11.22 Ideal tensile strength (in GPa), ideal shear strength
(in GPa), and ductility parameter , A, for Si nanowire calculated
using different computational approaches (data from [156]). Ductile
fracture condition is A � 1, brittle fracture is expected when A � 1
S σc
Potential Ideal tensile Ideal shear
A�
strength, σc strength, τc
τc
Fracture
behavior
Ideal tensile strength along the [110] direction, ideal shear strength on
the (111) plane and along [11 � 1]. Schmidt factor S � 0.4082 along
the [110] direction.
SW
113
19.1
2.42
ductile
Tersoff
41.6
9.51
1.79
ductile
Lenosky
33.5
11.3
1.21
ductile
Baskes
32.0
13.9
0.940
brittle
SWmod
41.0
19.5
0.858
brittle
VASP/LDA
25.2
14.0
0.735
N/A
VASP/GGA
23.0
13.7
0.685
N/A
Ideal tensile strength along the [111] direction, ideal shear strength on
the (11 � 1) plane and along [101] Schmidt factor S � 0.2722 along
the [111] direction.
11.4.1 General Remarks
SW
38.5
9.51
1.10
ductile
Over the past decade, a vast array of MEMS applica­
tions, such as pressure transducers, inertial sensors, ink
jet cartridge nozzles, and more have emerged and many
commercial products ranging from medical to comput­
ing devices have entered the marketplace. The conven­
ience and success of silicon material and micromachining
technology have made silicon a natural choice for many
MEMS applications, such as actuator, power generator,
etc. The reliability of these applications is extremely
important to ensure their effective performance (“highperformance” applications) and safeguarding human life
(“safety-critical” applications). In particular, the mate­
rials used for the safety-critical applications are often
subjected to aggressive mechanical and chemical environ­
ments, such as, for example, a large number of the cyclic
stresses within relatively short periods of time. In a case
when cyclic stresses are applied, most materials undergo
mechanical property degradation resulting in failure.
Fatigue, or the delayed failure of a material under
cyclic loading conditions, is very important and is the
most commonly experienced form of structural failure,
but nevertheless is one of the least understood. As in the
fracture process there are two generally accepted types
of mechanisms of fatigue: ductile and brittle. The ductile
mechanism is usually attributed to the metallic materials
and is accompanied by the cyclic accumulation of plastic
Tersoff
102
19.1
1.45
ductile
Lenosky
30.4
11.3
0.73
brittle
Baskes
29.8
13.9
0.58
brittle
SWmod
38.5
19.5
0.53
brittle
VASP/LDA
22.0
14.0
0.43
brittle
VASP/GGA
20.0
13.7
0.40
brittle
210
deformation through the generation and motion of dis­
locations. The failure, in this case, is the result of the
crack nucleation and its crack propagation, either preex­
isting or created by alternately blunting and sharpening
the crack tip. In contrast with ductile materials, brittle
materials, to which the single-crystal silicon belongs,
manifest very low dislocation mobility at ambient tem­
peratures as a result of high Peierls forces. This means
that if the fatigue takes place in these materials, it fol­
lows the fundamentally different mechanism for which
dislocations are not involved. Indeed, as has been found
for some polycrystalline ceramics and ordered interme­
tallic compounds [284, 285], the fatigue is governed
by kinematically irreversible deformations via so-called
Mechanical Properties of Silicon Microstructures
crack-tip shielding mechanisms leading to the cycle
dependent degradation of the toughness of the material
in the wake of the crack tip. Single-crystal silicon or any
other solid with the covalently bonded diamond struc­
ture, however, do not exhibit any degree of shielding
to degrade. Hence, the crack-tip shielding mechanisms
would not be expected in these materials. Moreover,
there is also little evidence of other extrinsic toughening
mechanisms, such as, for example, grain bridging [286]).
Moreover, as it is well established experimentally ([195,
286–289] and theoretically [290], bulk single-crystal
silicon is immune from both cyclic fatigue and environ­
mentally assisted (e.g., stress–corrosion) cracking [195,
288, 291–294]. Such immunity to long-lifetime degra­
dation would clearly be of benefit in applications where
periodic mechanical, electrical, or thermal stresses oper­
ate (e.g., sensor technology, electronic packaging, solar
panels, and optical systems) [287].
For all of these reasons, fatigue of silicon was unex­
pected when Connally and Brown in 1992 [295] dem­
onstrated that a silicon specimen of micrometer-size
dimensions failed prematurely under cyclic fatigue loading
in room-temperature air. This finding has been confirmed
in many other studies during the last decade [95, 249,
250, 286, 296]. In these works it has been found that
both mono and polycrystalline silicon films display failure
stresses of approximately half their (single-cycle) fracture
strength after fatigue lives in excess of ~1011 cycles.
This fact is rather unfortunate because silicon thin
film is one of the most common materials used in
microelectromechanical systems to date.
In order to control fatigue damage in silicon-based
MEMS devices the understanding of the fatigue mecha­
nism is of an extreme importance. Within the last decade,
there have been several models for silicon fatigue origin
proposed (e.g. by native oxide cracking, room-temperature
plasticity) [297]. However, there has been no direct exper­
imental evidence to support any mechanism of silicon
fatigue so far. The experimental studies have only estab­
lished the importance of subcritical crack growth showing
that consideration of fatigue-crack initiation and growth
must be a crucial part of critical component design.
11.4.2 Single-Crystal Silicon
If thin film silicon is fatigued at high enough stress
amplitudes, cracks will initiate and grow, and the mate­
rial will eventually fail. Connally and Brown were the
first investigators who showed that thin free-standing
film of a single-crystal silicon could undergo cyclic
fatigue failure [295]. In that pioneering work they used a
notched, electrostatically actuated resonator system with
a resonance frequency of 12 kHz and a stress ratio (the
ratio of applied stresses) of �1, and demonstrated that
CHAPTER 11
fatigue was caused by slow crack growth that occurred
by environmentally assisted cracking in the silica layer
that forms on silicon upon exposure to oxygen. They
proposed, in particular, that fatigue-crack growth rates
are rate-limited by the reaction rates at the crack tip or
by transport of reaction species to, or from, the cracktip region [298]. On the basis of this work Connally and
Brown concluded that the actual mechanism govern­
ing crack growth in micron-scale silicon devices is more
complex than simple environmentally assisted fatigue of
silica, even though water, indeed, accelerates or initiates
crack propagation.
Following Connally and Brown, Tsuchiya and cow­
orkers confirmed the influence of environment on the
fatigue behavior in single-crystal silicon films [334].
According to their observations the longer the fatigue
life, the more the fatigue damage accumulation, even
though no direct evidence of this damage were made.
They also found that cycling in humid air (78% relative
humidity) led to failures in fewer cycles than cycling in
dry air (11% relative humidity), which shows that the
specimen’s fracture strength and fatigue life are highly
affected by the testing environment. These authors
attributed their findings to a mechanism involving oxi­
dation at a crack initiation site on the silicon surface
that allowed further crack growth. These results have
been confirmed further by the number of more recent
works (e.g., Refs. [299, 300]) providing additional evi­
dences that silicon films manifest much more significant
degradation over time in air than in vacuum.
In order to gain information about the crack initia­
tion and failure mechanisms, scanning electron micros­
copy (SEM) and atomic force microscopy (AFM) have
been used for the fracture surface examination. It has
been shown that there is no evident fracture initiation
region in specimens with short lives and that specimens
contain ridges, ledges, steps, and other features com­
monly observed on brittle material fracture surfaces.
Furthermore, it has been found that the failure in a
short-life specimen progresses by cracking on multiple
{111} planes with final failure taking place by cleavage
on a (111) plane after coalescence of multiple crack
fronts, where the dominant mode of the fracture is
cleavage [249, 301, 302]. This is the result of the cleav­
age crystallography of the silicon crystal as discussed
in Section 11.2. Cleavage steps, formed on the {111}
fracture surfaces as a means of dissipating energy, were
addressed by Muhlstein et al. [249] with regard to per­
turbations in the applied loads, obstacles in the crack
path, bifurcation of fast-running cracks, and the coales­
cence of microcracks.
In contrast with the short-life surfaces, for long-life
fracture surfaces the initiation region can be clearly
identified and found to be near the surface of the
notch. In this case the fracture surface is smooth and
211
PA R T I I
Modeling in MEMS
does not contain any steps like the short-life surfaces.
The fracture proceeds predominantly along {110},
which is unusual for silicon and suggests that the active
cracking mechanism under cyclic fatigue loading is dif­
ferent from that seen during quasi-static overload fail­
ure [249]. Sundurarajan and Bhushan [191], however,
obtained scanning electron micrographs, which indicate
a high-energy fracture on a {100} plane in combination
with low-energy cleavage on {111} planes. The frac­
ture surfaces were found to be smooth, without facets
or irregularities. These authors proposed that fracture
occurred by low-energy cleavage on the {111} planes,
with a fatigue mechanism similar to environmentally
assisted cracking.
The growth of a subcritical crack is affected also by
the way of loading. In a case of monotonic loading a dis­
crete step-like crack growth process is observed [289,
303]. The increase of the load leads to the unstable
fracture mode when the stress intensity, KI, approaches
the toughness of the material. Sometimes, however, due
to the geometry of the specimen KI can decrease with
crack extension leading to the crack arrest [289, 303].
The experimental observations for a constant-load
mode show that subcritical cracking only occurs for 0.9
KIc � KI � 0.98 KIc , where KIc is the toughness of the
material. This means that subcritical crack growth occurs
in the region III in v-KI curves (v is the crack growth
rate) where the crack velocity outpaces transport of the
environmental species. A crack growth rate is v� CKn,
where C and n are constants, and n is higher than 100.
Based on that understanding it has been concluded that
environmentally assisted subcritical cracking is absent in
monotonically loaded micron-scale silicon [289, 303].
For cyclically loaded specimens the crack-growth
behavior is observed to be step-like in nature, with
unstable crack extension when the maximum applied
stress intensity reached the fracture toughness [289,
303]. Under decreasing K conditions, cracks were
observed to arrest. The resulting growth rate versus
Kmax curves were similar to the curves obtained under
monotonic loading, which suggested that the relevant
crack-growth process in single-crystal silicon was not
true cyclic fatigue. This conclusion was further sup­
ported by the fact that fracture surfaces under cyclic
and monotonic loading were similar. The authors also
conclude that fatigue mechanisms involving cracking of
a surface reaction-layer would be a viable mechanism.
11.4.3 Polysilicon
Similar to the data for single-crystal silicon films, all the
available experimental observations for the polysilicon
specimens say that material failure is affected by factors
such as loading conditions, operating frequency, and,
212
most importantly, environment. So, in early work on
fatigue in polycrystalline silicon films, Van Arsdell and
Brown [95] reported the change in resonant frequency of
a precracked polysilicon device under fatigue loading in
wet air. Specifically, they observed that the resonant fre­
quency of the device decreased when it was fatigued in
humid air (50% or 75% relative humidity), but remained
unchanged when it was fatigued in dry air. These results
were interpreted as subcritical crack growth via an envi­
ronmentally assisted cracking mechanism.
On the basis of the fracture surface examination,
which showed a transgranular crack path, Van Arsdell
and Brown [95] suggested that this environmentally
assisted cracking involves the native oxide film rather
than the polysilicon itself. They claimed that this mech­
anism would facilitate further growth of the oxide film
at the crack tip. This mechanism was called “static
fatigue” and includes only effects of the environment
and stress level, but claims the fatigue behavior is inde­
pendent of the number of load cycles.
Muhlstein et al. [250, 296, 302, 304–308], using the
same devices as those used by Van Arsdell and Brown
[95] and also transmission electron microscopy (TEM),
measured the thickness of the surface silica layers on
the specimens. They found that after fatigue cycling to
failure the surface oxide thicknesses were up to three
times greater in the highly stressed regions than in the
nonstressed regions without heating occurring dur­
ing the test, as was also suggested by Van Arsdell and
Brown [95]. The same authors reported TEM studies of
one specimen that was cyclically stressed but not to fail­
ure, which showed several stable small cracks within the
thickened surface oxide layer, indicating the presence
of subcritical crack growth. Furthermore, it has been
shown that the specimens, which were treated with a
self-assembled monolayer (SAM) coating during fabrica­
tion that prevented surface oxide formation, revealed a
smaller dependence of lifetime on the peak stress ampli­
tude. Similar to this, Alsem et al. found that the absence
of oxygen and water vapor in a 2 � 10 � 5 Pa vacuum
environment completely suppressed the occurrence of
delayed fatigue [298]. They also showed that samples
tested in high relative humidity (�95% RH) air failed
after fewer numbers of cycles than corresponding sam­
ples tested in ambient air (~35% RH). In light of these
results, the fatigue of silicon thin films was attributed to
a mechanism of sequential, cyclic stress-assisted oxida­
tion and environmentally assisted cracking of the surface
oxide layer which forms upon exposure to moistureand/or oxygen-containing atmospheres, a mechanism
that they termed reaction-layer fatigue [298].
In order to support a reaction-layer model Muhlstein
et al. [304, 306] performed a finite-element modeling,
on the basis of which they claimed the decrease in natu­
ral frequency of the fatigue characterization structure
Mechanical Properties of Silicon Microstructures
during testing is consistent with the modeled damage
evolution in the form of oxide thickening (�0.5 Hz per
nm of oxide growth) and subcritical crack growth (�1 Hz
per nm of crack extension) within the oxide. In particu­
lar, the calculated critical crack size was found to be
similar to the experimentally observed maximum crack
extension. The fact that this size is less than the surface
oxide layer implies that the entire process of fatigue
crack initiation, growth, and the onset of final failure
of the entire structure occurred within the oxide layer
[309]. Following these observations and the fact that a
crack in the oxide layer must cause failure of the entire
structure, the criterion for this mechanism was proposed,
which says that the thickness of the oxide layer, h, must
be greater than or equal to the critical crack size, ac, to
fail the entire structure (i.e., when ac � h).
Later, Pierron and Muhlstein [310] expanded this
numerical model to account for an alternative failure
scenario where stable crack growth in the oxide changes
to unstable crack growth when the crack hits the sili­
con/oxide interface (i.e., when ac � h; this lowered the
oxide thickness that is potentially susceptible to reactionlayer fatigue to ~15 nm, compared to ~50 nm required
in the previous model). The mechanism also explained
the decreasing growth rates observed for cracks propa­
gating within the oxide layer; as these cracks approach
the SiO2/Si interface (with its three-fold modulus mis­
match), fracture mechanics calculations of the crackdriving force showed that it decreased as cracks got
closer to the interface [309].
Thus, the reaction-layer fatigue model involves cyclic
stress-enhanced surface oxide thickening, which then
undergoes environmentally assisted stress corrosion
cracking. The process repeats until a critical crack size
is reached, and the silicon itself fractures catastrophi­
cally. In other words, the fatigue damage occurs only
in the surface oxide. While stress corrosion has both a
time dependence and a monotonic stress dependence,
if the rate-controlling step is the oxide thickening which
depends only on the cyclic stresses, the time depend­
ence of fatigue failure is avoided. However, Kahn et al.
[311] argued that TEM, which was used by Muhlstein
et al. [306] to obtain the images of surface layers that
contain cracks that were then used to support this model,
is both unconventional and quite difficult to use to
determine the thickness of a surface layer on a sidewall
because the microfabricated sidewalls of the polysilicon
specimens are neither perfectly flat nor perfectly vertical.
Furthermore, they claimed that this type of analysis can­
not determine whether the thickness of the surface oxide
is uniform through the 2000-nm height of the polysili­
con device, or whether the observed thickness increase
is due to redistribution of the initial oxide [311]. Finally,
Kahn et al. considered another concern about the SAMcoated results, which showed failures at 107 and 108
CHAPTER 11
cycles (4.2 and 42 min) for specimens with peak stresses
of 2.8 GPa. For these devices to fail via the reactionlayer mechanism the SAM must first break down, then a
surface oxide of sufficient thickness (20 nm) must grow,
followed by stress corrosion cracking of the oxide layer,
all within the time span of a few minutes.
Another mechanism, complementary to reactionlayer fatigue, was proposed on the basis of the surface
topology changes with increasing distance from the
notch seen in in situ AFM images of the region near
the notch, before and after cyclic actuation [312–316].
These changes indicated a role of stress in the evolution
of surface topography under cyclic loading and were
ascribed to the roughening of the surface oxide layer,
which in turn was associated with a mechanism of cyclic
stress-assisted dissolution of the surface oxide layer
such that deep grooves are formed where the dissolu­
tion is fastest that could result in fatigue crack nuclea­
tion. One drawback of this model as stated by Kahn
et al. [311] is that cyclic stress-enhanced oxidation has
never previously been observed. Though Allameh and
coworkers [314, 315] report that their specimens had
an initial surface oxide of 2–4 nm, they used the same
structures as Muhlstein et al. [306], who showed sur­
face oxides of about 30 nm. Another concern is that
Allameh and coworkers [312–316] used the model
based on the stress-dependent surface reaction model of
Yu and Suo [317], which involves monotonic stresses,
not the cyclic stresses that Allameh et al. used exclu­
sively. Also, this model has a time dependence, which
Bagdahn and Sharpe [318] have shown is not a feature
of silicon fatigue as discussed later in this section.
Completely different mechanisms for the fatigue of
micron-scale polysilicon were suggested by Kahn et al.
[286, 308, 319–322] on the basis of results from speci­
mens tested at varying stress ratios (�3 � R � 0.5) in
laboratory air and in a medium vacuum (8 Pa pressure).
First, Kahn et al. claimed that fatigue crack initiation
and growth occurred during cyclic loading in both air
and vacuum, although the process was faster in air. Then
these authors suggested a purely mechanical mechanism
for the fatigue behavior of silicon thin films via subcriti­
cal cracking of the silicon itself. Further, these authors
found that the low-cycle fatigue strength of the electro­
statically actuated single edge notched microspecimens
was affected more by the stress ratio than by the envi­
ronment. On the basis of this, they concluded that the
fatigue mechanism for silicon thin films was strongly
affected by the compressive portion of the loading cycle,
which they reasoned could create a microcrack at the
surface due to wedging on surface asperities and allow
further crack growth due to a mechanism similar to farfield cyclic compression fatigue of brittle ceramics. Later
their investigations of the high-cycle (104 � 3 � 108
cycles) fatigue behavior in air and vacuum found no
213
PA R T I I
Modeling in MEMS
fatigue failures in a medium vacuum. On the basis of
this work Kahn et al. postulated that thickened surface
oxide on newly formed crack surfaces in air could cause
wedging effects that would create additional subcritical
cracking or that wear debris formed in vacuum could
prevent crack closure and therefore decrease crack driv­
ing force and growth [311]. The fracture–mechanics–
based finite-element modeling used for calculations
of the crack-opening profile and the driving force for
advance of wedged cracks showed, however, that in
compression, such wedges do not cause an increase of
the magnitude of the stress-intensity factor, leading to
the conclusion that this mechanism cannot contribute
significantly to the fatigue of silicon thin films [298].
Then, in their experiments on mean stress effect
on the low-cycle fatigue of Pd-coated undoped and
B-doped polysilicon film, Kahn et al. [323] found that
increasing the amplitude of the cyclic stress with a
positive mean stress led to the higher fracture stress,
whereas negative mean stress led to the lower fracture
stress. They showed, in particular, that a cyclic, but not
monotonic, loading had an influence on the fracture
stress and that loading with an applied cyclic stress,
with mean stress offset below the fracture stress was
followed by a ramp to failure. These low-cycle fatigue
results were rationalized in terms of a “weakening and
strengthening map”, where weakening occurs when the
fatigue strengthening is found at low-fatigue amplitude
where the mean stress is highly compressive or highly
tensile. No effect was found at low fatigue amplitudes
with low mean stress (compressive or tensile).
To account for all their observations Kahn et al. suggested
three possible fatigue mechanisms. The first of these
was based on the idea of the microcracking of the silicon
and was discarded later as inappropriate as an explana­
tion of the weakening and the strengthening due to crack
tip shielding. A second mechanism was suggested involv­
ing dislocation activity, which would cause crack-tip
blunting in the case of a strengthening effect and cracktip blunting followed by sharpening for a weakening
effect. However, in order for this mechanism to operate
there should be a readily detectable dislocation den­
sity observed, but that is not the case for silicon [311].
Moreover, there has been no direct evidence to date of
dislocations at arrested crack tips in silicon; room tem­
perature dislocation plasticity in silicon has only been
observed to date during the high combined compressive
and shear loads of an indentation test [324]. Their third
proposed mechanism involved grain-boundary plastic­
ity, where an amorphous grain-boundary region hitting
the surface under stress would experience a nonconven­
tional plastic deformation in shear, which would then
cause a residual compressive stress, possibly resulting in
the observed strengthening effect. To support this model
Kahn et al. presented results of their element mode­
ling, where they showed that with such grain-boundary
plasticity residual compressive stresses could occur.
However, as argued by Alsem et al. [298], there is no
experimental evidence for these modeled results; fur­
thermore, the fact that single-crystal micron-scale silicon
is also susceptible to fatigue failure is totally inconsistent
with any mechanism involving only grain boundaries.
Bagdahn and coworkers [318, 325, 326] combined
their data on the influence of frequency on the highcycle fatigue behavior with those of Muhlstein et al.,
Kahn et al., and Kapels et al. into a single plot of nor­
malized peak stress versus fatigue lifetime and found
that all the data followed the same curve. They con­
cluded that fatigue lifetime depends only on the number
of cycles, not on the total time or the frequency of the
test, and fit the results to the equation
σf
σc
.02
� N�0
f
where σf is the peak stress in the fatigue cycle, σc is the
monotonic strength, and Nf is the number of cycles to
failure. They also noted an increase in surface rough­
ness of the top surface of their specimens in the vicin­
ity of the fatigue fracture [318]. Finally, they concluded
that there should be an additional effect (other than the
environmental influences) to account for all the results.
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219
12
Chapter Twelve
Electrostatic and
RF-Properties of MEMS
Structures
Ilkka Tittonen and Mika Koskenvuori
Micro and Nanosciences, Micronova, Helsinki University of Technology,
Espoo, Finland
12.1 Introduction
– Small size of MEMS and NEMS devices means also
Well-known examples of micromechanical sensors are
accelerometers, pressure sensors and cantilevers that
are used, for example, as fluid sensors and in various
microscopes.
In designing and modeling of nano and micromechanical systems the following general aspects should be
taken into account:
– Capacitive coupling leads to a novel capacitor of
high capacitance values.
which value is dynamic and depends on the applied
voltage across its gap (bias-voltage UDC).
– Small gaps (significantly below 1 μm) are still a
challenge for mass fabrication.
– Small (capacitive) mechanical sensors may
and affects the properties of dynamical systems.
easily suffer from charging of surfaces, diffusion,
contamination and break through currents and may
need to be surface passivated or encapsulated.
– Particular design finally determines basic resonance
– RF MEMS devices are highly potential candidates as
– The sound velocity depends on the chosen material
modes and frequencies and leads to the modification
of stiffness.
– Any mechanical device has an infinite number of
various mechanical vibrational modes.
– Dissipation of mechanical energy is often difficult
to predict, especially since total dissipation is a sum
of contributions of intrinsic and external losses of
energy.
– In case the material is anisotropic (like single crystal
silicon), the mechanical properties depend on the
crystal orientation.
– Both the capacitive and piezoelectric coupling make
it straightforward to create local forces that can be
used in actuation of micromechanical devices.
– Capacitive and piezoelectric couplings are also
potential ways to integrate the mechanical systems
as part of the electric circuit.
reference oscillators, filters and switches.
– Finite-element method (FEM) is often more or less
the only way to simultaneously model mechanical,
thermal and electric effects.
– Often finite-element modeling leads to higher level
circuit simulations by giving the necessary input
parameters.
12.2 Model System for a Dynamic
Micromechanical Device
A most simplified way of modeling a micromechanical
moving system is to form a lumped element model that
contains a minimum number of physical parameters
(Figure 12.1).
Resonators moving as a response to an external
force can be described using at least three different
221
Modeling in MEMS
PA R T I I
Fig 12.1 ● Model system of a dynamic micromechanical system.
parameters: the spring constant k, the effective mass
m and the damping constant c. The spring constant
depends on the chosen material and the design and in
resonant cases also on the particular vibrational mode.
The effective mass is a measure of the size of the
moving part, but it is also affected by the strength of
coupling to the support (substrate, etc.). Damping takes
into account both the internal and external sources of
energy leakage.
Resonators are usually driven using harmonic forces,
which are often achieved by capacitive coupling. In such
cases the dynamic motion of a micromechanical resonator can be described by the differential equation of
motion:
mx��
cx�
kx F̂ cos ωt
(12.1)
The first term on the left describes acceleration that
becomes mediated by the effective mass m, the second
term originates from damping which is proportional to
the velocity x� , and the third term gives the displacement as a response to the external force via the spring
constant k. In some cases (e.g., k3x3) higher order nonlinear terms need to be added for more accurate modeling of the response. The right-hand-side of the equation
could be any time-dependent or static actuating force.
In case of harmonic excitation with the force amplitude F̂, the displacement and the solution to the equation
of motion can be found in a closed form:
x
F̂
m
⋅
2
⎛
⎞
cω
ω02 − ω
⎜⎜⎝⎜ ⎠⎟⎟⎟
m
⎡
⎛ cω ⎞⎟⎤
⎜⎜
⎢
⎟⎟⎥
⎢
⎜⎜
m
⎟⎟⎥
cos ⎢ ωt − arctan ⎜ 2
⎥
2⎟
⎜
⎢
⎜⎜ ω0 − ω ⎟⎟⎟⎥⎥
⎢
⎠⎟⎦
⎝⎜
⎣
(
222
)
As is obvious, the phase of the mechanical motion
is usually delayed relative to the excitation signal. The
maximum amplitude can usually be found at resonance.
At this frequency the phase of the oscillation is 90°
behind that of the force.
The resonance frequency becomes also affected by
damping
2 2
(12.2)
2
1 ⎛ c ⎞⎟
⎟⎟
ωr ω0 1 − ⎜⎜⎜
2 ⎜⎝ mω0 ⎟⎠
(12.3)
where
ω0 k
meff
(12.4)
where k is the mechanical spring constant of the resonator and meff is the effective mass of the resonator. It
should be noted that the effective mass is different
from the dimensional mass m V·ρ that is derived
from the volume V of the resonator and the density ρ
of the resonator material. The relationship between the
two masses is determined by the vibration mode of the
resonator. Some examples can be seen from Table 12.1.
In principle the modification of the damping could
lead to a feasible tuning of the resonance frequency;
however, usually this is not easily accomplished in
practice.
A more detailed effect of damping on the amplitude
and phase is shown in Figure 12.2. The dynamic amplitude at the resonance frequency over the static displacement is the Q-factor, Q,
Electrostatic and RF-Properties of MEMS Structures
CHAPTER 12
Fig 12.2 ● Effect of damping on the amplitude and phase response near the resonance frequency that has been normalized to one.
Q-factor is varied between 0.1 and 100.
Q
x̂r
x st
ω02
(
ω02 − ω 2
)
2
⎛ cω ⎞⎟2
⎜⎜⎝⎜ ⎠⎟⎟
m
≈
mω0
c
(12.5)
The last approximation of Eq. 12.5 is valid, when Q
is high (i.e., the frequency shift is negligible). We notice
that high damping (low Q) makes the resonance invisible as a function of frequency. Often some acoustic
microsystems are heavily gas-damped and do not show
any typical resonant behavior. The same holds true also
for certain sensors where the operation principle is the
detection of the mechanical displacement. Typical of
such examples are accelerometers.
As an example we study a simple (silicon) beam that
is fixed from one end and also a bridge that is being supported from both ends (Figure 12.3).
By using FEM one can create exaggerated vibrational
mode patterns that are useful in understanding the
motion and especially the frequency response.
Any (micro)mechanical device can be excited to
vibrate in an infinite number of modes. What is maybe
not so well known is that FEM calculations give us
mode-dependent parameters to be used in lumped
models in further analysis of the microsystems. In this
case we take a piece of single crystal silicon and assume
that it is of isotropic material with length L 100 μm,
width w 10 μm and height h 10 μm. For Young’s
modulus for silicon we use E 131 GPa, for density
ρ 2330 kg/m3 and for Poisson ratio ν 0.27.
These examples reveal that the way of supporting
and fixing a micromechanical device drastically affects
the boundary conditions and the corresponding dynamic
response of the system (Figures 12.4–12.5). One should
also note that rather simple equations of motion can be
used in many cases to predict response by including the
effect of the particular vibration mode on the effective
mass (Table 12.2 and Figure 12.6). One should especially notice that the dimensional mass obtained by
density times volume does not give the correct resonant
frequencies since the coupling to the support modifies
the free mass response.
12.3 Electrical Equivalent Circuit
The mechanical model presented in the previous chapter is
useful in many analyses. Often in practice an electrical circuit simulator is used to obtain detailed information of the
behavior of this model as a part of an electronic circuit. It
is useful to transform the previous information into a form
that is readily usable in circuit design calculations.
In electrical domain, the basic resonator consists of
reactive components such as inductance and capacitance. Since the mechanical oscillator is in practice
always damped, a finite Q-factor requires a resistive
223
Modeling in MEMS
PA R T I I
Fig 12.3 ● A mechanical bridge that is fixed from both ends. The force is acting in the transverse direction at the center point of
the bridge. This system shows also rather strong mechanical nonlinearity, since the stiffness in the longitudinal (horizontal) direction
increases with increasing the strength of the force (see Figure 12.6).
load to be included in the equivalent circuit. A series
electrical resonance circuit (Figure 12.7) for resonator
obeys a differential equation
L
d2q
dt 2
Table 12.2 Resonant mode frequencies and the corresponding
effective mass values of a micromechanical bridge
Mode #
dq
R
dt
q
û ⋅ cos ωt
C
(12.6)
where q stands for charge. This equation is of analogous
form with the equation of mechanical motion. If we scale
the electrical equations with the electromechanical coupling
factor η, where q ηx, we can calculate the corresponding
values of the components in this equivalent circuit as
Frequency, f (Hz)
Effective mass, meff (kg)
Bridge supported from both ends (Figure 12.4)
1
7331179
9.46E-12
2
18898040
1.42E-12
3
34302020
4.32E-13
4
52256380
1.86E-13
Beam supported only from one end (Figure 12.5)
Rm Lm c
η2
m
≈
η2
η2
Cm k
F
and
u
η
224
mω0
Qη 2
(12.7)
q ηx
1
1228723
3.37E-10
2
7394308
9.3E-12
3
19509020
1.34E-12
4
35484160
4.04E-13
The effective masses are calculated from Eq. 12.4 based on the simulated
resonance frequency f and the spring constant k (Figure 12.6). The corresponding
resonant modes are shown in Figures 12.4 and 12.5.
Electrostatic and RF-Properties of MEMS Structures
CHAPTER 12
Fig 12.4 ● The first four fundamental resonance modes of a beam that is fixed only at one end. The movement of the beam is fixed to
take place only in-plane. The amplitudes in each sub-figure (a–d) are individually scaled and are not therefore mutually comparable.
The strength of the coupling factor η depends on the
coupling scheme. Here we use only electrostatic (capacitive) coupling between the mechanical and electrical
domain (Figure 12.8).
When a voltage difference U is applied between the
electrodes of a capacitor C, the electrostatic energy E
stored in the capacitor is
E=
1
CU 2
2
(12.8)
The value of the capacitance C (in Figures 12.8 and
12.9) depends on the separation of the electrodes (socalled gap size) d, which is varied due to the displacement of the moving resonator, denoted by x and on the
capacitance with zero displacement C0 A0/d
C
ε0 A
C0 d
d−x
d−x
(12.9)
where A is the effective area between the electrode
and the resonator, usually determined by the thick-
ness of the device layer of the wafer and by the
width of the electrodes used to excite and detect the
movement.
12.4 Electrostatic Force
If the biasing voltage used is a DC voltage UDC, the
electrostatic force can be calculated as a negative gradient of energy. Using Taylor’s expansion, the electrostatic
force can be written as
�
U 2C0
U 2 ∂C �
.
F−
ux ≈ −
2 ∂x
2d
2
⎡
⎛ x ⎞⎟3
⎢1 2⎛⎜ x ⎞⎟⎟ 3⎛⎜ x ⎞⎟⎟
⎜⎜ ⎟
4
⎜⎜ ⎟
⎜⎜ ⎟
⎢
⎜⎝ d ⎟⎠
⎝d⎠
⎝d⎠
⎢⎣
�
(n
⎛ x ⎞n ⎤ �
1)⎜⎜ ⎟⎟⎟ ⎥⎥ ux
⎜⎝ d ⎠
⎥⎦
(12.10)
where the capacitance C is defined by Eq. 12.9.
225
Modeling in MEMS
PA R T I I
Fig 12.5 ● The first four fundamental resonance modes of a bridge having the two ends fixed. The movement of the beam is fixed to
take place only in-plane. The amplitudes in each sub-figure (a–d) are individually scaled and are not therefore mutually comparable.
drive voltage frequency. This can be seen by calculating
the second power of voltage U as
0.12
0.1
y = 1.5077·1014·x3 + 2.0237·107·x2 + 20082·x + 3·10–6
F (N)
0.08
U 2 (U DC
0.06
1 2
ûac cos 2ωt
2
0.04
0.02
1 2
ûac
2
(12.11)
2U DC ûac cosωt
and by calculating the force F by inserting Eq. 12.11
into Eq. 12.10 as
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
x (μm)
Fig 12.6 ● Deflection amplitude of the bridge shown in Figure 12.3
as the transverse force is increased. As is obvious, weak forces
cause a rather linear response, but the system shows also a
nonlinear spring constant when strong forces are present. This
property can be used to fine tune the resonance frequencies.
From Eq. 12.10 it is evident that the force is proportional to the second power of the voltage. Thus, if the
excitation of the resonator is performed with AC voltage, a DC bias voltage is required to create the force
that excites the resonator at the frequency of the AC
226
2
ûac cosωt)2 U DC
�
1 ∂C
F−
.
2 ∂x
⎛ 2
1 2
⎜⎜U DC
uac
⎜⎝
2
1 2
uac cos 2ωt
2
⎞�
2U DC uac cos ωt⎟⎟⎟ ux
⎠
(12.12)
From Eq. 12.12 we can see that the electrostatic
force can have components at zero frequency, at ω and at
2ω, when the frequency of the exciting AC voltage is ω.
Since we aim at having an excitation at ω frequency, the
DC voltage amplitude should typically be stronger than
the AC voltage amplitude. Eq. 12.12 also reveals that
Electrostatic and RF-Properties of MEMS Structures
Rs
Rm
Cm
where the factor multiplying x can be interpreted as the
electrical spring constant ke
Lm
ZL
Fig 12.7 ● An electrical equivalent circuit presentation of a simple
mass-spring system presented in Section 12.2. The shaded parts
represent the source and load that are used to excite and detect
the resonance, respectively.
x
Static
electrode
m
Y
C(t)
Fig 12.8 ● Model system of a dynamical micromechanical device
coupled by a time-dependent capacitance C(t).
Static
electrode
U
F
x
Fig 12.9 ● Electrostatic force depends on the voltage over the
coupling capacitance that is generated by the static and movable
electrodes.
the DC voltage significantly amplifies the excitation
strength.
As the generated displacement x is typically small
compared with the gap size d (i.e., the resonator operates
in the linear region), the force can be approximated as
⎛ x ⎞⎤
C ⎡
C U2
F ≈ − 0 ⎢1 2⎜⎜ ⎟⎟⎟⎥ U 2 ≈ − 0 DC
⎝⎜ d ⎠⎥⎦
2d ⎢⎣
2d
C U û
C U2 x
− 0 DC ac cos ωt − 0 2DC
d
d
2
C0U DC
d2
(12.14)
We thus obtain a very useful result that the DC
voltage directly leads to one-directional tuning of the
resonance frequency of the mechanical resonator. The
strength of this tuning can be calculated by replacing
the mechanical spring constant k with the sum of electrical and mechanical spring constants k → km ke in
case of no damping:
ke
C U2
ω0 1 − 0 Dc
km
km d 2
⎛
C U 2 ⎞⎟⎟
≈ ω0 ⎜⎜⎜1 − 0 Dc
⎟
⎜⎝
km d 2 ⎟⎟⎠
F
d
ke −
ω ω0 1 −
k
Movable
electrode
CHAPTER 12
(12.13)
(12.15)
This spring softening effect can be seen from Figure
12.10.
In various RF applications, this is a very useful property. From Eq. 12.15 it appears, that the electric field
which is generated by the applied DC bias-voltage UDC
can be used to tune the spring constant of the resonator. This opens at least two options: (i) by applying a
constant voltage (U UDC) the resonant frequency of
the resonator can be tuned and (ii) by applying a periodically changing voltage (U uac), the spring constant
can be modulated, this can be used to realize mechanical parametric amplification of the electromechanical
device [1]. Additional effects caused by the capacitive
nonlinearity will be discussed later in more detail.
We can thus summarize that for the electrostatic
coupling realized via voltage-biased parallel plate transducers the magnitude of the electrostatic force at the
excitation frequency ω depends both on the applied
AC and DC voltages and also on the gradient of capacitance. It should also be noted, that even when high DC
bias voltage is used, the electrostatic coupling leads to a
minimal power consumption.
If the nonlinear contribution to the excitation force
is unacceptable, another way to perform the biasing of a
micromechanical device is to keep the charge q instead
of the voltage of the capacitor constant. In this case the
force becomes
F−
q2 ∂ ⎛⎜ 1 ⎞⎟ �
⎜ ⎟ ux
2 ∂x ⎜⎝ C ⎟⎠
(12.16)
As a difference to the voltage biasing, the charge biasing leads to the force amplitude F that is independent
of the actual displacement x.
227
Modeling in MEMS
PA R T I I
180
–20
150 V
112.5V
75 V
90
S21 (dB)
37.5 V
–60
0
–80
–90
–100
Phase (degree)
–40
–180
5.100M
5.225M
5.350M
5.475M
5.600M
Frequency (Hz)
Fig 12.10 ● The bias-voltage UDC is varied between UDC [0…150] V. The effects of increased electromechanical coupling are evident by
(i) the increased transmission S21 and (ii) lowering of the resonance frequency (spring softening). For UDC 0 V, there is no output signal.
Another way to reduce the nonlinearity is to use
comb-shaped electrodes instead of the parallel plate
electrodes. Then the capacitance becomes
ε h( Le − x)
C 0
d
12.5 Electromechanical Coupling
The relation between the AC-voltage and the force is
∂C
uac
∂x
U DC
(12.17)
where Le is the length of the comb finger.
F U DC
since UDC uac. If we assume that the motion is
sinusoidal, we get
(12.18)
In addition to the voltage and the vibration amplitude, the motional current also depends on the frequency and the gradient of the capacitance between the
electrode and the resonator. By dividing the force with
the spring constant and noting that the force is actually
multiplied by the quality factor of the device, we get
the vibration amplitude at resonance
x̂ R Q
where the electromechanical coupling factor is
η U DC
C
∂C
≈ U DC 0
∂x
d
(12.19)
Therefore, the coupling between electrostatic and
mechanical domains depends on the coupling capacitance and the gap size between the electrodes as well as
on the DC bias voltage over the gap. Thus, narrow gaps
can be used to increase the electromechanical coupling.
12.6 Sensing of Motion
The oscillating MEMS resonator can be sensed using a
DC-biased electrode. To analyze the motional current
induced by this vibration, we can start by writing down
the expression for the electrical current
im 228
dq
d(CU )
∂C
≈ U DC
dt
dt
∂t
∂C �
∂C ∂(x� ⋅ sin ωt)
U DC
ωx ⋅
(12.21)
∂x
∂t
∂x
cos ωt η 2ωûac ⋅ cos ωt
(12.20)
ηûac
C U û
≈ Q 0 dc ac
k
kd
(12.22)
Thus, the amplitude of the motional current at resonance can be written in a form
η 2 ûac ω
U 2 û ωC2
ˆi
≈ Q DC ac2 0
m, R Q
k
kd
(12.23)
The motional current depends strongly on the electromechanical coupling factor (i.e., DC bias voltage and
the gradient of the coupling capacitance). On the other
hand, the gradient of the capacitance C/x in Eq.
12.20 can again be approximated by Taylor’s series as
dq
∂C
∂C ∂x
U Dc
U Dc
dt
∂t
∂x ∂t
⎛
⎞⎟ ∂x
⎛ x ⎞2
C ⎜
x
U DC 0 ⎜⎜1 2
3⎜⎜ ⎟⎟⎟
�⎟⎟⎟
⎜⎝ d ⎠
d ⎜⎝
d
⎟⎠ ∂t
imot (12.24)
Electrostatic and RF-Properties of MEMS Structures
From Eq. 12.24 it is clear that even linear vibrations
can result in higher harmonics in the motional current.
Therefore, for practical purposes the amplitude of
vibration should be maintained at a reasonable level.
The total force exerted onto the resonator is a sum of
the electrostatic force (Eq. 12.10) generated by the
applied voltage and the mechanical spring restoring
force, Fm kx, due to the displacement of the resonator. When the electrostatic force is increased and the
resonator becomes more displaced, the spring restoring
force also increases leading finally to the equilibrium
position (Figure 12.11). However, when comparing
the electrical and mechanical forces in Figure 12.11 it
is evident that when the applied voltage exceeds a certain threshold value, the electrical force will always be
greater than the mechanical force and no equilibrium
position exists. The exact voltage corresponding to this
phenomenon is called the pull-in voltage, Upi.
The pull-in behavior is observed when the mechanical and electrical forces (and simultaneously also their
derivatives) cancel each other. In a static case with one
electrode it is given by
U pi km d 2
2C0
(12.26)
From Eqs 12.25 and 12.26 one can observe that the
pull-in voltage depends on the coupling strength and on
the mechanical spring constant. For capacitive switches the
pull-in phenomenon is desired and thus such devices are
usually designed for low pull-in voltages—however, low
pull-in voltage usually results in a mechanically soft structure which on the other hand reduces the operating speed
(frequency) of the switch. For capacitively coupled resonators the pull-in voltage limits the tunability of the resonance of the device. This limit can be seen by inserting the
value of the pull-in voltage (Eq. 12.25) into the equation
describing tuning (Eq. 12.15). In case of one electrode the
maximum frequency tuning is only in the order 16%, since
ω0
2
C0U Dc
kmd 2
ω0 1 UDCUpi
8
≈ 0.84ω0
1
27
|Fe|, U > Upi
|Fm|
2
Pull-in point
1.5
1
Equilibrium points
0.5
0
0
0.2
0.4
0.6
0.8
Relative displacement, x/d
Fig 12.11 ● Comparison between the electrostatic force (black
curves), Fe and mechanical spring restoring force (gray line),
Fm. When the bias-voltage is kept below the pull-in voltage,
increasing the displacement the mechanical spring restoring
force also increases and the system reaches equilibrium when
the forces are equal to each other. However, it is evident that
with increasing bias-voltage, the electrostatic force eventually
becomes larger than the mechanical spring restoring force and
the pull-in occurs.
(12.25)
Similarly, in a static case with the electrodes on both
sides of the moving device the pull-in voltage is
ω ω0 1 |Fe|, U = Upi
12.8 Parasitic Capacitance
8d 2 km
27C0
U pi |Fe|, U < Upi
2.5
Force, F (a.u)
12.7 Pull-in Phenomenon
3
CHAPTER 12
C0U 2pi
kmd 2
(12.27)
The capacitive coupling has a significant drawback. The
capacitor C0, which is used to couple electrical voltage
to the mechanical force, also conducts the drive current
across the capacitor. The equivalent circuit presented
earlier should therefore be corrected by a parallel capacitor, which has the same value as the coupling capacitance C0 (Figure 12.12).
The parasitic current is often much stronger than the
induced motional current (it is a problem, because both
currents oscillate at the same frequency). The ratio of
the induced motional current and parasitic current is
ˆi
m, R
îp
Q
2
U DC
ûac ωC02
kd 2
ω uˆac C0
2
QC0U DC
kd 2
(12.28)
Thus, high-Q, high DC-voltage and a narrow gap
help in improving coupling resulting simultaneously in a
lower parasitic current. In addition, we can see that the
AC-voltage has no effect on the motional to parasitic
current ratio. The effect of the parasitic capacitance can
also be seen from the frequency response of the resonator (Figure 12.13).
There are also other sources of parasitic capacitance
associated with the MEMS-resonators. Read-out electronics circuits are not usually directly integrated with
229
Modeling in MEMS
PA R T I I
MEMS, which means that we need for example bonded
wires and packaging to apply resonators. The result is
the increase of the parasitic capacitance.
One potential option to reduce the effect of parasitic capacitance could be to use a parametric amplification scheme, which means that the spring constant
is modulated with a frequency ωpump 2ω0/n, where
ω0 is the resonant frequency of the device and n is an
integer. Usually n 1 and the modulation of the spring
constant is performed at the frequency of ωpump 2ω0.
Then the parasitic current oscillates at frequency which
is different from the desired motional current resulting
in the situation that the parasitic capacitances may not
anymore be such a severe problem. The other possibility
is to use separate electrodes for driving and sensing. If
the (parasitic) capacitance between the drive and sensing electrodes is low and the resonator is AC-grounded,
most of the parasitic current can be eliminated (in the
case of integrated MEMS-resonators).
12.9 Effect of Built-in Potential
on Capacitively Coupled MEMSDevices
As the strength of the capacitive coupling and also
the effects of the capacitive nonlinearity are strongly
dependent on the bias-voltage, it is clear that the stability of the bias-voltage is essential when considering
the stability of electrostatically coupled MEMS-devices.
A DC biased capacitive coupling gap is shown in Figure
12.14. Here the system consists of a static electrode
and a vibrating electrode (resonator) and the static electrode is coated with a layer of dielectric. The system is
biased with a DC voltage UDC. However, in addition to
the applied bias voltage, UDC, the material parameters
(work-functions of the materials 1 and 2) and the
charges residing in the dielectric layer contribute to the
total bias voltage experienced by the coupling gap.
When calculating the total bias-voltage in the coupling gap d, we get the result
C0
U UDC ϕ12 Rs
Rm
Cm
QOX
C2
where UDC is the applied bias-voltage, 12 is the difference of the work-functions between the two electrodes,
QOX is the charge in the dielectric on top of the static
electrode and C2 is the capacitance over the dielectric.
The additional term to the applied bias-voltage UDC is
usually called the built-in voltage Vbi of the system
Lm
ZL
Fig 12.12 ● Electrical equivalent circuit of a resonator including
the drive signal and the parasitic capacitance parallel with the
RLC-tanks.
Vbi ϕ12
QOX
C2
(12.30)
180
–10
0.1 pF
90
10 fF
0
–55
1 fF
Phase (deg)
S21 (dB)
–32.5
0.1 fF
–90
–77.5
10 aF
–180
–100
5.100M
5.225M
5.350M
5.475M
5.600M
Frequency (Hz)
Fig 12.13 ● Influence of parasitic capacitance C0 on the transmission (frequency and phase) response of the resonator. The
feed-through capacitor C0 is varied in a range of [0…1 pF].
230
(12.29)
Electrostatic and RF-Properties of MEMS Structures
the resonance frequency of the device as can be seen
from Eq. 12.15. The effect could be further increased
if the coupling of the MEMS-devices is improved by
introducing the dielectric layers in the coupling gap
[13]. On the other hand, the spontaneous built-in voltage can also be useful, one such example is the vibrating
power harvester system utilizing built-in voltages [14].
UDC
(a)
Qox
xvib
Q2
ϕ1
V2
Static
electrode
(b)
Q1
ϕ2
d
V1
Vibrating
electrode
UDC
ϕ12
C2
C1
V2
V1
CHAPTER 12
Fig 12.14 ● . (a) Schematic view of a DC-biased capacitive RFMEMS device illustrating various contributions to the total bias
voltage over the air gap and (b) a simplified electrical equivalent
circuit for the system. Source: Reproduced from [7] with
permission from IOP Publishing Ltd.
Equation 12.29 reveals that Vbi plays a role in the stability of various MEMS-devices. Even though its origin is
rather well known, the effect on the stability has been
much less studied. Built-in voltages are generated when
two dissimilar materials are brought into contact—it is
in principle a direct measure of the difference in the
work functions [2]. In practice, however, the observed
work functions are modified due to the thin layers of
dielectrics present on the surfaces [3, 4] and vary as a
function of the temperature and due to the adsorbents
on the surfaces [5, 6]. Therefore, for many practical
cases experimental methods are needed to unambiguously determine the built-in potentials of the interfaces.
A good example of the effect of the built-in potential in case of a capacitive accelerometer is shown in
Figure 12.15 [7]. Here the built-in potential causes
the displacement of the proof-mass even in the case of
zero acceleration of the device. The built-in potential
has also been seen to affect the stability in the MEMSbased voltage-references [8, 9] with what some practical
solutions have been found to minimize its effect [10].
For RF-MEMS switches the effect of built-in potential
could become an issue by modifying the threshold value
of the pull-in voltage, but can also lead to stiction due to
the charging of the dielectrics [11, 12]. A similar effect
takes place in MEMS-resonators where this voltage
modifies the electric spring constant and thus changes
12.10 Further Effects of
Electrostatic Nonlinearities
from Applications Point of View
Electrostatic nonlinearities discussed earlier can generate harmful side-effects in capacitively coupled devices.
In the following, these effects are studied in detail with
respect to the two perhaps most promising application
areas of MEMS-devices in RF-electronics which are filters and reference oscillators.
12.10.1 Case 1: Capacitively
Coupled Filter
The narrow resonance of MEMS-resonators gives the
possibility of using them as highly selective bandpass filters. With proper biasing, the input signals at the resonance frequency of the resonator will introduce a force
that is amplified by the quality factor Q of the resonator and therefore the signals at this frequency will be
transmitted to the readout electronics. On the other
hand, the signals lying outside the resonance passband
will generate significantly weaker force and are in principle rejected (Figure 12.16a). If a broader passband is
required, it can be achieved by parallelizing resonators
since the capacitive coupling provides a simple method
to couple the input and output signals as long as the
impedance matching is taken care of. However, the nonlinearity of the capacitive coupling can seriously deteriorate the performance of the filter due to the introduced
intermodulation distortion (IM).
The intermodulation distortion is responsible for converting the off-resonance signals into the resonance band.
This is especially harmful in the case of filter-applications
where those signals that are outside the filter passband
would be converted inside the passband (Figure 12.16b).
The third order nonlinearity that arises from the
capacitive coupling brings along intermodulation distortion even when the vibration is in the linear regime.
This can be seen by writing a Taylor’s expansion of the
coupling gap capacitance C as
C
⎛
Aε0
x
⎜
≈ C0 ⎜⎜1 ∓
⎜⎝
(d ± x)
d
⎛ x ⎞⎟2 ⎛ x ⎞⎟3
⎜⎜ ⎟ ∓ ⎜⎜ ⎟
⎝⎜ d ⎟⎠
⎝⎜ d ⎟⎠
⎞⎟
�⎟⎟⎟
⎟⎠ (12.31)
231
Modeling in MEMS
PA R T I I
(a) 8.42
8.4
Vbi = Avg(Vpi2 +Vpi1)
Vbi = (–1.51+ 0.1) / 2
Vbi = –705 mV
Capacitance (pF)
8.38
8.36
8.34
8.32
Vpi2
Vpi1
y = 0.03x2 + 0.0437x + 8.3028
Vbi = –0.0437/(2*0.03)
Vbi = –728 mV
Vbi determined by
parabolic fit
Vbi determined by pull-in
8.3
8.28
–2.5
–1.5
–0.5
0.5
1.5
2.5
Applied voltage (V)
(b)
(c)
(d)
Vbi
Vbi
UDC
UDC
U
Fig 12.15 ● (a) In capacitive sensors the built-in potential manifests itself as a zero-point offset that can be observed by measuring the
capacitance of the sensor as a function of the applied bias-voltage UDC. (b) The capacitance is at minimum when UDC Vbi. (c) When
UDC Vbi the capacitance increases due to the electrostatic force. (d) When the voltage between the electrodes (U UDC Vbi)
exceeds the pull-in voltage, the electrostatic force draws the electrodes into contact. Source: Reproduced from [7] with permission from
IOP Publishing Ltd.
fr + Δf
f
Fig 12.16 ● (a) Operating principle of a microelectromechanical
resonator used as a filter. The signals within the resonance band
of the device are transmitted to the readout electronics while the
signals outside the resonance band are rejected. (b) The principle
of third order intermodulation generation. The cubic mixing due
to the capacitive nonlinearity of the electrostatic transduction
converts the signals outside the resonance band into the
resonance band.
232
where C0 is the coupling gap capacitance at rest or
C0 A0/d.
In practice if two signals at frequencies
ω1 ωres Δω, ω2 ωres 2Δω are coupled to the resonator acting as a filter the cubic (third order) mixing of
these signals produces in addition to other contributions
a third-order term at frequency 2ω1 ω2 which is identified as ωres. It is the resonant frequency of the device;
therefore, the signal possessing this frequency will be
transmitted through the system. This process of IM3
(third order intermodulation distortion) product generation is depicted in frequency domain in Figure 12.16b.
To quantify the strength of capacitive nonlinearity, a
parameter called the third order intercept point (IIP3) can
be measured. It is a measure of how strong off-resonance
interferers at frequencies ω1 and ω2 are needed in order
to produce equally strong signal in the carrier frequency
as if the same power was applied directly at the carrier
Electrostatic and RF-Properties of MEMS Structures
CHAPTER 12
Linear fits to the measured
IM products
30
Output signal, Vout (dBmV)
10
–10
Direct excitation
of the resonator
–30
–50
Measured
intermodulation
products
–70
Δω = 1 kHz
–90
–110
Δω = 200 Hz
–130
–150
–30
Δω = 20 kHz
–20
–10
0
10
20
30
40
50
Input signal,Vin (dBmV)
Fig 12.17 ● Method of determining the IM3 product that is caused by the capacitive nonlinearity due to the electrostatic transduction.
The IM3 product is characterized at three different separations Δω [20, 1000, 20000] Hz from the resonant frequency ω.
frequency. Schematically this is depicted in Figure 12.17.
The intermodulation in capacitive devices is studied for
example in Refs. [15–18].
Capacitively coupled silicon microresonators have been
studied as a replacement for piezoelectric quartz crystals
as a central component in reference oscillators for quite
some time. It has been shown, that the silicon microresonators are capable of competing with the macroscopic
quartz resonators both in terms of short-term stability
[19–22] and in long-term stability [23–25]. However,
the capacitive coupling used with silicon microresonators brings an interesting contribution to the short-term
instability.
The short-term stability dictates the spectral purity
of the signal. It is usually specified through the phasenoise referenced at carrier power at certain offset
from the carrier frequency (Figure 12.18). For example in order to meet the GSM-specifications [26] for
the receiver sensitivity and blocking, a 13 MHz reference oscillator must meet the phase-noise specifications Lf 130 dBc/Hz at Δf 1 kHz offset from the
carrier and L 150 dBc/Hz far away from the carrier (so called noise floor) [20]. The strict phase-noise
requirements arise from the fact that for practical use
the output frequency of an oscillator is multiplied in a
phase-locked loop (PLL) to match the carrier frequency
(e.g., 900 MHz for GSM-900) and naturally the existing low-frequency noise becomes multiplied in a same
process.
Noise floor
L ∝ 1ω 3
m
Lf
L (dBc/Hz)
12.10.2 Case 2: Capacitively Coupled
Reference Oscillator
Carrier level
1
L∝ ω2
1
L∝ ω1
m
m
1
L∝ ω0
m
Δf
1
Frequency offset from carrier (Hz)
Fig 12.18 ● Definition of SSB (single-side-band) noise. The
nonlinear mixing of the low-frequency 1/f noise increases the
near carrier noise and changes the slope of the near carrier
phase-noise from 1/ω2 to 1/ω3.
Typically the single-sideband phase-noise-to-carrier
ratio for an ideal oscillator can be approximated by
Leeson’s equation [27, 28]
L(Δω) 2
1 kb T ⎛⎜ ω0 ⎞⎟
⎟⎟
⎜⎜
4π Evib ⎝QΔω ⎟⎠
(12.32)
from which two important factors can be seen:
(i) in practice the phase-noise reflects the competition
between the mechanical energy Evib of the resonator
and thermal noise kbT and (ii) the width of the resonance (1/Q) leads to a bandpass filtering of the noise
reducing the noise as the frequency difference to the
carrier Δω increases.
233
Modeling in MEMS
PA R T I I
In a more generic form of Eq. 12.32 the noise voltage
includes also the noise contribution from the amplifier
electronics.
L(Δω) 2 ⎡
2
⎢⎛⎜ ω0 ⎞⎟⎟
⎜
⎟
2 ⎢
uac ⎢⎣⎜⎝ 2QΔω ⎟⎠
un
⎤
1⎥⎥
⎥⎦
(12.33)
where uac is the signal voltage which is usually limited
by the nonlinearities of the reference component (i.e.,
MEMS resonator) and un is the total noise voltage.
From Eq. 12.33 the phase-noise can be seen to decrease
as 1/ω2. However, for capacitively coupled devices Eq.
12.33 does not take into account the effect of aliasing
of the 1/f noise due to the capacitive coupling. In the
capacitive transduction gap, the 1/f noise is mixed with
the signal voltage produced by the resonator giving an
additional noise term. A more accurate equation for the
dual side-band noise has been presented in [29] as
L(Δω ) un
2
uac
2
Z0
US
ZSW
U1
Z0
U2
ZL
UL
Fig 12.19 ● Micromechanical switch (impedance ZSW) connected
in series with the transmission line. The transmission line
(impedance Z0) is assumed to be perfectly matched to the
source and load impedances, ZS and ZL, respectively.
ZS
US
Z0
Z0
U1 ZSW
U2
ZL
UL
Fig 12.20 ● A micromechanical switch (impedance ZSW)
connected in parallel (shunt) with the transmission line. The
transmission line (impedance Z0) is assumed to be matched to
the source and load impedances ZS and ZL, respectively.
.
2
⎡
⎢⎛⎜ ω0 ⎞⎟⎟ ⋅ ⎛⎜1
⎜
⎢⎜
⎟ ⎜
⎢⎣⎝ 2QΔω ⎟⎠ ⎜⎝
2
2
uac
2 Γ Rm
2
ωc ⎞⎟
⎟
Δω ⎟⎠
⎤ (12.34)
1⎥⎥
⎥⎦
which leads to Eq. 12.33 using an aliasing factor 0.
One can deduce from Eq. 12.34 that the phase-noise
will decrease as 1/ω3 instead of 1/ω2 as is the case in
Eq. 12.33 due to the mixing of low-frequency amplifier
noise present at the resonator input in the capacitive
transduction gap. This can easily increase the near carrier noise by more than 30 dB [30]. It is evident from
Eq. 12.34 that increasing the vibration amplitude does
not help with aliasing of 1/f noise when it comes to the
noise that is very close to the carrier frequency as it is
produced by mixing of the thermal noise and the signal produced by the resonator. However, the noise floor
becomes lower by increasing the vibration energy of the
resonator. Therefore, if capacitive transduction is used
to realize an oscillator, attention must be paid to minimize the low-frequency noise of the amplifier or filter
the noise prior to reaching the resonator.
12.11 RF-Properties
RF-properties are studied from switching point of view.
The intention of this chapter is to discuss some aspects
related to the RF-properties, but to be in no way a comprehensive study of the RF-properties of MEMS-devices.
A micromechanical switch is usually a MEMS-tunable
capacitor that operates either in series or in shunt-mode.
A series switch, (Figure 12.19) is used to shortcut (in onstate) or isolate (in off-state) the signal pathway between
the input and the output in a transmission line. A shunt
234
ZS
switch (Figure 12.20) shortcuts the transmission line to
the ground (in off-state) or isolates the transmission line
from the ground (in on-state). In the following, some RFparameters are derived for both series and shunt switches.
Again, the devices used are capacitively actuated even
though the actuation principle does not significantly affect
the studied parameters. It should also be noted, that the
following is true for a contact switch where in the downstate the switch makes a metal–metal contact between
the terminals of the switch and in the up-state the terminals are separated from each other by an air gap showing
significant capacitance between the terminals.
The RF-properties are usually characterized by such
concepts as isolation (ISOL), insertion loss, (IL) and reflection. Actually both the isolation and insertion loss describe
the forward power transmission, S21, of the switch, but
the difference is that isolation refers to the case when the
switch is in the off state and insertion loss is defined when
the switch is in the on state. The switch can be represented
as a transmission line with impedance ZSW in Figure 12.19.
The forward transmission can be calculated as
S21 U2
2U L
U1
US
(12.35)
Equation 12.35 assumes that the transmission
line is matched to the source and load impedances or
ZS ZL Z0.
When the voltage at the load UL is calculated the forward power transmission gets the value
S21
2
1
1
Z SW
2Z0
2
(12.36)
Electrostatic and RF-Properties of MEMS Structures
When a MEMS-switch is in the down-state, the
switch can be represented by the resistance RS of the
metal–metal contact of the switch. With this, the insertion loss of the series switch becomes
R
≈ 1− S
Z0
down 2
S21
IL ISOL up 2
S21
2
≈ (2ωCS Z0 )
(12.38)
From Eqs 12.37 and 12.38 it is clear that the isolation and the insertion loss of a contact switch can be
determined by the contact resistance RS and the upstate capacitance CS of the switch.
For a parallel (shunt) switch in Figure 12.20 the operation principle is opposite—when the switch is closed, it
provides a large capacitance (usually in the pico farads) to
the ground and the source signal is therefore shorted to the
ground. When the switch is in the open-state, the capacitance to the ground is small (usually in the femto farads)
and the switch does not affect the signal in the transmission line—therefore, the electrical equivalent of a capacitive shunt switch is a parallel capacitor in the up-state and a
parallel connected series resonant circuit in the down-state.
The forward power transmission is given in Eq. 12.39:
S21
2
1
Z0
2Z SW
1
2
(12.39)
ISOL ⎛ 2Z SW ⎞⎟2
⎟
≈ ⎜⎜⎜
⎜⎝ Z ⎟⎟⎠
(12.40)
0
As previously stated, in the down-state, the switch
can be represented with a resonant circuit; therefore,
the impedance of a down-state switch can be written as
Z SW RP
jω LP
1
jωCP
1
2π
1
LP CP
(12.43)
and the isolation is the given by
⎪⎪⎧⎛ 2 ⎞2
⎟⎟ , f � f
⎪⎪⎜⎜
LC
⎪⎪⎝⎜⎜ ωCP Z0 ⎠⎟⎟
⎪⎪
2
⎪⎛
⎪ 2R ⎞
down 2
≈ ⎨⎜⎜⎜ P ⎟⎟⎟ , f fLC
ISOL S21
⎪⎪⎜⎝ Z0 ⎟⎠
⎪⎪
2
⎪⎛
⎪⎪⎜ 2ωLP ⎞⎟⎟ , f � f
LC
⎪⎪⎜⎜⎜ Z ⎟⎟
⎝ 0 ⎠
⎩⎪⎪
(12.44)
The insertion loss for the up-state switch is mainly
the loss of the transmission line and, therefore, not
determined by the switch itself. However, in addition
2
the power reflection S11 from the switch must be
taken into account according to
S11
2
1
2
(12.45)
⎛ ωC Z ⎞2
≈ ⎜⎜ U 0 ⎟⎟⎟
⎜⎝ 2 ⎠
(12.46)
1
2Z SW
Z0
or
2
where CU indicates the capacitance of the up-state (or
open) switch.
In addition an important figure of merit in terms of
switches, the so called cutoff frequency, fc, should be
noted. It is usually determined by the resistance and
capacitance of the switch as
f 1 1
2π CS RS
(12.47)
(12.41)
where the resistance, inductance and capacitance
denoted with a subscript P indicate the values for downstate switch (connected in parallel). The isolation of the
switch can be calculated in three frequency ranges, determined by the LC series-resonant frequency of the switch
fLC ⎧⎪ 1
⎪
, f � fLC
⎪⎪⎪ jωCP
Z SW ⎪⎨ RP , f fLC
⎪⎪
⎪⎪ jω LP , f � fLC
⎪⎪
⎪⎩
S11
By using the condition defined as ZSW Z0 the isolation becomes
down 2
S21
Therefore, the impedance of the switch becomes
(12.37)
In the up-state, the switch becomes a capacitor with
a capacitance of CS and the isolation can be calculated as
CHAPTER 12
(12.42)
The cutoff frequency is the frequency where the ratio of
the up-state to the down-state impedance becomes unity.
However, as one can deduce from Eq. 12.47 this definition
of the cutoff frequency is actually valid for series switches
and for MEMS shunt switches the cutoff frequency is not
strictly applicable as the switch inductance usually limits the down-state performance before fc. Due to this and
because the MEMS shunt switches usually result in acceptable isolation up to twice their LC resonance frequency,
this limit or 2·fLC is used instead of fc [31].
235
PA R T I I
Modeling in MEMS
Acknowledgments
The authors would like to thank the following people for
the collaboration in the research that has led among other
things to the results discussed in this chapter: Nikolai
Chekurov, Osmo Vänskä, Ville-Pekka Rytkönen, Pekka
Rantakari, Tuomas Lamminmäki, Tomi Mattila, Aarne
Oja, Ari Alastalo, Heikki Seppä, Jyrki Kiihamäki, Hannu
Kattelus and Ville Kaajakari.
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237
13
Chapter Thirteen
Optical Modeling of MEMS
Timo Aalto and Juuso Olkkonen
VTT Technical Research Centre of Finland, Espoo, Finland
Optics is related to the processing of silicon MEMS in
many ways. For example, photolithography is used to
pattern MEMS structures, while ellipsometry and optical microscopy are used to characterize them. However,
the use of optics in the fabrication or characterization
of nonoptical MEMS is not discussed in this chapter.
Instead, we concentrate on the theory and modeling of
optical MEMS structures. A typical example of optical
MEMS (or micro-optical-electromechanical systems,
MOEMS) is a movable mirror on silicon. However, we
extend the concept of optical MEMS to also cover static
optical structures that are realized on silicon with similar processing methods as those used in the fabrication
of movable MEMS structures. Such structures include
static mirrors and lenses, optical thin film stacks, gratings, waveguides and pixel detectors.
Chapter 13 is divided into three main parts. In Section
13.1 we briefly review the optical properties of silicon
and some other materials commonly used in MEMS.
Next, in Section 13.2, we summarize the fundamental
theory of optics to create the necessary background for
understanding the practical implementation of optical
modeling of MEMS. Finally, the optical modeling methods for silicon-based MEMS are presented in Section
13.3 and illustrated with practical application examples.
The examples also serve to provide an overview of typical optical components realized with MEMS technology.
Due to the complexity of rigorous optical theory, the
vast number of modeling methods, and the large variety of optical applications somehow related to MEMS
only a coarse overview of the optical modeling methods
for MEMS can be provided here. To get a deeper understanding of the underlying theory, modeling methods
or applications we encourage the reader to resort to the
specific books written about topics such as the fundamentals of optics and photonics [1, 2], optical properties of silicon and other materials [3], numerical
modeling [4–9], MOEMS [10], integrated optics [11–13]
and silicon photonics [14, 15].
13.1 Optical Properties of Silicon
and Related Materials
In this chapter we review the most relevant optical
properties of silicon and the ways to manipulate them.
The optical properties of some other materials commonly used in optical MEMS, such as silicon dioxide
and silicon nitride, are also briefly reviewed. We concentrate on the bulk properties, but one should take
into account that thin films and microstructures, such
as waveguides, may have somewhat different properties depending on their process parameters, dimensions,
geometry and stress distribution. The two fundamental
optical parameters considered here for any material are
the refractive index n and the extinction coefficient k.
Together they define the complex refractive index
nc = n + ik. The real (1) and imaginary (2) part of the
complex dielectric constant (c) are linked to n and k via
2
εc = ε1 + iε2 = ( n + ik)
(13.1)
Absorption coefficient α provides a simple factor
eαz that represents intensity attenuation when light
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Modeling in MEMS
PA R T I I
propagates along the z-axis. It is linked to the extinction
coefficient k and the free space wavelength (λ0) of
light via
α = 4πk λ 0
Most non-metallic solids have two main absorption
mechanisms, namely, electronic transitions and lattice
vibrations. When the wavelength is so short that the photon energy exceeds the electronic bandgap of the material, the photons can excite electronic transitions across
the bandgap and the absorption becomes very large. On
the other hand, smaller photon energies can efficiently
excite lattice vibrations. Between these wavelength
regions of high absorption there is typically a relatively
wide spectral range where both absorption mechanisms
are negligible and the material is optically transparent.
However, some smaller absorption can also be seen in
this region because of material impurities, lattice defects,
multiphonon absorption or phonon-assisted electrical transitions. In case of high optical intensity some
nonlinear multiphoton absorption processes can also
be seen.
(13.2)
The impact of any other parameters is evaluated
through their influence on n and k. Manipulation of
light propagation is most often based on the tuning of either one of these fundamental parameters in
the medium where light propagates. The wavelength
dependencies of n and k are related to each other via
the Kramers–Kronig relation [1] (p. 179), which enables the calculation of chromatic dispersion (i.e., wavelength dependence of n) from a measured absorption
spectrum.
Sometimes it is convenient to express the absorption
α in decibels per centimeter (dB/cm), especially when
the absorption is very small and light propagates a long
distance inside the material. The conversion from the
standard SI units (1/m) can be made with the formula
α(dB cm ) = 10 ln (10) × α(1 m) =
k × 0.4π
⎡λ0 ln (10)⎤
⎣
⎦
13.1.1 Optical Properties of Silicon
The n and k of silicon are plotted as a function of wavelength in Figure 13.1. In the near-IR region, where Si is
transparent, the monotonic reduction of n between 3.6
and 3.4 as function of λ can be approximated with the
Sellmeier-type dispersion formula
(13.3)
In decibel units the propagation of length L in the
material of device 1 produces a total absorption loss
of α1 αL(dB). The transmission coefficient T for
the device is simply the opposite number of the loss
(T1 α1). The total optical loss of successive components can be calculated by simply summing up the
individual losses (αtotal α1 α2 …). In standard
SI units the transmission of device 1 is T1 eαL and
the total transmission through successive components is
obtained by multiplying (Ttotal eα1α2α3…).
8
6
n 4
0.001
3
0.0001
2
0.00001
1
(a)
3.55
1
10
Wavelength (μm)
0.00810461λ12
λ 2 − λ12
(13.4)
0.01
Sellmeier fit
0.001
3.5
0.0001
k
n 3.45
0.00001
3.4
0.000001
3.35
0.0000001
100
3.3
0.1 dB/cm
+
0.1
0.01
5
λ
2
3.6
1
10 dB/cm
0.939816
where λ and λ1 1.1071 μm are given in micrometers. Bandgap absorption becomes strong at approximately 1.2 μm. Thus, silicon is opaque at λ 1.2 μm
and not a suitable transmission medium for visible light,
for example. For near infrared wavelengths between
10
Sellmeier fit
7
0
0.1
n 2 = 11.6858 +
10 dB/cm
0.1 dB/cm
(b)
k
0.000001
0.0000001
0.00000001
1 1.5 2 2.5 3 3.5 4 4.5 5
Wavelength (μm)
Fig 13.1 ● Refractive index n and extinction coefficient k of bulk silicon as a function of wavelength (data taken from literature [3]).
The two figures show different parts of the wavelength spectrum. The circles correspond to the analytical dispersion formula based
on the Sellmeier coefficients. A vertical line is drawn at 1.2 μm to illustrate the edge of the transparent region. The other straight lines
correspond to the 0.1 and 10 dB/cm absorption limits.
240
Optical Modeling of MEMS
approximately 1.2 and 4 μm the absorption of undoped
silicon is negligible (0.01 dB/cm). Above 4 μm the
absorption again starts to increase due to multiphonon
absorption. The wavelength range between approximately 6 and 20 μm includes several multiphonon
absorption peaks that partially overlap with each other,
as well as some absorption peaks caused by oxygen and
carbon impurities. At low temperatures the multiphonon
absorption peaks become somewhat smaller and narrower. Between approximately 20 and 100 μm the absorption is fairly constant, so that k increases approximately
linearly with λ.
The absorption of silicon is strongly dependent on
doping. In microelectronics and MEMS it is often preferred to use doped silicon that has lower resistivity
than undoped silicon. However, the free carriers (electrons and holes) in doped silicon absorb light, which
makes undoped silicon the preferred choice for optical
MEMS if light should propagate through silicon. The
relationship between resistivity and absorption is illustrated in Figure 13.2.
13.1.2 Manipulation of Silicon’s
Optical Properties
There are many ways to manipulate the optical properties
of silicon. Often the simplest way to change n is heating. The thermo-optical constant [18] of 1.86.104 K1
and the thermal conductivity [16] (p. 54) of
1.41 Wcm1K1 are both quite high in silicon, which
enables very efficient and relatively fast thermal tuning of
the refractive index.
CHAPTER 13
As explained before (see Figure 13.2), absorption
in silicon depends on doping and the related density
of free carriers. One can therefore change the absorption by electrically injecting free carriers into silicon.
This also induces a refractive index change that can be
exploited if the density of free carriers is so low that all
light is not absorbed. These effects are commonly used
to integrate amplitude and phase modulators into silicon
waveguides. This is a much faster process than thermal
tuning and with small silicon waveguides modulation
frequencies of several GHz have been demonstrated.
The optical properties of silicon can also be tuned with
an externally applied electric or magnetic field, or even
with the light itself. The linear electro-optic (Pockels)
effect in silicon is normally negligible. However, by
breaking the crystal symmetry with stress, for example,
it is possible to somewhat tune the refractive index with
an externally applied electric field. However, the nonlinear optical effects [19] are much stronger and more
commonly used. When the optical intensity in silicon
becomes sufficiently high, the two-photon absorption
starts to cause losses or cross-amplitude modulation.
Also, light propagating in silicon can generate free carriers, which then cause free carrier absorption and refractive index changes. These effects lead to cross-amplitude
modulation and cross-phase modulation. If light propagating in silicon has high intensity and at least two
frequency bands, then new frequency bands can be generated around them via four wave mixing. Finally, the
interaction of the photons with the phonons of the silicon lattice causes Raman scattering, which enables the
realization of Raman lasers and Raman amplifiers.
13.1.3 Optical Properties of Other
Materials Commonly Used in Optical
MEMS
Figure 13.2 ● Absorption of bulk silicon at 1550 nm wavelength
as a function of resistivity, based on the approximation that the
free carrier density is equal to the dopant density. The two curves
correspond to P and B doped silicon, also known as p and n
type silicon, respectively. The data is collected from [16] (Figure
1.14) and [17].
In addition to silicon, many other materials are used in
optical MEMS. Some of the most important materials are crystalline silicon dioxide (SiO2, quartz), amorphous silicon dioxide (SiO2, fused silica), silicon-rich
silica (SiOx), silicon nitride (Si3N4), silicon oxynitride
(SiOxNy), and PyrexTM. Typical unwanted or intentional
impurities in silica are hydrogen, boron, sodium, potassium, and lead. The transparent region of quartz and
pure silica reaches from UV to near IR wavelengths. In
practice, however, the impurities cause several absorption peaks. Thus, proper deposition and processing
methods must be selected based on the wavelength
range of the given application.
For silicon dioxide, the n and k spectra are illustrated
in Figure 13.3. For other materials the reader can find
corresponding data, for example, from Ref. [3].
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Modeling in MEMS
PA R T I I
n
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
10
0.1
Quartz (ordinary ray)
k 0.01
Glass
Glass
0.001
10 dB/cm
0.0001
0.5
0.1
(a)
Quartz (ordinary ray)
1
1
Wavelength (μm)
10
0.00001
0.1
1
10
Wavelength (μm)
(b)
Figure 13.3 ● Refractive index n (a) and extinction coefficient k (b) of silicon dioxide as a function of wavelength. The data are taken from
literature [3] separately for crystalline SiO2 (quartz) and amorphous SiO2 (glass).
13.2. Theoretical Background
ni
Before presenting any details of optical MEMS structures or their modeling methods, we shall first summarize the fundamentals of the related optical theory.
By dropping off one approximation after another we
proceed from simple ray optical principles towards
full-vectorial fields and quantum optics. To simplify the
discussion we assume that the absorption of the propagation medium is negligible, unless otherwise stated.
ni
nt
qr
qt
qi
nt
qt
qr
qi
nt > ni
nt < ni
Figure 13.4 ● Reflection and refraction of optical rays at a planar
interface separating two transparent media characterized by
refractive indices ni and nt. When nt ni, the refracted ray bends
toward the surface normal, while for nt ni, the refracted ray
bends away from the normal.
13.2.1 Geometrical Optics
The simplest model for representing light propagation
is called geometrical optics. It describes light as rectilinear rays and is therefore also known as ray optics. Light
propagates along the rays with a velocity of c/n, where c
is the velocity of light in vacuum (sometimes denoted
with c0) and n is the refractive index that describes how
light slows down in a given propagation medium. For
vacuum n 1 and for most optically transparent materials 1 n 4. The duration of light propagation over
a physical distance of L is nL/c, where nL is the corresponding optical path length. For nonuniform medium
the propagation time is calculated by the integral
1
n( x, y, z)dL
c ∫L
(13.5)
Even in geometrical optics, it