University of Maryland Baltimore County
CMPE 415
Programmable Logic Device
Spring 2021
HW1: Tools Introduction
In this homework, students working in identified pairs are allowed to collaborate without restriction
on this assignment but each students should install the software and complete steps on their
computer and submit independently. Submission instructions are TBD, but expect them soon (back
up your work in the meantime).
The objective of this lab is to learn the fundamental components of the Xilinx FGPA tools required
to enter and assemble HDL code and program an FPGA. This includes integrating HDL into a
schematic, as well as creating and updating symbols.
Install Xilinx Vivado and drivers.
In this lab you will program an FPGA to display LEDs counting in the binary number sequence. You
will first implement the design that you are given on the FPGA. This code can be used to play
around with Xilinx Vivado tool and also explore Verilog.
You are then expected to modify this code in such a way that the FPGA leds change its values only
when a push button (which was initially a flip-switch in the code given to you) is clicked.
Start Xilinx Vivado:
On windows go to start and search vivado 2019.2
On linux:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
vivado
Create New Project
1. In main window menu: File->New Project...
2.
3.
4.
5. You’ll now need to enter information about the FPGA. You can look in the reference
manual to find the information https://reference.digilentinc.com/reference/programmablelogic/nexys-4-ddr/reference-manual or you can use the board support files if you downloaded
and installed them:
6. The next screen shows a summary.
7. Hit Finish. Result:
Download the verilog & xdc file and Add to project
1. Download the Verilog file from below link,
https://drive.google.com/drive/folders/1wICIhDkF_Da8bKeem7d-rZE3iGoTWCri?usp=sharing
Then go to the HW1 and download blinky.v & timing.xdc
2. Add the source to the project using File-> Add Sources...
3. We will use the second option:
4. Click Add Files
navigate to src dir (e.g. D:/Xilinx_2/projects/project_3) and select the blinky.v file
You now have a new Design Source listed
Add constraints file
We will now create a second source file.
1.
Add a source as before, but this time select Add or create constraints
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Final picture after adding constraints
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Now go to RTL Analysis >- Open Elaborated Design >-ok
You will get a Elaborated design as below. This can be used to visualize the rtl that was written in the blinly.v.
❖
Next, SYNTHESIS>-Run Synthesis
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After completing the synthesis Run IMPLEMENTATION>-Run
Implementation
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After Successfully completing implementation, PROGRAM AND
DEBUG>-Generate bit stream
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Then Open Hardware Manager>-Open Target>-Auto connect
❖
Program device
Demonstration
Your Design Assignment
In the code that was given, the LEDs light up in the binary number sequence for as long
as the start switch (L16 on FPGA) is in its ON position. Modify this code in such a way
that the FPGA LEDs change the values only when a start push button (which was
initially a flip-switch in the code given to you) is clicked. You can pick the center push
button as it shows in the video. The pin location of the center button in the xdc file in
N17. You need to change both the blinky.v Verilog code and the xdc file in the project so
you can make this changes in the design work on the FPGA. Once you made the
changes you are going to repeat all steps to synthesize, implement and program the
FPGA.
What to return
1. Written Report Document: A word or pdf report document explaining what you did and
how you changed the code to make the new design working.
2. Clearly Explain in the Report On the Top of the page, if your design is Functional on
FPGA or not. If only the first part works and second you also need to clarify.
3. Submit the zipped file of the whole project in Blackboard so the TA can open the
project for grading.
Please NOTE if the TA can not open your project or can not demonstrate your project on
FPGA there is no guarantee for a grade. So please make sure all your assignments have
all required files and can be implemented on another machine.
Grade Breakdown
1. 15% Clear Report with explanation and blockdiagram and pictures. Also explain
whether the design is functional on board or not.
2. 50% Complete Project filles and FPGA demonstration of the Tutorial
3. 25% FPGA Demonstration of the complete design for the assignment