Diagonal 7.77 mm (Type 1/2.3) CMOS Image Sensor with Square Pixel for Color
Cameras
IMX206CQC
Description
AL
The IMX206CQC is a diagonal 7.77 mm (Type 1/2.3) CMOS image sensor with a color square pixel array and
approximately 16.35 M effective pixels. 12-bit digital output makes it possible to output the signals of approximately
16.35 M effective pixels with high definition for shooting still picture.
Furthermore, it realizes 10-bit digital output for shooting high-speed and high-definition moving pictures by horizontal
and vertical binning and subsampling. Realizing high-sensitivity, low dark current, this sensor also has an electronic
shutter function with variable storage time.
In addition, this product is designed for use in consumer use digital still camera and consumer use camcorder. When
using this for another application, Sony does not guarantee the quality and reliability of product.
Therefore, don't use this for applications other than consumer use digital still camera and consumer use camcorder.
In addition, individual specification change cannot be supported because this is a standard product.
Consult your Sony sales representative if you have any questions.
TI
Features
C
O
N
FI
D
EN
◆ CMOS active pixel type pixels
◆ Input clock frequency can be selected from 72 MHz / 36 MHz / 24 MHz / 12 MHz
◆ Vertical arbitrary cropping (All-pixel scan mode)
◆ Horizontal arbitrary cropping
◆ High-sensitivity, low dark current, no smear, excellent anti-blooming characteristics
◆ Variable-speed shutter function (minimum unit: 1 horizontal sync signal period (1XHS))
◆ All-pixel simultaneous reset supported (use with mechanical shutter)
◆ H driver, V driver and serial communication circuit on chip
◆ CDS/PGA on chip. Gain +24 dB (step pitch 0.1 dB)
◆ 10-bit/12-bit A/D conversion on chip
◆ R, G, B primary color mosaic filters on chip
◆ 80-pin small low-profile ceramic package (thickness of 1.52 mm)
* “Exmor R” is a trademark of Sony Corporation. The “Exmor R” is a Sony's CMOS image sensor with significantly enhanced imaging
characteristics including sensitivity and low noise by changing fundamental structure of “ Exmor” pixel adopted column parallel A/D converter
to back-illuminated type.
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.
1
IMX206CQC
Device Structure
◆ CMOS image sensor
◆ Image size
Diagonal 7.77 mm (Type 1/2.3)
◆ Total number of pixels
4768 (H) × 3516 (V) approx. 16.76 M pixels
: 4672 (H) × 3500 (V) approx. 16.35 M pixels
: 4672 (H) × 2780 (V) approx. 12.99 M pixels
: 3712 (H) × 2780 (V) approx. 10.32 M pixels
: 2176 (H) × 1612 (V) approx. 3.51 M pixels
◆ Number of active pixels
- Type 1/2.3 approx. 16.35 M pixels use
- Type 1/2.5 approx. 12.99 M pixels use
- Type 1/3 approx. 10.32 M pixels use
- Type 1/5 approx. 3.51M pixels use
: 4632 (H) × 3492 (V) approx. 16.17 M pixels diagonal 7.77 mm
: 4632 (H) × 2772 (V) approx. 12.84 M pixels diagonal 7.23 mm
: 3672 (H) × 2772 (V) approx. 10.18 M pixels diagonal 6.17 mm
: 2136 (H) × 1604 (V) approx. 3.43 M pixels diagonal 3.58 mm
◆ Number of recommended recording pixels
- Type 1/2.3 approx. 16.35 M pixels use
- Type 1/2.5 approx. 12.99 M pixels use
- Type 1/3 approx. 10.32 M pixels use
- Type 1/5 approx. 3.51 M pixels use
: 4608 (H) × 3456 (V) approx. 15.93 M pixels aspect ratio 4:3
: 4608 (H) × 2736 (V) approx. 12.61 M pixels aspect ratio approx. 16:9
: 3648 (H) × 2736 (V) approx. 9.98 M pixels aspect ratio 4:3
: 2112 (H) × 1584 (V) approx. 3.35 M pixels aspect ratio 4:3
AL
Number of effective pixels
- Type 1/2.3 approx. 16.35 M pixels use
- Type 1/2.5 approx. 12.99 M pixels use
- Type 1/3 approx. 10.32 M pixels use
- Type 1/5 approx. 3.51 M pixels use
TI
◆ Chip size
8.30 mm (H) × 6.72 mm (V)
EN
◆ Unit cell size
1.34 µm (H) × 1.34 µm (V)
N
FI
D
◆ Optical black
Horizontal (H) direction : Front 48 pixels, rear 0 pixel
Vertical (V) direction : Front 16 pixels, rear 0 pixel
O
◆ Substrate material
Silicon
(Top View)
C
Optical Black Array and Readout Scan Direction
M1
A1 (1PIN)
V
M10
H
A10
Note) Arrows in the figure indicate scanning direction during normal readout in the vertical direction.
注) 図中の矢印は，垂直方向通常読み出し時の走査方向を示します。
2
IMX206CQC
Absolute Maximum Ratings
◆ Supply voltage 1
VADD*1
–0.3 to +3.3
V
◆ Supply voltage 2
VDDD1*2
–0.5 to +2.0
V
◆ Supply voltage 3
VDDD2
*3
–0.5 to +3.3
V
◆ Input voltage (digital)
VI
–0.3 to VDDD2 + 0.3
V
◆ Output voltage (digital)
VO
–0.3 to VDDD2 + 0.3
V
◆ Guaranteed operating temperature
TOPR
–10 to +75
˚C
◆ Storage guarantee temperature
TSTG
–30 to +80
˚C
◆ Performance guarantee temperature
TSPEC
–10 to +60
˚C
*1
2.8 ± 0.1
V
VDDD1
*2
1.2 ± 0.1
V
◆ Supply voltage 3
VDDD2
*3
1.8 ± 0.1
V
◆ Input voltage (digital)
VI
–0.1 to VDDD2 + 0.1
V
◆ Output voltage (digital)
VO
–0.1 to VDDD2 + 0.1
V
Recommended Operating Conditions
D
N
FI
*3
VADD: VDDSUB, VDDHCM, VDDHPX, VDDHDA, VDDHCP (2.8 V power supply)
VDDD1: VDDLCN, VDDLSC1 and VDDLSC2, VDDLPL (1.2 V power supply)
VDDD2: VDDMIO, VDDMIF1 and VDDMIF2 (1.8 V power supply)
O
*2
C
*1
EN
◆ Supply voltage 2
AL
VADD
TI
◆ Supply voltage 1
3
IMX206CQC
USE RESTRICTION NOTICE
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the
image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,
at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.
AL
Use Restrictions
 The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with
the terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
 You should not use the Products for critical applications which may pose a life- or injury-threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
 Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
EN
TI
Design for Safety
 Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care
to ensure the safe design of your products such as component redundancy, anti-conflagration features,
and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or
other social damage as a result of such failure.
N
FI
D
Export Control
 If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.
C
O
No License Implied
 The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.
Governing Law
 This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the
court of first instance.
Other Applicable Terms and Conditions
 The terms and conditions in the Sony additional specifications, which will be made available to you when
you order the Products, shall also be applicable to your use of the Products as well as to this
specifications book. You should review those terms and conditions when you consider purchasing
and/or using the Products.
4
IMX206CQC
Contents
C
O
N
FI
D
EN
TI
AL
Description ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 1
Features --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 1
Device Structure ----------------------------------------------------------------------------------------------------------------------------------------------------------------- 2
Optical Black Array and Readout Scan Direction ----------------------------------------------------------------------------------------------------------------------- 2
Absolute Maximum Ratings -------------------------------------------------------------------------------------------------------------------------------------------------- 3
Recommended Operating Conditions ------------------------------------------------------------------------------------------------------------------------------------- 3
USE RESTRICTION NOTICE ----------------------------------------------------------------------------------------------------------------------------------------------- 4
Pin Configuration ---------------------------------------------------------------------------------------------------------------------------------------------------------------- 7
Pin Description ------------------------------------------------------------------------------------------------------------------------------------------------------------------- 8
Electrical Characteristics ---------------------------------------------------------------------------------------------------------------------------------------------------- 10
1. DC Characteristics ----------------------------------------------------------------------------------------------------------------------------------------------------- 10
2. AC Characteristics ----------------------------------------------------------------------------------------------------------------------------------------------------- 12
3. LVDS output ------------------------------------------------------------------------------------------------------------------------------------------------------------- 14
I/O Equivalent Circuit Diagram -------------------------------------------------------------------------------------------------------------------------------------------- 15
Spectral Sensitivity Characteristics --------------------------------------------------------------------------------------------------------------------------------------- 20
Image Sensor Characteristics --------------------------------------------------------------------------------------------------------------------------------------------- 21
1. Zone Definition of Video Signal Shading ------------------------------------------------------------------------------------------------------------------------- 21
Image Sensor Characteristics Measurement Method --------------------------------------------------------------------------------------------------------------- 22
1. Measurement Conditions --------------------------------------------------------------------------------------------------------------------------------------------- 22
2. Color Coding of this Image Sensor and Readout -------------------------------------------------------------------------------------------------------------- 22
3. Definition of Standard Imaging Conditions ---------------------------------------------------------------------------------------------------------------------- 22
Setting Registers by Serial Communication---------------------------------------------------------------------------------------------------------------------------- 24
Register Map ------------------------------------------------------------------------------------------------------------------------------------------------------------------- 25
1. Register Value Reflection Timing to Output Data -------------------------------------------------------------------------------------------------------------- 27
2. Description of Register ------------------------------------------------------------------------------------------------------------------------------------------------ 28
3. Register Setting for Each Readout Drive Mode ---------------------------------------------------------------------------------------------------------------- 38
3-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3) -------------------------------------------------------------------------------------------------- 38
3-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9) ------------------------------------------------------------------------------------- 39
3-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)----------------------------------------------------------------------------------------------------- 40
3-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3) ------------------------------------------------------------------------------------------------------ 41
Readout Drive Modes -------------------------------------------------------------------------------------------------------------------------------------------------------- 42
1. Readout Drive Modes ------------------------------------------------------------------------------------------------------------------------------------------------- 42
1-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3) -------------------------------------------------------------------------------------------------- 42
1-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9) ------------------------------------------------------------------------------------- 43
1-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)----------------------------------------------------------------------------------------------------- 43
1-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3) ------------------------------------------------------------------------------------------------------ 43
1-5. Relationship between Arithmetic Processing and the Number of Output Bits in Each Readout Drive Mode ---------------------------- 44
2. Sync Signals and Data Output Timing ---------------------------------------------------------------------------------------------------------------------------- 47
3. Output Range of LVDS Output Data ------------------------------------------------------------------------------------------------------------------------------ 49
4. Detailed Specification of Each Mode ------------------------------------------------------------------------------------------------------------------------------ 50
4-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3) -------------------------------------------------------------------------------------------------- 50
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode ------------------------------------------------------------------------------- 50
(2) NTSC/PAL Compatible Drive -------------------------------------------------------------------------------------------------------------------------------- 51
(3) Image Data Output Format ---------------------------------------------------------------------------------------------------------------------------------- 52
4-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9) ------------------------------------------------------------------------------------- 62
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode ------------------------------------------------------------------------------- 62
(2) NTSC/PAL Compatible Drive -------------------------------------------------------------------------------------------------------------------------------- 62
(3) Image Data Output Format ---------------------------------------------------------------------------------------------------------------------------------- 64
4-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)----------------------------------------------------------------------------------------------------- 68
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode ------------------------------------------------------------------------------- 68
(2) NTSC/PAL Compatible Drive -------------------------------------------------------------------------------------------------------------------------------- 68
(3) Image Data Output Format ---------------------------------------------------------------------------------------------------------------------------------- 70
4-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3) ------------------------------------------------------------------------------------------------------ 74
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode ------------------------------------------------------------------------------- 74
(2) NTSC/PAL Compatible Drive -------------------------------------------------------------------------------------------------------------------------------- 74
(3) Image Data Output Format ---------------------------------------------------------------------------------------------------------------------------------- 75
4-5. Vertical Arbitrary Cropping (All-pixel scan, 10 bits) ------------------------------------------------------------------------------------------------------ 77
(1) Readout Drive Mode Outlines ------------------------------------------------------------------------------------------------------------------------------- 77
(2) Register Settings ----------------------------------------------------------------------------------------------------------------------------------------------- 77
(3) Detailed Specification of Each Mode ---------------------------------------------------------------------------------------------------------------------- 79
(4) Image Data Output Format ---------------------------------------------------------------------------------------------------------------------------------- 80
4-6. Horizontal arbitrary cropping function ----------------------------------------------------------------------------------------------------------------------- 81
Integration Time in Each Readout Drive Mode and Mode Changes --------------------------------------------------------------------------------------------- 85
1. Integration Time in Each Readout Drive Mode ----------------------------------------------------------------------------------------------------------------- 85
2. Operation when Changing the Readout Drive Mode --------------------------------------------------------------------------------------------------------- 87
3. Recommended Global Reset Shutter Operation Sequence ------------------------------------------------------------------------------------------------ 88
4. Interruptive Mode Change ------------------------------------------------------------------------------------------------------------------------------------------- 90
5
IMX206CQC
C
O
N
FI
D
EN
TI
AL
Power-on/off Sequence------------------------------------------------------------------------------------------------------------------------------------------------------ 91
1. Power-on Sequence --------------------------------------------------------------------------------------------------------------------------------------------------- 91
2. Slew Rate Limitation of Power-on Sequence ------------------------------------------------------------------------------------------------------------------- 92
3. Power-off Sequence --------------------------------------------------------------------------------------------------------------------------------------------------- 93
Standby Cancel Sequence ---------------------------------------------------------------------------------------------------------------------------------------------- 94
Peripheral Circuit Diagram -------------------------------------------------------------------------------------------------------------------------------------------------- 95
Notes on Handling ------------------------------------------------------------------------------------------------------------------------------------------------------------ 96
Package Outline --------------------------------------------------------------------------------------------------------------------------------------------------------------- 99
6
IMX206CQC
Pin Configuration
(Bottom View)
NC
1
VSSLSC1
VDDLSC1
VDDLCN
VSSLCN
VDDMIF1
NC
NC
NC
NC
NC
2
3
VSSLCB
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD LPL
VSSLPL
NC
NC
NC
NC
NC
NC
NC
NC
VDDMIF2
NC
VSSMIF1
VSSMIF2
NC
NC
NC
NC
NC
NC
VSSMIF3
DOM0
DOP0
VBGR
DCKM
DOM1
DOP1
VSSHDA
VRLT
DCKP
DOM2
DOP2
VDDHCP
VSSHCP
VRLS
VSSMIF4
DOM3
DOP3
NC
TEST1
TEST2
VSSMIF5
NC
NC
NC
NC
NC
NC
NC
NC
VDDHCM
VSSHPX
BIASRES
VDDHPX
VLOADLM
VDDHDA
1pin index
4
5
7
SCK
NC
10
NC
NC
NC
NC
NC
XCE
N
FI
C
XHS
D
E
F
TEST5
SDI
G
O
B
XCLR
SDO
V SSLSC2
VDDMIO
VSSLSC3
7
NC
NC
V DDLSC2
INCK
NC
NC
NC
D
NC
TEST3
XVS
TI
NC
9
A
TEST4
EN
NC
NC
C
8
VDDSUB
AL
6
H
J
K
L
M
IMX206CQC
Pin Description
Symbol
I/O
A/D
VDDHCM
VDDHPX
VDDHDA
VDDHCP
VSSHPX
VLOADLM
VSSHDA
VSSHCP
Power
Power
Power
Power
GND
O
GND
GND
A
A
A
A
A
A
A
A
Analog power supply (2.8 V)
Analog power supply (2.8 V)
Analog power supply (2.8 V)
Analog power supply (2.8 V)
Analog GND (2.8 V)
Capacitor connection
Analog GND (2.8 V)
Analog GND (2.8 V)
B8
TEST1
O
A
Test
Hi-Z
C3
C4
C5
C6
C7
VDDLPL
BIASRES
VBGR
VRLT
VRLS
Power
O
O
O
O
D
A
A
A
A
Digital power supply (1.2 V)
Resistor connection
Capacitor connection
Capacitor connection
Capacitor connection
—
—
—
—
—
C8
TEST2
O
A
Test
Hi-Z
D1
D3
D8
D10
E1
VSSLCB
VSSLPL
VDDSUB
XCE
VSSLSC1
GND
GND
Power
I
GND
D
D
A
D
D
Digital GND (1.2 V)
Digital GND (1.2 V)
Analog power supply (2.8 V)
Serial communication enable input
Digital GND (1.2 V)
E9
TEST3
O
D
Test
E10
F1
XCLR
VDDLSC1
I
Power
D
D
Reset pulse input
Digital power supply (1.2 V)
—
—
F8
TEST4
I
D
N
FI
State in
Standby mode
—
—
—
—
—
—
—
—
Pin
No.
A4
A5
A6
A7
B4
B5
B6
B7
Test
—
F9
SDO
O
Test output
Low Level
F10
G1
G8
XHS
VDDLCN
SCK
I
Power
I
D
D
D
Horizontal sync signal input
Digital power supply (1.2 V)
Serial communication clock input
—
—
—
G9
TEST5
I
D
Test
—
G10
SDI
I
D
Serial communication data input
—
O
D
EN
TI
AL
Pin description
C
D
8
Remarks
Leave open.
(No connection)
Leave open.
(No connection)
—
—
—
—
—
Low Level
Leave open.
(No connection)
Leave open.
(No connection)
Leave open.
(No connection)
Leave open.
(No connection)
Pin
No.
Symbol
I/O
A/D
H1
VSSLCN
GND
D
Digital GND (1.2 V)
—
H8
XVS
I
D
Vertical sync signal input
—
H9
VSSLSC2
GND
D
Digital GND (1.2 V)
—
H10
VDDLSC2
Power
D
Digital power supply (1.2 V)
—
J1
VDDMIF1
Power
D
Digital power supply (1.8 V)
—
J2
VDDMIF2
Power
D
Digital power supply (1.8 V)
—
J3
VSSMIF1
GND
D
Digital GND (1.8 V)
—
J8
VDDMIO
Power
D
Digital power supply (1.8 V)
—
J9
VSSLSC3
GND
D
Digital GND (1.2 V)
—
J10
INCK
I
D
Input clock
—
K3
VSSMIF2
GND
D
Digital GND (1.8 V)
—
K4
VSSMIF3
GND
D
Digital GND (1.8 V)
—
K5
DCKM
O
D
Digital LVDS output
Hi-Z
K6
DCKP
O
D
Digital LVDS output
Hi-Z
K7
VSSMIF4
GND
D
Digital GND (1.8 V)
—
K8
VSSMIF5
GND
D
Digital GND (1.8 V)
L4
DOM0
O
D
Digital LVDS output
L5
DOM1
O
D
Digital LVDS output
L6
DOM2
O
D
Digital LVDS output
Hi-Z
L7
DOM3
O
D
Digital LVDS output
Hi-Z
M4
DOP0
O
D
Digital LVDS output
Hi-Z
M5
DOP1
O
D
D
IMX206CQC
State in
Standby mode
Digital LVDS output
Hi-Z
M6
DOP2
O
D
Digital LVDS output
Hi-Z
M7
DOP3
O
D
Digital LVDS output
Hi-Z
C
O
N
FI
EN
TI
AL
Pin description
9
—
Hi-Z
Hi-Z
Remarks
IMX206CQC
Electrical Characteristics
Electrical characteristics of the IMX206CQC are shown below.
1. DC Characteristics
Current Consumption and Gain Variable Range
(VADD = 2.9 V, VDDD1 = 1.3 V, VDDD2 = 1.9 V, Tj = 60 ˚C, Reference Gain (0 dB),
approximately 16.35 M pixels readout (MODE0), 9.99 frame/s)
Symbol
Min.
Typ.
Max.
Unit
Current consumption (Analog)
IADD
—
—
68
mA
Current consumption (Digital)
IDDD1
—
—
85
mA
Current consumption (I/O)
IDDD2
—
—
13
mA
Standby current (Analog)
IADDSTB
—
—
100
µA
In the dark
Standby current (Digital)
IDDD1STB
—
—
4000
µA
In the dark
Standby current (I/O)
IDDD2STB
—
—
50
µA
In the dark
PGA gain variable range
PGAG
0
—
24
dB
Symbol
Min.
Typ.
Max.
Unit
2.70
2.80
2.90
V
Digital
VDDLCN,
VDDLSC1 to 2,
VDDLPL
VDDD1
1.10
1.20
1.30
V
I/O
VDDMIO,
VDDMIF1 to 2
VDDD2
1.70
1.80
1.90
V
VIH
0.8 × VDDD2
—
VDDD2 + 0.1
V
VIL
–0.1
—
0.2 × VDDD2
V
ILI
–1.0
—
1.0
µA
Digital input
voltage
Digital input
leakage current
Remarks
O
N
FI
D
VADD
EN
Analog
VDDSUB,
VDDHCM,
VDDHPX,
VDDHDA,
VDDHCP
C
Supply
voltage
Pins
TI
Supply Voltage and I/O Voltage
Item
Remarks
AL
Item
XCLR, INCK,
SCK, SDI, XCE,
XHS, XVS
10
(VI = –0.1 to
VDDD2 + 0.1 V)
IMX206CQC
LVDS Output DC Characteristics
(Termination resistance: 100 Ω, LVDS current: 1.5 mA)
Item
Digital
output
voltage
Pins
Item
DOP0 to DOP3,
DOM0 to DOM3,
DCKP, DCKM
Symbol
Min.
Typ.
Max.
Unit
Amplitude voltage
VOD
100
150
200
mV
Common voltage
VCM
VDDD2/2
– 100
VDDD2/2
VDDD2/2
+ 100
mV
Common voltage
fluctuation
VOS
—
20
—
mV
High level output voltage
VOHD
VCM + 50
VCM + 75
VCM +
100
mV
Low level output voltage
VOLD
VCM – 100
VCM – 75
VCM – 50
mV
Difference between
amplitude voltage channels
VODP
—
—
50
mV
Difference between
common voltage channels
VOSP
—
—
50
mV
LVDS output
DOP0 to DOP3
DCKP
TI
AL
DOM0 to DOM3
DCKM
C
O
N
FI
V OS
D
EN
V OD
11
V OHD
V CM
V OLD
V CM
IMX206CQC
2. AC Characteristics
INCK, XVS, XHS, XCLR
1/fINCK
twh
90 %
INCK
twl
10 %
XCLR
XVS
t LOW
t LOW
XHS
t HFDLY
t LOW
Min.
Typ.
Max.
Unit
Remarks
72.0
73.0
MHz
INCK 72 MHz setting
35.5
36.0
36.5
MHz
INCK 36 MHz setting
23.7
24.0
24.3
MHz
INCK 24 MHz setting
11.9
12.0
12.1
MHz
INCK 12 MHz setting
5
N
FI
—
—
ns
5
—
—
ns
—
40
50
60
%
O
71.0
55
—
167
ns
fINCK
INCK Low level pulse width
D
INCK clock frequency
twl
INCK High level pulse width
Clock duty
twh
tLOW
C
XVS Low level pulse width
TI
Symbol
EN
Item
AL
t HRDLY
XHS Low level pulse width
tLOW
55
—
167
ns
XVS fall – XHS fall width
tHFDLY
0
—
—
ns
XVS fall – XHS rise width
tHRDLY
55
—
167
ns
XCLR Low level pulse width
tLOW
100
—
—
ns
12
IMX206CQC
Serial Communication
Serial Control Interface Timing
t HIXCE
t SIXCE
XCE
1/ fSCK
SCK
t HI
DATA
SDI
DATA
DATA
t SI
Item
Symbol
Min.
Typ.
Max.
Unit
fSCK
—
—
36
MHz
SDI input setup time
tSI
7
—
—
ns
SDI input hold time
tHI
7
—
—
ns
XCE input setup time
tSIXCE
10
—
—
ns
XCE input hold time
tHIXCE
10
—
—
ns
C
O
N
FI
D
EN
TI
AL
SCK clock frequency
13
IMX206CQC
3. LVDS output
DCKM
DCKP
Twh
DCKP – DCKM
Twl
tDOS tDOH
DOPx
DOMx
DOPx – DOMx
tDOSQ
tDOSQ
80 %
DCKP – DCKM
DOPx – DOMx
20 %
tDOHLT
AL
tDOLHT
EN
(Termination resistance: 100 Ω, load capacitance: 0 pF)
TI
注) xには0～3までの数字が入り，全ての出力チャネルに対しての規定となります。
Note) "x" stands
for the number of 0 to 3 and the time chart is specified for all output channels.
Typ.
Max.
Unit
—
361
ps
Data rate 288 MHzDDR
420
—
—
ps
Data rate 288 MHzDDR
420
—
—
ps
Data rate 288 MHzDDR
tDOLHT
—
500
—
ps
Simulated value with
load capacitance (4 pF)
tDOHLT
—
500
—
ps
Simulated value with
load capacitance (4 pF)
DCK duty cycle
DDCDCK
45
50
55
%
DCK pulse width
Twh, Twl
1319
—
—
ps
Min.
DO skew time
(including jitter)
tDOSQ
—
DO setup time
tDOS
DO hold time
tDOH
DO rise time
N
FI
O
DO fall time
D
Symbol
C
Item
14
Remarks
Including period jitter
IMX206CQC
I/O Equivalent Circuit Diagram
Symbol
Equivalent circuit
P *1
VDDSUB
VSSLSC
VDDMIO
P *1
VSSLSC
XCLR
VSSLSC
AL
VDDLSC
VDDMIO
N
FI
D
VDDMIO
VSSLSC
VSSLSC
C
O
XCE
SCK
SDI
XHS
XVS
INCK
EN
TI
VSSLSC
P *1
VDDMIO
VSSLSC
VDDMIO
VDDMIO
SDO
VSSLSC
VSSLSC
□External pins
15
IMX206CQC
Symbol
Equivalent circuit
P *1
VDDLCN
VSSLCN
VDDLCN
VSSLCN
P *1
P *1
VDDLSC1
VDDLSC2
AL
VSSLSC
VDDLSC
VSSLSC1
VSSLSC2
VSSLSC3
N
FI
VDDLSC
P *1
VDDHCM
C
O
VSSLCB
D
EN
TI
P *1
P *1
VSSHPX
□External pins
16
IMX206CQC
Symbol
Equivalent circuit
P *1
VDDHPX
VSSHPX
VDDHPX
VSSHPX
P *1
P *1
VDDLPL
AL
VSSLPL
VDDLPL
VSSLPL
N
FI
O
VSSMIF1
VSSMIF2
VSSMIF3
VSSMIF4
VSSMIF5
P *1
VSSMIF
VDDMIF
C
VDDMIF1
VDDMIF2
D
EN
TI
P *1
P *1
□External pins
17
IMX206CQC
Symbol
Equivalent circuit
VDDMIF
VDDMIF
DOPx (x = 0 to 3)
External
pins
DOPx,DCKP
DOMx (x = 0 to 3)
DCKP
VSSMIF
DCKM
VDDMIF
External
pins
DOMx,DCKM
VSSMIF
VSSMIF
VDDHPX
TI
AL
VLOADLM
N
FI
O
BIASRES
VBGR
VDDHDA
D
EN
VSSHPX
C
VSSHDA
P *1
VDDHDA
VSSHDA
VDDHDA
VSSHDA
P *1
□External pins
18
IMX206CQC
Symbol
Equivalent circuit
P *1
VDDHCP
VSSHCP
VDDHCP
VSSHCP
P *1
VSSHCP
VRLS
P *1
AL
VRLT
TI
Description of special symbol
D
O
N
FI
P *1
Equivalent circuit
EN
Symbol
C
□External pins
19
IMX206CQC
Spectral Sensitivity Characteristics
C
O
N
FI
D
EN
TI
AL
(Excludes lens characteristics and light source characteristics)
20
IMX206CQC
Image Sensor Characteristics
(VADD = 2.8 V, VDDD1 = 1.2 V, VDDD2 = 1.8 V, Tj = 60 ˚C, 9.99 frame/s, Reference Gain (0 dB))
Symbol
Min.
Typ.
Max.
Unit
Measurement
method
Sg
822 *1
1096
1370
digit
1
R
Rr
36
—
62
%
1
B
Rb
35
—
55
%
1
Vsat
2739
—
—
digit
2
—
—
20
—
—
25
G sensitivity
Sensitivity
ratio
Saturation signal
Dark signal
Vdt
0
—
Dark signal shading
ΔVdt
0
Dark signal difference
VdOB
Line crawl R
Line crawl B
%
3
0.772
digit
4
1/30 s integration
conversion value
—
1.080
digit
5
1/30 s integration
conversion value
-0.370
—
0.370
digit
6
1/30 s integration
conversion value
Lcr
-3.8
—
TI
SHg
1/30 s integration
conversion value
3.8
%
Lcb
-3.8
—
3.8
%
7
D
EN
Zone 0, zone I,
zone II and zone II’
(the figure below)
Shows digit when 12-bit output.
N
FI
*1
Video signal
shading
Remarks
Zone 0 and zone I
(the figure below)
AL
Item
Example of digit conversion: 1 digit ≈ 0.518 mV when 10-bit output, 1 digit ≈ 0.1296 mV when 12-bit output.
O
1. Zone Definition of Video Signal Shading
C
Zone definition of video signal shading and reference position during dark signal measurement are shown below.
4672 (H)
16
24
VOPB
4
V
10
H
8
H
8
Zone 0 and I
3500 (V)
4
Zone II and II’
V
10
Ignored area
Effective pixel area
Zone Definition of Video Signal Shading and Reference Position during Dark Signal Measurement
21
IMX206CQC
Image Sensor Characteristics Measurement Method
1. Measurement Conditions
(1) In the following measurements, the device drive conditions are at the typical values of the bias conditions and
clock voltage conditions.
(2) In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black (OB)
level is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output
or the R/B channel signal output of the measurement system.
2. Color Coding of this Image Sensor and Readout
The primary color filters of this image sensor are arranged in the layout shown in the figure below. Gr and Gb
represent the G signal on the same line as the R and B signals, respectively. The Gb signal and B signal lines and
the R signal and Gr signal lines are output successively.
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
TI
AL
Gb
3. Definition of Standard Imaging Conditions
EN
Color Coding Diagram
N
FI
D
◆ Standard imaging condition I:
Use a pattern box (luminance: 706 cd/m2, color temperature of 3200 K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter
and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
C
O
◆ Standard imaging condition II:
Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles.
Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter. The luminous intensity is adjusted to the
value indicated in each testing item by the lens diaphragm.
◆ Standard imaging condition III:
Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles.
Use a testing standard lens (exit pupil distance –18.5 mm) with CM500S (t = 1.0 mm) as an IR cut filter.
The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, Sensitivity ratio
Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode with
a shutter speed of 53.1 s, measure the Gr, Gb, R and B signal outputs (VGr, VGb, VR and VB) at the center of
the screen, and substitute the values into the following formula.
VG = (VGr + VGb)/2
Sg = VG × 53.1 /30 [digit]
Rr = VR/VG × 100 [%]
Rb = VB/VG × 100 [%]
2. Saturation signal
Set the measurement condition to the standard imaging condition II. Adjust the luminous intensity to 20 times the
intensity with the average value of the G (= (Gr + Gb)/2) signal output, 282 digit when 10-bit output (1127 digit
when 12-bit output). Measure the minimum values of the Gr, Gb, R and B signals when shooting in rolling shutter
mode.
22
IMX206CQC
3. Video signal shading
Set the measurement condition to the standard imaging condition III. With the lens diaphragm at F5.6 to F8,
adjust the luminous intensity so that the average value of the G signal output is 282 digit when 10-bit output
(1127 digit when 12-bit output). Then measure the maximum value (Gmax [digit]) and the minimum value
(Gmin [digit]) of the G signal output, and substitute the values into the following formula.
 When 10-bit output
SHg = (Gmax – Gmin) / 282 × 100 [%]
 When 12-bit output
SHg = (Gmax – Gmin) / 1127 × 100 [%]
4. Dark signal
Measure the average value (Vdt [digit]) of the signal output in zone 0 to zone II’ in the light-obstructed state.
Define the average value of the signal output accumulated in 1 frame period (t1v) as Vdt1V and the average
value of the signal output accumulated in the shortest period (1H period: t1h) as Vdt1H, and then substitute the
values into the following formula.
Vdt = (Vdt1V – Vdt1H) / (t1v – t1h) /30 [digit]
5. Dark signal shading
AL
Following the item 4, measure the maximum value (Vdmax [digit]) and minimum value (Vdmin [digit]) of the dark
signal output, and substitute the values into the following formula.
EN
TI
ΔVdt = Vdmax – Vdmin [digit]
6. Dark signal difference
7. Line crawl
N
FI
D
Following the item 5, measure the average value of the dark signal output (VdOB [digit]) in zone 0 to zone II'
using the optical black (vertical direction VOPB area) level as a reference.
C
O
Set the measurement condition to the standard imaging condition III. After adjusting the average value of the
G (= (Gr + Gb)/2) signal output when inserting G filter to 282 digit when 10-bit output (1127 digit when 12-bit
output), measure the average values of the Gr and Gb signal output (GGr, GGb).
After adjusting the average value of the R signal output when inserting R filter to 282 digit when 10-bit output
(1127 digit when 12-bit output), measure the average values of the Gr and Gb signal output (RGr, RGb).
Substitute the values into the following formula.
Lcr = {RGr – (GGr/GGb) × RGb}/[{RGr + (GGr/GGb) × RGb}/2] × 100 [%]
Then, after adjusting the average value of the B signal output when inserting B filter to 282 digit when 10-bit
output (1127 digit when 12-bit output), measure the average values of the Gr and Gb signal output (BGr, BGb).
Substitute the values into the following formula.
Lcb = {BGb – (GGb/GGr) × BGr}/[{BGb + (GGb/GGr) × BGr}/2] × 100 [%]
23
IMX206CQC
Setting Registers by Serial Communication
Sensor operation is controlled by the register settings. Follow the procedure below and make the register settings by
serial communication.
1. Set XCE Low to enable the chip's serial communication function.
2. Transmit serial data (SDI) synchronized with SCK 1 bit at a time from the lower bits.
3. Transmit the Chip ID (fixed value: 81h) in the first byte.
4. Transmit the address value of the register to be set in the second and third bytes.
5. Transmit the register setting value to the address designated by the second and third bytes in the fourth byte.
6. Transmit the register setting value to the address following the address designated by the second and third bytes
in the fifth byte.
7. Transmit the register setting values to subsequent addresses in order thereafter.
8. Set XCE High to end serial communication.
EN
Communication is always accepted.
Communication should be completed within the recommended serial communication period to prevent
noise. However, this restriction does not apply during the readout period of non-picture frames in which
noise is ignored (immediately after power-on or immediately after switching the drive mode, etc.), so
register communication can be performed other than during the communication period of those frames.
N
FI
D
Note) 1.
2.
TI
AL
The IMX206CQC clears the Chip ID and address setting data by setting XCE High.
Therefore, the Chip ID and address settings must also be made when the next serial communication is performed.
Continuous write across upper bytes is prohibited. When writing across upper bytes, first complete the above
sequence, and then perform communication again. In addition, when jumping to a discontinuous address, also first
complete the above sequence, and then perform communication again.
Perform serial communication within the 6XHS period (recommended serial communication period) after the fall of
XVS to avoid affecting the image quality.
Settings made by serial communication are basically updated immediately each time 1 byte of setting values is
transmitted. However, in some exceptional cases (electronic shutter setting, etc.), register setting values are updated
immediately before the start of readout immediately after the recommended serial communication period (7th XHS).
For details, see “Register Map” on pages 25 to 26 and “1. Register Value Reflection Timing to Output Data” on page
27.
O
Example of Serial Communication Timing 1
C
XCE
SCK
SDI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
MSB LSB
LSB
7
0
1
2
3
4
5
6
MSB LSB
7
0
1
2
5
6
MSB LSB
7
MSB
Data established
timing
Chip ID
Start address
(Upper 1 byte)
Start address
(Lower 1 byte)
N byte data
Example of Serial Communication 1
Example of Serial Communication Timing 2
XCE
SCK
SDI
Data established
timing
0 1
6 7 0 1
6 7 0 1
6 7 0 1
6 7
0 1
6 7 0 1
6 7 0 1
6 7 0 1
6 7
LSB
MSB LSB
MSB LSB
MSB LSB
MSB
LSB
MSB LSB
MSB LSB
MSB LSB
MSB
Chip ID
Start address Start address
(Upper 1 byte) (Lower 1 byte)
M byte data
Chip ID
Example of Serial Communication 2
24
Start address Start address
(Upper 1 byte) (Lower 1 byte)
N byte data
IMX206CQC
Register Map
The register map is given below.
0003h
[0]
1h
Immediately
STANDBY
[1]
1h
Immediately
STBLOGIC
[3:2]
0h
[4]
0h
[7:5]
0h
Immediately
DCKRST
When changed from 0h to 1h:
Fixes the LVDS clock
output phase
0h
—
[4]
0h
CLPSQRST
When changed from 0h to 1h:
Resets the internal clamp circuit
operation mode
[7:5]
0h
[0]
0h
[7:1]
00h
[2:0]
5h
[3]
0h
[6:4]
5h
[3:1]
Immediately
Communication
*1
end frame
—
*1
*1
[7]
0h
18h
0005h
[7:0]
18h
[7:0]
A3h
0007h
[7:0]
05h
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
001Ah
002Ch
C
0006h
0009h
STBLVDS
*1
[7:0]
000Ah
SSBRK
CHSEL
*1
MDSEL1
*1
MDSEL2
*1
MDSEL3
*1
MDSEL4
*1
SMD
[0]
0h
[3:1]
0h
[7:4]
0h
*1
GSVR
000h
*1
PGC
[7:0]
[2:0]
[7:3]
[7:0]
[6:0]
[7]
[7:0]
[7:0]
[7:0]
[7:0]
00h
0008h
When changed from 0h to 1h:
Interrupt enable
AL
0h
—
0 to 3h: 4 ch
4h: 2 ch
5h: 1 ch
7h: All channel standby
—
Number of LVDS output
0 to 3h: 4 ch
4h: 2 ch
5h: 1 ch
—
TI
[0]
0004h
0008h
SLEEP
Function
0h: Normal operation
1h: Overall standby
0h: Normal operation
1h: Digital circuit standby other
than serial communication
block
—
0h: Normal operation
1h: Low power consumption
drive in exposure of global
reset shutter operation
—
EN
0002h
Register name
D
0001h
Reflection timing
N
FI
0000h
Bit
Default
assignment value
O
Address
0h: Rolling shutter
1h: Global reset shutter
—
Specifies the vertical period
to perform readout during
global reset shutter drive
Analog gain setting
—
Next frame
after communication
*2
end
SHR
0h
0007h
*2
SVR
0000h
*2
SPL
[1:0]
0h
*1
DGAIN
[7:2]
00h
[0]
0h
[7:1]
[3:0]
[4]
[7:5]
00h
1h
1h
0h
*1
*1
MDVREV
PLSTMG01
25
Remarks
Setting range:
0h to 1h
Setting range:
0h to 1h
Set the default value.
Setting range:
0h to 1h
Set the default value.
Setting range:
0h to 1h
After the reset, the value is
automatically returned to 0h.
Set the default value.
Setting range:
0h to 1h
After the reset, the value is
automatically returned to 0h.
Set the default value.
Setting range:
0h to 1h
After the interrupt, the value is
automatically returned to 0h.
Set the default value.
Setting range:
0h to 5h and 7h
Set the default value.
Setting range:
0h to 5h
Set the default value.
Set the value according to each
readout mode register setting.
Set the value according to each
readout mode register setting.
Set the value according to each
readout mode register setting.
Set the value according to each
readout mode register setting.
Setting range:
0h to 1h
Set the default value.
Setting range:
0h to Fh
Setting range:
000h to 780h
Set the default value.
Specifies the integration start
horizontal period
Setting range is shown
in ”Description of Registers”
—
Specifies the integration
shutdown vertical period
Specifies the integration start
vertical period
Digital gain setting
0h: 0 dB gain setting value
1h: +6 dB gain setting value
2h: +12 dB gain setting value
3h: +18 dB gain setting value
—
0h: Vertical direction normal
readout
1h: Vertical direction inversion
readout
—
—
Drive pulse timing setting 01
—
Set the default value.
Setting range:
0000h to FFFFh
Setting range:
0000h to FFFFh
Setting range:
0h to 3h
Set the default value.
Setting range:
0h to 1h
Set the default value.
Set the default value.
Set to 0h
Set the default value.
IMX206CQC
Address
Bit
Default
assignment value
0045h
[7:0]
006Fh
[7:0]
[3:0]
[7:4]
[7:0]
[2:0]
[7:3]
[7:0]
0070h
0071h
0072h
007Ch
007Dh
[2:0]
Register name
32h
Immediately
BLKLEVEL
000h
*1
VWINPOS
*1
VWIDCUT
0h
000h
00h
*2
16Ch
Function
Digital black level offset setting
Start position of vertical arbitrary
cropping (two's complement)
—
Width of vertical arbitrary
cropping
—
HCOUNTHALF Timing setting in 1XHS period
0h
010Eh
0308h
0309h
030Ah
0320h
0321h
0322h
0323h
0338h
0342h
0343h
0344h
0345h
034Ah
034Bh
034Ch
034Dh
0352h
0353h
0354h
0359h
035Fh
0360h
0361h
0362h
0406h
0407h
048Bh
0506h
0507h
050Eh
050Fh
053Eh
053Fh
0540h
0542h
055Bh
0578h
0579h
057Ah
057Bh
057Dh
[7:1]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
00h
10h
14h
11h
12h
Immediately
Immediately
Immediately
Immediately
PLSTMG02
PLSTMG03
PLSTMG04
PLSTMG05
0005h
Immediately
PLSTMG06
Drive pulse timing setting 06
Set to 0114h
0012h
Immediately
PLSTMG07
Drive pulse timing setting 07
Set to 0018h
05h
Immediately
PLSTMG08
Drive pulse timing setting 08
Set to 00h
009Ah
Immediately
PLSTMG09
Drive pulse timing setting 09
Set to 0006h
0087h
Immediately
PLSTMG10
Drive pulse timing setting 10
0088h
Immediately
PLSTMG11
Drive pulse timing setting 11
Set to 0112h
009Bh
Immediately
PLSTMG12
Drive pulse timing setting 12
Set to 0007h
05A2h
[7:0]
0h
HTRIMMING
_EN
Setting range:
0h to 1h
Set the default value.
Set to 11h
Set to 13h
Set to 10h
Set to 11h
Set to 0113h
01h
Immediately
PLSTMG13
Drive pulse timing setting 13
Set to 00h
0700h
Immediately
PLSTMG14
Drive pulse timing setting 14
Set to 0000h
01h
Immediately
PLSTMG15
Drive pulse timing setting 15
Set to 11h
0115h
Immediately
PLSTMG16
Drive pulse timing setting 16
Set to 01FFh
PLSTMG17
Drive pulse timing setting 17
Set to 0000h
000Bh
D
EN
*1
TI
HTRIMMING
_END
N
FI
00FCh
*1
0000h
O
00FBh
HTRIMMING
_START
0h
Immediately
C
00FAh
*1
0000h
AL
[0]
00F9h
00h
Remarks
Setting range:
00h to FFh
10-bit readout mode: 1 digit/1h
12-bit readout mode: 4 digit/1h
Setting range is shown
in ”Description of Register”.
Set the default value.
Setting range is shown
in ”Description of Register”.
Set the default value.
Setting range: 000h to 7FFh
Set XHS period [INCK] / 2
(round down after the decimal point)
Set the default value.
Setting range is shown
in ”Description of Register”.
Set the default value.
Setting range is shown
in ”Description of Register”.
Set the default value.
—
horizontal cropping
start position
—
horizontal cropping end
position + 1
—
0h: Normal operation
1h: Horizontal arbitrary
cropping enabled
—
Drive pulse timing setting 02
Drive pulse timing setting 03
Drive pulse timing setting 04
Drive pulse timing setting 05
00F8h
[7:3]
[7:0]
[4:0]
[7:5]
[7:0]
[4:0]
[7:5]
Reflection timing
0081h
Immediately
PLSTMG18
Drive pulse timing setting 18
Set to 007Eh
00h
Immediately
PLSTMG30
Drive pulse timing setting 30
Set to 01h
0005h
Immediately
PLSTMG31
Drive pulse timing setting 31
Set to 001Bh
0089h
Immediately
PLSTMG32
Drive pulse timing setting 32
Set to 00B7h
07h
07h
04h
00h
01h
Immediately
Immediately
Immediately
Immediately
Immediately
PLSTMG33
PLSTMG34
PLSTMG35
PLSTMG23
PLSTMG24
Drive pulse timing setting 33
Drive pulse timing setting 34
Drive pulse timing setting 35
Drive pulse timing setting 23
Drive pulse timing setting 24
Set to 0Ch
Set to 08h
Set to 03h
Set to 01h
Set to 00h
0113h
Immediately
PLSTMG25
Drive pulse timing setting 25
Set to 01FFh
000Bh
Immediately
PLSTMG26
Drive pulse timing setting 26
Set to 0000h
0Ch
Immediately
PLSTMG36
Set to 08h
10h
Immediately
PLRD
Drive pulse timing setting 36
Input clock frequency setting
10h: INCK 72MHz setting
20h: INCK 36MHz setting
30h: INCK 24MHz setting
60h: INCK 12MHz setting
Setting range:
10h, 20h, 30h and 60h
Note) •
The “Default value” column indicates the initial value set in each register in the status before register communication is performed after
•
Operation is not guaranteed when using register settings other than noted in these specifications. Do not access addresses not noted in
•
When changing the mode, the address set designated in “3. Register Settings for Each Readout Drive Mode” on pages 38 to 41 must be
start-up or after the reset signal XCLR is set to Low to reset the sensor.
the table above, and do not set register values other than those noted in “2. Description of Registers” on page 28 to 37.
written.
•
For the detailed reflection timing, see “1. Register Value Reflection Timing to Output Data” on page 27.
26
IMX206CQC
1. Register Value Reflection Timing to Output Data
The register values established by register communication are reflected to the output data at the following timings.
Reflection timing
Explanation
*1.
Communication end frame
The communication contents are reflected to the output data from the
V period during which communication was performed.
*2.
Next frame after
communication end
The communication contents are reflected to the output data from the next
V period after the V period during which communication was performed.
For which reflection timing of each register, see “Register Map” on pages 25 to 26.
Register
communication
timing
Serial
communication
XVS
6XHS
6XHS
6XHS
...
XHS
6XHS
6XHS
...
...
6XHS
...
...
...
Sensor internal
TI
EN
Valid data output
*2 Next frame after communication ends: Reflected to the output data of these periods
O
N
FI
D
*1 Communication end frame: Reflected to the output data of these periods
C
Y
r
t
ou
te
ut
sh
ad
re
Valid data output
r
te
ut
t
ou
r
Valid data output
sh
ad
re
te
ut
sh
t
Valid data output
ou
t
Valid data output
ad
re
r
ou
te
ut
sh
ad
re
r
t
ou
r
te
ut
ad
sh
re
te
ut
sh
Output frame
AL
V drive
27
IMX206CQC
2. Description of Register
Total Standby Control
All sensor operation is stopped and the standby mode that reduces power consumption is established by setting the
overall standby control register STANDBY (address 0000h, bit [0]) to “1h”.
(Standby mode is established immediately after reset.)
The serial communication block operates even in standby mode, so standby mode can be canceled by setting “0h” in
the STANDBY register.
STANDBY Setting
Register value
Function
0h
Normal operation
1h
Overall standby
Digital Circuit Standby Control
AL
Sensor digital circuit operation other than the serial communication block is stopped by setting the digital circuit
standby control register STBLOGIC (address 0000h, bit [1]) to "1h". This register is valid only when STANDBY = 0h.
(Standby mode is established according to the STANDBY register initial value immediately after a reset.)
Set this register according to the recommended sequence during power-on or when canceling standby mode.
Function
EN
Register value
TI
STBLOGIC Setting
Normal operation
1h
Digital circuit standby other than
serial communications block
N
FI
D
0h
Low Power Consumption Drive in Exposure of Global Reset Shutter Operation
C
O
In global reset shutter operation, low power consumption drive in exposure period can be performed by SLEEP
(address 0000h, bit [4]), the register of low power consumption drive in exposure of global reset shutter operation.
Set this register according to “Low power consumption drive in exposure of global reset shutter operation sequence”
on page 89.
SLEEP Setting
Register value
Function
0h
Normal operation
1h
Low power consumption drive in exposure
of global reset shutter operation
28
IMX206CQC
Input Clock Frequency Setting
The frequency of the clock signal INCK input to the sensor can be selected by the input clock frequency setting
register PLRD (address 05A2h, bit [7:0]).
Sensor internal operating speed is the same between INCK frequency 72 MHz setting and other settings, because
INCK is multiplied by PLL inside the sensor.
Make this setting according to the recommended sequence during power-on or when canceling standby mode.
PLRD Setting
Register value
Function
10h
INCK frequency 72MHz setting
20h
INCK frequency 36MHz setting
30h
INCK frequency 24MHz setting
60h
INCK frequency 12MHz setting
LVDS Clock Output Phase Fixed
TI
AL
The clock phase relative to the sync code start data in the LVDS data output is fixed by the LVDS clock output phase
fixing register DCKRST (address 0001h, bit [0]). Make this setting according to the recommended sequence during
power-on or when canceling standby mode.
This register automatically returns to “0h” after the phase fixing process, so there is no need to write “0h”.
DCKRST Operation Setting
Function
Fixes the LVDS clock output phase
D
Changed from 0h to 1h
EN
Register value
N
FI
Clamp Reset
O
The internal clamp circuit operation status is reset by the clamp reset register CLPSQRST (address 0001h, bit [4]).
Make this setting according to the recommended sequence during power-on or when canceling standby mode.
This register automatically returns to “0h” after the reset process, so there is no need to write “0h”.
Register value
C
CLPSQRST Operation Setting
Changed from 0h to 1h
Function
Resets the internal clamp circuit operation status
29
IMX206CQC
LVDS Standby Control
This sensor can set the LVDS to standby mode according to the setting value by setting the LVDS standby control
register STBLVDS (address 0003h, bit [2:0]).
STBLVDS Setting
Register value
Function
0h to 3h
4 ch
4h
2 ch
5h
1 ch
7h
All channel standby
LVDS standby control is shown below.
hex
Function
0
1
DCK
2
3
0h to 3h
4h
5h
7h
4 ch
2 ch
1 ch
All Standby
Active
STBY
STBY
STBY
Active
Active
Active
STBY
Active
Active
Active
STBY
Active
Active
STBY
STBY
Active
STBY
STBY
STBY
AL
bin
dec
STBLVDS[3:0]
0d to 3d 000b to 011b
100b
4d
101b
5d
111b
7d
Number of LVDS Output Channels Selection
EN
TI
This sensor can set the number of output channels according to the setting value by setting the number of LVDS
output channels selection register CHSEL (address 0003h, bit [6:4]).
CHSEL Setting
Function
0h to 3h
4 ch
N
FI
D
Register value
4h
2 ch
1 ch
O
5h
dec
CHSEL[2:0]
0d to 3d
bin
000b to 011b
C
Number of LVDS channels control is shown below.
hex
Function
0
1
DCK
2
3
0h to 3h
4 ch
Active
Active
Active
Active
Active
Fixed
Low
Fixed
Low
Active
Active
Active
Active
Active
Fixed
Low
4d
100b
4h
2 ch
5d
101b
5h
1 ch
30
Fixed
Low
Fixed
Low
IMX206CQC
Electronic Shutter Timing
The exposure start timing can be designated by setting the electronic shutter timing register SHR (address 000Bh, bit
[7:0] and address 000Ch, bit [6:0]). Designate the lower 8 bits in address 000Bh and the upper 7 bits in address
000Ch, for a total of 15 bits.
Note that this setting value unit is 1XHS period regardless of the readout drive mode. In addition, the vertical sync
signal XVS can be subsampled inside the sensor according to the SVR register (address 000Dh, bit [7:0] and
address 000Eh, bit [7:0]). The vertical sync signal period inside the sensor is (SVR value + 1) times as long as XVS
signal period.
When setting the electronic shutter during the vertical sync signal subsampling period, the SPL register (address
000Fh, bit [7:0] and address 0010h, bit [7:0]) is available.
Shutter Setting
6 to {(SVR + 1) × Number of XHS
pulses per frame – 2}
6 to {(SVR + 1) × Number of XHS
pulses per frame/4 – 2}
6 to {(SVR + 1) × Number of XHS
pulses per frame – 4}
0 to {(SVR + 1) × Number of XHS
pulses per frame − 130}
1.
2.
3.
Specifies the integration
shutdown vertical period
Specifies the integration start
0h to FFFFh *Note 2.
vertical period
See “Integration Time in Each Readout Drive Mode” on page 85 for the integration time calculation formula.
The SVR and SPL register definition areas are guaranteed as sensor functions, but the characteristics are not guaranteed.
SMD is the electronic shutter drive mode register (address 0008h, bit [0]).
0h to FFFFh *Note 2.
SVR
changed to "1"
N
FI
SVR = 0
SPL = 0
6XHS
...
6XHS
...
...
SHR
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ut
r
ou
r
r
t
t
t
ou
tte
ad
sh
re
u
sh
ad
re
tte
r
ou
tte
ad
u
sh
re
u
sh
C
6XHS
6XHS
...
SHR
SHR
Y
Communication
prohibited
6XHS
...
O
Sensor internal
V drive
Communication
prohibited
6XHS
.. .
XHS
Output frame
D
Example of Electronic Shutter Operation 1
Serial
communication
XVS
TI
SPL
Note)
Global reset shutter mode (SMD = 1)
EN
SVR
Specifies the integration start
horizontal period
AL
10 to {(SVR + 1) × Number of XHS
pulses per frame – 4}
11 to {(SVR + 1) × Number of XHS
pulses per frame – 4}
12 to {(SVR + 1) × Number of XHS
pulses per frame – 4}
SHR
Function
Register value
Readout mode No.0 and 1
All-pixel scan mode (12 bits/10 bits)
Readout mode No.2 and 2A
Horizontal/vertical 2/2-line binning mode
Readout mode No.3 and 8
Vertical 2/3 subsampling binning mode
Readout mode No.4 and 6
Vertical 2/9 subsampling binning mode Vertical
2/19 subsampling binning mode
Readout mode No.5
Vertical 2/9 subsampling binning mode (low power
consumption drive)
Readout mode No.7
Vertical 2 binning horizontal 2/4 subsampling mode
Register
Valid data output
Valid data output
V1 period
V2 period
Valid data output
V3 period
V5 period
V4 period
Example of SVR operation
Example of Electronic Shutter Operation 2
SPL
changed to “1”
SVR = 1
SPL = 0
Serial
communication
XVS
6XHS
6XHS
.. .
XHS
...
6XHS
...
.. .
.. .
SHR
re
ou
r
ou
te
ut
ad
sh
ad
t
r
te
ou
ut
ad
r
te
Valid data output
V2 period
Valid data output
V4 period
V3 period
t
t
t
ou
Valid data output
V1 period
6XHS
.. .
re
re
ut
ad
sh
re
Output frame
Communication
prohibited
6XHS
SHR
SHR
Y
.. .
sh
Sensor internal
V drive
Communication
prohibited
6XHS
V5 period
Valid data output
V6 period
Example of SVR and SPL operation
Note) In vertical sync signal subsampling periods (Example of Electronic Shutter Operation 1: V3 and V5 periods,
Example of Electronic Shutter Operation 2: V4 and V6 periods), communication is prohibited during the normal
communication period (the 6XHS period after the vertical sync signal XVS is input), except in the f ollowing case.
 When stopping vertical sync signal subsampling using the break mode register SSBRK.
31
IMX206CQC
Electronic Shutter Drive Mode
Global reset shutter operation can be performed by setting the electronic shutter drive mode register SMD (address
0008h, bit [0]). Rolling shutter operation performs pixel reset and integration sequentially in line units in sync with the
XHS signal. Global reset shutter operation resets all pixels at once and then starts integration after that.
(“Integration” is the state of a pixel between the reset and the readout. Pixels accumulate all the power of input light.)
The mechanical shutter must also be used during global reset shutter operation to make the exposure time the same
for all pixels.
SMD Setting
Register value
Function
0h
Rolling shutter (normal shutter mode)
1h
Global reset shutter
XVS
XHS
AL
TI
(LAST–3) H
(LAST–2) H
(LAST–1) H
(LAST) H
Integration
Readout
Exposure time
D
Reset
EN
Operation
for each line
0H
1H
2H
3H
N
FI
Rolling Shutter Operation
O
XVS
Operation
for each line
C
XHS
0H
1H
2H
3H
(LAST–3) H
(LAST–2) H
(LAST–1) H
(LAST) H
Reset
Integration
Integration time
OPEN
Mechanical shutter operation
CLOSE
Exposure time
Global Reset Shutter Operation
32
Readout
IMX206CQC
Readout Timing
The vertical sync signal XVS can be subsampled inside the sensor during the readout period (V3 and V4 periods) in
global reset shutter drive mode (address 0008h, bit [0], SMD = 1h) by setting the readout timing register GSVR
(address 0008h, bit [7:4]).
This is the same operation as that performed by the SVR register (address 000Dh, bit [7:0] and address 000Eh, bit
[7:0]). However, separate control is performed in global reset shutter drive mode (SMD = 1h), with the SVR register
designating the vertical period of the exposure period (V2 period), and the GSVR register designating the vertical
period of the readout period (V3 and V4 periods). This register is invalid in rolling shutter drive mode (SMD = 0h).
GSVR Setting
Register value
Function
Specifies the vertical period for reading during
global reset shutter drive.
0h to Fh
SMD= 1 (Global reset shutter)
SHR=0
GSVR=1
MODE : All-pixel scan, 12 bits
Communication
prohibited
Serial
communication
XVS
XHS
6XHS
...
...
6XHS
...
Communication
prohibited
6XHS
6XHS
...
...
...
...
6XHS
...
...
AL
TI
D
V3 period
C
O
N
FI
Example of GSVR operation
33
t
V2 period
ou
t)
ou
All-pixel scan (12 bits)
Invalid data output
Exposure start period (no data output)
V1 period
ad
re
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te
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r
t
EN
SHR
sh
rea
ad
(re
te
ou
r
te
Mode A
XHS period
change
(sh
u
d o tter)
ut
shutter
ut
ad
ut
t
ou
r
te
Mode A
6XHS
↑
XHS period
change
sh
re
sh
SHR
ad
SHR
re
ut
sh
Y
6XHS
↑
Sensor internal
V drive
Output frame
MODE : Mode A
SMD = 0 (Rolling shutter)
GSVR = x (Invalid)
SHR = Setting
V4 period
V5 period
Mode A
IMX206CQC
Break Mode
In rolling shutter (normal shutter) operating mode (address 0008h, bit [0], SMD = 0h), XVS can be subsampled
according to SVR.
In addition, in global reset shutter operating mode (SMD = 1h), XVS can be subsampled according to SVR during the
exposure period, and then according to GSVR during the readout period.
This XVS subsampling operation can be stopped and then restarted from the start of the exposure period using the
break mode register SSBRK (address 0002h, bit [0]).
This register automatically returns to “0h” after the break process, so there is no need to write “0h”.
SSBRK Setting
Register value
Changed from 0h to 1h
Function
Interrupt enable
Example of sequence using SSBRK is shown below. In the example, operation across 3 XVS periods (SVR=2) is
interrupted in the midst of period and change to operation of 1 XVS period (SVR=0).
In the figure, V1 period is a XVS period in the midst of subsampling, and V2 period is the next XVS period of V1. By
setting SVR to 0h and SSBRK to 1h at the top of V1 period, valid data under new integration time is output from V2
period. Usually output of V1 period is invalid data because its integration time is interrupted.
Communication
prohibited
Communication
prohibited
SSBRK=1
SVR=0
Communication
prohibited
XVS
・・・
・・・
・・・
・・・
tte
u
sh
r
sh
re
te
ut
r
ad
ad
r
valid data output
V2 period
t
ou
valid data output
V1 period
t
ou
invalid data output
t
ou
t
ou
EN
・・・
re
te
ut
ad
r
ad
r
valid data output
t
ou
valid data output
・・・
re
te
ut
re
te
ut
TI
・・・
sh
sh
sh
ad
Output
frame
・・・
re
sensor internal
V drive
XHS
AL
(SVR=2)
D
Example of using the break mode register SSBRK
C
(i)
O
N
FI
If output of V1 period in which SSBRK is set to 1h is going to be used as valid data, register PLSTMG23 (address
0542h, bit [7:0]) must be set. Set PLSTMG23 to 0h in the communication period of V1 and return to 1h at the top of
next frame. Example of setting timing of PLSTMG23 in chief cases is shown below. In addition, setting timing of
PLSTMG23 from 1h to 0h in this sequence must be within recommended serial communication period.
(SVR=2)
Communication
prohibited
SSBRK=1
SVR=0
PLSTMG23=0
PLSTMG23=1
XVS
・・・
・・・
・・・
・・・
r
te
ut
sh
r
ad
re
te
ut
sh
r
ad
re
te
ut
sh
r
ad
re
te
ut
sh
ad
t
ou
t
ou
t
ou
t
ou
Output
frame
・・・
re
sensor internal
V drive
XHS
valid data output
valid data output
valid data output
valid data output
V1 period
V2 period
(ii)
(SVR=2)
Communication
prohibited
SSBRK=1
SVR=1
PLSTMG23=0
PLSTMG23=1
XVS
・・・
・・・
・・・
・・・
r
te
ut
sh
ad
t
ou
V1 period
re
t
ou
valid data output
r
t
ou
valid data output
te
ut
sh
ad
re
r
te
ut
sh
ad
Output
frame
・・・
re
sensor internal
V drive
XHS
valid data output
V2 period
V3 period
Example of setting timing of PLSTMG23
(i) change to SVR is 0h (ii) change to SVR is larger than 0h
34
IMX206CQC
Analog Gain
The analog gain value can be set by setting the analog gain register PGC (address 0009h, bit [7:0] and address
000Ah, bit [2:0]). Set the lower 8 bits in address 0009h and the upper 3 bits in address 000Ah, for a total of 11 bits.
PGC Setting
Register value
Function
0h to 780h
(0d to 1920d)
Analog gain setting
In addition, the figure below shows the relationship between the register setting value and the set gain value.
When the register setting value is “0h (0d)”, the gain value is 0 dB (minimum settable value), and when “780h
(1920d)”, the gain value is approximately 24 dB (maximum settable value).
Relational Formula
Gain [dB] = –20log{(2048 – PGC [10:0])/2048}
AL
24
EN
12
N
FI
D
Gain [dB]
TI
18
0
0
C
O
6
128
256
384
512
640
768
896 1024 1152 1280 1408 1536 1664 1792 1920
PGC [dec]
Relationship between Register Setting Value and Set Gain Value
Digital Gain
The digital gain applied to the data after pixel binning can be set by the digital gain setting register DGAIN (address
0011h, bit [1:0]).
DGAIN Setting
Register value
Function
0h
Digital gain setting value = 0 dB
1h
Digital gain setting value = +6 dB
2h
Digital gain setting value = +12 dB
3h
Digital gain setting value = +18 dB
35
IMX206CQC
Digital Black Level Offset
The black level offset applied to the data after digital gain processing by the DGAIN register is set by the digital black
level offset setting register BLKLEVEL (address 0045h, bit [7:0]).
Note that the offset unit changes according to the readout drive mode.
When the output data length is 10-bit output, increasing the register setting value by 1h increases the black level by 1
digit. When the output data length is 12-bit output, increasing the register setting value by 1h increases the black
level by 4 digits.
BLKLEVEL Setting
Register value
0h to FFh
Function
Digital black level offset setting
Vertical Direction Readout Inversion
The direction of vertical readout order can be set by the vertical direction readout inversion register MDVREV
(address 001Ah, bit [0]).
MDVREV Setting
Function
Vertical direction normal readout
1h
Vertical direction inversion readout
TI
0h
AL
Register value
EN
Vertical Arbitrary Cropping
Horizontal Arbitrary Cropping
N
FI
D
By setting VWIDCUT and VWINPOS, the registers of vertical arbitrary cropping, arbitrary cropping in vertical
direction can be performed in all-pixel scan mode (10bits). See “Vertical Arbitrary Cropping (All-pixel scan 10 bit)” on
page 77 for details.
Readout Drive Mode
C
O
By setting HTRIMMING_EN, HTRIMMING_START and HTRIMMING_END, the registers of horizontal arbitrary
cropping, arbitrary cropping in horizontal direction can be performed in each readout drive mode. See “Horizontal
Arbitrary Cropping” on page 81 for details.
The readout drive mode of this sensor can be switched by setting the readout drive mode register MDSEL1 to
MDSEL4, VWIDCUT, VWINPOS, and HCOUNTHALF. When changing the mode, make the setting according to “3.
Register Settings for Each Readout Drive Mode” on pages 38 to 41.
The HCOUNTHALF register must be set to XHS period [INCK@72 MHz] / 2 (round down after the decimal point)
according to the sequence “2. Operation when Changing the Readout Drive Mode” on page 87 when the XHS period
is changed.
For example, when XHS period is to be changed to 200 [INCK@12 MHz] under INCK = 12 MHz, the value to be set
to the register HCOUNTHALF is 258h (600d) as this XHS period is 1200 [INCK@72 MHz] in INCK = 72 MHz
conversion.
36
IMX206CQC
Readout Drive Pulse Timing
The drive pulse timing is set by readout drive pulse timing registers PLSTMG01 to PLSTMG36.
PLSTMG Settings
Default value
Register name
Register Value
[4]
1h
PLSTMG01
Set to 0h.
010Eh
[7:0]
10h
PLSTMG02
Set to 11h.
0308h
[7:0]
14h
PLSTMG03
Set to 13h.
0309h
[7:0]
11h
PLSTMG04
Set to 10h.
030Ah
[7:0]
12h
PLSTMG05
Set to 11h.
0320h
[7:0]
0321h
[7:0]
0005h
PLSTMG06
Set to 0114h.
0322h
[7:0]
0323h
[7:0]
0012h
PLSTMG07
Set to 0018h.
0338h
[7:0]
05h
PLSTMG08
Set to 00h.
0342h
[7:0]
0343h
[7:0]
009Ah
PLSTMG09
Set to 0006h.
0344h
[7:0]
0345h
[7:0]
0087h
PLSTMG10
Set to 0113h.
034Ah
[7:0]
034Bh
[7:0]
0088h
PLSTMG11
AL
Bit assignment
002Ch
034Ch
[7:0]
034Dh
[7:0]
009Bh
PLSTMG12
Set to 0007h.
0352h
[7:0]
PLSTMG13
Set to 00h.
0353h
[7:0]
EN
Address
0354h
[7:0]
PLSTMG14
Set to 0000h.
TI
01h
PLSTMG15
Set to 11h.
0115h
PLSTMG16
Set to 01FFh.
000Bh
PLSTMG17
Set to 0000h.
0081h
PLSTMG18
Set to 007Eh.
00h
PLSTMG30
Set to 01h.
0005h
PLSTMG31
Set to 001Bh.
0089h
PLSTMG32
Set to 00B7h
[7:0]
07h
PLSTMG33
Set to 0Ch
053Fh
[7:0]
07h
PLSTMG34
Set to 08h
0540h
[7:0]
04h
PLSTMG35
Set to 03h
[7:0]
[7:0]
0360h
[7:0]
0361h
[7:0]
0362h
[7:0]
0406h
[7:0]
0407h
[7:0]
048Bh
[7:0]
0506h
[7:0]
0507h
[7:0]
050Eh
[7:0]
050Fh
[7:0]
053Eh
C
0359h
035Fh
O
N
FI
0700h
D
01h
Set to 0112h.
0542h
[7:0]
00h
PLSTMG23
Set to 01h.
055Bh
[7:0]
01h
PLSTMG24
Set to 00h.
0578h
[7:0]
0579h
[7:0]
0113h
PLSTMG25
Set to 01FFh.
057Ah
[7:0]
057Bh
[7:0]
000Bh
PLSTMG26
Set to 0000h.
057Dh
[7:0]
0Ch
PLSTMG36
Set to 08h
37
IMX206CQC
3. Register Setting for Each Readout Drive Mode
The register setting for each readout drive mode available with this sensor is shown in the table below.
3-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3)
Description of Register Setting for Each Readout Drive Mode
Register
name
0
1
2
2A
3
4
5
6
7
8
[2:0]
STBLVDS
3h
3h
3h
3h
3h
3h
5h
3h
3h
3h
5h
3h
3h
3h
0003h
Readout mode No.
[3]
[6:4]
0h
CHSEL
3h
3h
3h
3h
3h
[7:0]
MDSEL1
00h
00h
10h
10h
14h
18h
18h
1Ch
10h
14h
0005h
[7:0]
MDSEL2
03h
01h
11h
11h
19h
19h
19h
19h
21h
19h
0006h
[7:0]
MDSEL3
30h
20h
20h
20h
20h
20h
A3h
20h
20h
20h
0007h
[7:0]
MDSEL4
00h
00h
09h
09h
05h
05h
05h
05h
09h
05h
*1
*1
0h
0h
0h
0h
0h
0h
[7:0]
[0]
0071h
0072h
007Ch
007Dh
[7:0]
[2:0]
MDVREV
[2:0]
TI
Multiple
of 8 – 1
000h 000h
O
VWINPOS
VWIDCUT
According to
exposure time
0h: vertical direction normal/1h:inverted
00h
06Ch
normal
F94h
inverted
000h
000h
000h
000h
000h
06Ch
090h
normal normal
F94h
F70h
inverted inverted
000h
000h
0D8h
0h
000h 000h
0D8h
[7:3]
[7:0]
(invalid)
According to exposure time
SVR
[7:0]
[7:4]
*3
GSVR
[7:1]
[3:0]
0h
EN
000Eh
0h
0h
D
[7:0]
0070h
0h
N
FI
000Dh
006Fh
0h
[3:1]
[7:4]
001Ah
SMD
C
0008h
*3
0h
0004h
[0]
*2
3h
AL
[7]
*1
*2
Bit
Address assignment
000h
000h
000h
00h
HCOUNTHALF
Set XHS period [INCK, 72 MHz conversion] / 2
(round down after the decimal point)
[7:3]
00h
Can be used in combination with global reset shutter (address 0008h, bit [0], when SMD = 1h)
See “1-1. Readout Drive Modes” on page 42 for details of readout mode No.
Specifies the vertical period for reading during global reset shutter drive. (0h to Fh)
38
120h
IMX206CQC
3-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9)
Description of Register Setting for Each Readout Drive Mode
Address
0003h
Readout mode No. *2
Bit
assignment
Register
name
0
1
2
5
[2:0]
STBLVDS
3h
3h
3h
5h
[3]
[6:4]
0h
CHSEL
3h
3h
3h
[7]
0h
0004h
[7:0]
MDSEL1
00h
00h
10h
18h
0005h
[7:0]
MDSEL2
03h
01h
11h
19h
0006h
[7:0]
MDSEL3
30h
20h
20h
A3h
0007h
[7:0]
MDSEL4
00h
00h
09h
05h
*1
*1
0h
0h
[0]
0h
0h
[3:1]
[7:0]
000Eh
[7:0]
[0]
GSVR
According to
exposure time
SVR
0071h
0072h
007Ch
007Dh
*2
*3
[7:0]
[2:0]
0B4h
normal
F4Ch
inverted
D
0B4h
normal
F4Ch
inverted
N
FI
O
[7:4]
VWINPOS
VWIDCUT
C
0070h
00h
[7:0]
[3:0]
168h
[2:0]
05Ah
normal
FA6h
inverted
014h
normal
FECh
inverted
0h
168h
[7:3]
[7:0]
Multiple
of 8 – 1
0h: vertical direction normal
/1h:inverted
MDVREV
[7:1]
006Fh
(invalid)
AL
000Dh
0h
*3
TI
[7:4]
001Ah
SMD
EN
0008h
*1
5h
0B4h
028h
00h
HCOUNTHALF
Set XHS period [INCK, 72 MHz conversion] / 2
(round down after the decimal point)
[7:3]
00h
Can be used in combination with global reset shutter (address 0008h, bit [0], when SMD = 1h)
See “1-2. Readout Drive Modes” on page 43 for details of readout mode No.
Specifies the vertical period for reading during global reset shutter drive. (0h to Fh)
39
IMX206CQC
3-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)
Description of Register Setting for Each Readout Drive Mode
Address
0003h
Readout mode No. *2
Bit
assignment
Register
name
0
1
2
5
[2:0]
STBLVDS
3h
3h
3h
5h
[3]
[6:4]
0h
CHSEL
3h
3h
3h
[7]
0h
0004h
[7:0]
MDSEL1
00h
00h
10h
18h
0005h
[7:0]
MDSEL2
43h
41h
51h
59h
0006h
[7:0]
MDSEL3
30h
20h
20h
A3h
0007h
[7:0]
MDSEL4
00h
00h
09h
05h
*1
*1
0h
0h
[0]
0h
0h
[3:1]
[7:0]
000Eh
[7:0]
[0]
GSVR
According to
exposure time
SVR
0071h
0072h
007Ch
007Dh
*2
*3
[7:0]
[2:0]
0B4h
normal
F4Ch
inverted
D
0B4h
normal
F4Ch
inverted
N
FI
O
[7:4]
VWINPOS
VWIDCUT
C
0070h
00h
[7:0]
[3:0]
168h
[2:0]
05Ah
normal
FA6h
inverted
014h
normal
FECh
inverted
0h
168h
[7:3]
[7:0]
Multiple
of 8 – 1
0h: vertical direction normal
/1h:inverted
MDVREV
[7:1]
006Fh
(invalid)
AL
000Dh
0h
*3
TI
[7:4]
001Ah
SMD
EN
0008h
*1
5h
0B4h
028h
00h
HCOUNTHALF
Set XHS period [INCK, 72 MHz conversion] / 2
(round down after the decimal point)
[7:3]
00h
Can be used in combination with global reset shutter (address 0008h, bit [0], when SMD = 1h)
See “1-3. Readout Drive Modes” on page 43 for details of readout mode No.
Specifies the vertical period for reading during global reset shutter drive. (0h to Fh)
40
IMX206CQC
3-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3)
Description of Register Setting for Each Readout Drive Mode
Address
0003h
Readout mode No. *2
Bit
assignment
Register
name
0
5
[2:0]
STBLVDS
3h
5h
[3]
[6:4]
0h
CHSEL
3h
5h
[7]
0h
0004h
[7:0]
MDSEL1
00h
18h
0005h
[7:0]
MDSEL2
81h
99h
0006h
[7:0]
MDSEL3
00h
83h
0007h
[7:0]
MDSEL4
00h
05h
*1
0h
GSVR
*3
[3:1]
[7:0]
000Eh
[7:0]
[0]
According to
exposure time
SVR
MDVREV
[7:1]
0071h
0072h
007Ch
007Dh
*1
*2
*3
[7:0]
[2:0]
0h: vertical direction normal
/1h:inverted
1D8h
normal
E28h
inverted
N
FI
[7:4]
VWINPOS
O
0070h
[7:0]
[3:0]
VWIDCUT
[2:0]
034h
normal
FCCh
inverted
0h
3B0h
068h
[7:3]
[7:0]
Multiple
of 8 – 1
00h
C
006Fh
(invalid)
AL
000Dh
0h
EN
[7:4]
001Ah
0h
D
0008h
SMD
TI
[0]
00h
HCOUNTHALF
Set XHS period [INCK, 72 MHz conversion] / 2
(round down after the decimal point)
[7:3]
00h
Can be used in combination with global reset shutter (address 0008h, bit [0], when SMD = 1h)
See “1-4. Readout Drive Modes” on page 43 for details of readout mode No.
Specifies the vertical period for reading during global reset shutter drive. (0h to Fh)
41
IMX206CQC
Readout Drive Modes
1. Readout Drive Modes
The table below describes the readout drive modes that can be used to operate this sensor.
All of the modes listed in the table below support vertical direction inversion operation (MDVREV = 0h/1h).
Note that some readout drive modes need different (1) register settings and (2) vertical front blanking when vertical
readout direction is normal and inverted.
See “3. Register Setting for Each Readout Drive Mode” on pages 38 to 41 for the register setting, and “Minimum
Vertical Operation Period in Each Readout Drive Mode” on pages 50, 62, 68 and 74, and “Image Data Output Format”
on pages 52 to 61, 64 to 67, 70 to 73 and 75 to 76 for the vertical front blanking.
1-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3)
Description of Readout Drive Modes
Readout
mode No.
Readout drive mode
Mode description
All-pixel scan mode (12 bits)
All pixels are readout with 12-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
1
All-pixel scan mode (10 bits)
All pixels are readout with 10-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
2
Horizontal/vertical
2/2-line binning 16:9 cropping
(Horizontal and vertical
weighted binning)
Horizontal and vertical direction 2-line weighted binning readout
of pixels of the same color at the all-pixel scan area (16:9 cropping)
(See the image of binning on page 45.)
2A
Horizontal/vertical 2/2-line binning Horizontal and vertical direction 2-line weighted binning readout
(Horizontal and vertical
of pixels of the same color at the all-pixel scan area
weighted binning)
(See the image of binning on page 45.)
3
Vertical 2/3 subsampling binning
horizontal 3 binning
4
Vertical 2/9 subsampling binning
horizontal 3 binning
2 of every 9 lines in the vertical direction at the all-pixel scan area
are added. Then, 3 pixels of the same color in the horizontal direction
are added and output.
(See the image of binning on page 46.)
5
Vertical 2/9 subsampling binning
horizontal 3 binning
low power consumption drive
2 of every 9 lines in the vertical direction at the all-pixel scan area
are added. Then, 3 pixels of the same color in the horizontal
direction are added and output.
(See the image of binning on page 46.)
6
2 of every 19 lines in the vertical direction at the all-pixel scan area
Vertical 2/19 subsampling binning are added. Then, 3 pixels of the same color in the horizontal
horizontal 3 binning
direction are added and output.
(See the image of binning on page 46.)
7
Vertical 2 binning horizontal 2/4
subsampling 16:9 cropping
(Vertical weighted binning)
Add 2 lines with weighting in the vertical direction at the all-pixel
scan area (16:9 cropping) and 2 of every 4 lines in the horizontal
direction are output. (See the image of binning on page 45.)
8
Vertical 2/3 subsampling binning
horizontal 3 binning cropping
2 of every 3 lines in the vertical direction at the all-pixel scan area
(cropping) are added. Then, 3 pixels of the same color in the
horizontal direction are added and output.
(See the image of binning on page 45.)
D
EN
TI
AL
0
C
O
N
FI
2 of every 3 lines in the vertical direction at the all-pixel scan area are
added. Then, 3 pixels of the same color in the horizontal direction are
added and output.
(See the image of binning on page 45.)
See the following pages for the detailed specifications of each mode noted in the table above.
(1)
(2)
Horizontal/vertical operation periods in each readout drive mode
NTSC/PAL compatible drive
: Page 50
: Page 51
(3)
Image data output format
: Pages 52 to 61
42
IMX206CQC
1-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9)
Description of Readout Drive Modes
Readout
mode No.
Readout drive mode
0
All-pixel scan mode (12 bits)
1
All-pixel scan mode (10 bits)
2
Horizontal/vertical 2/2-line binning
(Horizontal and vertical
weighted binning)
5
Vertical 2/9 subsampling binning
horizontal 3 binning
low power consumption drive
Mode description
All pixels are readout with 12-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
All pixels are readout with 10-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
Horizontal and vertical direction 2-line weighted binning readout
of pixels of the same color at the all-pixel scan area (See the image of
binning on page 45.)
2 of every 9 lines in the vertical direction at the all-pixel scan area
are added. Then, 3 pixels of the same color in the horizontal
direction are added and output.
(See the image of binning on page 46.)
See the following pages for the detailed specifications of each mode noted in the table above.
(1)
(2)
(3)
Horizontal/vertical operation periods in each readout drive mode
NTSC/PAL compatible drive
Image data output format
: Page 62
: Page 62
: Pages 64 to 67
AL
1-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)
Description of Readout Drive Modes
1
All-pixel scan mode (10 bits)
2
Horizontal/vertical 2/2-line binning
(Horizontal and vertical
weighted binning)
5
Vertical 2/9 subsampling binning
horizontal 3 binning
low power consumption drive
All pixels are readout with 12-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
All pixels are readout with 10-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
Horizontal and vertical direction 2-line weighted binning readout
of pixels of the same color at the all-pixel scan area (See the image of
binning on page 45.)
2 of every 9 lines in the vertical direction at the all-pixel scan area
are added. Then, 3 pixels of the same color in the horizontal
direction are added and output.
(See the image of binning on page 46.)
EN
All-pixel scan mode (12 bits)
Mode description
O
N
FI
0
TI
Readout drive mode
D
Readout
mode No.
(1)
(2)
(3)
C
See the following pages for the detailed specifications of each mode noted in the table above.
Horizontal/vertical operation periods in each readout drive mode
NTSC/PAL compatible drive
Image data output format
: Page 68
: Page 68
: Pages 70 to 73
1-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3)
Description of Readout Drive Modes
Readout
mode No.
Readout drive mode
1
All-pixel scan mode (10 bits)
5
Vertical 2/9 subsampling binning
horizontal 3 binning
low power consumption drive
Mode description
All pixels are readout with 10-bit output.
This mode can be used together with the global reset shutter
function according to the SMD register setting.
2 of every 9 lines in the vertical direction at the all-pixel scan area
are added. Then, 3 pixels of the same color in the horizontal
direction are added and output.
(See the image of binning on page 46.)
See the following pages for the detailed specifications of each mode noted in the table above.
(1)
(2)
(3)
Horizontal/vertical operation periods in each readout drive mode
NTSC/PAL compatible drive
Image data output format
43
: Page 74
: Page 74
: Pages 75 to 76
IMX206CQC
1-5. Relationship between Arithmetic Processing and the Number of Output Bits in Each Readout Drive
Mode
The table below shows the relationship between the A/D conversion resolution, number of binning pixels, internal
arithmetic processing, and number of output bits in each readout mode.
Note that the number of output bits differs in each mode.
Vertical pixel
processing
Total number
of binning
pixels
Internal
arithmetic
processing
Number of
output bits
0
12 bits
—
—
—
—
10 bits + 2 bits *1
1
10 bits
—
—
—
—
10 bits
2, 2A
10 bits
2 binning
2 binning
4 pixels
9/16, 3/16,
1/16
(weighted
*2
binning )
10 bits
3, 8
10 bits
3 binning
2/3
subsampling
binning
6 pixels
1/6
10 bits
4, 5
10 bits
3 binning
2/9
subsampling
binning
6 pixels
1/6
10 bits
6
10 bits
3 binning
2/19
subsampling
binning
6 pixels
1/6
10 bits
7
10 bits
2/4
subsampling
2 pixels
3/4, 1/4
(weighted
binning *2)
10 bits
EN
TI
Horizontal
pixel
processing
N
FI
D
2 binning
A/D conversion is performed with a resolution 4 times that of 10-bit A/D conversion, and the results are output
in 12 bits regarded as a 10-bit integer item and a 2-bit decimal item.
See pages 45 to 46 “Binning Image” for details of weighted binning.
O
*2
A/D
conversion
resolution
C
*1
Readout
mode
No.
AL
Relationship between Arithmetic Processing and the Number of Output Bits in Each Readout Drive Mode
44
IMX206CQC
B
Gb
B
Gb
B
Gb
Gr R1 Gr1 R2 Gr2 R
B Gb1 B1 Gb2 B2 Gb
Gr R3 Gr3 R4 Gr4 R
B Gb3 B3 Gb4 B4 Gb
Gr
R
Gr
R
Gr
R
R' = ( 9×R1 + 3×R2 + 3×R3 + R4 ) / 16
Gr' = ( 3×Gr1 + 9×Gr2 + Gr3 + 3×Gr4 ) / 16
Gb' = ( 3×Gb1 + Gb2 + 9×Gb3 + 3×Gb4 ) / 16
B' = ( B1 + 3×B2 + 3×B3 + 9×B4 ) / 16
R’ Gr’
Gb’ B’
Horizontal/Vertical 2/2-line Binning
(horizontal and vertical weighted binning)
Binning Image
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr R1 Gr R2 Gr1 R3 Gr2 R Gr3 R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
AL
Gr R4 Gr R5 Gr4 R6 Gr5 R Gr6 R
B Gb1 B Gb2 B1 Gb3 B2 Gb B3 Gb
R
Gr
R
Gr
R
Gr
R
Gr
R
TI
Gr
Gr
R
Gr
R
EN
B Gb4 B Gb5 B4 Gb6 B5 Gb B6 Gb
Gr
R
Gr
R
Gr
R
R' = ( R1+R2+R3+R4+R5+R6 )/6
Gr' = ( Gr1+Gr2+Gr3+Gr4+Gr5+Gr6 )/6
Gb' = ( Gb1+Gb2+Gb3+Gb4+Gb5+Gb6 )/6
B' = ( B1+B2+B3+B4+B5+B6 )/6
D
R’ Gr’
N
FI
Gb’ B’
C
O
Vertical 2/3 Subsampling Binning Horizontal 3 Binning
Binning Image
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr R1 Gr1 R
Gr
R
B
Gb
B Gb1 B1 Gb
B
Gb
Gr
R
Gr R2 Gr2 R
Gr
R
B
Gb
B Gb2 B2 Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
R’ Gr’
Gb’ B’
R'=(3×R1 + R2)/4
Gr'=(3×Gr1 + Gr2)/4
Gb'=(Gb1 + 3×Gb2)/4
B'=(B1 + 3×B2)/4
Vertical 2 Binning Horizontal 2/4 Subsampling
(vertical weighted binning)
Binning Image
Note) White letters in the diagram indicate pixels which are not read out.
45
IMX206CQC
B
Gb
B
Gb
B
Gb
B
Gb
B
Gr
R
Gr
R
Gr
R
Gr
R
Gr
Gb
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr R1 Gr R2 Gr1 R3 Gr2 R Gr3 R
B
Gb
B
Gb
B
Gr
R
B
Gb
Gr
R
Gb
B
Gr
R
B
Gb
Gr
R
Gb
B
Gr
R
B
Gb
Gr
R
Gb
Gr
R
Gr
R
B
Gb
B
Gb
Gr
R
Gr
R
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr R4 Gr R5 Gr4 R6 Gr5 R Gr6 R
B
Gb
B
Gr
R
B
Gb
Gb
B
Gr
R
B
Gb
Gb
B
Gr
R
B
Gb
Gb
Gr
R
Gr
R
B
Gb
B
Gb
Gr R1 Gr R2 Gr1 R3 Gr2 R Gr3 R
B
Gb
B
Gr
R
B
Gb
Gb
B
Gr
R
B
Gb
Gb
B
Gr
R
B
Gb
Gb
Gr
R
Gr
R
B
Gb
B
Gb
D
Gb
Gr
R
Gr
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gr
R
Gr
R
Gr
B
Gb
B
Gb
Gr
R
Gr
R
B
R
Gr
Gb
B
Gb
B
R
Gb
Gr
R
Gr
R
B
Gb
B
Gb
Gr
R
Gr
R
Gb
B
Gb
B
Gb
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
B Gb1 B Gb2 B1 Gb3 B2 Gb B3 Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gb
B
Gb
B
Gb
B
Gb
B
Gb
N
FI
B
Gb
TI
Gb
B
EN
B
Gb
AL
B
Gr
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr R4 Gr R5 Gr4 R6 Gr5 R Gr6 R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
R
Gr
R
Gr
R
Gr
R
Gr
R
Gb
R
Gr
R
Gr
R
Gr
B
Gb
B
Gb
B
Gb
B
O
Gr
B
Gb
B
Gb
B
Gb
B
Gb
B
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B Gb4 B Gb5 B4 Gb6 B5 Gb B6 Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gb
B
Gb
B
Gb
B
Gb
B
Gb
C
R
B Gb1 B Gb2 B1 Gb3 B2 Gb B3 Gb
R
B
B Gb4 B Gb5 B4 Gb6 B5 Gb B6 Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
Gr
R
R’ Gr’
Gb’ B’
Gr
R
Gr
R
Gr
R
Gr
R'=(R1+R2+R3+R4+R5+R6)/6
Gr'=(Gr1+Gr2+Gr3+Gr4+Gr5+Gr6)/6
Gb'=(Gb1+Gb2+Gb3+Gb4+Gb5+Gb6)/6
B'=(B1+B2+B3+B4+B5+B6)/6
R’ Gr’
Gb’ B’
R'=(R1+R2+R3+R4+R5+R6)/6
Gr'=(Gr1+Gr2+Gr3+Gr4+Gr5+Gr6)/6
Gb'=(Gb1+Gb2+Gb3+Gb4+Gb5+Gb6)/6
B'=(B1+B2+B3+B4+B5+B6)/6
Vertical 2/9 Subsampling Binning
Vertical 2/19 Subsampling Binning
Horizontal 3 Binning
Horizontal 3 Binning
Binning Image
Binning Image
Note) White letters in the diagram indicate pixels which are not read out.
46
IMX206CQC
2. Sync Signals and Data Output Timing
The figure below shows the sync signal and data output timing during 12-bit length serial output for this sensor.
The horizontal and vertical timing of the output data are controlled by the XVS and XHS sync signals. Timing control
is performed at the falling edge of both the XVS and XHS signals. The data is output in order from the start sync code
(SAV) after the horizontal front blanking period after the falling edge.
See “Minimum Horizontal Operation Period in Each Readout Drive Mode” on pages 50, 62, 68 and 74 for the detailed
blanking length and number of OPB pixels. The length of horizontal front blanking pixels varies greatly according to
the mode as described in “Minimum Horizontal Operation Period in Each Readout Drive Mode” on pages 50, 62, 68
and 74, so using the sync code as the trigger is recommended for the recording pixel start timing.
The sync code details are shown below.
In addition, the length of horizontal rear blanking changes when the XHS period is changed.
Horizontal front blanking
Start sync code (SAV)
Pixel data
XVS
XHS
DCK
[11]・・・[0]
[11]・・・[0]
[11]・・・[0]
[11]・・・[0]
[11]・・・[0]
[11]・・・[0]
SAV1
SAV2
SAV3
SAV4
OPB ignored
OPB ignored
Pixel data
AL
DO
End sync code (EAV)
Horizontal rear blanking
XVS
DCK
[11]・・・[0]
[11]・・・[0]
EAV1
EAV2
[11]・・・[0]
[11]・・・[0]
EAV3
EAV4
D
[11]・・・[0]
Effective ignored
N
FI
DO
EN
TI
XHS
Sync Signal and Data Output Timing
DOP0/DOM0
1st
[11]
DOP3/DOM3
1st
[11]
C
O
DCKP/DCKM
1st
[10]
1st
[9]
1st
[8]
1st
[7]
1st
[6]
1st
[5]
1st
[4]
1st
[3]
1st
[2]
1st
[1]
1st
[0]
1st
[10]
1st
[9]
1st
[8]
1st
[7]
1st
[6]
1st
[5]
1st
[4]
1st
[3]
1st
[2]
1st
[1]
1st
[0]
Serial Data Details (Sync Code Block)
DCKP/DCKM
DOP0/DOM0
D0
[11]
D0
[10]
D0
[9]
D0
[8]
D0
[7]
D0
[6]
D0
[5]
D0
[4]
D0
[3]
D0
[2]
D0
[1]
D0
[0]
DOP3/DOM3
D3
[11]
D3
[10]
D3
[9]
D3
[8]
D3
[7]
D3
[6]
D3
[5]
D3
[4]
D3
[3]
D3
[2]
D3
[1]
D3
[0]
Serial Data Details (Pixel Data Block)
47
IMX206CQC
Sync code details
Sync code (4 words)
12-bit output
10-bit output
1st word
2nd word
3rd word
4th word
11
9
1
0
0
1
10
8
1
0
0
0
9
7
1
0
0
V
1: Blanking line
0: Except blanking line
8
6
1
0
0
H
1: End sync code
0: Start sync code
7
5
1
0
0
P3
6
4
1
0
0
P2
5
3
1
0
0
P1
4
2
1
0
0
P0
3
1
1
0
0
0
2
0
1
0
0
0
1
—
1
0
0
0
0
—
1
0
AL
LVDS output bit No.
0
TI
0
Protection bits
P1
EN
P0
0
0
D
Protection bits
0
1
0
1
1
1
1
0
H
P3
P2
0
0
0
0
0
1
1
1
1
0
1
1
1
0
O
N
FI
V
C
Sync code details (hexadecimal notation) 12-bit output
Blanking line
Except blanking line
1st word
2nd word
3rd word
Start sync code (SAV)
4th word
AB0h
End sync code (EAV)
FFFh
Start sync code (SAV)
000h
000h
End sync code (EAV)
B60h
800h
9D0h
Sync code details (hexadecimal notation) 10-bit output
1st word
Blanking line
Except blanking line
2nd word
3rd word
Start sync code (SAV)
4th word
2ACh
End sync code (EAV)
3FFh
Start sync code (SAV)
End sync code (EAV)
000h
000h
2D8h
200h
274h
48
IMX206CQC
3. Output Range of LVDS Output Data
The table below shows the decimal point position, output bit length and output range of the output data in each
readout mode. Note that the value of the first word of the sync code (3FFh, FFFh) and the maximum data value do
not overlap in any readout mode.
Data output range in each readout mode
LVDS output
Readout
mode No.
Decimal point position
Output bit length [bit]
Output range [hex]
0
2
12
001h to FFEh
1 to 8
0
10
001h to 3FEh
Output value during horizontal blanking period is fixed to Low (all 0).
Horizontal sync signal
SAV
EAV
Pixel data
[Pixel data]
12 bits: 001h to FFEh
10 bits: 001h to 3FEh
TI
[Horizontal blanking]
Fixed Low
AL
Horizontal blanking
C
O
N
FI
D
EN
Readout Drive Timing
49
Horizontal blanking
[Horizontal blanking]
Fixed Low
IMX206CQC
4. Detailed Specification of Each Mode
4-1. When Using Type 1/2.3 Approx. 16.35 M Pixels (4:3)
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode
Horizontal operation period (Number of pixels conversion)
XHS
Horizontal
minimum
Recommended
Front
Rear
front blanking Front
Rear
period
effective
recording
effective
*2 *3
[DCK]
OPB pixel margin
OPB
*2 *4
pixel
margin
[INCK]
pixels
0
576
(288DDR*1)
380 to 385
96
28
4608
36
0
1804
1
576
*1
(288DDR )
380 to 385
96
28
4608
36
0
1504
2
576
(288DDR*1)
388 to 393
48
14
2304
18
0
760
2A
576
*1
(288DDR )
388 to 393
48
14
2304
18
0
760
3
576
(288DDR*1)
388 to 393
32
10
1536
12
0
714
4
576
(288DDR*1)
388 to 393
32
10
1536
12
0
714
5
576
(288DDR*1)
388 to 393
32
10
12
0
714
6
576
(288DDR*1)
388 to 393
32
10
1536
12
0
714
7
576
(288DDR*1)
380 to 385
48
14
2304
18
0
758
8
576
(288DDR*1)
388 to 393
32
10
1536
12
0
714
EN
D
DDR: Double Data Rate
If XHS period is shorter than the (XHS minimum period + horizontal front blanking), the data from the previous
line may be output during the horizontal front blanking period.
Number of LVDS output signal DCK clock
Number of clocks in conversion of INCK = 72 MHz.
C
*4
N
FI
*3
1536
O
*1
*2
AL
Readout
mode No.
Data rate
[MHz]
TI
Horizontal Operation Period in Each Readout Drive Mode
Vertical Operation Period in Each Readout Drive Mode
Number of lines per vertical operation period (output data 1H conversion)
Readout
mode No.
Vertical front
blanking
Recommended
Front Front effective
Rear effective
recording
pixel margin
OPB pixel margin
pixels
Rear
OPB
XVS
minimum
period
[XHS]
0
16
16
22
3456
22
0
3532
1
16
16
22
3456
22
0
3532
2
14
4
8
1296
8
0
1330
2A
14
4
8
1728
8
0
1762
3
11
4
8
1152
8
0
1183
4
11
4
4
384
4
0
407
5
26
4
4
384
4
0
403
6
11
4
4
180
4
0
203
7
14
4
8
1296
8
0
1330
8
11
4
8
576
8
0
607
50
IMX206CQC
(2) NTSC/PAL Compatible Drive
This sensor can be used with a frame frequency that supports NTSC or PAL by using the recommended horizontal
operating period (XHS period) and recommended vertical operating period (V period) for each readout drive mode
shown in the table below. Note that the number of XHS pulses input within the horizontal operating period (H
period) varies according to the drive mode.
Recommended H Period and V Periods (NTSC/PAL Compatible)
NTSC compatible drive
H period
Readout
XHS period (number of
mode No.
*1
(INCK)
XHS
pulses) *2
Frame
frequency
[frame/s]
H period
V period
XHS period (number of (number of
*1
(INCK)
XHS
XHS
pulses) *2
pulses)
9.99
2000
1
3600
10.00
Frame
frequency
[frame/s]
2016
1
3575
1
1680
1
3575
11.99
2000
1
3600
10.00
2
880
1
1365
59.94
900
1
1600
50.00
2A
1320
1
1820
29.97
1440
1
2000
25.00
3
880
1
1365
59.94
900
1
1600
50.00
4
715
1
420
239.76
750
1
480
200.00
5
715
4
3360
29.97
800
4
3600
25.00
6
780
1
220
419.58
750
1
240
400.00
7
880
1
1365
59.94
900
1
1600
50.00
8
728
1
825
119.88
750
1
960
100.00
TI
AL
0
Number of clocks in conversion of INCK = 72 MHz
Number of XHS pulses required to output the data for one sensor line
EN
*2
V period
(number
of XHS
pulses)
D
*1
PAL compatible drive
Number of
LVDS
output
channels [ch]
O
Data rate
[MHz]
C
Readout
mode No.
N
FI
Imaging Conditions in Each Readout Drive Mode (NTSC/PAL Compatible Drive)
Imaging conditions
Number of
A/D
conversion
bits [bit]
Output
data bit
length [bit]
Number of
horizontal
recording
pixels
Number of
vertical
recording
pixels
Number of
recording pixels
0
576
(288DDR)
4
12
12
4608
3456
Approximately
15.93 M Pixels
1
576
(288DDR)
4
10
10
4608
3456
Approximately
15.93 M Pixels
2
576
(288DDR)
4
10
10
2304
1296
Approximately
2.99 M Pixels
2A
576
(288DDR)
4
10
10
2304
1728
Approximately
3.98 M Pixels
3
576
(288DDR)
4
10
10
1536
1152
Approximately
1.77 M Pixels
4
576
(288DDR)
4
10
10
1536
384
Approximately
0.59 M Pixels
5
576
(288DDR)
1
10
10
1536
384
Approximately
0.59 M Pixels
6
576
(288DDR)
4
10
10
1536
180
Approximately
0.28 M Pixels
7
576
(288DDR)
4
10
10
2304
1296
Approximately
2.99 M Pixels
8
576
(288DDR)
4
10
10
1536
576
Approximately
0.88 M Pixels
51
IMX206CQC
(3) Image Data Output Format
The output format in each readout drive mode is as follows.
MODE0: All-pixel scan mode (9.99 frame/s, 12-bit A/D conversion, 12-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
4608
AL
4632
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
3456
3492
3500
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 effective margin for color processing
3516
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
TI
4672
18 Effective margin for color processing
4 Ignored area of effective pixel
EN
V blank
4768
N
FI
D
Readout Pixel Image Diagram (4608 × 3456)
1[XVS] = 3575[XHS]
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
36
37
38
39
14
15
16
17
18
19
20
21
0
1
DO
C
XHS
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
3492
3493
3494
3495
O
XVS
Effective pixels
3456H[3456XHS]
VBLK period
43XHS
3510
3511
3512
3513
3514
3515
Front dummy 16XHS
[Communication
period +
sensor clamp]
1[H] = 1[XHS] = 2016[INCK@72MHz] = 8064[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
Sync code
HOPB
ignored
24
36
HOPB
72
HOPB
ignored
36
Ignored
area of
effective
pixel
24
Margin for
Color
processing
18
Effective pixels
6912
Margin for
Color
processing
Ignored
area of
effective
pixel
18
36
Sync code
24
XHS
SAV1[11]
SAV1[10]
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
4760
4764
EAV1
EAV2
EAV3
EAV4
4762
4766
EAV1
EAV2
EAV3
EAV4
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4720
4724
4728
4732
4736
4740
4744
4748
4722
4726
4730
4734
4738
4742
4746
4750
4723
4727
4731
4735
4739
4743
4747
4751
DCK(288MHz)
DO
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
89
93
97
101
105
109
113
117
121
125
129
133
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
18
22
26
30
DO3
19
23
27
31
DO2
SAV1
SAV2
SAV3
SAV4
2
6
DO1
LVDS output
4ch 12bit serial
SAV1
SAV2
SAV3
SAV4
3
7
SAV1
SAV2
SAV3
SAV4
1
5
DO0
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
DCK
(288MHz)
6[DCK] * Detected both edges.
Readout Drive Timing
52
HBLK period
IMX206CQC
MODE1: All-pixel scan mode (11.99 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
4608
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
3456
3492
3500
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 effective margin for color processing
3516
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
4632
4672
AL
18 Effective margin for color processing
4 Ignored area of effective pixel
V blank
TI
4768
EN
Readout Pixel Image Diagram (4608 × 3456)
1[XVS] = 3575[XHS]
O
3510
3511
3512
3513
3514
3515
Ignored area
of effective
Margin for
pixel
Color processing
VBLK period
4H[4XHS]
18H[18XHS]
43XHS
3492
3493
3494
3495
0
1
14
15
16
17
18
19
20
21
XHS
DO
Effective pixels
3456H[3456XHS]
N
FI
XVS
D
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
36
37
38
39
Front dummy 16XHS
[Communication
period +
sensor clamp]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
C
1[H] = 1[XHS] = 1680[INCK@72MHz] = 6720[DCK]
Sync code
HOPB
ignored
HOPB
ignored
20
30
30
HOPB
60
Ignored
area of
effective
pixel
20
Margin for
Color
processing
15
Effective pixels
5760
Ignored
Margin for area of
effective
Color
processing pixel
15
30
Sync code
20
XHS
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
4760
4764
EAV1
EAV2
EAV3
EAV4
4762
4766
EAV1
EAV2
EAV3
EAV4
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4720
4724
4728
4732
4736
4740
4744
4748
4722
4726
4730
4734
4738
4742
4746
4750
4723
4727
4731
4735
4739
4743
4747
4751
DCK(288MHz)
DO
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
89
93
97
101
105
109
113
117
121
125
129
133
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
18
22
26
30
DO3
19
23
27
31
DO2
SAV1
SAV2
SAV3
SAV4
2
6
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
SAV1
SAV2
SAV3
SAV4
1
5
DO0
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
53
HBLK period
IMX206CQC
MODE2: Horizontal/vertical 2/2-line binning mode 16:9 cropping (horizontal and vertical weighted binning)
(59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 14XHS (communication period + sensor clamp)
2304
2316
H blank
6 Effective margin for color processing
12 Ignored area of effective pixel
1296
1308
1312
24 HOPB
12 Ignored OPB
8 Ignored area of effective pixel
6 Effective margin for color processing
12 Ignored OPB
1316
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
2336
6 Effective margin for color processing
2 Ignored area of effective pixel
AL
V blank
2384
EN
TI
Readout Pixel Image Diagram (2304 × 1296)
1[XVS] = 1365[XHS]
D
VBLK period
35XHS
O
0
1
2
3
4
5
6
7
DO
10
11
12
13
XHS
Color processing
6H[6XHS]
1306
1307
1308
1309
N
FI
XVS
Effective pixels
1296H[1296XHS]
Ignored area
of effective
pixel
Margin for 2H[2XHS]
1312
1313
1314
1315
Ignored area
of effective
Front dummy 14XHS
pixel
[Communication
2H[2XHS] Margin for
period +
Color processing
User
clamp
sensor clamp]
6H[6XHS]
4H[4XHS]
Number of DCK clock
[@288MHz]
HBLK period
388 to 393
C
1[H] = 1[XHS] = 880[INCK@72MHz] = 3520[DCK]
HOPB
Sync code ignored
20
15
HOPB
ignored
HOPB
30
15
Ignored
area of Margin for
effective
Color
pixel processing
10
10
Effective pixels
2880
Ignored
Margin for area of
effective
Color
pixel Sync code
processing
5
15
20
XHS
2352
2356
2360
2364
2368
2372
2376
2380
EAV1
EAV2
EAV3
EAV4
2354
2358
2362
2366
2370
2374
2378
2382
EAV1
EAV2
EAV3
EAV4
2355
2359
2363
2367
2371
2375
2379
2383
EAV1
EAV2
EAV3
EAV4
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
2353
2357
2361
2365
2369
2373
2377
2381
EAV1
EAV2
EAV3
EAV4
28
32
36
40
44
48
52
56
60
64
68
72
30
34
38
42
46
50
54
58
62
66
70
74
DO3
31
35
39
43
47
51
55
59
63
67
71
75
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
DO0
29
33
37
41
45
49
53
57
61
65
69
73
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
54
HBLK period
IMX206CQC
MODE2A: Horizontal/vertical 2/2-line binning mode (horizontal and vertical weighted binning)
(29.97 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 14XHS (communication period + sensor clamp)
2304
H blank
6 Effective margin for color processing
12 Ignored area of effective pixel
1728
1740
1744
24 HOPB
12 Ignored OPB
8 Ignored area of effective pixel
6 Effective margin for color processing
12 Ignored OPB
1748
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
2316
AL
2336
6 Effective margin for color processing
2 Ignored area of effective pixel
EN
2384
TI
V blank
D
Readout Pixel Image Diagram (2304 × 1728)
1[XVS] = 1820[XHS]
Margin for
Color processing
6H[6XHS]
Effective pixels
1728H[1728XHS]
10
11
12
13
0
1
2
3
4
5
6
7
C
DO
1738
1739
1740
1741
O
XVS
XHS
Ignored area
of effective
pixel
2H[2XHS]
Margin for
Color processing
VBLK period
6H[6XHS]
58XHS
1744
1745
1746
1747
Front dummy 14XHS
[Communication
period +
User clamp
sensor clamp]
4H[4XHS]
N
FI
Ignored area
of effective
pixel
2H[2XHS]
1[H] = 1[XHS] = 1320[INCK@72MHz] = 5280[DCK]
Number of DCK clock
[@288MHz]
HBLK period
388 to 393
HOPB
Sync code ignored
20
15
HOPB
ignored
HOPB
30
15
Ignored
area of Margin for
effective Color
pixel processing
10
10
Effective pixels
2880
Ignored
Margin for area of
effective
Color
pixel Sync code
processing
5
15
20
XHS
2352
2356
2360
2364
2368
2372
2376
2380
EAV1
EAV2
EAV3
EAV4
2354
2358
2362
2366
2370
2374
2378
2382
EAV1
EAV2
EAV3
EAV4
2355
2359
2363
2367
2371
2375
2379
2383
EAV1
EAV2
EAV3
EAV4
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
2353
2357
2361
2365
2369
2373
2377
2381
EAV1
EAV2
EAV3
EAV4
28
32
36
40
44
48
52
56
60
64
68
72
30
34
38
42
46
50
54
58
62
66
70
74
DO3
31
35
39
43
47
51
55
59
63
67
71
75
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
DO0
29
33
37
41
45
49
53
57
61
65
69
73
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
55
HBLK period
IMX206CQC
MODE3: Vertical 2/3 subsampling binning horizontal 3 binning mode
(59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 11XHS (communication period + sensor clamp)
1536
1544
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
1152
1164
1168
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
14 HOPB
1172
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
1558
6 Effective margin for color processing
2 Ignored area of effective pixel
V blank
AL
1590
TI
Readout Pixel Image Diagram (1536 × 1152)
1[XVS] = 1365[XHS]
Effective pixels
1152H[1152XHS]
10
11
12
13
O
0
1
2
3
4
5
6
7
DO
1162
1163
1164
1165
N
FI
XHS
1168
1169
1170
1171
D
XVS
Ignored area
of effective
pixel
2H[2XHS]
Margin for
Color processing
VBLK period
6H[6XHS]
182XHS
EN
Ignored area
of effective
pixel
Front dummy 11XHS
2H[2XHS] Margin for
[Communication
period +
Color processing
User clamp
sensor clamp]
6H[6XHS]
4H[4XHS]
1[H] = 1[XHS] = 880[INCK@72MHz] = 3520[DCK]
HBLK period
388 to 393
C
Number of DCK clock
[@288MHz]
Ignored
HOPB area of Margin for
ignored effective Color
HOPB
pixel processing
Sync code ignored HOPB
20
10
20
10
10 5
Effective pixels
1920
Ignored
Margin for area of
effective
Color
processing pixel Sync code
5 10
20
XHS
1564
1568
1572
1576
1580
1584
1588
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
DCK(288MHz)
DO
1565
1569
1573
1577
1581
1585
1589
EAV1
EAV2
EAV3
EAV4
1566
1570
1574
1578
1582
1586
DO3
1567
1571
1575
1579
1583
1587
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
22
26
30
34
38
42
46
50
54
DO1
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
23
27
31
35
39
43
47
51
55
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
21
25
29
33
37
41
45
49
53
DO0
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
20
24
28
32
36
40
44
48
52
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
56
HBLK period
IMX206CQC
MODE4: Vertical 2/9 subsampling binning horizontal 3 binning mode
(239.76 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 11XHS (communication period + sensor clamp)
1536
1544
1558
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
384
388
392
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
396
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1590
AL
Readout Pixel Image Diagram (1536 × 384)
1[XVS] = 420[XHS]
VBLK period
13XHS
395
394
393
392
390
TI
Ignored area
Margin for of effective
Color processing pixel
2H[2XHS] 2H[2XHS]
N
FI
D
7
6
5
4
3
2
1
0
DO
9
XVS
XHS
Effective pixels
384H[384XHS]
EN
User clamp
4H[4XHS]
391
Ignored area
of effective Margin for
pixel Color processing
2H[2XHS] 2H[2XHS]
8
Front dummy 11XHS
[Communication
period +
sensor clamp]
1[H] = 1[XHS] = 715[INCK@72MHz] = 2860[DCK]
HBLK period
Effective pixels
1920
Ignored
Margin for area of
Color effective
processing pixel Sync code
5 10
20
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
20
24
28
32
36
40
44
48
52
C
DCK
(288MHz)
1566
1570
1574
1578
1582
1586
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
DO3
1567
1571
1575
1579
1583
1587
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
22
26
30
34
38
42
46
50
54
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
23
27
31
35
39
43
47
51
55
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
21
25
29
33
37
41
45
49
53
DO0
DCK(288MHz)
DO
1565
1569
1573
1577
1581
1585
1589
EAV1
EAV2
EAV3
EAV4
XHS
1564
1568
1572
1576
1580
1584
1588
EAV1
EAV2
EAV3
EAV4
O
388 to 393
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
Number of DCK clock
[@288MHz]
Ignored
HOPB area of Margin for
ignored effective Color
HOPB
pixel processing
Sync code ignored HOPB
20
10
20
10
10 5
5[DCK] * Detected both edges.
Readout Drive Timing
57
HBLK period
IMX206CQC
MODE5: Vertical 2/9 subsampling binning horizontal 3 binning mode
low power consumption drive
(29.97 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 26XHS (communication period + sensor clamp)
1536
1544
1558
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
384
388
392
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
396
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1590
AL
Readout Pixel Image Diagram (1536 × 384)
395
394
390
VBLK period
1750XHS
D
9
8
7
6
5
4
3
2
1
0
393
XVS
XHS
DO
Ignored area
Margin for of effective
Color processing pixel
2H[8XHS] 2H[8XHS]
392
Effective pixels
384H[1536XHS]
EN
User clamp
4H[16XHS]
391
Ignored area
of effective Margin for
pixel Color processing
2H[8XHS] 2H[8XHS]
TI
8[XVS] = 3360[XHS]
Front dummy 26XHS
[Communication
period +
sensor clamp]
DCK(288MHz)
DO
Effective pixels
20
7680
5[DCK] * Detected both edges.
Readout Drive Timing
58
Ignored
area of
effective
pixel
20
40
Sync code
20
1588
1589
EAV1
EAV2
EAV3
EAV4
30
Margin for
Color
processing
1575
1576
1577
1578
1579
1580
1581
1582
1583
50
Margin for
Color
processing
36
37
38
39
40
41
42
43
44
C
DO1
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
LVDS output
1ch 10bit serial
SAV1
SAV2
SAV3
SAV4
0
1
DCK
(288MHz)
HOPB
70
Ignored
area of
effective
pixel
30
31
32
33
XHS
HOPB
ignored
O
20
HOPB
ignored
40
20
21
22
23
388 to 393
Sync code
6
7
8
9
Number of DCK clock
[@288MHz]
HBLK period
N
FI
1[H] = 4[XHS] = 2860[INCK@72MHz] = 11440[DCK]
HBLK period
IMX206CQC
MODE6: Vertical 2/19 subsampling binning horizontal 3 binning mode
(419.58 frame/s, 10-bit A/D conversion, 10-bit length output)
4 ダミー
8 センサクランプ
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
1536
1544
1558
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
180
184
188
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
192
Front dummy 11XHS (communication period + sensor clamp)
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1590
Readout Pixel Image Diagram (1536 × 180)
AL
1[XVS] = 220[XHS]
Front dummy 11XHS
[Communication
period +
sensor clamp]
Ignored area
of effective Margin for
pixel Color processing
2H[2XHS] 2H[2XHS]
User clamp
4H[4XHS]
Effective pixels
180H[180XHS]
VBLK period
17XHS
191
190
189
188
9
186
EN
8
D
7
6
5
4
3
2
0
DO
1
XHS
187
TI
XVS
Ignored area
Margin for of effective
Color processing pixel
2H[2XHS] 2H[2XHS]
1[H] = 1[XHS] = 780[INCK@72MHz] = 3120[DCK]
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
20
24
28
32
36
40
44
48
52
DCK
(288MHz)
1566
1570
1574
1578
1582
1586
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
DO3
1567
1571
1575
1579
1583
1587
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
22
26
30
34
38
42
46
50
54
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
23
27
31
35
39
43
47
51
55
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
21
25
29
33
37
41
45
49
53
C
DO0
DCK(288MHz)
DO
1564
1568
1572
1576
1580
1584
1588
EAV1
EAV2
EAV3
EAV4
1920
Ignored
Margin for area of
Color effective
processing pixel Sync code
5 10
20
1565
1569
1573
1577
1581
1585
1589
EAV1
EAV2
EAV3
EAV4
Effective pixels
O
XHS
N
FI
HBLK period
388 to 393
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
Number of DCK clock
[@288MHz]
Ignored
HOPB area of Margin for
ignored effective Color
HOPB
pixel processing
Sync code ignored HOPB
20
10
20
10
10 5
5[DCK] * Detected both edges.
Readout Drive Timing
59
HBLK period
IMX206CQC
MODE7: Vertical 2 binning horizontal 2/4 subsampling mode 16:9 cropping
(vertical weighted binning)
(59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 14XHS (communication period + sensor clamp)
2304
2316
H blank
6 Effective margin for color processing
12 Ignored area of effective pixel
1296
1308
1312
24 HOPB
12 Ignored OPB
8 Ignored area of effective pixel
6 Effective margin for color processing
12 Ignored OPB
1316
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
2336
AL
6 Effective margin for color processing
2 Ignored area of effective pixel
V blank
TI
2384
EN
Readout Pixel Image Diagram (2304 × 1296)
1[XVS] = 1365[XHS]
C
O
0
1
2
3
4
5
6
7
DO
10
11
12
13
XVS
XHS
1306
1307
1308
1309
N
FI
Effective pixels
1296H[1296XHS]
Ignored area
of effective
pixel
2H[2XHS]
Margin for
Color processing
VBLK period
6H[6XHS]
35XHS
1312
1313
1314
1315
D
Ignored area
of effective
pixel
Front dummy 14XHS
2H[2XHS] Margin for
[Communication
period +
Color processing
User clamp
sensor clamp]
6H[6XHS]
4H[4XHS]
1[H] = 1[XHS] = 880[INCK@72MHz] = 3520[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
HOPB
Sync code ignored
20
15
HOPB
ignored
HOPB
30
15
Ignored
area of Margin for
effective Color
pixel processing
10
10
Effective pixels
2880
Ignored
Margin for area of
effective
Color
pixel Sync code
processing
5
15
20
XHS
2352
2356
2360
2364
2368
2372
2376
2380
EAV1
EAV2
EAV3
EAV4
2354
2358
2362
2366
2370
2374
2378
2382
EAV1
EAV2
EAV3
EAV4
2355
2359
2363
2367
2371
2375
2379
2383
EAV1
EAV2
EAV3
EAV4
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
2353
2357
2361
2365
2369
2373
2377
2381
EAV1
EAV2
EAV3
EAV4
28
32
36
40
44
48
52
56
60
64
68
72
30
34
38
42
46
50
54
58
62
66
70
74
DO3
31
35
39
43
47
51
55
59
63
67
71
75
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
DO0
29
33
37
41
45
49
53
57
61
65
69
73
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
60
HBLK period
IMX206CQC
MODE8: Vertical 2/3 subsampling binning horizontal 3 binning mode cropping
(119.88 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 11XHS (communication period + sensor clamp)
1536
1544
1558
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
576
588
592
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
596
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
6 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1590
1[XVS] = 825[XHS]
Effective pixels
576H[576XHS]
N
FI
D
10
11
12
13
0
1
2
3
4
5
6
7
586
587
588
589
XVS
592
593
594
595
Color processing
6H[6XHS]
XHS
DO
Ignored area
of effective
pixel
2H[2XHS]
Margin for
Color processing
VBLK period
6H[6XHS]
218XHS
EN
Front dummy 11XHS
[Communication
period +
User clamp
sensor clamp]
4H[4XHS]
TI
Ignored area
of effective
pixel
2H[2XHS] Margin for
AL
Readout Pixel Image Diagram (1536 × 576)
1[H] = 1[XHS] = 728[INCK@72MHz] = 2912[DCK]
1920
Ignored
Margin for area of
Color effective
processing pixel Sync code
5 10
20
1566
1570
1574
1578
1582
1586
EAV1
EAV2
EAV3
EAV4
EAV1
EAV2
EAV3
EAV4
DO3
1567
1571
1575
1579
1583
1587
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
22
26
30
34
38
42
46
50
54
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
23
27
31
35
39
43
47
51
55
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
21
25
29
33
37
41
45
49
53
DO0
DCK(288MHz)
DO
1565
1569
1573
1577
1581
1585
1589
EAV1
EAV2
EAV3
EAV4
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
20
24
28
32
36
40
44
48
52
DCK
(288MHz)
1564
1568
1572
1576
1580
1584
1588
EAV1
EAV2
EAV3
EAV4
C
XHS
Effective pixels
O
HBLK period
388 to 393
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
Number of DCK clock
[@288MHz]
Ignored
HOPB area of Margin for
ignored effective Color
HOPB
pixel processing
Sync code ignored HOPB
20
10
20
10
10 5
5[DCK] * Detected both edges.
Readout Drive Timing
61
HBLK period
IMX206CQC
4-2. When Using Type 1/2.5 Approx. 12.99 M Pixels (Approx. 16:9)
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode
Horizontal Operation Period in Each Readout Drive Mode
Readout
mode No.
Data rate
[MHz]
Horizontal operation period (Number of pixels conversion)
XHS
Horizontal
minimum
Recommended
Front
Rear
front blanking Front
Rear
period
effective
recording
effective
*2 *3
[DCK]
OPB pixel margin
pixel margin OPB [INCK] *2 *4
pixels
0
576
(288DDR*1)
380 to 385
96
28
4608
36
0
1804
1
576
*1
(288DDR )
380 to 385
96
28
4608
36
0
1504
2
576
*1
(288DDR )
388 to 393
48
14
2304
18
0
760
5
576
(288DDR*1)
388 to 393
32
10
1536
12
0
714
*3
*4
DDR: Double Data Rate
If XHS period is shorter than the (XHS minimum period + horizontal front blanking), the data from the previous
line may be output during the horizontal front blanking period.
Number of LVDS output signal DCK clock
Number of clocks in conversion of INCK = 72 MHz.
AL
*1
*2
TI
Vertical Operation Period in Each Readout Drive Mode
EN
Number of lines per vertical operation period (output data 1H conversion)
1
16
2
14
5
26
16
Rear
OPB
22
2736
22
0
2816
16
22
2736
22
0
2816
4
8
1368
8
0
1406
4
304
4
0
325
N
FI
16
Recommended
Rear effective
recording
pixel margin
pixels
4
C
0
Front Front effective
OPB pixel margin
D
Vertical front
blanking
XVS
minimum
period
[XHS]
O
Readout
mode No.
(2) NTSC/PAL Compatible Drive
This sensor can be used with a frame frequency that supports NTSC or PAL by using the recommended horizontal
operating period (XHS period) and recommended vertical operating period (V period) for each readout drive mode
shown in the table below. Note that the number of XHS pulses input within the horizontal operating period (H
period) varies according to the drive mode.
Recommended H Period and V Periods (NTSC/PAL Compatible)
NTSC compatible drive
H period
Readout
(number of
mode No. XHS period
*1
(INCK)
XHS
pulses) *2
*1
*2
PAL compatible drive
V period
(number
of XHS
pulses)
Frame
frequency
[frame/s]
H period
V period
XHS period (number of (number of
*1
(INCK)
XHS
XHS
pulses) *2
pulses)
Frame
frequency
[frame/s]
0
1820
1
3300
11.99
2000
1
3600
10.00
1
1540
1
2925
15.98
1600
1
3600
12.50
2
840
1
1430
59.94
900
1
1600
50.00
5
924
4
2600
29.97
1000
4
2880
25.00
Number of clocks in conversion of INCK = 72 MHz
Number of XHS pulses required to output the data for one sensor line
62
IMX206CQC
Imaging Conditions in Each Readout Drive Mode (NTSC/PAL Compatible Drive)
Imaging conditions
Number of
A/D
conversion
bits
[bit]
Output
data bit
length [bit]
Number
of
horizontal
recording
pixels
Number
of
vertical
recording
pixels
Number of
recording
pixels
0
576
(288DDR)
4
12
12
4608
2736
Approximately
12.61 M pixels
1
576
(288DDR)
4
10
10
4608
2736
Approximately
12.61 M pixels
2
576
(288DDR)
4
10
10
2304
1368
Approximately
3.15 M pixels
5
576
(288DDR)
1
10
10
1536
304
Approximately
0.47 M pixels
C
O
N
FI
D
EN
TI
AL
Data rate
[MHz]
Number
of
LVDS
output
channels
[ch]
Readout
mode No.
63
IMX206CQC
(3) Image Data Output Format
The output format in each readout drive mode is as follows.
MODE0: All-pixel scan mode (11.99 frame/s, 12-bit A/D conversion, 12-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
4608
AL
4632
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
2736
2772
2780
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color processing
2796
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
TI
4672
18 Effective margin for color processing
4 Ignored area of effective pixel
EN
V blank
4768
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
1[XVS] = 3300[XHS]
Effective pixels
2736H[2736XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
VBLK period
488XHS
36
37
38
39
C
14
15
16
17
18
19
20
21
0
1
DO
2790
2791
2792
2793
2794
2795
XVS
XHS
2772
2773
2774
2775
O
Front dummy 16XHS
[Communication
period +
sensor clamp]
N
FI
D
Readout Pixel Image Diagram (4608 × 2736)
1[H] = 1[XHS] = 1820[INCK@72MHz] = 7280[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
HOPB
Sync code ignored
24
36
HOPB
ignored
Ignored
area of
effective
pixel
36
24
HOPB
72
Margin for
Color
processing
Effective pixels
18
6912
Margin for
Color
processing
Ignored
area of
effective
pixel
18
36
Sync code
24
XHS
4760
4764
EAV1
EAV2
EAV3
EAV4
4762
4766
EAV1
EAV2
EAV3
EAV4
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4720
4724
4728
4732
4736
4740
4744
4748
4722
4726
4730
4734
4738
4742
4746
4750
4723
4727
4731
4735
4739
4743
4747
4751
data from previous line
SAV1[11]
SAV1[10]
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
SAV1
SAV2
SAV3
SAV4
1
5
18
22
26
30
EAV1
EAV2
EAV3
EAV4
19
23
27
31
EAV1
EAV2
EAV3
EAV4
DO3
SAV1
SAV2
SAV3
SAV4
2
6
DO2
SAV1
SAV2
SAV3
SAV4
3
7
DO1
LVDS output
4ch 12bit serial
EAV1
EAV2
EAV3
EAV4
DO0
EAV1
EAV2
EAV3
EAV4
DCK
(288MHz)
6[DCK] * Detected both edges.
Readout Drive Timing
64
IMX206CQC
MODE1: All-pixel scan mode (15.98 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
4608
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
2736
2772
2780
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color processing
2796
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
4632
4672
AL
18 Effective margin for color processing
4 Ignored area of effective pixel
4768
TI
V blank
EN
Readout Pixel Image Diagram (4608 × 2736)
1[XVS] = 2925[XHS]
VBLK period
113XHS
2790
2791
2792
2793
2794
2795
2772
2773
2774
2775
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
C
O
14
15
16
17
18
19
20
21
0
1
Effective pixels
2736H[2736XHS]
36
37
38
39
XVS
XHS
DO
D
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
N
FI
Front dummy 16XHS
[Communication
period +
sensor clamp]
1[H] = 1[XHS] = 1540[INCK@72MHz] = 6160[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
HOPB
Sync code ignored
20
30
HOPB
60
HOPB
ignored
Ignored
area of
effective
pixel
30
20
Margin for
Color
processing
Effective pixels
15
5760
Ignored
Margin for area of
Color
effective
processing
pixel
15
30
Sync code
20
XHS
4760
4764
EAV1
EAV2
EAV3
EAV4
4762
4766
EAV1
EAV2
EAV3
EAV4
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4720
4724
4728
4732
4736
4740
4744
4748
4722
4726
4730
4734
4738
4742
4746
4750
4723
4727
4731
4735
4739
4743
4747
4751
data from previous line
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
SAV1
SAV2
SAV3
SAV4
1
5
18
22
26
30
EAV1
EAV2
EAV3
EAV4
19
23
27
31
EAV1
EAV2
EAV3
EAV4
DO3
SAV1
SAV2
SAV3
SAV4
2
6
DO2
SAV1
SAV2
SAV3
SAV4
3
7
DO1
LVDS output
4ch 10bit serial
EAV1
EAV2
EAV3
EAV4
DO0
EAV1
EAV2
EAV3
EAV4
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
65
IMX206CQC
MODE2: Horizontal/vertical 2/2-line binning mode (horizontal and vertical weighted binning)
(59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 14XHS (communication period + sensor clamp)
2304
2316
H blank
6 Effective margin for color processing
12 Ignored area of effective pixel
1368
1380
1384
24 HOPB
12 Ignored OPB
8 Ignored area of effective pixel
6 Effective margin for color processing
12 Ignored OPB
1388
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
2336
6 Effective margin for color processing
2 Ignored area of effective pixel
AL
V blank
2384
EN
TI
Readout Pixel Image Diagram (2304 × 1368)
1[XVS] = 1430[XHS]
Effective pixels
1368H[1368XHS]
1378
1379
1380
1381
Margin for
Color processing
6H[6XHS]
VBLK period
28XHS
O
0
1
2
3
4
5
6
7
DO
10
11
12
13
XHS
Ignored area
of effective
pixel
2H[2XHS]
1384
1385
1386
1387
Margin for
Color processing
6H[6XHS]
N
FI
XVS
User clamp
4H[4XHS]
D
Front dummy 14XHS
[Communication
period +
sensor clamp]
Ignored area
of effective
pixel
2H[2XHS]
Number of DCK clock
[@288MHz]
HBLK period
388 to 393
C
1[H] = 1[XHS] = 840[INCK@72MHz] = 3360[DCK]
HOPB
Sync code ignored
20
15
HOPB
ignored
HOPB
30
15
Ignored
area of Margin for
effective Color
pixel processing
10
10
Effective pixels
2880
Ignored
Margin for area of
effective
Color
pixel Sync code
processing
5
15
20
XHS
2352
2356
2360
2364
2368
2372
2376
2380
EAV1
EAV2
EAV3
EAV4
2354
2358
2362
2366
2370
2374
2378
2382
EAV1
EAV2
EAV3
EAV4
2355
2359
2363
2367
2371
2375
2379
2383
EAV1
EAV2
EAV3
EAV4
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
2353
2357
2361
2365
2369
2373
2377
2381
EAV1
EAV2
EAV3
EAV4
28
32
36
40
44
48
52
56
60
64
68
72
30
34
38
42
46
50
54
58
62
66
70
74
DO3
31
35
39
43
47
51
55
59
63
67
71
75
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
DO0
29
33
37
41
45
49
53
57
61
65
69
73
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
66
HBLK period
IMX206CQC
MODE5: Vertical 2/9 subsampling binning horizontal 3 binning mode
low power consumption drive
(29.97 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 26XHS (communication period + sensor clamp)
1536
1544
1558
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
304
308
312
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
316
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1590
AL
Readout Pixel Image Diagram (1536 × 304)
315
314
310
VBLK period
1310XHS
D
9
8
7
6
5
4
3
2
1
0
313
XVS
XHS
DO
Ignored area
Margin for of effective
Color processing pixel
2H[8XHS] 2H[8XHS]
312
Effective pixels
304H[1216XHS]
EN
User clamp
4H[16XHS]
311
Ignored area
of effective Margin for
pixel Color processing
2H[8XHS] 2H[8XHS]
TI
8[XVS] = 2600[XHS]
Front dummy 26XHS
[Communication
period +
sensor clamp]
DCK(288MHz)
DO
Margin for
Color
processing
Ignored
area of
effective
pixel
20
7680
20
40
5[DCK] * Detected both edges.
Readout Drive Timing
67
Sync code
20
1588
1589
EAV1
EAV2
EAV3
EAV4
Effective pixels
1575
1576
1577
1578
1579
1580
1581
1582
1583
C
DO1
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
LVDS output
1ch 10bit serial
SAV1
SAV2
SAV3
SAV4
0
1
DCK
(288MHz)
30
Margin for
Color
processing
36
37
38
39
40
41
42
43
44
XHS
50
HOPB
70
30
31
32
33
40
Ignored
area of
effective
pixel
O
20
HOPB
ignored
20
21
22
23
388 to 393
HOPB
Sync code ignored
6
7
8
9
Number of DCK clock
[@288MHz]
HBLK period
N
FI
1[H] = 4[XHS] = 3696[INCK@72MHz] = 14784[DCK]
HBLK period
IMX206CQC
4-3. When Using Type 1/3 Approx. 10.32 M Pixels (4:3)
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode
Horizontal Operation Period in Each Readout Drive Mode
Readout
mode No.
Data rate
[MHz]
Horizontal operation period (Number of pixels conversion)
XHS
Horizontal
minimum
Recommended
Front
Rear
front blanking Front
Rear
period
effective
recording
effective
*2 *3
[DCK]
OPB pixel margin
pixel margin OPB [INCK] *2 *4
pixels
0
576
(288DDR*1)
380 to 385
96
28
3648
36
0
1444
1
576
*1
(288DDR )
380 to 385
96
28
3648
36
0
1204
2
576
*1
(288DDR )
388 to 393
48
14
1824
18
0
714
5
576
(288DDR*1)
388 to 393
32
10
1216
12
0
714
*3
*4
DDR: Double Data Rate
If XHS period is shorter than the (XHS minimum period + horizontal front blanking), the data from the previous
line may be output during the horizontal front blanking period.
Number of LVDS output signal DCK clock
Number of clocks in conversion of INCK = 72 MHz.
AL
*1
*2
TI
Vertical Operation Period in Each Readout Drive Mode
EN
Number of lines per vertical operation period (output data 1H conversion)
1
16
2
14
5
26
16
Rear
OPB
22
2736
22
0
2816
16
22
2736
22
0
2816
4
8
1368
8
0
1406
4
304
4
0
325
N
FI
16
Recommended
Rear effective
recording
pixel margin
pixels
4
C
0
Front Front effective
OPB pixel margin
D
Vertical front
blanking
XVS
minimum
period
[XHS]
O
Readout
mode No.
(2) NTSC/PAL Compatible Drive
This sensor can be used with a frame frequency that supports NTSC or PAL by using the recommended horizontal
operating period (XHS period) and recommended vertical operating period (V period) for each readout drive mode
shown in the table below. Note that the number of XHS pulses input within the horizontal operating period (H
period) varies according to the drive mode.
Recommended H Period and V Periods (NTSC/PAL Compatible)
NTSC compatible drive
H period
Readout
(number of
mode No. XHS period
*1
(INCK)
XHS
pulses) *2
*1
*2
PAL compatible drive
V period
(number
of XHS
pulses)
Frame
frequency
[frame/s]
H period
V period
XHS period (number of (number of
*1
(INCK)
XHS
XHS
pulses) *2
pulses)
Frame
frequency
[frame/s]
0
1456
1
3300
14.99
1600
1
3600
12.50
1
1260
1
2860
19.98
1600
1
3600
12.50
2
840
1
1430
59.94
900
1
1600
50.00
5
924
4
2600
29.97
1000
4
2880
25.00
Number of clocks in conversion of INCK = 72 MHz
Number of XHS pulses required to output the data for one sensor line
68
IMX206CQC
Imaging Conditions in Each Readout Drive Mode (NTSC/PAL Compatible Drive)
Imaging conditions
Number of
A/D
conversion
bits
[bit]
Output
data bit
length [bit]
Number
of
horizontal
recording
pixels
Number
of
vertical
recording
pixels
Number of
recording
pixels
0
576
(288DDR)
4
12
12
3648
2736
Approximately
9.98 M pixels
1
576
(288DDR)
4
10
10
3648
2736
Approximately
9.98 M pixels
2
576
(288DDR)
4
10
10
1824
1368
Approximately
2.50 M pixels
5
576
(288DDR)
1
10
10
1216
304
Approximately
0.37 M pixels
C
O
N
FI
D
EN
TI
AL
Data rate
[MHz]
Number
of
LVDS
output
channels
[ch]
Readout
mode No.
69
IMX206CQC
(3) Image Data Output Format
The output format in each readout drive mode is as follows.
MODE0: All-pixel scan mode (14.99 frame/s, 12-bit A/D conversion, 12-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
3648
AL
3672
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
2736
2772
2780
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color processing
2796
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
TI
3712
18 Effective margin for color processing
4 Ignored area of effective pixel
EN
V blank
3808
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
1[XVS] = 3300[XHS]
Effective pixels
2736H[2736XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
VBLK period
488XHS
36
37
38
39
C
14
15
16
17
18
19
20
21
0
1
DO
2790
2791
2792
2793
2794
2795
XVS
XHS
2772
2773
2774
2775
O
Front dummy 16XHS
[Communication
period +
sensor clamp]
N
FI
D
Readout Pixel Image Diagram (3648 × 2736)
1[H] = 1[XHS] = 1456[INCK@72MHz] = 5824[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
Sync code
24
HOPB
ignored
36
HOPB
72
HOPB
ignored
Ignored
area of
effective
pixel
36
24
Margin for
Color
processing
Effective pixels
18
5472
Ignored
Margin for area of
effective
Color
processing pixel
18
36
Sync code
24
XHS
3800
3804
EAV1
EAV2
EAV3
EAV4
3802
3806
EAV1
EAV2
EAV3
EAV4
3803
3807
EAV1
EAV2
EAV3
EAV4
3801
3805
EAV1
EAV2
EAV3
EAV4
3760
3764
3768
3772
3776
3780
3784
3788
3762
3766
3770
3774
3778
3782
3786
3790
3763
3767
3771
3775
3779
3783
3787
3791
data from previous line
SAV1[11]
SAV1[10]
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
3761
3765
3769
3773
3777
3781
3785
3789
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
SAV1
SAV2
SAV3
SAV4
1
5
18
22
26
30
EAV1
EAV2
EAV3
EAV4
19
23
27
31
EAV1
EAV2
EAV3
EAV4
DO3
SAV1
SAV2
SAV3
SAV4
2
6
DO2
SAV1
SAV2
SAV3
SAV4
3
7
DO1
LVDS output
4ch 12bit serial
EAV1
EAV2
EAV3
EAV4
DO0
EAV1
EAV2
EAV3
EAV4
DCK
(288MHz)
6[DCK] * Detected both edges.
Readout Drive Timing
70
IMX206CQC
MODE1: All-pixel scan mode (19.98 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
3648
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
2736
2772
2780
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color processing
2796
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
3672
3712
AL
18 Effective margin for color processing
4 Ignored area of effective pixel
V blank
TI
3808
EN
Readout Pixel Image Diagram (3648 × 2736)
1[XVS] = 2860[XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
2772
2773
2774
2775
14
15
16
17
18
19
20
21
VBLK period
48XHS
C
O
0
1
36
37
38
39
XVS
XHS
DO
Effective pixels
2736H[2736XHS]
2790
2791
2792
2793
2794
2795
D
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
N
FI
Front dummy 16XHS
[Communication
period +
sensor clamp]
1[H] = 1[XHS] = 1260[INCK@72MHz] = 5040[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
Sync code
20
HOPB
ignored
30
HOPB
60
HOtPB
ignored
Ignored
area of
effective
pixel
30
20
Margin for
Color
processing
Effective pixels
15
4560
Ignored
Margin for area of
effective
Color
processing
pixel
15
30
Sync code
20
XHS
3800
3804
EAV1
EAV2
EAV3
EAV4
3802
3806
EAV1
EAV2
EAV3
EAV4
3803
3807
EAV1
EAV2
EAV3
EAV4
3801
3805
EAV1
EAV2
EAV3
EAV4
3760
3764
3768
3772
3776
3780
3784
3788
3762
3766
3770
3774
3778
3782
3786
3790
3763
3767
3771
3775
3779
3783
3787
3791
data from previous line
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
3761
3765
3769
3773
3777
3781
3785
3789
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
SAV1
SAV2
SAV3
SAV4
1
5
18
22
26
30
EAV1
EAV2
EAV3
EAV4
19
23
27
31
EAV1
EAV2
EAV3
EAV4
DO3
SAV1
SAV2
SAV3
SAV4
2
6
DO2
SAV1
SAV2
SAV3
SAV4
3
7
DO1
LVDS output
4ch 10bit serial
EAV1
EAV2
EAV3
EAV4
DO0
EAV1
EAV2
EAV3
EAV4
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
71
IMX206CQC
MODE2: Horizontal/vertical 2/2-line binning mode (horizontal and vertical weighted binning)
(59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
7 ダミー
8 センサクランプ
4 User clamp
2 Ignored area of effective pixel
6 Effective margin for color processing
1824
H blank
6 Effective margin for color processing
12 Ignored area of effective pixel
1368
1380
1384
24 HOPB
12 Ignored OPB
8 Ignored area of effective pixel
6 Effective margin for color processing
12 Ignored OPB
1388
Front dummy 14XHS (communication period + sensor clamp)
1836
AL
1856
6 Effective margin for color processing
2 Ignored area of effective pixel
EN
1904
TI
V blank
D
Readout Pixel Image Diagram (1824 × 1368)
1[XVS] = 1430[XHS]
1378
1379
1380
1381
0
1
2
3
4
5
6
7
C
DO
10
11
12
13
XHS
Margin for
Color processing
6H[6XHS]
Effective pixels
1368H[1368XHS]
VBLK period
28XHS
1384
1385
1386
1387
Margin for
Color processing
6H[6XHS]
O
XVS
User clamp
4H[4XHS]
Ignored area
of effective
pixel
2H[2XHS]
N
FI
Front dummy 14XHS
[Communication
period +
sensor clamp]
Ignored area
of effective
pixel
2H[2XHS]
1[H] = 1[XHS] = 840[INCK@72MHz] = 3360[DCK]
Number of DCK clock
[@288MHz]
HBLK period
388 to 393
HOPB
Sync code ignored
20
15
HOPB
30
HOPB
ignored
15
Ignored
area of Margin for
effective
Color
pixel processing
10
10
Effective pixels
2280
Ignored
Margin for area of
effective
Color
pixel Sync code
processing
5
15
20
XHS
1872
1876
1880
1884
1888
1892
1896
1900
EAV1
EAV2
EAV3
EAV4
1874
1878
1882
1886
1890
1894
1898
1902
EAV1
EAV2
EAV3
EAV4
1875
1879
1883
1887
1891
1895
1899
1903
EAV1
EAV2
EAV3
EAV4
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
1873
1877
1881
1885
1889
1893
1897
1901
EAV1
EAV2
EAV3
EAV4
28
32
36
40
44
48
52
56
60
64
68
72
30
34
38
42
46
50
54
58
62
66
70
74
DO3
31
35
39
43
47
51
55
59
63
67
71
75
DO2
SAV1
SAV2
SAV3
SAV4
2
6
10
14
18
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
11
15
19
SAV1
SAV2
SAV3
SAV4
1
5
9
13
17
DO0
29
33
37
41
45
49
53
57
61
65
69
73
SAV1
SAV2
SAV3
SAV4
0
4
8
12
16
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
72
HBLK period
IMX206CQC
MODE5: Vertical 2/9 subsampling binning horizontal 3 binning mode
low power consumption drive
(29.97 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 26XHS (communication period + sensor clamp)
1216
1224
1238
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
304
308
312
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
316
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
1270
AL
Readout Pixel Image Diagram (1216 × 304)
315
314
310
VBLK period
1310XHS
N
FI
D
9
8
7
6
5
4
3
2
1
0
313
XVS
XHS
DO
Ignored area
Margin for of effective
Color processing pixel
2H[8XHS] 2H[8XHS]
312
Effective pixels
304H[1216XHS]
EN
User clamp
4H[16XHS]
311
Ignored area
of effective Margin for
pixel Color processing
2H[8XHS] 2H[8XHS]
TI
8[XVS] = 2600[XHS]
Front dummy 26XHS
[Communication
period +
sensor clamp]
1[H] = 4[XHS] = 3696[INCK@72MHz] = 14784[DCK]
DCK(288MHz)
DO
30
Effective pixels
20
6080
36
37
38
39
40
41
42
43
44
C
DO1
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
LVDS output
1ch 10bit serial
SAV1
SAV2
SAV3
SAV4
0
1
DCK
(288MHz)
50
30
31
32
33
XHS
HOPB
70
Margin for
Color
processing
5[DCK] * Detected both edges.
Readout Drive Timing
73
Margin for
Color
processing
Ignored
area of
effective
pixel
20
40
Sync code
20
1268
1269
EAV1
EAV2
EAV3
EAV4
40
Ignored
area of
effective
pixel
1255
1256
1257
1258
1259
1260
1261
1262
1263
20
HOPB
ignored
O
HOPB
ignored
20
21
22
23
388 to 393
Sync code
6
7
8
9
Number of DCK clock
[@288MHz]
HBLK period
HBLK period
IMX206CQC
4-4. When Using Type 1/5 Approx. 3.51 M Pixels (4:3)
(1) Horizontal/Vertical Operation Period in Each Readout Drive Mode
Horizontal Operation Period in Each Readout Drive Mode
Readout
mode No.
Data rate
[MHz]
Horizontal operation period (Number of pixels conversion)
XHS
Horizontal
minimum
Recommended
Front
Rear
front blanking Front
Rear
period
effective
recording
effective
[DCK] *2 *3
OPB pixel margin
pixel margin OPB [INCK] *2 *4
pixels
1
576
(288DDR*1)
380 to 385
96
28
2112
36
0
724
576
388 to 393
32
10
704
12
0
714
*1
(288DDR )
DDR: Double Data Rate
If XHS period is shorter than the (XHS minimum period + horizontal front blanking), the data from the previous
line may be output during the horizontal front blanking period.
Number of LVDS output signal DCK clock
Number of clocks in conversion of INCK = 72 MHz.
5
*1
*2
*3
*4
Vertical Operation Period in Each Readout Drive Mode
Number of lines per vertical operation period (output data 1H conversion)
AL
Recommended
Front Front effective
Rear effective
recording
pixel margin
OPB pixel margin
pixels
Vertical front
blanking
16
16
14
5
26
4
4
14
0
1648
176
4
0
197
D
(2) NTSC/PAL Compatible Drive
Rear
OPB
XVS
minimum
period
[XHS]
1584
EN
1
TI
Readout
mode No.
O
N
FI
This sensor can be used with a frame frequency that supports NTSC or PAL by using the recommended horizontal
operating period (XHS period) and recommended vertical operating period (V period) for each readout drive mode
shown in the table below. Note that the number of XHS pulses input within the horizontal operating period (H
period) varies according to the drive mode.
C
Recommended H Period and V Periods (NTSC/PAL Compatible)
NTSC compatible drive
H period
Readout
XHS period (number of
mode No.
*1
(INCK)
XHS
pulses) *2
1
*1
*2
728
1
PAL compatible drive
V period
(number
of XHS
pulses)
Frame
frequency
[frame/s]
1650
59.94
H period
V period
XHS period (number of (number of
*1
(INCK)
XHS
XHS
pulses) *2
pulses)
800
5
1430
4
1680
29.97
1000
Number of clocks in conversion of INCK = 72 MHz
Number of XHS pulses required to output the data for one sensor line
Frame
frequency
[frame/s]
1
1800
50.00
4
2880
25.00
Imaging Conditions in Each Readout Drive Mode (NTSC/PAL Compatible Drive)
Imaging conditions
Readout
Number of
mode Data rate LVDS output
No.
channels
[MHz]
[ch]
Number of
A/D
conversion
bits
[bit]
Output data
bit
length [bit]
Number of
horizontal
recording
pixels
Number of
vertical
recording
pixels
Number of
recording
pixels
1
576
(288DDR)
4
10
10
2112
1584
Approximately
3.35 M pixels
5
576
(288DDR)
1
10
10
704
176
Approximately
0.12 M pixels
74
IMX206CQC
(3) Image Data Output Format
The output format in each readout drive mode is as follows.
MODE1: All-pixel scan mode (59.94 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy (communication period + sensor clamp) 16XHS
2112
AL
2136
H blank
12 Effective margin for color processing
24 Ignored area of effective pixel
1584
1604
1612
48 HOPB
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color processing
1628
24 Ignored OPB
16 User clamp
4 Ignored area of effective pixel
10 Effective margin for color processing
TI
2176
10 Effective margin for color processing
4 Ignored area of effective pixel
EN
V blank
2272
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
10H[10XHS]
1[XVS] = 1650[XHS]
Effective pixels
1584H[1584XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
10H[10XHS]
VBLK period
6XHS
28
29
30
31
C
14
15
16
17
18
19
20
21
0
1
DO
1622
1623
1624
1625
1626
1627
XVS
XHS
1612
1613
1614
1615
O
Front dummy 16XHS
[Communication
period +
sensor clamp]
N
FI
D
Readout Pixel Image Diagram (2112 × 1584)
1[H] = 1[XHS] = 728[INCK@72MHz] = 2912[DCK]
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
Sync code
HOPB
ignored
20
30
HOPB
ignored
Ignored
area of
effective
pixel
30
20
HOPB
60
Margin for
Color
processing
15
Effective pixels
2640
Margin for
Color
processing
Ignored
area of
effective
pixel
15
30
Sync code
20
XHS
2264
2268
EAV1
EAV2
EAV3
EAV4
2266
2270
EAV1
EAV2
EAV3
EAV4
2267
2271
EAV1
EAV2
EAV3
EAV4
2265
2269
EAV1
EAV2
EAV3
EAV4
2224
2228
2232
2236
2240
2244
2248
2252
2226
2230
2234
2238
2242
2246
2250
2254
2227
2231
2235
2239
2243
2247
2251
2255
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
data from previous line
DCK(288MHz)
DO
2225
2229
2233
2237
2241
2245
2249
2253
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
SAV1
SAV2
SAV3
SAV4
1
5
18
22
26
30
EAV1
EAV2
EAV3
EAV4
19
23
27
31
EAV1
EAV2
EAV3
EAV4
DO3
SAV1
SAV2
SAV3
SAV4
2
6
DO2
SAV1
SAV2
SAV3
SAV4
3
7
DO1
LVDS output
4ch 10bit serial
EAV1
EAV2
EAV3
EAV4
DO0
EAV1
EAV2
EAV3
EAV4
DCK
(288MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
75
IMX206CQC
MODE5: Vertical 2/9 subsampling binning horizontal 3 binning mode
low power consumption drive
(29.97 frame/s, 10-bit A/D conversion, 10-bit length output)
Front dummy 26XHS (communication period + sensor clamp)
704
712
726
H blank
4 Effective margin for color processing
8 Ignored area of effective pixel
176
180
184
14 HOPB
10 Ignored OPB
6 Ignored area of effective pixel
4 Effective margin for color processing
8 Ignored OPB
188
4 User clamp
2 Ignored area of effective pixel
2 Effective margin for color processing
2 Effective margin for color processing
2 Ignored area of effective pixel
V blank
758
AL
Readout Pixel Image Diagram (704 × 176)
8[XVS] = 1680[XHS]
VBLK period
902XHS
187
186
182
EN
D
9
8
7
6
5
4
3
2
1
0
DO
185
XVS
XHS
Ignored area
Margin for of effective
Color processing pixel
2H[8XHS] 2H[8XHS]
TI
Effective pixels
176H[704XHS]
184
Ignored area
of effective Margin for
pixel Color processing
2H[8XHS] 2H[8XHS]
User clamp
4H[16XHS]
183
Front dummy 26XHS
[Communication
period +
sensor clamp]
1[H] = 4[XHS] = 5720[INCK@72MHz] = 22880[DCK]
XHS
DO
O
C
DCK(288MHz)
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DO1
6
7
8
9
SAV1
SAV2
SAV3
SAV4
0
1
DCK
(288MHz)
LVDS output
1ch 10bit serial
50
30
20
5[DCK] * Detected both edges.
Readout Drive Timing
76
Effective pixels
3520
Ignored
area of
effective
pixel
20
40
Sync code
20
756
757
EAV1
EAV2
EAV3
EAV4
HOPB
70
Margin for
Color
processing
743
744
745
746
747
748
749
750
751
40
Margin for
Color
processing
36
37
38
39
40
41
42
43
44
20
30
31
32
33
Sync code
Ignored
area of
effective
pixel
N
FI
HBLK period
388 to 393
HOPB
ignored
20
21
22
23
Number of DCK clock
[@288MHz]
HOPB
ignored
HBLK period
IMX206CQC
4-5. Vertical Arbitrary Cropping (All-pixel scan, 10 bits)
(1) Readout Drive Mode Outlines
Vertical cropping region can be arbitrarily changed by registers in the readout drive mode of this sensor described in
the table below.
Readout
mode No.
Readout drive mode
1
All-pixel scan mode (10 bits)
Mode description
In vertical arbitrary cropping area from type 1/2.3 approx. 16.35M
pixels (4:3) all pixels are readout with 10-bit output.
(2) Register Settings
Set registers for readout mode No. 1, all-pixel scan mode (10 bits), when using type 1/2.3 approx. 16.35M pixels (4:3).
Specify cropping width by the vertical cropping width register VWIDCUT (address 0071h, bit [7:0] and address 0072h,
bit [2:0]), and cropping position by the vertical cropping start position register VWINPOS (address 006Fh, bit [7:0]
and address 0070h, bit [3:0]).
Set VWINPOS negative value (two’s complement) when the direction of vertical readout is inverted (address 001Ah,
bit[0], MDVREV = 1h)
VWIDCUT Setting
0 to 2047
EN
VWINPOS Setting
Function
Vertical cropping start position
N
FI
D
Register
VWINPOS
AL
Function
Specify vertical cropping width
3500 - VWIDCUT × 2 [line]
TI
Register value
O
When vertical readout direction is normal (MDVREV=0h), relation between register setting values of VWINPOS /
VWIDCUT and cropping region on physical pixel array is shown below.
As cropping region must not exceed all-pixel scan area, register setting values must satisfy following relations.
(Setting ranges are within those values which satisfy following.)
(Starting position of readout must be 0 or more)
(Number of readout lines must be 1750 or more)
(End position of readout must be within all-pixel scan area)
C
VWINPOS × 2 ≧0
3500 – VWIDCUT × 2 ≧ 1750
(VWINPOS × 2) + 3500 – VWIDCUT × 2 ≦3500
4672
Effective pixel area of
vertical arbitrary cropping mode
(all-pixel scan (10-bit))
3500
(HOPB)
vertical readout direction
(MDVREV=0h)
Effective pixel area of all-pixel scan
(4672×3500)
cropping width: 3500 – VWIDCUT × 2
cropping start position: VWINPOS × 2
V
(VOPB)
H
Relation between Register Settings of VWINPOS / VWIDCUT and Cropping Region on Physical Pixel Array
(Vertical Readout Direction Normal)
77
IMX206CQC
For example, when the top 400 lines of all-pixel scan area is skipped and start cropping readout from the 401st line,
setting value to the register VWINPOS is 0C8h (200d).
When vertical readout direction is inverted (MDVREV=1h), relation between register setting value of VWINPOS /
VWIDCUT and cropping region is shown below. Register setting values must satisfy following relations also.
| VWINPOS | × 2 ≥ 0
3500 – VWIDCUT × 2 ≥ 1750
( | VWINPOS | × 2) + 3500 – VWIDCUT × 2 ≤ 3500
(Starting position of readout must be 0 or more)
(Number of readout lines must be 1750 or more)
(End position of readout must be within all-pixel scan area)
4672
cropping width: 3500 – VWIDCUT × 2
Effective pixel area of
vertical arbitrary cropping mode
(all-pixel scan (10-bit))
3500
(HOPB)
vertical readout direction
(MDVREV=1h)
cropping start position: | VWINPOS | × 2
V
AL
Effective pixel area of all-pixel scan
(4672×3500)
(VOPB)
TI
H
EN
Relation between Register Settings of VWINPOS / VWIDCUT and Cropping Region on Physical Pixel Array
(Vertical Readout Direction Inverted)
C
O
N
FI
D
For example, when the top 400 lines of all-pixel scan area (when vertical readout direction inverted) is skipped and
start cropping readout from the 401st line, setting value to the register VWINPOS is F38h (-200d).
78
IMX206CQC
(3) Detailed Specification of Each Mode
Horizontal Operation Period in Each Readout Drive Mode
Horizontal operation period
Readout
mode No.
1
*1
*2
*3
*4
Data rate
front blanking
[MHz]
576
*1
(288DDR )
Recommended
Front
Rear effective
effective
recording
pixel margin
pixel margin
pixels
Front
*2 *3
[DCK]
XHS
(Number of pixels conversion)
Horizontal
OPB
380 to 385
96
28
4608
36
minimum
Rear
OPB
period
[INCK]
0
*2 *4
1504
DDR: Double Data Rate
If XHS period is shorter than the (XHS minimum period + horizontal front blanking), the data from the previous line may be
output during the horizontal front blanking period.
Number of LVDS output signal DCK clock
Number of clocks in conversion of INCK = 72 MHz.
Vertical Operation Period in Each Readout Drive Mode
Number of lines per vertical operation period (output data 1H conversion)
blanking
1
16
Front Front effective
OPB pixel margin
16
Recommended
Rear effective Rear
pixel margin OPB
AL
Vertical
front
recording pixels
TI
mode No.
22
3456 – VWIDCUT × 2
22
0
XVS minimum
period [XHS]
3532 – VWIDCUT × 2
EN
Readout
NTSC/PAL Compatible Drive
N
FI
D
The recommended H period and V period (NTSC/PAL compatible) of vertical arbitrary cropping mode are unable
to be shown because available frame rate changes depending on cropping area. Select XHS and XVS period
which is more than XHS and XVS minimum period arbitrarily.
1
Number of Number of
LVDS
A/D
output
conversion
channels
bits
[ch]
[bit]
C
Readout
mode
No.
O
Imaging Conditions in Each Readout Drive Mode (NTSC/PAL Compatible Drive)
Data rate
[MHz]
576
(288DDR)
4
Imaging conditions
Output
data bit
length
[bit]
10
10
79
Number of
horizontal
recording
pixels
4608
Number of
vertical
recording
pixels
Number of
Recording
pixels
Approximately
7.86 M pixels to
1706 to 3456
approximately
15.93 M pixels
IMX206CQC
(4) Image Data Output Format
The output format in each readout drive mode is as follows.
MODE1: All-pixel scan mode vertical arbitrary cropping
(10-bit A/D conversion, 10-bit length output)
4608
4632
H blank
12 Effective margin for color
24 Ignored area of effective pixel
1706 to 3456
1742 to 3492
1750 to 3500
48 HOPB
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
24 Ignored OPB
16 Ignored area of effective pixel
12 Effective margin for color
24 Ignored OPB
1766 to 3516
Front dummy(communication period + sensor clamp) 16XHS
4672
18 Effective margin for color processing
4 Ignored area of effective pixel
V blank
AL
4768
TI
Readout Pixel Image Diagram (4608 × 1706 to 4608 × 3456)
User clamp
16H[16XHS]
EN
1[XVS]
Front dummy 16XHS
[Communication
period +
sensor clamp]
Ignored area
Margin for
of effective
Color processing
pixel
18H[18XHS]
4H[4XHS]
Effective pixels
1706～3456H[1706～3456XHS]
36
37
38
39
14
15
16
17
18
19
20
21
0
1
DO
N
FI
XHS
VBLK
period
1765～3515
D
XVS
Ignored area
Margin for
of effective
Color processing
pixel
18H[18XHS]
4H[4XHS]
HBLK period
380 to 385
XHS
Sync code
HOPB
ignored
30
C
Number of DCK clock
[@288 MHz]
O
1[H] = 1[XHS]
20
HOPB
60
HOPB
ignored
30
Ignored
area of Margin for
effective
Color
pixel processing
20
15
Effective pixels
5760
Ignored
Margin for area of
Color
effective
processing
pixel
15
30
Sync code
20
4760
4764
EAV1
EAV2
EAV3
EAV4
4762
4766
EAV1
EAV2
EAV3
EAV4
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4720
4724
4728
4732
4736
4740
4744
4748
4722
4726
4730
4734
4738
4742
4746
4750
4723
4727
4731
4735
4739
4743
4747
4751
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288 MHz)
DO
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
90
94
98
102
106
110
114
118
122
126
130
134
91
95
99
103
107
111
115
119
123
127
131
135
89
93
97
101
105
109
113
117
121
125
129
133
64
68
72
76
66
70
74
78
67
71
75
79
65
69
73
77
16
20
24
28
18
22
26
30
DO3
19
23
27
31
DO2
SAV1
SAV2
SAV3
SAV4
2
6
DO1
LVDS output
4ch 10 bit serial
SAV1
SAV2
SAV3
SAV4
3
7
SAV1
SAV2
SAV3
SAV4
1
5
DO0
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
DCK
(288 MHz)
5[DCK] * Detected both edges.
Readout Drive Timing
80
HBLK period
IMX206CQC
4-6. Horizontal arbitrary cropping function
(1) Outline of the Function
In this sensor horizontal cropping area can be arbitrary changed by register settings. Horizontal front blanking does
not change by cropping position, and horizontal rear blanking is always extended.
XHS
(a)
Horizontal
SAV
Blanking
LVDS Output
HOPB
Pixel data
(removed)
(removed)
EAV
Horizontal
Blanking
Cropping
XHS
Horizontal rear blanking
are extended
(b)
Horizontal
SAV
Blanking
LVDS Output
HOPB
Pixel data
EAV
Horizontal Blanking
AL
Relation between Horizontal Arbitrary Cropping and LVDS Output
(a) Without Horizontal Cropping (b) With Horizontal Cropping
(2) Register Settings
N
FI
HTRIMMING_EN Setting
D
EN
TI
Horizontal cropping enable register HTRIMMING_EN (address 00FCh, bit [0]) switches horizontal arbitrary cropping
function, and horizontal cropping area are determined by horizontal cropping position register HTRIMMING_START
(address 00F8h, bit [7:0] and address 00F9h, bit [4:0]) and HTRIMMING_END (address 00FAh, bit [7:0] and address
00FBh, bit [4:0])
Function
0
Horizontal arbitrary cropping OFF
1
Horizontal arbitrary cropping ON
Remarks
O
Register
value
C
Send with register setting for each
readout drive mode.
Horizontal Arbitrary Cropping Setting
Register
*1
Function
Remarks
*1
HTRIMMING_START
horizontal cropping start position
HTRIMMING_END
horizontal cropping end position*1 + 1
Unit: pixel
Send with register setting for each
readout drive mode.
Set the value of HTRIMMING_START and HTRIMMING_END according to the position after processing
horizontal binning or subsampling in the readout mode with horizontal binning or subsampling.
81
IMX206CQC
HTRIMMING_START and HTRIMMING_END must satisfy following 3 restrictions.
HTRIMMING_START = N × step
HTRIMMING_END = HNUM – M × step
HTRIMMING_END – HTRIMMING_START ≥ 240
(M and N are integers equal or more than 0)
Refer to the following tables in the value of step and HNUM.
Step Value
Readout mode No.
0, 1 and 7
2 and 2A
3 to 6 and 8
(horizontal no binning)
(horizontal 2 binning)
(horizontal 3 binning)
8
4
8
step
HNUM value
Readout mode No.
When using type 1/2.3 approx. 16.35 M pixels (4:3)
When using type 1/2.5 approx. 12.99 M pixels (Approx. 16:9)
TI
When using type 1/3 approx. 10.32 M pixels (4:3)
2, 2A, 7
3, 4, 5, 6, 8
4672
2336
1558
4672
2336
1558
3712
1856
1238
2176
―
726
EN
When using type 1/5 approx. 3.51 M pixels (4:3)
0, 1
AL
View angle to be used
D
(3) Column Width of Horizontal Arbitrary Cropping
N
FI
Column width after horizontal arbitrary cropping setting can be calculated by following formulas:
0, 1
2, 2A, 7
3, 4, 5, 6, 8
Column width
HTRIMMING_END – HTRIMMING_START + 96
C
Readout mode No.
O
Column Width of Horizontal Arbitrary Cropping
HTRIMMING_END – HTRIMMING_START + 48
HTRIMMING_END – HTRIMMING_START + 32
82
IMX206CQC
(5) Image Data Output Format
Readout pixel image and readout drive timing change when horizontal arbitrary cropping function is used.
For example, (a) Readout pixel image diagram of all-pixel scan mode when using type 1/2.3 approx. 16.35 M pixels
(4:3) and (b) Readout drive timing of the same mode (when 48 columns are cut at both left and right side) are shown
below.
(a) Readout Pixel Image Diagram of All-pixel Scan Mode When Using Type 1/2.3 Approx. 16.35 M Pixels
(4:3)
Front dummy(communication period + sensor clamp) 16XHS
H blank
(not output)
AL
12 Effective margin for color processing
24 Ignored area of effective pixel
TI
N
FI
D
EN
3456
3492
24 Ignored area of effective pixel
12 Effective margin for color processing
3500
(not output)
24 Ignored OPB
336 to 4768
O
240 to 4672
18
C
48 HOPB
24 Ignored OPB
3516
16 User clamp
4 Ignored area of effective pixel
18 Effective margin for color processing
0
Effective margin for color processing
4 Ignored area of effective pixel
V blank
HTRIMMING_END
Setting Range （step: 8 or 4 column）
HTRIMMING_START
Setting Range （step: 8 or 4 column）
(2216)
2336
center
(2456)
Readout Pixel Image Diagram (when horizontal arbitrary cropping function is used)
83
4672
IMX206CQC
(b) Readout Drive Timing of the Same Mode (When 48 Columns are Cut at Both Left and Right Side)
1[XVS] = 3575[XHS]
Front dummy 16XHS
[Communication
period +
sensor clamp]
User clamp
16H[16XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
Ignored area
of effective
Margin for
pixel
Color processing
4H[4XHS]
18H[18XHS]
Effective pixels
3456H[3456XHS]
VBLK period
43XHS
XVS
3510
3511
3512
3513
3514
3515
3492
3493
3494
3495
36
37
38
39
0
1
DO
14
15
16
17
18
19
20
21
XHS
1[H] = 1[XHS] = 1680[INCK@72MHz] = 6720[DCK]
(i)
Number of DCK clock
[@288MHz]
HBLK period
380 to 385
Sync code
HOPB
ignored
20
30
HOPB
60
HOPB
ignored
Ignored
area of
effective
pixel
30
20
Margin for
Color
processing
Effective pixels
15
Margin for
Color
processing
Ignored
area of
effective
pixel
15
30
5760
Sync code
20
HBLK period
XHS
4760
4764
EAV1
EAV2
EAV3
EAV4
SAV1
SAV2
SAV3
SAV4
2
6
18
22
26
30
66
70
74
78
90
94
98
102
106
110
114
118
122
126
130
134
138
142
146
150
154
158
4710
4714
4718
4722
4726
4730
4734
4738
4742
4746
4750
4762
4766
EAV1
EAV2
EAV3
EAV4
DO3
19
23
27
31
67
71
75
79
91
95
99
103
107
111
115
119
123
127
131
135
139
143
147
151
155
159
4711
4715
4719
4723
4727
4731
4735
4739
4743
4747
4751
4763
4767
EAV1
EAV2
EAV3
EAV4
4761
4765
EAV1
EAV2
EAV3
EAV4
4708
4712
4716
4720
4724
4728
4732
4736
4740
4744
4748
4709
4713
4717
4721
4725
4729
4733
4737
4741
4745
4749
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
64
68
72
76
16
20
24
28
DO2
SAV1
SAV2
SAV3
SAV4
3
7
89
93
97
101
105
109
113
117
121
125
129
133
137
141
145
149
153
157
DO1
LVDS output
4ch 10bit serial
65
69
73
77
SAV1
SAV2
SAV3
SAV4
1
5
DO0
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
DCK
(288MHz)
(removed)
(removed)
Horizontal Cropping
(wipe out each 48 pixels of right and left)
HBLK period
(ii)
380 to 385
4712
4716
EAV1
EAV2
EAV3
EAV4
4714
4718
EAV1
EAV2
EAV3
EAV4
4715
4719
EAV1
EAV2
EAV3
EAV4
4713
4717
EAV1
EAV2
EAV3
EAV4
4624
4628
4632
4636
4640
4644
4648
4652
4626
4630
4634
4638
4642
4646
4650
4654
TI
EN
90
94
146
150
154
158
162
166
170
174
178
182
186
190
194
198
202
206
91
95
147
151
155
159
163
167
171
175
179
183
187
191
195
199
203
207
D
4627
4631
4635
4639
4643
4647
4651
4655
88
92
144
148
152
156
160
164
168
172
176
180
184
188
192
196
200
204
89
93
145
149
153
157
161
165
169
173
177
181
185
189
193
197
201
205
64
68
72
76
66
70
74
78
67
71
75
79
5[DCK] * Detected both edges.
N
FI
SAV1[9]
SAV1[8]
SAV1[7]
SAV1[6]
SAV1[5]
SAV1[4]
SAV1[3]
SAV1[2]
SAV1[1]
SAV1[0]
DCK(288MHz)
DO
65
69
73
77
16
20
24
28
18
22
26
30
DO3
19
23
27
31
DO2
SAV1
SAV2
SAV3
SAV4
2
6
DO1
LVDS output
4ch 10bit serial
SAV1
SAV2
SAV3
SAV4
3
7
SAV1
SAV2
SAV3
SAV4
1
5
DO0
17
21
25
29
SAV1
SAV2
SAV3
SAV4
0
4
DCK
(288MHz)
4625
4629
4633
4637
4641
4645
4649
4653
AL
XHS
C
O
Readout Drive Timing
(i) without horizontal arbitrary cropping
(ii) with horizontal arbitrary cropping (when 48 columns are cut at both left and right side)
(6) XHS Minimum Period When Using Horizontal Arbitrary Cropping Function
XHS minimum periods when using horizontal arbitrary cropping function are as follows.
They are given by the formulas in the table below along with readout mode No. (independent with pixel number
using).
XHS Minimum Period When Using Horizontal Arbitrary Cropping
Readout mode No.
XHS minimum period [INCK]
0
max(1374, [HTRIMMING_END – HTRIMMING START] × 3/8 + 52)
1
max(714, [HTRIMMING_END – HTRIMMING START] × 5/16 + 44)
2
max(714, [HTRIMMING_END – HTRIMMING START] × 5/16 + 30)
2A
max(714, [HTRIMMING_END – HTRIMMING START] × 5/16 + 30)
3
714
4
714
5
714
6
714
7
max(714, [HTRIMMING_END – HTRIMMING START] × 5/16 + 28)
8
* Number of clocks in conversion of INCK = 72 MHz
* max(A, B) means larger value of A and B.
* Fractions should be rounded up.
714
84
IMX206CQC
Integration Time in Each Readout Drive Mode and Mode Changes
1. Integration Time in Each Readout Drive Mode
The integration time for this sensor's output data is set using the electronic shutter timing setting registers SHR, SVR
and SPL. The formulas and constants used to calculate the integration time are shown below.
In addition, the frame rate can be reduced by setting the SVR register to “1” or more.
◆ Integration time of normal readout drive mode (other than mode No.5 [Vertical 2/9 subsampling binning
horizontal 3 binning mode low power consumption drive])
Integration Time [s] = [{Number of XHS per XVS period × (SVR value – SPL value + 1) – (SHR value)}
× Number of clock per XHS Period + Number of clocks per internal offset period]
/ (INCK frequency [Hz] × INCK multiply rate)
* Number of clock per XHS Period is in conversion of INCK = 72 MHz.
* See the following tables for the numbers of clocks per internal offset period and INCK multiply rate.
* See “Electronic Shutter Timing” on page 31 for the SHR register setting range.
◆ Integration time of low power consumption drive mode (Mode No.5 [Vertical 2/9 subsampling binning
horizontal 3 binning mode low power consumption drive])
TI
AL
Integration Time [s] = [{Number of XHS per XVS period × (SVR value + 1) – SHR value × 4} × Number of clock
per XHS period + Number of clocks per internal offset period]
/ (INCK frequency [Hz] × INCK multiply rate)
D
EN
* Number of clock per XHS Period is in conversion of INCK = 72 MHz.
* See the following tables for the numbers of clocks per internal offset period and INCK multiply rate.
* See “Electronic Shutter Timing” on page 31 for the SHR register setting range.
* Only SPL = 0 can be used.
0
1
2
2A
3
4
5
6
7
8
Number of clocks per
internal offset period
218
149
149
149
149
149
149
149
149
149
INCK frequency setting [MHz]
72
36
24
12
INCK multiply rate
1
2
3
6
C
INCK multiply rate
O
Readout mode No.
N
FI
Number of clocks per internal offset period
The figure below shows operation when changing SHR. The V1 and V2 periods in the figure below are two
continuous XVS periods. The SHR value set within the first 6XHS periods (recommended serial communication
period) of V1 is updated internally at the end of the 6XHS periods, and then output data which reflect the new
setting is output in the V2 period. Note that the SHR setting and output are offset by 1XVS period.
SHR
change
Serial
communication
XVS
6XHS
6XHS
Sensor internal
V drive
SHR
r
t
ou
Valid data output
te
ut
sh
ad
re
r
te
ut
sh
t
Valid data output
ou
SHR Change Sequence
...
SHR
ad
re
V2 period
r
Valid data output
V1 period
te
ut
sh
Valid data output
85
6XHS
...
SHR
t
ou
t
ou
r
te
ad
re
ut
sh
ad
re
r
te
ut
t
ou
Y
6XHS
...
...
SHR
sh
ad
re
r
te
ut
Valid data output
6XHS
...
SHR
sh
Output frame
6XHS
.. .
XHS
IMX206CQC
The vertical sync signal XVS can be subsampled inside the sensor according to the SVR register. The vertical
sync signal period inside the sensor is (SVR value + 1) times as long as XVS signal period. Therefore the frame
rate is multiplied by 1/(SVR value + 1) according to the SVR value.
The figure below shows the operation when changing the SVR register. The example in the figure below shows
the update timing when SPL = 0 and the SVR value is changed from “0” to “1”. The SVR value set within the first
6XHS periods (recommended serial communication period) of V2 is updated internally at the end of the 6XHS
periods, and then applied from the shutter operation in the V2 period. Readout operation is not performed in the
V3 period, and output data which reflect the changing of SVR is output in the V4 period.
The image data of the V1 period before the SVR value is changed is output as valid data in the V2 period.
In addition, note that communication is also prohibited during the first 6XHS periods (recommended serial
communication period) of the V3 period (the frame during which readout operation is not performed)
Serial
communication
XVS
SVR
changed to “1”
SVR = 0
SPL = 0
6XHS
.. .
XHS
.. .
6XHS
6XHS
.. .
...
SHR
SHR
6XHS
.. .
...
SHR
ut
te
r
r
ad
te
re
ut
sh
r
ad
tte
re
u
sh
t
ou
t
ou
ou
r
ad
te
re
ut
sh
Y
Communication
prohibited
6XHS
sh
Sensor internal
V drive
Communication
prohibited
6XHS
t
Valid data output
Valid data output
V1 period
V2 period
Valid data output
V3 period
V4 period
V5 period
AL
Output frame
TI
SVR Change Sequence
C
O
N
FI
D
EN
When the internal vertical sync signal is subsampled by the SVR register, the SPL register can be used to set the
shutter in the vertical sync signal subsampling periods (the V2, V4 and V6 periods in the figure below).
The figure below shows the operation when changing the SPL register. The example in the figure below shows the
update timing when SVR = 1 and SPL is changed from “0” to “1”. SVR = 1 and SPL = 0 in the continuous frames of
the V1 and V2 periods, so shutter operation is performed in the V1 period and the corresponding data is output in
the V3 period. (See the aforementioned description of operation when SVR ≥ 1.)
The SPL value set within the first 6XHS periods (recommended serial communication period) of V3 is updated
internally at the end of the 6XHS periods, and then applied from the shutter operation in the V3 and V4 periods.
Readout operation is not performed in the V4 period, and output data which reflect the SPL change is output in the
V5 period. The image data of the V1 and V2 periods before the SPL value is changed is output as valid data in the
V3 period.
In addition, note that communication is also prohibited during the first 6XHS periods (recommended serial
communication period) of the V4 period (the frame during which readout operation is not performed).
The SPL register cannot be used in readout mode No.5: Vertical 2/9 subsampling binning mode (low power
consumption drive), so use the SHR register when setting the shutter in the vertical sync signal subsampling
period.
Serial
communication
XVS
SPL
changed to “1”
SVR = 1
SPL = 0
6XHS
6XHS
...
.. .
XHS
Communication
prohibited
6XHS
6XHS
...
.. .
.. .
SHR
SHR
6XHS
...
.. .
SHR
ad
re
ad
r
t
t
ou
te
r
ou
te
ut
sh
re
ut
sh
ou
r
t
t
ou
te
ut
ad
sh
ad
re
Y
6XHS
re
Sensor internal
V drive
Communication
prohibited
Output frame
Valid data output
V1 period
Valid data output
V2 period
Valid data output
V4 period
V3 period
SPL Change Sequence
86
V5 period
Valid data output
V6 period
IMX206CQC
2. Operation when Changing the Readout Drive Mode
The following change cases are treated as mode transition on this sensor and one frame of invalid data is generated.
1. Changing the readout mode setting
2. Changing the vertical direction readout inversion setting
3. Changing the vertical arbitrary cropping setting
* Changing the horizontal arbitrary cropping setting is not treated as mode transition and no invalid data
is generated.
The figure below shows the mode transition sequence (Mode A to Mode B). When performing mode transition in
three continuous XVS periods V1 to V3:
(1) If the XHS period for Mode A and Mode B differs, set XHS period / 2 (unit: INCK, in conversion of INCK = 72 MHz,
round down after the decimal point) of Mode B to the register HCOUNTHALF (address 007Ch, bit [7:0] and address
007Dh, bit [2:0]) between the top of V1 period and the top of V2 period. Then change actual XHS period at the timing
shown in the figure below (V2 head) *1.
(2) Set the register setting for Mode B at the top of V2 period. The output data of V2 period become invalid.
(3) Valid data which reflect the new setting is output from the next frame (V3 period).
*1
If output data of V1 period is to be used, register communication to the register HCOUNTHALF can be noise.
So it is recommended to perform the communication in the first 6XHS periods of V1 period or vertical rear
blanking period of V1.
TI
AL
In addition, note that when the output data length or the output data rate differ in Mode A and Mode B, the new data
format is output from the start of the 7th XHS of the frame (V2 period) in which the setting is changed to Mode B.
Set the SHR for
MODE = B here.
MODE
changed to “B”
6XHS
6XHS
6XHS
.. .
XHS
SHR
6XHS
.. .
.. .
SHR
SHR
B
u
sh
t
O
t
Mode B data format
data format
C
Mode A
V1 period
Invalid data output
Mode B
V2 period
V3 period
XHS period
change timing
Mode Transition
87
Mode B
Mode B
r
tte
t
ou
t
ou
r
tte
ad
re
u
sh
B
B
t
t
ou
ou
ou
ou
r
r
te
ad
re
ut
te
ad
ut
re
sh
B
B
B
sh
ad
te
r
N
FI
6XHS
.. .
SHR
re
ut
r
ad
te
re
ut
ad
Mode A
sh
A
sh
re
Mode A
Output data format
B
A
A
A
Y
SHR
SHR
6XHS
...
B
Sensor internal
V drive
...
D
Serial
communication
XVS
Output frame
EN
Set HCOUNTHALF
within this period
IMX206CQC
3. Recommended Global Reset Shutter Operation Sequence
The recommended global reset shutter operation sequence is shown below. Operation in this mode spans plural
XVS periods. Global reset shutter is performed in the first XVS period, and the data is output in following other XVS
periods.
The exposure time can be adjusted by varying the XVS input period. However, the minimum XVS period is 14XHS
periods. In addition, the mechanical shutter must also be used to make the exposure time the same for all pixels. See
“Electronic Shutter Timing” on page 31 for the SHR register setting range.
Recommended Operating Sequence for Global Reset Shutter
Operation item
Description
Normal
When performing global reset shutter
partway through rolling shutter operation
Global reset shutter normal operation
When performing global reset shutter
operation continuously
Global reset shutter continuous operation
Continuous
Explanatory diagram
Normal Operation
N
FI
D
EN
TI
AL
Operation when performing global reset shutter + all-pixel scan (12 bits) one time partway through rolling shutter
operation is shown below.
Vertical 2/9 subsampling binning horizontal 3 binning mode is described as a typical example of rolling shutter
operation, but the transition operation is the same for all modes that use rolling shutter.
V1 to V3 in the figure below are three continuous XVS periods. When the global reset shutter settings (SMD = 1,
register setting for all-pixel scan mode (12 bits) ) are made within the first 6XHS periods (recommended serial
communication period) of the V1 period, integration starts simultaneously for all pixels at the end of the 6XHS
period. Global reset shutter readout data is output during the V2 period.
Communication to return to the original mode (SMD = 0, register setting for vertical 2/9 subsampling binning
horizontal 3 binning, SHR should also be changed as necessary) is performed at the start of the V3 period.
The output data for the frame immediately after that (the V3 period in the figure) is invalid.
Note that communication is also prohibited during the first 6XHS periods (recommended serial communication
period) of the V2 period. The table below shows the integration start time of the exposure start period (V1 period).
Integration Start Time of the Exposure Start Period
*1
Integration start time of the exposure start period
(XVS reference)
C
O
Readout
mode No.
Approx. 435 [INCK] after the (6 + SHR) XHS period ends
1
Approx. 366 [INCK] after the (6 + SHR) XHS period ends *1
Number of clocks in conversion of INCK = 72 MHz
SMD = 1 (Global reset shutter)
SHR = 0
MODE: All-pixel scan, 12 bit
Serial
communication
XVS
6XHS
XHS
6XHS
…
6XHS
…
SHR
SMD = 0 (Rolling shutter)
SHR = Setting
MODE: Vertical 2/9 sub sampling
Communication
prohibited
6XHS
…
6XHS
…
…
SHR
r
t
ou
Vertical 2/9 sub sampling
V2 period
V3 period
Global Reset Shutter Normal Operation
88
tte
Invalid data output
Exposure start period
(no data output)
V1 period
ad
re
r
te
All-pixel scan (12 bit)
t)
Vertical 2/9 sub sampling
ut
ou
Vertical 2/9 sub sampling
sh
ut
SHR
ad
(re
t
t
ou
do
r
te
ou
shutter
r
te
ut
sh
r
te
ut
rea
…
…
SHR
ad
re
sh
ad
re
ut
sh
Output frame
6XHS
…
u
sh
Sensor internal
Vdrive
Y
*1
0
IMX206CQC
Continuous Operation
Operation when continuously performing global reset shutter + all-pixel scan (12 bits) is shown below.
V1 to V3 in the figure below are three continuous XVS periods. When the global reset shutter + all-pixel scan (12 bits)
settings (SMD = 1, register setting for all-pixel scan mode (12 bits)) are made within the first 6XHS periods
(recommended serial communication period) of the V1 period, integration starts simultaneously for all pixels at the
end of the first 6XHS period of the V1 period, and the all-pixel scan (12 bits) data is output in the V2 period. The
operation during V1 and V2 periods is then repeated each time XVS is input until the mode setting is changed next.
Note that communication is also prohibited during the first 6XHS periods (recommended serial communication
period) in the V2 period.
See the previous section for a description of the procedure when changing from continuous operation to a different
readout mode.
(Global reset shutter operation is performed in the
next V period even when SMD is not set here.)
SMD = 1 (Global reset shutter)
Serial
communication
MODE: All-pixel scan, 12 bit
XVS
6XHS
XHS
Communication
prohibited
6XHS
6XHS
…
Sensor internal
Vdrive
Communication
prohibited
6XHS
…
6XHS
…
…
…
…
SHR
r
Y
shutter
shutter
te
do
ut
rea
do
ut
r
tte
t
ou
u
sh
ad
ut
sh
re
rea
All-pixel scan (12 bit)
Vertical 2/9 sub sampling
Exposure start period
(no data output)
All-pixel scan (12 bit)
AL
Output frame
Exposure start period
(no data output)
V2 period
V3 period
TI
V1 period
EN
Global Reset Shutter Continuous Operation
D
Low Power Consumption Drive in Exposure of Global Reset Shutter Operation Sequence
C
O
N
FI
The sequence of low power consumption drive when exposing of global reset shutter operation is shown below.
To change to low power consumption drive, set the register SLEEP (address 0000h, bit [4]) to 1h after (SHR setting
value + 1) × XHS period or more in the frame of changing the register SMD from 0h to 1h.
And for readout, set SLEEP to 0h before 16 ms of readout frame in order to cancel low power consumption mode.
SLEEP = 0h
SMD = 1 (Global reset shutter)
SHR = SHR0
MODE: All-pixel scan, 12bit
XVS
6XHS
Communication
prohibited
6XHS
≥ 16 msec 6XHS
…
XHS
…
…
≥ (SHR0 + 1)XHS
SHR
SHR0
r
ou
rea
do
t
te
shutter
tte
u
sh
ad
re
ut
sh
Y
SLEEP = 1h
ut
r
Output frame
SMD
SLEEP
All-pixel scan(12bit)
Vertical 2/9 subsampling
0
1
OFF
ON
OFF
Exposure start period (no data output)
V1 period
V2 period
Low Power Consumption Drive in Exposure of Global Reset Shutter Operation Sequence
89
IMX206CQC
4. Interruptive Mode Change
The sensor mode can be changed using interrupts in all modes.
When changing the mode using an interrupt, the mode can be changed by inputting XVS in sync with XHS after
14XHS periods or more*1 have elapsed from the start of the frame, and transmitting the mode setting register value
within the communication period. In addition, the data output before the interrupt mode change is cut off at the timing
of the interrupt mode change.
If XHS period is to be changed in V2 period, set the register HCOUNTHALF between the top of V1 period and the top
of V2 period.
*1
When the mode before the change (Mode A in the figure below) is readout mode No.5 (low power consumption
drive), wait 38XHS periods or more from the start of the frame.
Set HCOUNTHALF
within this period
Serial
communication
XVS
14XHS or more
(1XHS increments)
6XHS
6XHS
...
SHR
B
u
sh
B
B
r
t
t
AL
t
ou
ou
ou
t
ad
ad
r
re
tte
tte
B
u
sh
re
r
t
ad
ou
re
tte
B
B
u
sh
r
r
ad
te
re
tte
ou
Mode B data format
Invalid data output
V2 period
Interrupt
timing
EN
V1 period
TI
Mode A data format
Mode A
SHR
SHR
ut
A
u
sh
ad
O
N
FI
D
Interruptive Mode Change
C
Output frame
...
sh
A
re
Output data format
6XHS
...
A
SHR
SHR
A
Y
6XHS
6XHS
...
.. .
XHS
Sensor internal
V drive
Set the SHR for MODE = B here.
MODE
changed to "B"
90
Mode B
Mode B
IMX206CQC
Power-on/off Sequence
1. Power-on Sequence
0.8 × VDDD1
VDDD1(1.2 V)
0.8 × VDDD2
VDDD2(1.8 V)
0.8 × VADD
VADD(2.8 V)
≥100 ns
≥100 ns
≥100 ns
Reset signal
XCLR
≥100 ns
3-wire serial input signals
XCE/SCK/SDI
AL
≥0 μs
TI
Sync signal input signals
XVS/XHS
≥0 μs
Master clock
INCK
EN
* INCK must not be over VDDD2
(1)
(2)
N
FI
D
Status
O
Power-on Sequence
Period name
Remarks
All input signals are at Low level.
There are no constraints of the power-on sequence with VADD, VDDD1, VDDD2.
(2) Standby cancel register
communication
Wait 100 ns after the last power supply in VADD, VDDD1, VDDD2. Then set XCLR
to “H” and start the standby cancel sequence.
C
(1) Power stabilization time
91
IMX206CQC
2. Slew Rate Limitation of Power-on Sequence
Conform the slew rate limitation shown below when power supply change 0 V to each voltage (0 % to 100 %) in
power-on sequence.
100 %
VDDD1
VDDD1
VDDD2
VADD
VDDD2
SR = ΔV/Δt
ΔV
Δt
0V
VADD
Max.
Unit
VDDD1 (1.2 V)
—
25
mV/µs
VDDD2 (1.8 V)
—
25
mV/µs
VADD (2.8 V)
—
25
mV/µs
AL
Min.
N
FI
D
EN
TI
SR
Power supply
O
Slew rate
Symbol
C
Item
92
Remarks
IMX206CQC
3. Power-off Sequence
Make sure that all input signals for the 3-wire serial interface and other signals are at Low level in the area of (2).
VDDD1 (1.2 V)
0.8 × VDDD1
VDDD2 (1.8 V)
0.8 × VDDD2
VADD (2.8 V)
0.2 × VADD
≥ 0 μs
3-wire serial input signals
XCE/SCK/SDI
≥ 0 μs
AL
Reset signal
XCLR
Sync signal input signals
XVS/XHS
TI
≥ 0 μs
EN
Master clock
INCK
(2)
(1)
N
FI
D
Status
≥ 0 μs
* INCK must not be over VDDD2
(1) Pixel output period
(2) Power-off time
Remarks
C
Period name
O
Power-off Sequence
Pixel signal output period
Turn the power supplies off after "L" level is set to all input signals.
There are no constraints of the power-off sequence with VADD, VDDD1, VDDD2.
93
IMX206CQC
Standby Cancel Sequence
After the power-on start-up sequence is performed, this sensor is in standby mode. The standby cancel sequence is
described below. Also perform this same sequence when canceling standby mode after shifting from normal
operation to standby mode.
1. After performing the power-on start-up sequence, set address 0000h, bit [1:0] to “2h” (STANDBY register = 0h,
STBLOGIC register = 1h). And if a clock which is not 72 MHz is to be used as input clock INCK, also set the
register PLRD (address 05A2h, bit [7:0]). When initialize communication is performed before the register
communication period in the V1 period, there are no restrictions on the communication order.
Register communication can be performed even when STANDBY = 1h.
2. After a stabilization period of 1 ms or more, set address 0000h, bit [1:0] to “0h” (STANDBY register = 0h,
STBLOGIC register = 0h).
If the data of V4 period after canceling standby mode is to be used:
(1) Transmit the value of XHS period / 2 (unit: INCK, in conversion of INCK = 72 MHz, round down after the
decimal point) to the register HCOUNTHALF (address 007Ch, bit [7:0] and address 007Dh, bit [2:0]) before
the end of V1 period.
(2) Transmit 0000h to the register SVR (address 000Dh, bit [7:0] and address 000Eh, bit [7:0]) and required
shutter settings and mode settings before the end of the communication period of V2 period.
D
Power-on sequence
EN
Vertical and horizontal sync signal can be input during initialize communication.
The V1 period requires a time of 16 ms or more.
Analog stabilization period
XCLR
XCE
≥ 1 ms
≥ 16 ms
XVS
set HCOUNTHALF
SVR=0, mode select
Register communication period
6XHS
6XHS
...
6XHS
.. .
SHR
SHR
SHR
te
r
r
ou
t
ou
t
t
t
Standby Cancel Sequence
94
t
ou
V4 period
ad
te
ad
r
ou
Valid data output
V3 period
re
ut
re
te
ut
ad
r
te
re
ut
d
Invalid data output
V2 period
ou
Invalid data output
V1 period
ut
sh
sh
sh
r
a
re
tte
d
Invalid data output
XHS period
change
...
sh
SHR
u
sh
Output frame
6XHS
.. .
SHR
a
re
Y
6XHS
.. .
XHS
Sensor internal
V drive
Normal operation
CLPSQRST = 1
DCKRST = 1
SSBRK=1
STBLOGIC = 0
O
STANDBY = 0
STBLOGIC = 1
(set PLRD)
Initialize communication
C
Serial
communication
Standby cancel sequence
N
FI
Note) 1.
2.
TI
AL
3. After an analog stabilization period of 16 ms or more, set "1h" in the LVDS clock output phase locking register
DCKRST (address 0001h, bit [0]), “1h” in the clamp reset register CLPSQRST (address 0001h, bit [4]) and “1h” in
the break mode register SSBRK (address 0002h, bit [0]) during the register communication period of the next
frame (the V2 period).
Valid data output
IMX206CQC
Peripheral Circuit Diagram
1000 pF
1.0 μF
0.1 μF
VDDMIF1
DCKP,
DOP#
VSSMIF1
VSSMIF2
VSSMIF3
VSSMIF4
VSSMIF5
VSSLCN1
Tx
TI
1.0 μF
AL
VSSLCB
VLOADLM
2.2 μF
VSSHPX
VRLT
VRLS
2.2 μF
0.1 μF
VBGR
VSSHDA
47 kΩ ± 5 % BIASRES
VSSHCP
VSSLPL
Common GND
D
EN
72/36/24/12
MHz
VDDMIO
Logic
Bias
BGR
Buffer
O
N
FI
Note) Locate a bypass capacitor for each pin. Note that even when pins have the same voltage, connecting the
power supply wiring before these capacitors produces common impedance and may result in unexpected
trouble.
C
INCK
VDDMIF2
1.0 μF
0.1 μF
Data
Bus
(XVS,XHS,SDI,SCK,XCE,XCLR)
Counter
DCKM,
DOM#
Control
Comp
VDDLSC2
VDDLSC1
VDDLCN
VDDHCM
Pixel
Array
V
Scan
VSSLSC1
VSSLSC2
VSSLSC3
Ramp
4.7 μF
1.0 μF
4.7 μF
VDDHPX
1.0 μF
VDDHDA
VDDHCP
CP
0.1 μF
1000
pF
0.1 μF
VDDLPL
0.1 μF
VDDSUB
PLL
I/F 1.8 V
Digital 1.2 V
Analog 2.8 V
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IMX206CQC
Notes on Handling
1. Static charge prevention
Image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
(1) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
(2) Use a wrist strap when handling directly.
(3) Install grounded conductive mats on the floor and working table to prevent the generation of static
electricity.
(4) Ionized air is recommended for discharge when handling image sensors.
(5) For the shipment of mounted boards, use boxes treated for the prevention of static charges.
2. Protection from dust and dirt
Image sensors are packed and delivered with care taken to protect the element glass surfaces from
harmful dust and dirt. Clean glass surfaces with the following operations as required before use.
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TI
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(1) Perform all lens assembly and other work in a clean environment (class 1000 or less).
(2) Do not touch the glass surface with hand and make any object contact with it.
If dust or other is stuck to a glass surface, blow it off with an air blower.
(For dust stuck through static electricity, ionized air is recommended.)
(3) Clean with a cotton swab with ethyl alcohol if grease stained. Be careful not to scratch the glass.
(4) Keep in a dedicated case to protect from dust and dirt. To prevent dew condensation, preheat or
precool when moving to a room with great temperature differences.
(5) When a protective tape is applied before shipping, remove the tape applied for electrostatic
protection just before use. Do not reuse the tape.
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3. Installing (attaching)
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(1) If a load is applied to the entire surface by a hard component, bending stress may be generated
and the package may fracture, etc., depending on the flatness of the bottom of the package.
Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive.
(2) The adhesive may cause the marking on the rear surface to disappear.
(3) If metal, etc., clash or rub against the package surface, the package may chip or fragment and
generate dust.
(4) Acrylate anaerobic adhesives are generally used to attach this product. In addition, cyanoacrylate
instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives to hold
the product in place until the adhesive completely hardens. (Reference)
(5) Note that the sensor may be damaged when using ultraviolet ray and infrared laser for mounting it.
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IMX206CQC
4. Recommended reflow soldering conditions
The following items should be observed for reflow soldering.
(1) Temperature profile for reflow soldering
Control item
Profile (at part side surface)
1. Preheating
150 to 180 °C
60 to 120 s
2. Temperature up (down)
+4 °C/s or less (– 6 °C/s or less)
3. Reflow temperature
Over 230 °C
10 to 30 s
Max. 5 °C/s
4. Peak temperature
Max. 240 ± 5 °C
Temperature
Peak 240 ± 5 °C
230 °C
Max. 5 °C/s
180 °C
– 6 °C/s or less
10 to 30 s
+4 °C/s
or less
60 to 120 s
AL
150 °C
Preheating
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Reflow
(2) Reflow conditions
Time
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(a) Make sure the temperature of the upper surface of the seal glass resin adhesive portion of the
package does not exceed 245 °C.
* For details, see Sony’s recommended temperature profile.
(b) Perform the reflow soldering up to three times.
(c) When performing reflow soldering one time.
Perform the first reflow soldering within 24 h after unsealing the degassed packing.
Store the products under the condition of temperature of 30 °C or less and humidity of 70 % RH or less after
unsealing the degassed packing. When more than 24 h has passed after unsealing the degassed packing,
perform baking at 125 °C for 24 h before performing reflow soldering.
No
More than
24 h at 30 ˚C,
70 % RH after
unsealing
Packing
unsealed
Yes
Baking
125 ˚C 24 h
Reflow
245 ˚C
(d) When performing reflow soldering two times
After the first reflow soldering, perform baking at 125 °C for 24 h within 72 h under the condition of
temperature of 30 °C or less and humidity of 70 % RH or less, and then immediately perform the second
reflow soldering.
No
Packing
unsealed
More than
24 h at 30 ˚C,
70 % RH after
unsealing
Baking
125 ˚C 24 h
Yes
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Reflow (first)
245 ˚C
Baking
125 ˚C 24 h
Reflow (second)
245 ˚C
IMX206CQC
(e) When removing the sensor from the board (three reflow soldering times)
Remove the sensor from the board (second reflow soldering) in accordance with Sony’s recommended
temperature profile, within 72 h after the first reflow soldering under the condition of temperature of 30 °C or
less and humidity of 70 % RH or less.
After removing the sensor from the board, perform baking at 125 °C for 24 h within 72 h under the condition
of temperature of 30 °C or less and humidity of 70 % RH or less, and then immediately perform the third
reflow soldering.
No
More than
24 h at 30 ˚C,
70 % RH after
unsealing
Packing
unsealed
Baking
125 ˚C 24 h
Yes
Reflow (first)
245 ˚C
Reflow for Removing
Sensor (second)
245 ˚C
Baking
125 ˚C 24 h
Re-mounting
Reflow (third)
245 ˚C
(f) Perform re-baking a maximum of two times under the condition of 125 °C for 24 h.
(3) Others
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(a) Carry out evaluation for the solder joint reliability in your company.
(b) After the reflow, the paste residue of protective tape may remain around the seal glass.
(The paste residue of protective tape should be ignored except remarkable one.)
(c) Note that X-ray inspection may damage characteristics of the sensor.
5. Others
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(1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will
be discolored.
(2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage
or use in such conditions.
(3) This product is precision optical parts, so care should be taken not to apply excessive mechanical
shocks or force.
(4) Note that imaging characteristics of the sensor may be affected when approaching strong
electromagnetic wave or magnetic field during operation.
(5) Note that image may be affected by the light leaked to optical black when using an infrared cut
filter that has transparency in near infrared ray area during shooting subjects with high luminance.
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IMX206CQC
Package Outline
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(Unit: mm)
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