ASIC Design Flow
Himanshu Patel
Space Applications Centre (ISRO)
hnpatel@sac.isro.gov.in
Contents
o
o
o
o
o
o
Introduction
ASIC Design Methodologies
n Full custom
n Standard Cell
n Gate Array ASIC
n Structured ASIC
ASIC Design Flow
n Design Entry
n Functional Verification
n Synthesis
n Design For Test (DFT)
n Place & Route
n Timing Verification
n Formal Verification
n Proto ASIC Test
Mixed Signal ASIC
Challenges for Deep Submicron ASIC
CASE Study : OBC ASIC
ASIC Design Flow
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Himanshu Patel
ASIC
o ASIC stands for Application Specific
Integrated Circuits.
o It means an integrated circuit designed for
a specific application.
o An application could be a microprocessor,
cell phone, modem, router, etc.
o Nowadays, ASIC has a complete system on
it, often called as System on a Chip (SOC)
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ASIC Design Methodologies
Full-custom
design
Ø Each
primitive logic
function or
transistor is
manually
designed
ASIC Design Flow
Standard-cell
based design
Gate-array
based design
Structured
ASIC
Standard
library cells
(NAND,NOR,
XOR,FF etc)
are used for
design
Wafers are
pre-fabricated
with
unconnected
gate arrays
Wafers are
pre-fabricated
with
Standard
library cells
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Himanshu Patel
Full custom ASIC
o Each primitive logic function or transistor is
manually designed
o Manually manipulation of each transistor geometry
is done, so also called “polygon pushing”
o Rarely used today, (except for very high volume
products like microprocessor etc)
Advantages:
o It gives most optimized design : high speed, low
power, small gate count
Disadvantage:
o Long design cycle
o Higher NRE (Non- Recurring Engineering) cost
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Himanshu Patel
Standard Cell based ASIC design
o Pre-defined library cells (NAND,NOR,FF,RAM, Hard macro
cores etc) are used
o Designs are created using schematic capture or synthesis
from Hardware Description Languages (HDL)
o All mask layers are customized —transistors and
interconnect
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Himanshu Patel
Standard cell ASIC
Advantages:
o Shorter design time compared to full custom style
o “Mega cells” or Hard IP cores (Microprocessor, MAC
Memory etc) provided by vendor can be used easily
Disadvantage:
o Separate fabrication mask is required for each
design : High NRE cost compared to gate array
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Gate Array ASIC
o Wafers are pre-fabricated with unconnected gate
arrays (so wafers are common for all design)
o Top metallization for connecting transistors is done
according to different design at last stage
channelless gate array:
Only some (the top few) mask layers
are customized
channeled gate array:
The interconnect uses predefined
spaces between rows of base cells
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Gate Array ASIC
Advantages:
o Lower NRE cost as same base wafer is pre-fabricated
for multiple designs
o Low turn around time
Disadvantage:
o Low layout density,
o less optimized: Low speed, High power consumption
o Suitable only for lower volume products
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Himanshu Patel
Structured ASIC
o A Structured ASIC falls between an
Gate Array and a Standard Cellbased ASIC
o The design task involves mapping
the design into a library of building
block cells, and interconnecting
them as necessary.
o Largely Prefabricated
n Components are “almost”
connected in a variety of
predefined configurations
n Only a few metal layers are
needed for fabrication
n Drastically reduces turnaround
time
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Himanshu Patel
Structured ASIC
Advantages:
o Low NRE cost
o High performance
o Low power consumption
o Less Complex
n Fewer layers to fabricate
o Small marketing time
n Pre-made cell blocks available for placing
Disadvantages:
o Lack of adequate design tools
o Design constrained by pre-fabricated block
available in library
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Comparison Graph
Full Custom
Cost
Standard Cell
Gate Array
FPGA
Volume
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Digital ASIC Design Flow
1. Front End design :
o Specifications to Gate level netlist generation
o Normally done by customer
2. Back End design :
o From Gate Level netlist to GDS-II generation
o Normally done by vendor or third party designer
3. ASIC Fabrication:
o GDS-II to ASIC chip
o Done by foundry
ASIC Design Flow
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Front End Design
Design Flow
Verification Flow
Specifications
IP Cores
Design Entry
(RTL Coding)
Functional Verification
(Behavioral Simulation)
No
ASIC
cell Lib.
BIST & JTAG
Insertion (DFT)
Synthesis
Functionality
OK ?
Yes
Netlist & SDF
Pre Layout
Timing Simulation
Gate Level netlist
ASIC Design Flow
Testbench
coding
DRC
14
DRC Error
(Design Rule Check) Himanshu Patel
Specifications
o The chip functionality is described in
“Requirement & Specification Document”
o The targeted speed, power consumption,
area are also specified
o System Engineer conveys requirement in
plain English to Design team and
Verification team
n Design Team generates RTL code as per specs.
n Verification team generates Test benches/test
cases as per specs
Back
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Himanshu Patel
Design Entry
o Either by Scematic Capture or through
HDLs like VHDL,Verilog etc
o The quality of final chip depends largely on
quality of RTL code
o There are some design guidelines which
should be followed
n
n
n
n
Design should be synchronous
Clock gating should be avoided
Flip flops should be used instead of latches
Proper FSM coding styles (one hot, binary, etc)
o IP Cores or third party soft cores are used
for standard blocks like processor, MAC,
UART etc
Back
ASIC Design Flow
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Himanshu Patel
Testbench
Stimulus
Generator
Unit Under
Test
Output
Monitor
Test
Report
o First Test plan is worked out based on which
different test cases are identified
o Assertion based testbenchs checks
captured output with expected output and
writes report
Back
ASIC Design Flow
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Himanshu Patel
Functional Verification
o The functionality of RTL code is verified using
testbenchs it is also called “behavioral Simulation”
o Some of the popular simulators :
n ModelSim®
n NCSim®
o Code coverage indicates how much portion of RTL
code is covered by testvectors
n Statement coverage
n Expression coverage
n Branch Coverage
n Toggle coverage
o Typically a “good” testbench achieves more than 95%
code coverage
Back
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Himanshu Patel
Design For Test
o Along with user logic, extra blocks are added
for detection of manufacturing defects
o DFT is “structural test” (unlike, Dynamic
simulation which is functional test)
o DFT methodology
n Built In Self Test (BIST)
n Boundary Scan chain (JTAG)
n Internal Scan Chain
RTL level
Netlist level
o DFT Advantages:
n Improve quality by detecting defects
n Make it easier to generate vectors
n Reduce vector generation time
o DFT Disadvantages:
n Area overhead of 10-15%
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BIST (Built In Self Test) Insertion
o Along with user logic, additional blocks are
added for self test
n Memory BIST (MBIST)
n Logic BIST (LBIST)
MBIST
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JTAG Insertion
IEEE 1149.1 standard for Boundary Scan test
Back
ASIC Design Flow
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Synthesis
o Process of converting RTL code in to gate
level netlist
o ASIC Vendor provides Cell library of basic
gates (AND,OR,FF,RAM,FIFO..)
o Pre synthesized IP Core blocks
(DesignWare,…) are treated as “Black Box”
o Some of the popular synthesizer :
n Synopsys DC, Cadence Ambit BuildGates
Synplify ASIC
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Himanshu Patel
o Synthesis Script contains directives for
synthesizer
n Optimization goal : speed/area
n Timing constraints
n FSM encoding style etc
o Special care should be taken for “high
fanout nets” like clock & reset
n They are not synthesized at this level
Set_dont_touch_network
n During Clock Tree Synthesis process, layout tool
creates optimized clock tree
Back
ASIC Design Flow
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Himanshu Patel
Pre Layout Timing Simulation
o Two types Timing Delays
n Cell delay (input to output of a cell)
n Propagation delay (o/p of cell1 to i/p of cell2)
o Delays are specified as (min, typ, max) depending
on PVT (Process, Voltage, Temperature) condition
o Wireload models are used to estimate
propagation delay based on fanouts
because at this stage Layout is not done
o Setup violations must be addressed
n Pipelining
n Register retiming (balancing combi. Logic)
o Hold violations can be ignored at this stage
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Himanshu Patel
Setup violation: Data late, clock early
Max delays are considered
Decides maximum clock frequency
Hold violation: Data early, clock late
Min delays are considered
Back
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Himanshu Patel
Design Rule Check (DRC)
o The gate level netlist must be checked for
“design rules” before starting Back End design
o There are different DRCs/LRCs
n Illegal net connections (two outputs shorted, etc)
n Drive load limit violations
o (fanout of driver < total load to output)
n Undriven nets
n Naming convention errors
o DRC tool kit is provided by ASIC foundry
Back
ASIC Design Flow
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Himanshu Patel
Back End Design
Design Flow
Verification Flow
Gate Level netlist
Scan
Lib.
Testbench
Scan Insertion (DFT)
Floorplanning
Timing
Constr.
Placement
Scan Chain Stitching &
ATPG
(DFT)
Clock Tree Synthesis
Pre Layout
N/L
Post Layout
N/L
Formal Verification
Equivalence check
Routing
STA
Back Annotation SDF
(RC Delay Extraction)
ASIC Design Flow
GDS-II file
Static Timing Analysis
Netist
27
No
Post Layout
Timing Simulations
Timing
OK ?
Himanshu Patel
Scan Insertion (Design For Test)
o All internal flip-flops & latches are replaced by
Scan Flip-flops (FF with MUX)
o Testability
n Controllability
n Observability
o Scan Pins
n
n
n
Scan In
Scan Out
Scan Enable
o scan cells are
NOT connected until
placement is completed
so ‘chain’ is not formed
at this stage
ASICBack
Design Flow
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Floorplanning
o Floorplanning is a mapping between the
logical description (Hierarchical Netlist) and
the physical description (the floorplan).
The goals of floorplanning are to:
o arrange the blocks on a chip,
o decide the location of the I/O pads,
o decide the location and number of the
power pads,
o to minimize the chip area and delay
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Floorplanning
initial random floorplan
generated by a
floorplanning tool
Blocks are moved to reduce
congestion
Back
ASIC Design Flow
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Himanshu Patel
Placement
o Placement is arranging all the logic cells within
the flexible blocks on a chip.
o objectives of placement
n Guarantee the router can complete the
routing step
n Minimize all the critical net delays
n Make the chip as dense as possible
ASIC Design Flow
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Himanshu Patel
block A contains four rows of standard cells (A.211, A.19, A.43, A.25)
The Goal is to decide placement to achieve minimum distance between cells
Back
ASIC Design Flow
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Himanshu Patel
Scan chain stitching & ATPG
o After placement , Scan cells are stitched
together to form a ‘scan chain’
o Normally Different scan chains are formed
for different clock domain Flip Flops
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Himanshu Patel
ATPG (Automated Test Pattern Generation)
q ATPG generates Test patterns/vectors which are applied to DUT
for detection of manufacturing defects
q The goal of ATPG is to create a set of patterns that achieves a
given (maximum) test coverage,
Stuck at ‘0’ fault
q ATPG consists of two main steps:
qgenerating patterns
qfault simulation.
Fault models:
• Stuck-at-fault
• Transition fault : Propagation delay of cell
• Path delay : Sum of time delays in path
• IDDQ : Measurement of quiescent power supply
current during the stable state
Back
ASIC Design Flow
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Himanshu Patel
Clock Tree Synthesis (CTS)
o Clock Tree is defined by its startpoint (source) and
endpoints (sinks)
o During CTS, delay and skew from source to sinks are
optimized.
Step 1: Generate a clock tree
Step 2: Tune the clock tree to meet Skew & Slew target
Back
ASIC Design Flow
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Himanshu Patel
Routing
o Routing is done in 2 steps
n Global Routing : plans channels for routing between
blocks, Its goal are:
o Minimize the total interconnect length.
o Maximize the probability that the detailed router
can complete the routing.
o Minimize the critical path delay.
Global routing for a cell-based ASIC formulated as a graph problem.
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Detailed Routing :
n complete all the connections between
logic cells
n exact location and layers for each interconnect
are determined
Completed channel route (2 metal layers m1 and m).
Back
ASIC Design Flow
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Back Annotation & RC Extraction
o Delays are extracted from physical & RC
information in Standard Delay Format (SDF)
o Back annotated SDF file is used during post layout
timing simulation and STA.
The lumped-RC interconnect model.
Back
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Himanshu Patel
Formal Verification
o Equivalence check between pre-layout and
post layout
o Mathematical models are made to check
functionality equivalence at each node of
netlist
o FV can also be done between RTL & Netlist
o EDA Tool
n Formal Pro (Mentor)
n Formality (synopsis)
Back
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STA (Static Timing Analysis)
•
•
Static timing analysis is a method of validating the
timing performance of a design by checking all
possible paths for timing violations.
STA tool breaks the design down into a set of
timing paths, calculates the signal propagation
delay along each path
o Compared with dynamic simulation, STA is much
faster because it is not necessary to simulate the
logical operation of the circuit.
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STA - Timing Paths
Timing Paths :
o Input path (I/p pad to FF)
o Sequential path (FF to FF)
o Output path (FF to o/p)
o Combination path (i/p to o)
Back
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Himanshu Patel
Post Layout Timing Simulation
o Back annotated SDF with post layout netlist
is simulated at min, typ and max condition
o All interface timing (Ex. ROM/RAM access
timing, PCI bus timing etc) should be
modeled as Bus Functional Model (BFM)
o The simulation should be free from all
Setup and hold violation
o Whenever data is crossing clock domain,
metastable conditions should be checked.
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Setup and Hold Checking
Back
ASIC Design Flow
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Mixed Signal ASIC
o Digital + Analog blocks
o Analog blocks
n ADC, DAC
n Amplifiers, comparators etc
n RF Modulators & Demodulators
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Mixed Signal ASIC Design Flow
ASIC Design Flow
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Deep Submicron ASIC : Challenges
o As technology advances towards submicron
(below 0.13um/0.9um) issues like signal
integrity, power etc become prominent
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Deep Submicron issues
n
n
n
Power
o Increased DC power due to leakage
current
Signal Integrity
o Lower supply voltage reduces noise
margin
o Smaller geometries induces
coupling noise
o Higher current density causes EM
issues
Design Complexity
o Transistor Density doubles every
18 months (moor’s law)
o Clock frequency increases above 5
GHz
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OBC ASIC : A Case Study
o
OBC (On Board Controller) ASIC is designed for different
ISRO’s Satellite missions having on board Distributed
controllers
o
OBC ASIC Features
n On chip 8051 micro controller soft core
n 4 UARTs, 3 Timers, 6 Interrupts
n 3 synchronous serial receivers & transmitters
n 10 ports for parallel I/Os
n On chip 1KB ROM containing monitor program
n 16 programmable timing signal generator
o
ASIC Features
n CMOS Gate Array ASIC
n 256 pin package , 224 user I/Os
n 5 V core & 5V I/Os
n Radiation Hardened process
n Testability features like SCAN and ATPG with logic Fault
Coverage of > 95%
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OBC Block Diagram
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DW8051
Synopsys® DesignWare 8051
Soft IP Core
Features
o High–speed architecture
:4 clocks per instruction
cycle 2.5X improvement
over the standard 8051
o Dual data pointers
o 3 Timers, 2 UARTs
o Extended Interrupts (7 nos)
o Variable length MOVX to
access fast/slow RAM
peripherals
o Fully static synchronous
design
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OBC Peripheral Modules
o Watch Dog Timer : generates
reset/interrupt whenever the software
hangs
o Delta Sigma ADC: 8 bit digitization of lowrate analog data
o Programmable Combinatorial Logic
Module: A small FPGA CLB inside ASIC…!
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o Timing Signal Generator: This is generic
timing signal generator, which can generate
up to 16 programmable pulses
o Auxiliary Data Interface: This is
parallel/serial auxiliary interface with built in
dual port RAM.
o Serial Synchronous
Transmitter/Receiver This is 3-wire (clock,
strobe, data) synchronous tx/rx
o Monitor Program :OBC ASIC contains 1K
Bytes of on chip ROM which holds Monitor
program firmware.
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Event Programmable Parallel Interface
o In Phased array distributed controller it is required to
load Transmit & Receive characterization data within
time constraint as shown above
o This task was earlier implemented in software as
“Interrupt Service Routine”, but due to variable
interrupt latency it was not meeting timing constraint
o So a Hardware module was implemented
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EEPPI - Architectute
clk
reset_n
8
Micro-controller
SFR
Interface
PPI
Ports
addr[7:0]
din[7:0]
dout[7:0]
Register
RegisterBank
Bank
Bank
6Register
XX88Bits
Bank
6Register
66XX8Bits
8Bits
Bits
6X8
bits
MUX
48
48
Sfr_wr
reg sel
8
Port0_PPI [7:0]
Port1_PPI [7:0]
Port2_PPI [7:0]
8
8
Port3_PPI [7:0]
8
Port4_PPI [7:0]
8
Port5_PPI [7:0]
wr
2
1
Data out[2:0]
Look Up Table
Addr
(LUT)
(Event -Action)
6
64 X 3
bits
ASIC Design Flow
Flags
2
Timing_control_Sig1
MUX
54
2
2
Event
Detect
Module
Timing_control_Sig0
Himanshu Patel
UART_RRS
o
UART with Recursive Running Sum Filter to
remove noise samples from incoming serial data
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UART_RRS Test Results
o
UART_RRS has better performance than standard UART at
higher Noise levels
n
n
UART_RRS can decode data correctly up to 37% corrupted sample
Standard UART can decode data up to 6 % only
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Himanshu Patel
Challenges Faced during OBC design
o Almost all OBC modules are programmable/
configurable because exact funtionality was not
freezed during front-end design.
o Multi Clock Domain
n OBC contains 7 clock domains so 7 Scan Chains were
inserted.
o Data crossing clock domains
n Asynchronous DPRAM, with Left and Right Ports
accessing data at different clocks
n Series of FFs to avoid Metastable condition
o Rad Hard cells
n All Flip flops used in OBC are radhard (ASIC library
contained Soft, Rad Tol. & Rad hard)
o Monitor Program
n On chip 1K ROM contains assembly software , which
was regorously tested as lateron software
modification was not possible
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Proto ASIC Testing
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Thank You
To Probe Further :
http://Geocities.com/hnpatel81/asic.htm
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