Thermodynamic simulation of 6×6 Micro-LED array in flip-chip bonding
Haojie Zhou1,2, Xiaoxiao Ji2,3, Luqiao Yin2,4*, Jianhua Zhang2,4
School of Materials Science and Engineering, Shanghai University, Shanghai 200072, China
2
Key Laboratory of Advanced Display and System Applications, Shanghai University, Ministry of Education,
Shanghai,200072, China
3
School of Mechatronics and Automation, Shanghai University, Shanghai, 200072, China
4
School of Microelectronics,Shanghai University, Shanghai, 200444, China
2022 19th China International Forum on Solid State Lighting & 2022 8th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS) | 979-8-3503-4638-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/SSLChinaIFWS57942.2023.10070985
1
Abstract
In this paper, we first simulated the influence of different
diameters, heights and shapes on the In bumps by ANSYS
simulation software. The results show that the changes of these
conditions affect the deformation and stress of the In bumps to
varying degrees. The height of the bumps has the least effect
on the stress, while the diameter and shape of the bumps have
a great effect on the deformation as well as stress. Finally, a
sapphire based Mirco-LED array with a pixel pitch size of 7.5
µm was used to bond with silicon substrates with In bumps of
different heights, and turn it on with electricity. We found that
the In bumps height does affect the yield of Micro-LED, and
the best yield in the experiment is > 90%. This study provides
a theoretical basis for reducing the deformation and stress of In
bumps during flip-chip bonding, and an experimental basis for
improving bond yield and device performance.
1 Introduction
In the past few decades, display technology has developed
rapidly, and it is widely used in television, computers, large
advertising cards and small smart devices. In recent years,
Liquid Crystal Display (LCD) and Organic Light-Emitting
Diode (OLED) displays have gained wide applications and
have occupied major markets. But emerging display
applications, such as Virtual Reality (VR) and Augmented
Reality (AR), are placing higher demands on the current
mainstream displays[1].
Micro-LED displays are mainly prepared based on the
third-generation semiconductor material GaN, which have the
excellent characteristics of high luminous efficiency, high
brightness, short response time and high reliability, and have
been hailed as the ultimate display technology[2-4]. In order to
realize CMOS control of Micro-LED, both of them need to be
bonded together. The current realizations of Micro-LED
displays are mainly through two methods, one is the Mass
Transfer and bonding of a single chip, and the other is transfer
and bonding at the wafer level. The latter is to directly fabricate
the required pixel array on the wafer, and then design the
corresponding drive substrate for alignment bonding[5-7].
Wafer-level transfer and bonding not only overcome the single
chip transfer to achieve batch transfer, but also avoid the cost
and efficiency problems caused by making small nozzles.
There are mainly gold flip-chip bonding[8-10], indium flipchip bonding[11,12] and microtubule metal flip-chip
bonding[13] to integrate Micro-LEDs and CMOS. However,
flip-chip bonding is faced with the problems of high precision,
low yield and high cost. Moreover, the bonding process
requires the simultaneous action of heat and pressure, and the
thermal expansion coefficient and elastic modulus of materials
are different, which will lead to deformation and excessive
stress in the bonding process, resulting in interconnection or
fracture. These phenomena are particularly evident in small
size bonding.
In this paper, different diameters, heights and shapes of In
bumps were analyzed to compare the deformation and stress
under different conditions using finite element simulation.
Finally, we also verified the In bumps with different heights by
flip-chip bonding experiments.
2 Modeling
In this study, transient thermodynamic analysis of the flipchip bonding is performed using ANSYS simulation software.
A 3D model was established to simulate the deformation and
stress of a 6×6 Micro-LED array with a pixel pitch of 7.5 µm.
Fig. 1 shows the structure of Micro-LED array and silicon
substrate.
Fig. 1. Structure of Micro-LED array and silicon substrate.
Micro-LED array is grown on sapphire substrates, and Au
electrodes and In bumps with different diameters, heights and
shapes are grown on silicon substrate by lithography. For
transient thermodynamic analysis, temperature is applied to the
bottom surface of the silicon substrate and force is applied to
the top surface of the sapphire. The specific size parameters of
Micro-LED array and silicon substrate are shown in Table 1.
Table 1. Dimension of the model parts.
Thickness
Parts
Dimension/μm
/μm
Sapphire
46.5×46.5
20
GaN
6×6
5
Au
Φ4.5
2
Φ1~5
Top side：Φ2
Bottom side：Φ4
1~3
Cylinder
In
Circular
truncated cone
Φ1~5
Au
6×6
0.4
Si
46.5×46.5
40
In order to unify and obtain accurate simulation results, we
adopt the system default mesh generation method. Fig. 2 (a)
shows 6×6 Micro-LED array that has been meshed. In addition,
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we applied a temperature of 200℃ on the bottom surface of Si
substrate, and obtained the transient thermal distribution as
shown in Fig. 2 (b) after stabilization.
Fig. 3. (a) The deformation and stress of In bumps
with different diameters under 0.5 mN pressure;Deformation
distribution of (b) 1μm; (c) 4 μm diameter.
Fig. 2. 6×6 Micro-LED array model after (a) meshing; (b) thermal
stabilization.
3 Result and discussion
(1) Different diameters
Firstly, the deformation and stress of In bumps with
different diameters of 1-5 μm were simulated under the
pressure of 0.5 mN and 1 mN. As shown in Fig. 3, both
deformation and stress of the bumps decrease as the diameter
of the bumps increase. Since the pressure applied in the
simulation is uniformly applied on the top of the sapphire, the
stress can be regarded as the normal stress. The normal stress σ
can be calculated by
P
σ=
(1)
A
where P is the force and A is the cross-sectional area. So a
decrease In diameter leads to an increase in normal stress.
On the surface, the increase of In bumps have a beneficial
effect on the bonding, but it will increase the possibility of
interconnecting between the bumps, resulting in the inability to
control a single pixel independently. We also found from the
simulation that the 1μm and 1.5μm diameter In bumps have
been completely flattened under the force of 1mN, which is
likely to damage the CMOS substrate. In addition, the In bumps
with smaller diameter will also reduce the accuracy of bonding
and increase the possibility of oxidation, and the formed oxide
layer will lead to poor bonding between chip and CMOS, or
even lead to bond failure.
(2) Different heights and shapes
Then, the deformation and stress of columnar bumps and
cone-shaped bumps with 1-4 μm height were simulated under
the pressure of 0.5 mN and 1 mN. As can be seen from Fig. 4,
with the increase of the height of the In bumps, the deformation
of the bumps of the two shapes also increase. According to
Formula (1), only changing the height of the bumps without
changing the pressure and diameter have little influence on the
stress. However, under the same pressure, the deformation and
stress of the cone-shaped bumps are much higher than those of
the columnar, which indicates that the shape of the bumps has
a great influence on the deformation and stress results. Larger
deformation is more likely to lead to the interconnection of
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adjacent In bumps, and when CMOS drives Micro-LED array,
it will lead to short circuit and affect the control. The low In
bumps, like the small diameter bumps, will increase the
possibility of oxidation, thus affecting the bond yield and
device performance.
Finally, we also performed the bonding experiments
between the Mirco-LED array with sapphire substrate and the
Si substrate containing In bumps with height of 3μm and 4μm
with the pixel spacing of 7.5 µm. As shown in the Fig. 5, the
yield of 3 µ m and 4 µ m bonding are ＞ 90% and ＞ 80%
respectively. It can also be seen that the 3µm In bumps have
better luminescence area and brightness uniformity, the poor
yield of 4µm is due to the interconnection caused by excessive
deformation of In bumps. This corresponds to the simulation
results.
Fig. 5. Lighting of In bumps with different height after flip-chip
bonding. (a) 3µm; (b) 4µm
Fig. 4. (a) The deformation and (b) stress of In bumps with two kinds
of shapes;Stress distribution of (c) columnar bumps and
(d) cone-shaped bumps.
4 Conclusion
This study simulated the effect of a 6×6 Micro-LED array
with a pixel pitch size of 7.5 µm on its own deformation and
stress under In bumps with different diameters, heights and
shapes. By comparison, the change of In bumps height has the
least impact on the stress, while the change of diameter and
shape has a great impact on both deformation and stress. And
the deformation and stress of the cone-shaped bumps are far
greater than those of the columnar. We also verified through
experiments that the lower In bumps have a better bond yield,
which is better than 90%, because the lower bumps have a
small deformation and will not form the interconnection, which
is also in line with the simulation results. However, the In
bumps with too low height may be directly flattened due to
excessive deformation, thus damaging the CMOS substrate.
The In bumps with too small size is extremely easy to be
oxidized, which will lead to poor bonding between the chip and
CMOS, or even the possibility of failure to bond.
Acknowledgments
This work was supported by the Science and Technology
Commission
of
Shanghai
Municipality
Program
(20010500100, 21511101302).
References
1. K. Hayashi, S. Nomura, and Y. Sakai. “Glass Substrate for
Micro Display Devices,” SID International Symposium:
Digest of Technology Papers, Vol. 48, No. 2 (2017), pp.
1196-1200.
2. Xu Y, Cui J, Hu Z, et al. “Pixel crosstalk in naked-eye
micro-LED 3D display,” Applied Optics, Vol. 60, No. 20
(2021), pp. 5977-5983.
3. Huang Y, Hsiang E L, Deng M Y, et al. “Mini-LED,
Micro-LED and OLED displays: present status and future
perspectives,” Light: Science & Applications, Vol. 9, No.
1 (2020), pp. 1009-1024.
4. Wang Z, Zhu S, Shan X, et al. “Full-color micro-LED
display based on a single chip with two types of
InGaN/GaN MQWs,” Optics Letters, Vol. 46, No. 17
(2021), pp. 4358-4361.
(3) Experiment
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5.
F. Greer, M. Dickie, R. P. Vasquez, et al. “Pasma
Treatment Methods to Improve Indium Bump Bonding
Via Indium Oxide Removal,” Journal of Vacuum Science
& Technology B, Vol. 25, No. 5 (2009), pp. 2132-2137.
6. P. Kozłowski, K. Czuba, K. Chmielewski, et al. “IndiumBased Micro-Bump Array Fabrication Technology with
Added Pre-Reflow Wet Etching and Annealing,”
Materials (Basel), Vol. 14, No. 21 (2012), pp. 6269-6280.
7. K. Furuyama, K. Yamanaka, E. Higurashi, et al.
“Evaluation of Hydrogen Radical Treatment For Indium
Surface Oxide Removal and Analysis of Re-Oxidation
Behavior,” Japanese Journal of Applied Physics, Vol. 57,
No. 2 (2018), p. 02BC01.
8. McKendry, Jonathan. “Micro-Pixellated A1ingan LightEmitting Diode Arrays for Optical Communications and
Time-Resolved Fluorescence Lifetime Measurements,”
Diss. University of Strathclyde, 2011.
9. W. Chang, “Optimization of Micro-interconnection
Distribution of Gold Stud Bumps for Thermo-sonic Flip
Chip Bonding,” 23rd International Conference on
Electronic Packaging Technology, Dalian, China, Aug.
2022, pp. 1-4.
10. Li YC, Chang LB, Chen HJ, et al. “Phosphor-Free InGaN
White Light Emitting Diodes Using Flip-Chip
Technology,” Materials (Basel), Vol. 10, No. 4 (2017), pp.
432-443.
11. Z. J. Liu, W. C. Chong, K. M. Wong, et al. “360 PPI FlipChip Mounted Active Matrix Addressable Light Emitting
Diode on Silicon (LEDoS) Micro-Displays,” Journal of
Display Technology, Vol. 9, No. 8 (2013), pp. 678-682.
12. Lei, Chan U, Lev Krayzman, et al. “High Coherence
Superconducting Microwave Cavities with Indium Bump
Bonding,” Applied Physics Letters, Vol. 116, No. 15
(2020), p. 154002.
13. F. Templier. “High‐resolution GaN microdisplays and
solution for full‐color devices for AR/MR applications,”
SID Symposium Digest of Technical Papers, Vol. 52,
(2021), pp. 305-307.
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