2011機械產業藍白領人才培訓計畫
Chapter IV
FPGA-Based永磁同步馬達伺
服控制系統之設計與實現
Sep. 6, 2011
主講者： 龔應時
南台科大電機系 教授
Outline
1. Current vector control of PMSM drive
2. Speed control of PMSM drive
3. Experimental system and results
4. Conclusion
2
1. Current vector control of PMSM
1.1 Architecture of the current vector control
system for PMSM drive
1.2 FPGA-based current vector control IC for
PMSM drive
1.3 Experiment results of current vector
control
3
1.1 Architecture of the current vector
control system for PMSM drive
Current loop
Current
controller
iq*
vq
PI
+
id*  0
DC
Power
v
d,q
—
vd
PI
+
Park
-1
, 
v
modify
Clark-1
vref 1
, 
vref 2
SVPWM
v
a,b,c ref 3
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Inverter
—
iq
id
d,q
, 
Park
sin  e / cos e
sin /cos of
Flux angle
i
i
, 
a,b,c
ia
ib
ic
iu
A/D
converter
iv
LPF
LPF
Clark
e
QEP
circuit
A
B
Z
PMSM
Encoder
4
Mathematical model of PMSM
drives adopting the vector control
The mathematical model of a typical PMSM
described in two-axis d-q synchronous
rotating reference frame:
The dynamic equation of PMSM
includes the mechanical load
Lq
di d
R
1
  s id   e
iq 
vd
dt
Ld
Ld
Ld
di q
dt
  e
f
Ld
R
1
id  s iq   e

vq
Lq
Lq
Lq Lq
The developed electromagnetic torque:
3P
Te 
( d iq   q id )
4
Applying the vector control:
Te 
Jm
3P
3P
 f iq  K t iq with K t  4  f
4
d
 r  B m  r  Te  T L
dt
TL
iq*
Te Kt
+
PMSM
1
J m s  Bm
r
Equivalent block diagram for current
vector control of PMSM drives
5
Coordinate transformation
Park-1

q
 f  cos e  sin e   f d 
f 
 f 
sin

cos

e
e  q 
  
b
fS
fβ
f qs
e
e
d
f ds
f α}
Clark-1
a
stator

Clark
rotor
三相靜子座標軸
d q
兩軸同步旋轉軸
兩軸靜止座標軸

0 
3  f 
 
2  f 
3


2 
1
3
1
3
1  f 
a
3  f 
1  b 
 

3   f c 
 f d   cos  e
f 
 q   sin  e
sin  e   f 
 
cos  e   f  
2
 f   3
f 
   0

c
a b c
 


 fa   1
 f    1
 b  2
 f c   1

 2


Park
6
PI controller
• Analog PI controller
K
G(s)  KP  I
S
K P：Proportional gain
KI ：Integral gain
•Digital PI controller (Using Bilinear transformation)
Gc ( z)  KP 
zKI
z 1
U p (k )  K pe(k )
U I (k )  U I (k 1)  KI e(k 1)
U (k )  U P (k )  U I (k )
7
1.2 FPGA-realization of current vector
controller for PMSM drive
Nios II Processor
Current
controller
i
*
q
i 0
*
d
FPGA
vq
PI
+
PI
Park-1
v
d,q
—
+
DC
Power
vd
,  v
iq
i
Modify
Clark-1
vref 1
, 
vref 2
SVPWM
v
a,b,c ref 3
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Inverter
—
Current command
generation
id
d,q
, 
Park
sin  e / cos e
i
ia
ib
, 
a,b,c
ic
A/D
A/D
Interface
A/D
iu
iw
LPF
LPF
Clark
sin /cos of
Flux angle
e
A
p
QEP
circuit
B Comparator
Z
circuit
PMSM
Encoder
Current loop for PMSM
8
Implementation of current vector controller
PWM1
SVPWM
a,b,c
Modified
Clarke 1 , 
iq*
Park 1 d,q
-
i 0
+
Te
, 
i
a,b,c
Clarke
p
Block Diagram of
Current Vector Control
i
d,q
PI
QEP Circuit
A/D read
, 
+
*
d
A, B , Z
PWM6
,  Park
Digital Circuit of
Current Vector Control
iq
id
Sin &Cos
θe P
PI
-
CCCT
ADIN[11]
2
Clk
Clk-ctr
Clk-ctr
ia [11..0]
Clk-sp
iq* [11..0]
clk
A-pulse
B-pulse
Z-pulse
 p [15..0]
QEP detection
and
 e _ addr [11..0]
transformation
ADIN[0]
ADC read in
Clk
BDIN[11]
and
ib [11..0] transformation
Current controllers
and coordinate
transformation
(CCCT)
BDIN[0]
CHA
CHB
RCA
RCB
STSA
STSB
ic [11..0]
Clk
Clk-sp
v rx [11..0]
SVPWM
v ry [11..0]
generation
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
v rz [11..0]
9
Designed digital circuits in current
vector control loop of PMSM
1.2.1 SPWM circuit
1.2.2 QEP circuit
1.2.3 Circuit of A/D interface
1.2.4 Circuit of current controllers and
coordinate transformation
(CCCT circuit)
10
1.2.1 SVPWM circuit
Generation of
the symmetry
triangular wave
Clk
Q
Vrx
Vry
Vrz
CMPR1
S1
12
12
S12
S2
S..
S3
PWMEA_1
Comparator PWMEA_2
(1)
12
PWMEB_1
CMPR2
State Machine
12
CMPR3
12
SVPWM Algorithm
Clk
Comparator
PWMEB_2
(2)
PWMEC_1
12
Clk_sp
12
Comparator
PWMEC_2
(3)
Clk_sp
Dead-band
generation
unit
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
11
1.2.2 QEP circuit
12
1.2.2 QEP circuit
PHA
A-pulse
Digital
Filter
D
B-pulse
Digital
Filter
D
generation
DIR
of
DLA
Q
4-times
frequency
up/down
pulses and PLS counter
PHB
counter
DLB direction
Q
Clk
Z-pulse
Digital
Filter
PHZ
QEP-value
address
generation
of
electrical angle
16
p
12
 e _ addr
13
VHDL code of QEP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity QEP is
port(clk_500n ,seveo_on : in STD_LOGIC ;
PA,PB,PZ
: in STD_LOGIC ;
QEP_OUT
: out STD_LOGIC_VECTOR (31 downto 0);
Address
: out STD_LOGIC_VECTOR (9 downto 0));
end QEP ;
architecture QEP_ARCH of QEP is
signal CNT
: STD_LOGIC_VECTOR (15 downto 0) ;
signal ADDR
: STD_LOGIC_VECTOR (15 downto 0) ;
signal TADD
: STD_LOGIC_VECTOR (9 downto 0) ;
signal PHA,PHB,PHZ
: STD_LOGIC ;
signal DIR,PLS
: STD_LOGIC ;
begin
FILTER_A : block
signal D0,D1,D2 : STD_LOGIC ;
begin
process (clk_500n )
begin
if clk_500n'event and clk_500n = '1' then
D2 <= D1; D1 <= D0; D0 <= PA;
PHA <= (D0 and D1 and D2) or ((D0 or D1 or D2) and PHA);
end if;
end process;
end block FILTER_A;
14
FILTER_B : block
signal D0,D1,D2 : STD_LOGIC ;
begin
process (clk_500n )
begin
if clk_500n'event and clk_500n = '1' then
D2 <= D1; D1 <= D0; D0 <= PB;
PHB <= (D0 and D1 and D2) or ((D0 or D1 or D2) and PHB);
end if;
end process;
end block FILTER_B;
FILTER_Z : block
signal D0,D1,D2 : STD_LOGIC ;
begin
process (clk_500n )
begin
if clk_500n'event and clk_500n = '1' then
D2 <= D1; D1 <= D0; D0 <= PZ;
PHZ <= (D0 and D1 and D2) or ((D0 or D1 or D2) and PHZ);
end if;
end process;
end block FILTER_Z;
15
DECODER : block
signal DLA,DLB : STD_LOGIC ;
begin
process (clk_500n )
begin
if clk_500n'event and clk_500n='1' then
DLA<=PHA; DLB<=PHB;
end if ;
end process;
DIR <= (not PHA and DLA and not PHB) or (PHA and not DLA and PHB)
or (not PHB and DLB and PHA) or (PHB and not DLB and not PHA) ;
PLS <= (not PHA and DLA ) or (PHA and not DLA) or (not PHB and DLB ) or (PHB and not DLB) ;
end block DECODER;
COUNTER : block
signal EC : STD_LOGIC ;
begin
process (clk_500n )
begin
if clk_500n'event and clk_500n = '1' and seveo_on ='1' then
if EC = '1' then
if DIR = '1' then
CNT <= CNT - 1 ;
if CNT=X"0000" then
CNT<= X"270F"; -- X”270F” = 9999 (encoder: 2500 P/r X4=10000P)
end if;
else
CNT <= CNT + 1 ;
if CNT=X"270F" then
CNT<= X"0000";
end if;
end if;
end if;
end if;
end process;
EC <= PLS ;QEP_OUT <= x"0000" & CNT; end block COUNTER;
16
ADDR_GEN : block
signal EC : STD_LOGIC;
begin
process (clk_500n ,PHZ)
begin
if clk_500n'event and clk_500n = '1' then
if EC = '1' then
if DIR = '1' then
ADDR <= ADDR - 1 ;
if PHZ='1' then
ADDR<=X"09C3"; -- 2499
else
if ADDR = X"0000" then
ADDR <= X"09C3";
else
ADDR <= ADDR - 1 ;
end if;
end if;
else
E p  2500 pulse
P8
if PHZ='1' then
ADDR<=X"0000";
else
if ADDR = X"09C3" then -- 2499
ADDR <= X"0000";
else
ADDR <= ADDR + 1;
end if;
end if;
end if;
end if;
end if;
end process;
EC<=PLS;
Address <= ADDR(11 downto 2) when ADDR(11 downto 2)
>= "0000000000" else ("1001110001" - ADDR(11 downto 2) );
end block ADDR_GEN;
end QEP_ARCH;
K 4
sin & cos table: 625筆資料
17
1.2.3 ADC circuit – AD574
Unipolar Input Connections
1.在AD574晶片內有兩組控制接腳，通用控制接
腳(CE、CS 和R/C )和內部暫存器控制接腳(A0
和12/ 8 )。
2. AD574兩個主要控制功能，轉換開始和讀取致
能是由CE、CS 和R/C來控制。
當CE=1，CS =0，R/C =0時，轉換開始;
當CE=1，CS =0，R/C =1時，允許讀取資料。
對於一些系統，可以 CE接高電位，CS接低電位，
而R/C根據需要進行控制。
3. 轉換時間：15~35s
18
ADC Interface circuit in FPGA
R/C
AD574
轉態控制訊號
to AD 574
R/C
產生電路
DO_A[11..0]
ADI[11..0]
from AD 574
Unsigned
to
signed
19
VHDL code of ADC
20
-- Convert Start
-- ADC data output
-- Read ADC data
-- Continuous conversion
-- 62.5us (16kHz)
21
1.2.4 Implementation of the CCCT
circuit
1.2.4.1 using parallel processing method
1.2.4.2 using FSM method
22
1.2.4.1 FPGA-based control IC (CCCT circuit
design using parallel processing method)
A[22]
Nios II Embedded Processor IP
A[0]
D[31]
sram_be[3]
sram_be[2]
sram_be[1]
sram_be[0]
sram_oe
sram_we
sram_cs
On-chip
ROM
On-chip
RAM
Avalon Bus
Avalon Bus
D[0]
Altera FPGA
UART
CPU
iq* [11..0]
PIO
 p [15..0]
Timer
SPI
Application IP
Clk
Clk-ctr
Clk-sp
Frequency
divider
CK
ADIN[11]
Clk
Clk-ctr
ADC read in
Clk
Clk-ctr
Clk-sp
iq* [11..0]
clk
A-pulse
B-pulse
Z-pulse
 p [15..0]
QEP detection
and
 e _ addr [11..0]
transformation
ia [11..0]
and
ib [11..0] transformation
Current controllers ic [11..0]
and coordinate
Clk
transformation
Clk-sp
vref 1 [11..0]
(CCCT)
vref 2 [11..0]
vref 3 [11..0]
CCCT circuit design using
parallel processing method
ADIN[0]
BDIN[11]
SVPWM
generation
BDIN[0]
CHA
CHB
RCA
RCB
STSA
STSB
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
23
CCCT circuit
PWM1
 Clark-1 transformation
SVPWM
CCCT
 Clark transformation
a,b,c
Modified
1
,

Clarke
 Park-1 transformation
i
*
q
 Park transformation
 Look-up table for sin/cos
function
 PI controller
Park 1 d,q
+
-
i 0
*
d
+
PI
A, B , Z
PWM6
Te
QEP Circuit
A/D read
a,b,c
Clarke
, 
i
p
i
, 
d,q
,  Park
iq
id
Sin &Cos
θe P
PI
-
2
24
Clark -1 transformation


va   1
 v    1
 b  2
 v c   1

 2
3/2
8位元Q7
10位元Q9
12位元Q11
近似值
0.859375
0.864289314
0.866210937
誤差率
0.78%
0.2004%
0.0214%

0 
3   v 
 
2  v  
3


2 
V
Va
2‘S COMPLEMENT
1/2
1/2
1/4
1/16
V
1/32
3
 scaling ( Q11 )  0 1101110110 1
2
3 1 1 1 1 1
1
1
1
     


2
2 4 16 32 64 256 512 2048
 0.866210937
1/64
1/256
Vb
ADDER
ADDER
ADDER
2‘S COMPLEMENT
1/512
1/2048
25
Vc
Clark transformation
 I  1
 I   0
   
1/ 3
8位元Q7
近似值
0.5703125
誤差率
1.2189%
0
1
3
0  Ia 
1  I b 

 

3   I c 
12位元Q11
0.576171875 0.577148437
0.2041%
0.0214%
Ia
I
1/2
Ib
1/16
1/128
ADDER
1/256
1
 scaling(Q11)  010010011110
3
1
1 1 1
1
1
1
  



3 2 16 128 256 512 1024
 0.577148437
10位元Q9
Ic
1/512
1/1024
I
ADDER
1/2
1/16
1/128
1/256
ADDER
2‘S COMPLEMENT
1/512
1/1024
26
Park and Park -1 transformation
v  cose  sine vd 
v   
 v 
sin
cos


e
e  q 
  
id   cose sine  i 
i   
 i 
sin

cos


e
e   
 q 
Park-1
Park
cos  e
vd
 sin  e
vq
sin  e
vd
cos  e
vq
12 bits
multiplier
cos  e
12 bits
adder
v
sin  e
12 bits
multiplier
i
 sin  e
12 bits
multiplier
12 bits
multiplier
i
12 bits
adder
v
i
cos  e
i
12 bits
multiplier
12 bits
adder
id
12 bits
adder
iq
12 bits
multiplier
12 bits
multiplier
12 bits
multiplier
27
Implementation of PI controller
• Analog PI controller
K P：Proportional gain
K I ：Integral gain
K
G(s)  K P  I
S
•Digital PI controller
Gc ( z )  K P 
zK I
z 1
(Using Bilinear transformation)
U p ( k )  K p e( k )
U I (k )  U I (k  1)  K I e(k  1)
U (k )  U P (k )  U I (k )
PI Controller
CK
Ki
D-FF
Adder
CK
Kp
Limiter
Ui(k)
Multi
D-FF
CMD
FBK
Ui(k-1)
e(k-1)
e(k)
Sub
(Q11)
Limiter
Multi
Up(k) (Q11)
Adder
+/saturate
U(k)
28
CCCT circuit design using
parallel processing method
q-axis PI controller
12
12
D-FF
ck_ctr
ki_q
i*q
12
D-FF
12
iq 12
+
adder
kp_q
+
12
adder
12
+
12 multiplier
e(k-1)
12
e(k)
12
multiplier
12
12
+
adder
+
12
ki_d
id
12
12
D-FF
+
adder
kp_d
 e _ addr
vd
12
sin  e
12
D-FF
ck_ctr
12
vq
12
cos  e
d-axis PI controller
i*d  0
Park-1
12
+
12
adder
12
12
+
12 multiplier
vd
12
cos  e
12
vq
12
cos  e
12
vd
12
multiplier
v
12
12
1/2
12
+
12
1/16
v
12
12
1/32
12
1/64
12
12
1/256
12
+
1/512
1/2048
12
vref 1
2’S
Complement
12
12
adder
multiplier
1/2
1/4
multiplier
12
12
12
12
vq
12
+
multiplier
 sin  e
12
+
adder
12
Modified Clark-1
+
12
+
12
+
+
12
adder
+
+
adder
+
12
+
2’S
adder 12 Complement
+
vref 2
12
vref 3
+
+
+
12
12
12
12
multiplier
12
12
e(k-1)
e(k)
12
sin  e
LUT
for
sin and cos
12
Park
+
adder
+
12
cos  e
12
sin  e
12
id
+
+
12
adder
+
i
12
12
multiplier
12
12
cos  e
12
cos  e
12
sin  e
multiplier
12
 sin  e
12
i
multiplier
12
cos  e
i
adder
+
i
12
12
12
sin  e
adder
+
12
adder
+
iq
multiplier
12
Clark
+
+
+
+
+
12
i
12
2’S
Complement
12
adder
+
+
+
+
1/2
1/16
12
12
12
12
+
+
+
i
12
12
12
1/128
12
ib
12
ic
1/256
1/512
1/1024
1/2
1/16
12
12
12
12
1/128
1/256
1/512
1/1024
12
ia
29
Nios II processor and current
vector control IP in Quartus II
Nios II Processor
Current vector
control IP
(Command generation)
30
Current vector control IP
Current Command
from Nios processor
Current controller
DSPA[11..0]
IQ[11..0]
SAMPLE
sel
SEL1
SEL1
A/D Signal
STSA
STSB
ADIN[11..0]
BDIN[11..0]
KI[11..0]
VCC
ID[11..0]
CK1
SAMPLE
ID[11..0]
IDD[11..0]
KP[11..0]
PI
Controller
SAMPLE
SAMPLE
ADC
VCC
VCC
VCC
VCC
OT_U[11..0]
OT_W[11..0]
Control
CHA
CHB
RCA
RCB
sel
SEL1
KI[11..0]
SAMPLE
SCAN[1..0]
CLK
SYSCTRL
SPCLK
ID[11..0]
KP[11..0]
KI[11..0]
CK1
SAMPLE
IQC[11..0]
IQQ[11..0]
KP[11..0]
PI
Controller
IDC[11..0]
CK1
INT
CLK
SAMPLE
CLK
VM[11..0]
VA[11..0]
VM[11..0]
CLK
SAMPLE
CLK
SAMPLE
VAA[11..0]
VBB[11..0]
INV PARK
INV CLARK
SVPWM
PWM[6..1]
PWM 1~6
VC[11..0]
SIN/COS
Encoder SAMPLE
SPCLK
Signal ID[11..4]
VCC
QEP
EN_A
EN_B
EN_Z
HALL[3..1]
SEL2
ADB[15..0]
SCN[3..0]
SEG[7..0]
Display
SCAN[1..0]
sel
SAMPLE
VC[11..0]
OT_W[11..0]
RE
SPD[11..0]
12
CLK
12
LED[11..0]
IQQ[11..0]
IDD[11..0]
CLK
QEP[11..0]
Encoder Position
to Nios Processor
SAMPLE
PARK
IAA[11..0]
IBB[11..0]
SAMPLE
CLK
CLK
CLARK
sel
SAMPLE
VA[11..0]
OT_U[11..0]
Digital
Current
Signal
31
Utility evaluation of speed control IC
using parallel processing method
IP
Module Circuit
Sub-module
Circuit
3,440
679x2=
1,338
945
49,920
0
Modified Clark-1
222
0
Clark
209
0
Park
945
0
LUT of Sin&Cos
0
24,576
3,659
24,576
SVPWM generation
1,221
0
ADC read in and transformation
136
0
QEP detection and transformation
114
0
8,570
74,496
Nios II Embedded Processor IP
PI Controller x 2
Park-1
Part of
Logic Memory
Element
(bits)
Current controllers
and coordination
transformation (CCCT)
Application IP
Sub-total
Total
0
32
1.2.4.2 FPGA-based control IC (CCCT
circuit design using FSM method)
A[22]
Nios II Embedded Processor IP
A[0]
D[31]
sram_be[3]
sram_be[2]
sram_be[1]
sram_be[0]
sram_oe
sram_we
sram_cs
On-chip
ROM
On-chip
RAM
Avalon Bus
Avalon Bus
D[0]
Altera FPGA
UART
CPU
iq* [11..0]
PIO
 p [15..0]
Timer
Application IP
Clk
Clk-ctr
SPI
Clk-sp
Frequency
divider
CK
ADIN[11]
Clk
Clk-ctr
ADC read in
Clk
Clk-ctr
Clk-sp
iq* [11..0]
clk
A-pulse
B-pulse
Z-pulse
 p [15..0]
QEP detection
and
 e _ addr [11..0]
transformation
ia [11..0]
and
ib [11..0] transformation
Current controllers ic [11..0]
and coordinate
Clk
transformation
Clk-sp
vref 1 [11..0]
(CCCT)
vref 2 [11..0]
vref 3 [11..0]
CCCT circuit design using
FSM method
ADIN[0]
BDIN[11]
SVPWM
generation
BDIN[0]
CHA
CHB
RCA
RCB
STSA
STSB
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
33
Implementation of sum-of-product
computation
Example: Y  a1 * x1  a2 * x2  a3 * x3
 Parallel processing:
a1

three multipliers
and
two adders

x
x1
a2
x2
a3
x3
+
x
+
y
One clock
execute time
x
Sequential processing using Finite State Machine (FSM):
x1
a1
one multiplier
and
one adder
x
+
a2
x
x2
s1
s2
x3
a3
y
Five clock
execute time
+
x
s3
s4
s5
34
Nios II processor and current
vector control IP in Quartus II
Current command
Current vector
control IP
Nios Processor
(Current command)
Measured Current
35
Current vector control IP
(CCCT using FSM)
CLK generation
Encoder
Signal
QEP
Measured current
to Nios Processor
Current Command
from Nios processor
CCCT
Angle
compensation
SVPWM PWM 1~6
MUX
A/D Signal
ADC
control
SVPWM inputs
at initial
36
Designed CCCT circuit by using FSM method
 e _ addr
LUT
sin  e
cos  e
id*  0 + +
id
e_d
vref 1
-
x
kp_d
+
vd
vd
+
x
e_d
i_d
+
iq*
iq
LS,1
3
vd
x
ki_d
v
+
x
2
x
e_q
i_d
-
+ +
vq
-
kp_q
x
+
vq
++
- +
-
vref 3
vref 2
v
x
x
x
ki_q
e_q
i_q
x
+
-
i_q
ia
i 1
ib
 1
ic
s0
s1 s2 s3 s4 s5 s6
Look up d-axis PI
Sin/Cos controller
Table
s7 s8
q-axis PI
controller
s9
s10
Park-1
x
i
3
x
x
+
iq
3
x
+
x
+
id
s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23
Modified
Clark-1
Clark
Park
37
Utility evaluation of speed control IC
using FSM method
IP
Module Circuit
Nios II Embedded Processor IP
Part of
Application IP
Logic Memory
Element
(bits)
3,440
49,920
Current controllers and
coordination transformation (CCCT)
864
24,576
SVPWM generation
1,221
0
ADC read in and transformation
136
0
QEP detection and transformation
114
0
5,775
74,496
Total
38
1.3 Response of current vector
control
Current loop
Current
controller
i
*
q
current (A)
iq command
iq response
id*  0
PI
Park-1
v
d,q
—
+
1.0
vq
PI
+
1.5
DC
Power
vd
, 
v
vref 1
vref 2
SVPWM
a,b,c vref 3
, 
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Inverter
—
0.5
iq
id response
id command
id
0
d,q
, 
i
i
Park
-0.5
0
modify
Clark-1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (s)
sin  e / cos e
ia
ib
, 
a,b,c
ic
iu
A/D
converter
iv
LPF
LPF
Clark
e
sin /cos of
Flux angle
QEP
circuit
A
B
Z
PMSM
Encoder
current (A)
1.5
ia
1.0
ib
ic
1.5
0.5
1.0
0
-0.5
0.5
-1.0
-1.5
0
i ( A) 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (s)
-0.5
-1.0
-1.5
-1.5
-1.0
-0.5
0
i ( A)
0.5
1.0
1.5
39
2. Speed control of PMSM drive
2.1 Introduction to architecture of a fully
digital speed controller of PMSM drive
2.2 The block diagram of adaptive fuzzy
control for PMSM drive system
2.3 FPGA-realization of adaptive fuzzy
control IC for PMSM drive
40
2.1 Architecture of a Speed
Control System of PMSM

*
r
Speed loop
Speed
controller
+
Current
controller
i
*
q
PI
+
—
id*  0
vq
v
d,q
—
vd
PI
+
Park-1
, 
v
Current loop
modify
Clark v ref 1
, 
vref 2
SVPWM
v
a,b,c ref 3
DC
Power
-1
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Inverter
—
iq
id
d,q
, 
Park
sin  e / cos e
r
1-Z-1
Complexity computation
But low computation bandwidth
Sampling frequency (100Hz~2kHz)
sin /cos of
Flux angle
i
i
, 
a,b,c
ia
ib
ic
iu
A/D
convert
iv
Clark
e
r
QEP
A
B
Z
PMSM
Encoder
Fix and simple computation
But high computation bandwidth
Sampling frequency (8~16kHz)
PWM (~10MHz)
41
Speed controller
 PI controller
 Fuzzy controller
 Adaptive fuzzy controller
42
Controller design of PMSM drive
 Vector control is used to the current loop of
PMSM drive to let the motor drive reach the
linearity and decouple characteristics.
 Adaptive fuzzy control is adopted to the
speed loop of PMSM drive for coping with the
model uncertainty and load disturbance.
43
2.2 The block diagram of adaptive fuzzy
control for PMSM drive system
PMSM
Adaptive Fuzzy Controller
r*
Reference
Model
m +
e
e FI
_
1 Z
r
1
Inference
Mechanism
DFI
uf
Ki
1 Z 1
*
u I + iq
+
Kt
1
J m s  Bm
r
KP
Knowledge
Base
Adjust
Mechanism
em
m
+
_
r
Adaptive fuzzy controller includes :
1. Fuzzy controller
2. Adjust mechanism (adaptation law)
3. Reference model
44
Fuzzy controller (1/3)
1. Define e、e as input variable of fuzzy controller, with
e( k )  r* ( k )  m ( k )
e(k)  e(k)  e(k  1)
2. Define linguist value with { E, DE,U }. They are symmetrical triangular
membership function :
(e)
1
(e)
A0
A1
A2
A4
A3
A5
A6
1
Ai+1
Ai
 Ai 1 (e)
e
-6
-4
-2
0
(de)
1
B0
B1
B2
B3
e
2
4
 Ai (e)
6
ei = -6+2*i ei+1 = -4+2*i
B4
B5
If e is located between the ei and ei 1
then
e  e  4  2 *i  e
 Ai (e)  i 1

B6
2
de
-6
-4
-2
de
0
e
e
2
4
6
2
 Ai 1 (e)  1   Ai (e)
45
Fuzzy controller (3/3)
4. Construct the fuzzy system with u f e,de from those M rules using the singleton fuzzifier,
product-inference rule, and center average defuzzifier method.
i 1 j 1
i 1 j  1
  cm,n [ An (e) *  Bm (de)]
n i m  j
u f (e, de) 
i 1 j 1
   A (e) *  B (de)
n i m  j
n
  c m,n * d n,m
n i m  j

i  1 j 1
  d n ,m
m
A0
A1
A2
A4
A3
A5
A6
Fuzzy Inference and Output
e
A3
6
A4
A5
A6
c00 c01 c02 c03
c04 c05 c06
B1
c10 c11 c12 c13
c14 c15 c16
B2
c20 c21 c22 c23
c24 c25 c26
B3
c30 c31 c32 c33
c34 c35 c36
B4
c40 c41 c42 c43
c44 c45 c46
B5
c50 c51 c52
c53
c54 c55 c56
B6
c60 c61 c62 c63
c64 c65 c66
Fuzzy Rule Table
de
-6
A2
4
-4
A1
2
0
E A
0
dE
e
2
0
4
-2
6
-4
de
-6
B0
-2
n i m  j
Input of e (for i=3)
A3(e)
B1(de)
1
B2(de)=1- B1(de)
B0
B1
B2
B3
B4
B5
B6
Input of de (for j=1)
(de)
1
A4(e)=1- A3(e)
   c m,n * d n ,m
n i m  j
 c1 , c2 ,.., cM are adjustable parameters.
(e)
i 1 j 1
Rule 1: e is A3 and de is B1 then uf is c13
Rule 2: e is A3 and de is B2 then uf is c23
Rule 3: e is A4 and de is B1 then uf is c14
Rule 4: e is A4 and de is B2 then uf is c24
Defuzzification
uf 
c13 * d 31  c23 * d 32  c14 * d 41  c24 * d 42
d 31  d 32  d 41  d 42
 c13 * d 31  c23 * d 32  c14 * d 41  c24 * d 42
where
d31 =A3(e)*B1(de)
d32 =A3(e)*B2(de)=A3(e)*(1-B1(de))
d41 =A4(e)*B1(de) =(1-A3(e))*B1(de)
d42 = A4(e)*B2(de)=(1-A3(e))*(1-B1(de))
and
d31 +d32+d41+d42=1
46
2.3 FPGA-realization of adaptive fuzzy
control IC for PMSM drive
FPGA-based adaptive speed control IC
Current loop using vector controller
Speed loop designed by AFC
*r Reference m +
Model
K pw
e
de FI
_
r
1 Z
1
Inference
Mechanism
DFI
up
K iw

u f 1 Z
ui
1


i d* = 0
r
iq*

PI
vq
PI

id
Knowledge
Base
iq
r
Adjusting
Mechanism
m +
e
_
vd
Sin&Cos
e
Park 1
, 
d, q
d,q
, 
d, q
d,q
Park
v
Modified
Clarke1
vrx
a, b, c v
ry
v
iα
iβ
, 
a, b, c
, 

r
SVPWM
vrz
1  Z 1
Sampling frequency of Speed loop:2kHz

PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
ia
ib Current
detector
ic

U
3-Phase
inverter
W
A/D
LPF
A/D
LPF
V
PMSM
iu
Encoder
iw
Clarke






A , A ,B
Encoder
detection &
Transform.
r
ac source
Rectifier
A
B
Z
Comparator
B ,Z ,Z
Circuit
p
Sampling frequency of current loop: 16kHz
PMW: 4~8MHz
47
Realization method of adaptive
speed control IC based on FPGA

Two methods for the realization of adaptive speed
control IC based on FPGA
-- Current vector controller using digital hard
implementation in FPGA
-- Adaptive fuzzy controller using
1. Software implementation by Nios II Processor
2. Digital hard implementation in FPGA
48
Method 1: Nios-based adaptive
speed control IC
Rectifier
Inverter
L

TA


TB
TC
ac source
U,V,W
C

TA


Load
TC
TB
encoder
PMSM
Isolated and driving circuits
RS232 or
USB
PWM1
PC
LP filter
circuit
PWM6
ia
ADC
ib
Digital circuit (PLD)
of current vector
controller for PMSM
ADC
A, A
B, B
A, B
External
memory
z
Embedded Processor IP
(Nios II Processor)
Comparator
circuit
z, z
Application IP
FPGA-based speed control IC
49
Software implementation of adaptive
fuzzy controller by Nios processor
A[22]
Nios II Embedded Processor IP
A[0]
D[31]
UART
D[0]
sram_be[3]
sram_be[2]
sram_be[1]
sram_be[0]
sram_oe
sram_we
sram_cs
On-chip
ROM
On-chip
RAM
Avalon Bus
Avalon Bus
CPU
ia [11..0]
ib [11..0]
ic [11..0]
PIO
iq* [11..0]
Timer
Current control IP
 p [15..0]
Clk
Clk-ctr
SPI
Clk-sp
Frequency
divider
CK
ADIN[11]
Clk
Nios II processor is
Used for command
generation, AFC
calculation and
receive feedback
data
Clk-ctr
Clk-ctr
ia [11..0]
Clk-sp
iq* [11..0]
clk
A-pulse
B-pulse
Z-pulse
ADC read in
Clk
 p [15..0]
QEP detection
and
 e _ addr [11..0]
transformation
and
ib [11..0] transformation
Current controllers
and coordinate
transformation
(CCCT)
ic [11..0]
Clk
Clk-sp
v rx [11..0]
SVPWM
v ry [11..0]
generation
v rz [11..0]
ADIN[0]
BDIN[11]
BDIN[0]
CHA
CHB
RCA
RCB
STSA
STSB
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
50
Main and ISR program in Nios II
processor
Start of
main program
Initial interrupt
Initial timer
Initial all
peripherals
Setting of
speed command
loop
Start of ISR
( each 2kHz )
Read QEP from
application IP and
calculate speed value
of PMSM
Calculation of
speed error and
the change of error
Calculation of output
of fuzzy controller
Calculation of q-axis
current command and
send to application IP
Calculation of error
between speed of
rotor and output of
reference model
Parameters adjusting
of fuzzy controller
End
Note that: execution time of ISR in CPU is 120s
51
Method 2: All hardware implementation
of adaptive speed control IC
Rectifier
Inverter
L

TA


TB
TC
ac source
U,V,W
C

TA


Load
TC
TB
encoder
PMSM
Isolated and driving circuits
RS232 or
USB
PWM1
LP filter
circuit
PWM6
PC
ia
ADC
Digital circuit (PLD) of
adaptive speed control
and current vector
control for PMSM
External
memory
ib
ADC
A, A
z
Embedded Processor IP
(Nios II Processor)
B, B
A, B
Comparator
circuit
z, z
Application IP
FPGA-based speed control IC
52
Hardware implementation of
adaptive speed controller
A[22]
ia [11..0]
Nios II Embedded Processor IP
A[0]
D[31]
sram_be[3]
sram_be[2]
sram_be[1]
sram_be[0]
sram_oe
sram_we
sram_cs
On-chip
ROM
On-chip
RAM
Avalon Bus
Avalon Bus
D[0]
ib [11..0]
UART
CPU
ic [11..0]
PIO
iq* [11..0]
Speed control IP
 r [11..0]
Timer
 r* [11..0]
SPI
Clk
Clk-cur
Clk-sp
Clk-step
Frequency
divider
CK
ADIN[11]
Clk
Nios processor is
used for command
generation and
receive feedback
data
Clk
ADIN[0]
Clk-step
 r* [11..0]
 p [15..0]
Adaptive fuzzy
controller
(AFC)
Clk
QEP detection
and
transformation
ia [11..0]
Clk-cur
 e _ addr [11..0]
Current controllers
and coordinate
transformation
(CCCT)
BDIN[11]
and
ib [11..0] transformation
iq* [11..0]
 p [15..0]
clk
A-pulse
B-pulse
Z-pulse
ADC read in
Clk-sp
ic [11..0]
Clk
BDIN[0]
CHA
CHB
RCA
RCB
STSA
STSB
Clk-step
Clk-cur
v rx [11..0]
SVPWM
v ry [11..0]
generation
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
v rz [11..0]
53
Modeling of AFC by FSM (1/3)
 r* ( k )
a0
+
x
a1
 m ( k  2)
b1
b2
x
+
 r* ( k  2)
a2
s2
-
x
x
 r* ( k  1)
s1
 m ( k  1)
 m (k )
+
+
 m ( k  1)
 m ( k  2)
 r* ( k  1)
 r* ( k  2)
 m ( k  1)
 r* ( k )
 r* ( k  1)
-
+
 r (k )
e(k ) -
+
de(k )
e( k  1)
 p ( k  1)
x
s3
 m (k )
e( k  1)
 p (k ) -
s4
s5
Computation of reference model output
s6
+
s7
 r (k )
 p ( k  1)
s8
s9
s10
Computation of speed, speed error
and error change
54
Modeling of AFC by FSM (2/3)
i
e(k )
SD
ei  1
ek
-
+
j
 Ai (e )
RS,1
 B j (de )
SD
dek
s11
 B j (de )
de j  1
+
RS,1
s12
s13
-
c j ,i
c j ,i  1
c j  1,i
c j  1, i  1
Look-up
Fuzzy rule
table
 Ai (e )
de(k )
s10
&
j&i
Fuzzification
 B j (de ) -
di, j
x
1
-
+
 B j  1 (de )
x
d i , j1
 B j (de )
 Ai  1 (e )
d i  1, j
x
+
s14
 Ai (e )
1
s15
s16
x
s17
d i  1, j  1
s18
Look-up fuzzy table and defuzzification
SD: Section determination (Detailed design in the
following next two page)
RS,1: Right shifter with one bit
55
Modeling of AFC by FSM (3/3)
c j ,i
di, j
K iw
x
+
c j  1,i
d i , j 1
+
+
x
+
ui
r
x
c j  1, i  1
s20
s21
Defuzzification
K iw
x
s22
α
+
x
x
s25
s26
+
c j ,i
r
r
r
s27
s28
c j  1, i  1
c j  1, i  1
+
c j  1,i
d i , j 1
x
c i  1, j
d i  1, j  1
x
+
e(k )
s24
+
x
x
*
K pw
s23
c j ,i
di, j
iq
d i  1, j  1
s19
x
c j ,i  1
x
c i  1, j
d i  1, j
K pw
d i  1, j
s18
uf
r
ui
+
s29
c j  1,i
s30
s31
s32
Computation of current command and tuning of fuzzy rule parameters
Note that: the execution time of AFC is 40nsx32=1.28s
56
Nios II processor and speed
control IP in Quartus II
Speed control
IP
Nios II Processor
(Speed command)
Speed
Command
Measured
speed
57
Speed control IP
CLK generation
Speed Command
from Nios
processor
MUX
Measured speed to
Nios processor
CCCT
PWM 1~6
Angle
compensation
SVPWM
Speed
controller
MUX
(AFC)
Encoder
Signal
Encoder Position
A/D Signal
QEP
SVPWM inputs
at initial
ADC
control
58
The FPGA utility evaluation of the
proposed adaptive speed control IC
IP
Module circuit
3,440
49,920
Adaptive fuzzy controller (AFC)
Current controllers and
coordination transformation (CCCT)
4,085
0
864
24,576
SVPWM generation
1,221
0
ADC read in and transformation
136
0
QEP detection and transformation
114
0
12,655
74,496
Nios II Embedded Processor IP
Part of
Speed control IP
Logic Elements Memory
(LEs)
(bits)
Total
59
3. Experimental system and results
Two system are demonstrated the effectiveness of
the proposed system
1. PMSM drive system with 2,200W in our Lab.
Experiments are shown as follows:
 Speed step response
 Speed frequency response
 Effect by step external load
2. TECO PMSM drive system with 750W
 Demonstration

60
Experimental results of speed step
response (without adaptation)
1400
Speed (rpm)
1300
Without adaptation (learning rate=0)
Load torque : 1.5N*m
1200
1000
1000
800
Speed command
600
Output of reference model
Measured rotor speed
500
400
200
200
Control effort (A)
0
0
1
2
3
4
5
6
Time (s)
0
1
2
3
4
5
6
Time (s)
15
10
5
0
-5
(a)
61
Experimental results of speed
step response (with adaptation)
1400
With adaptation (learning rate=0.05)
Load torque : 1.5N*m
Speed (rpm)
1200
1000
1300
1000
800
Speed command
600
400
Output of reference model
Measured rotor speed
500
200
200
Control effort (A)
0
0
1
2
3
4
5
6
Time (s)
0
1
2
3
4
5
6
Time (s)
15
10
5
0
-5
(b)
62
Experimental results of speed
step response (with adaptation)
1400
Speed (rpm)
1200
1300
With adaptation (learning rate=0.15)
Load torque : 1.5N*m
1000
1000
800
Speed command
600
Output of reference model
Measured rotor speed
500
400
200
200
Control effort (A)
0
15
0
1
2
3
0
1
2
3
4
5
6
Time (s)
4
5
6
Time (s)
10
5
0
-5
(C)
63
Parameters adaptation of fuzzy
rule table and output surface
Without adaptation (learning rate=0)
Load torque : 1.5N*m
With adaptation (learning rate=0.15)
Load torque : 1.5N*m
64
Experimental results of frequency
response (with and without adaptation)
1400
Without adaptation (learning rate=0)
Load torque : 1.5 N*m
Speed (rpm)
1200
1000
3Hz Sinusoid (1000~1300rpm)
800
2Hz Sinusoid (200~500rpm)
600
400
Speed command
Measured rotor speed
200
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
1400
With adaptation (learning rate=0.15)
Load torque : 1.5 N*m
Speed (rpm)
1200
1000
3Hz Sinusoid (1000~1300rpm)
800
2Hz Sinusoid (200~500rpm)
600
400
Speed command
Measured rotor speed
200
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Time (s)
65
Parameters adaptation of fuzzy
rule table and output surface
Without adaptation (learning rate=0)
Load torque : 1.5N*m
With adaptation (learning rate=0.15)
Load torque : 1.5N*m
66
Load torque (N*m)
Effect of step external load
2.0
1.5
1.5 N*m
0.2 N*m
0
0
1
2
1200
Speed (rpm)
Start of adaptation
(learning rate=0.15)
Without adaptation
Without adaptation
1100
3
(a)
4
5
6
Time (s)
Start of adaptation
(learning rate=0.15)
1080 rpm
1032 rpm
1015 rpm
1000
0
1
972 rpm
952 rpm
940 rpm
900
2
3
(b)
4
5
6
Time (s)
67
FPGA-based PMSM drive system
(Project cooperated with TECO)
FPGA Chip
PMSM
68
FPGA-based PMSM drive system
(Project cooperated with TECO)
TECO PMSM
(750W)
Loader
FPGA Development Board
69
Demonstration of TECO motor system
300rpm
600rpm
900rpm
1200rpm
900rpm
600rpm
70
4. Conclusions

The functionalities required to build a fully digital adaptive servo
system for PMSM drive, such as the AFC, the current vector scheme,
SVPWM generation, coordinate transformation and QEP detection
etc., have been integrated in single FPGA chip.

Compared with DSP, using FPGA in the PMSM control architecture
has two benefits, which are described as follows.
(1) Current controller and speed controller implemented by software or
hardware can all be programmable design. Therefore, the flexibility of
designing a specified function of PMSM drive is greatly increased.
(2) Parallel processing of current loop vector controller and speed loop
adaptive controller makes the dynamic performance of the PMSM
drive improvable.
71