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Reconfigurable DC-DC Converter for Off-Grid Power Management
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Chapter 1 A Reconfigurable Bidirectional DC-DCConverter with Active Battery Charge Equalization for Power Management of Off-Grid Residential Complexes Submitted in partial fulfillment of the requirements of the degree of Master of Technology in Power Electronics and Drives by Siddhartha Suyal (202231008) Under the supervision of: Dr. Anmol Ratna Saxena (Assistant Professor) Department of Electrical and Electronics Engineering NATIONAL INSTITUTE OF TECHNOLOGY DELHI MAY 2022 Approval Sheet This dissertation entitled “A Reconfigurable Bi-directional DC-DC Converter with Active Battery Charge Equalization for Power Management of Off-Grid Residential Complexes” by Mr. Siddhartha Suyal, Roll No. 202231008, is approved for the degree of Master of Technology. Examiners Supervisor Dr. Anmol Ratna Saxena, Assistant Professor Department of Electrical and Electronics Engineering National Institute of Technology, Delhi Chairman Date: Place: Declaration I declare that this written submission represents my ideas in my own words and where others' ideas or words have been included, I have adequately cited and referenced the originalsources. I also declare that I have adhered to all principles of academic honesty and integrity and have not misrepresented or fabricated or falsified any idea/data/fact/source in my submission. I understand that any violation of the above will be cause for disciplinary action by the Institute and can also evoke penal action from the sources which have thus not been properly cited or from whom proper permission has not been taken when needed. SIDDHARTHA SUYAL Roll No: 202231008 Date: 26/05/2022 ii Certificate This is to certify that the dissertation work entitled “A Reconfigurable Bi-directional DC-DC Converter with Active Battery Charge Equalization for Power Management of Off-Grid Residential Complexes” submitted by Mr. Siddhartha Suyal, Roll No. 202231008, in partial fulfillment of the requirements for the award of the degree of Master of Technology in Power Electronics and Drives to the faculty of the Department of Electrical and Electronics Engineering, National Institute of Technology, Delhi is a bonafide record of the work carried out by him under the supervision of Dr. Anmol Ratna Saxena during the academic year 2021-2022. This work has not been submitted to any other institute for the award of degree or diploma. Submitted by: Siddhartha Suyal (202231008) ………………………………………………………………………………………………………… The M.Tech Viva-Voce Examination of Mr. Siddhartha Suyal has been held on 26/05/2022. Supervisor Dr. Anmol Ratna Saxena DPGC Convener iii Head of Department Acknowledgements I owe my deepest gratitude towards my supervisor, Dr. Anmol Ratna Saxena, Assistant Professor, Dept. of Electrical and Electronics Engineering, NIT Delhi, for his constant guidance, invaluable insight, encouragement, and support without which this project would not have been possible. I would also like to thank Ms. Ashima Kulshreshtha, and Mr. Deepak Kumar, Research Scholars in the Dept. of Electrical and Electronics Engineering, NIT Delhi for their support and co-operation and help during the course of the project. I would also like to express my gratitude towards PhD scholars Mr. Nitish Kumar, Mr. Rajvardhan Jigyasu, Mr. Shubham Singh, Mr. Nitesh Singh and Mrs. Surbhi Aggarwal, Dept. of Electrical and Electronics Engineering for their support and assistance. I acknowledge the kind assistance and thank my classmates. Finally, I would like to thank my parents who have given me unfailing support and love throughout, keeping me motivated and to whom I have dedicated this thesis. SIDDHARTHA SUYAL Roll No: 202231008 Date: 26/05/2022 iv Abstract With the depletion of fossil fuels and the increasing adverse impact of global warming, researchers and policymakers have been searching cleaner energy extraction processes. As a result, Renewable Energy Sources (RESs) like solar energy, wind energy etc. have been on rise. However a fundamental challenge of using RESs is their intermittent nature, making it necessary to integrate a Energy Storage Devices (ESDs) like Battery, Ultra-capacitors etc. for power backup and reliability. Here the power electronic converters are being extensively used to interface multiple RESs and ESDs together as per the requirements. In this thesis, a novel reconfigurable three-port battery integrated DC-DC Boost converter (RPBiC) with active battery charge equalization is proposed and analyzed for power management of solar photovoltaic fed dc distribution system for residential complexes. This converter have integrated battery management system inbuilt in the topology and hence integrates renewable sources like Photovoltaic Panels with a battery stack. The proposed RPBiC can obtain MPPT (Maximum Power Point Tracking) along with regulated voltage levels (48 Volts) under varying solar irradiance conditions. This RPBiC converter is able to perform in the five modes of power transfer scenarios, namely transfer of power from PV cell to battery and DC grid (P2BG), PV cell and battery to DC grid (PB2G), PV to DC grid (P2G), battery to DC grid (B2G) and DC grid to battery (G2B), hence the converter also have load side current reversibility feature. Steady state analysis of the RPBiC topology is presented. In addition to the charging/discharging of the battery stack integrated in the RPBiC, the proposed topology can also obtain the Active Charge Equalization for a m×n battery stack configuration, which makes it possible to obtain balancing of all the batteries in the battery stack in terms of both voltage and current, during charging, discharging, or even in idle condition. The complete equalization technique along with analysis on effect of duty ratios on equalization time and equalization current of battery stack is also presented. Results were obtained and found to be as per theoretical analysis. Keywords – PV System, DC-DC Converters, Renewable Active Charge Equalization, Parallel Charge Equalization, Three Port Converters. v Energy, Chapter 2 Table of Contents Approval Sheet………………………………………………...................... i Declaration………….……………………………………………………… ii Certificate………….……………………………………………………….. iii Acknowledgments...………..………………………………………………. iv Abstract………….…….…………………………………………………… v Table of Contents………..…………………………………………………. vi List of Figures……………..……………………………………………….. viii List of Tables………………..……………………………………………… xi List of Abbreviations Used…...……………………………………………. xii 1. Introduction 1 1.1 Overview and Motivation…………………………………………………. 1.2. State-of-the-Art…………………………………………............................. 1.2.1. Three Port Converters and its challenges…………………................. 1.2.2. Charge equalization techniques and its challenges…………………. 1.3. Research Gap……………………………………………............................ 1.4 Research Objective………………………………………........................... 1.5. Publications……………………………………………….......................... 1.6. Organization of thesis……………………………………………………... vi 1 3 3 7 12 12 13 13 14 2. Photovoltaic System 2.1. Solar Photovoltaic Systems……………………………………………….. 2.1.1. Single Diode model of PV cell……………………………………… 2.1.2. Characteristics of solar cell…………………………………………. 2.1.3. MPPT Algorithms…………………………………………………... 2.1.3.1. Perturb and Observe Algorithm……………………………. 2.1.3.2. Incremental Conductance…………………………………… 2.2. DC Grids…………………………………………………………………… 2.3. Conventional Bi-direction DC-DC Converter…………………………….. 3. Battery Integrated Reconfigurable DC-DC Converter (RPBiC) Port Bi-directional 14 15 16 18 18 19 20 21 22 3.1. Circuit configuration………………………………………………………. 22 3.2. Converter operation………………………………………………………... 23 3.2.1. Solar PV to Battery and DC Bus…………………………………….. 23 3.2.2. Solar PV and Battery to DC Bus……………………………………… 26 3.2.3. Solar PV to DC Bus………………………………………….............. 29 3.2.4. Battery to DC Bus…………………………………………................. 29 3.2.5. DC Bus to Battery……………………………………………………. 31 3.3. Converter steady-state analysis……………………………………………… 32 3.4. Results and Discussions…………………………………………………….. 36 40 4. Active Charge Equalization Technique 4.1. Active charge equalization of a series-connected strings of cells………………………………………………………….…………… 4.2. Effects of duty ratio on the charge equalization time……………………… 4.3. Parallel equalization and complete equalization topology………………… 4.4. Results and discussions……………………………………………………. 5. Conclusion and Future Scope 40 44 45 46 52 5.1. Conclusion………………………………………………………………….. 52 5.2. Future Scope………………………………………………........................... 52 References 53 Biography 56 vii List of Figures Figure Figure Title No. Page No. 1.1. (a) Conventional dc nano-grid, (b) TPC based DCNG……………... 2 1.2. Battery intergrated DC-DC converter……………………………….. 5 1.3. Multi-port DC-DC converter………………………………………... 5 1.4. Non-isolated TPC for standalone RES………………………………. 6 1.5. Bidirectional DC/DC converter with dual-battery energy storage…… 6 1.6. Battery integrated TPC………………………………………………. 6 1.7. Flyback converter for Active Charge Equalization………………….. 8 1.8. Active battery equalization method based on redundant battery…….. 9 1.9. Battery management system with two-stage equalization…………… 9 1.10. Modularized Two-stage charge equalizer…………………………… 10 1.11. Equalization strategy based on fuzzy logic control………………….. 10 1.12. ACE for a series string of cells………………………………………. 11 1.13. Dynamic resistance battery equalizaition……………………………. 11 viii 2.1. Single diode model of PV cell……………………………………….. 15 2.2. I-V and P-V characteristics of PV cell under varying solar irradiance 17 and temperature……………………………………………………… 2.3. Flowchart of Perturb and Observe algorithm………………………… 18 2.4. MPPT using boost converter using P&O algorithm………………….. 19 2.5. Flowchart of Incremental conductance algorithm…………………… 19 2.6. MPPT using Incremental conductance algorithm……………………. 20 2.7. Conventional DC-DC bidirectional converter power output ………... 21 3.1. Circuit configuration of RPBiC……………………………………... 23 3.2. Switching waveform for P2BG scenario……………………………. 24 3.3. Modes of operation of power flow from pv solar panel to battery and 26 dc bus………………………………………………………………... 3.4. Switching waveform for PB2G scenario…………………………….. 26 3.5. Modes of operation of power flow from pv solar panel and battery to 29 dc bus………………………………………………………………… 3.6. Modes of operation of power flow from pv solar panel to dc bus…… 29 3.7. Modes of operation of power flow from battery to dc bus…………… 31 3.8. Modes of operation of power flow from dc bus to battery…………… 32 3.9. (a) Linearly varying solar irradiance function, (b) voltage regulation, 38 (c) pv panel output ………………………………………………….... ix 3.10. (a) Step-wise varying Solar irradiance function (b) Voltage regulation 38 (c) PV panel output …………………………………………………… 3.11. 5 power flow scenarios of the proposed converter (a) pv panel output 39 (b) battery power output (c) dc grid output…………………………… 4.1. Active charge balancing of three cells BMS…………………………. 41 4.2. (a) Discharging of battery (b) Charging of battery with the proposed 42 switching scheme……………………………………………………… 4.3. Timing diagram for the power transfer from battery 1 to battery 3…… 43 4.4. Flowchart of active charge equalization technique used………………. 44 4.5. Complete active charge equalization circuit used……………………... 46 4.6. Active charge 48 equalization obtained under (a) Charging (b) Discharging (c) Isolated condition (c) Condition changing from discharging to charging to again discharging……………………………………………………………. 4.7. Charge equalization and equalization current under D-D’ ratio of 50 (a) 30-70 (b) 50-50 (c) 70-30…………………………………………... 4.8. Charge equalization of a 2x2 battery stack obtained under (a) Charging (b) Discharging (d) Isolated condition………………....... x 51 List of Tables Table No. Title Page No. 1.1. Characteristics of various converter topologies in the literature……. 7 1.2. Characteristics of various charge equalization techniques present in literature……………………………………………………………... 12 3.1. Converter topology parameters……………………………………… 37 xi List of Abbreviations Used RESs Renewable Energy Sources DCNGs DC Nano-Grids nZEB Net Zero Emission Building ESDs Energy Storage Devices TPC Three Port Converters RPBiC Reconfigurable Port Bidirectional DC-DC Converter MPP Maximum Power Point MPPT Maximum Power Point Tracking P2BG Power transfer from PV cell to Battery and Grid (DC) PB2G Power transfer from PV cell and Battery to Grid (DC) P2G Power transfer from PV cell to Grid (DC) B2G Power transfer from Battery to Grid (DC) G2B Power transfer from Grid (DC) to Battery DCM Discontinuous Conduction Mode CCM Continuous Conduction Mode SoC State of Charge xii Chapter-1 Introduction 1.1. Overview and Motivation 1 25]-[35]. 2 Motivation of this thesis is to find solutions to the problems stated above by proposing a novel high gain three port dc-dc converter that is also able to achieve cell balancing connected in series/parallel/2-d arrangements along-side with having current reversibility feature on load side with minimal complexity. 1.2. State-of-the-Art This section is arranged in two subsections with deals with the two problems (TPCs and Charge Balancing) separately. Each giving a brief overview of the existing solutions, their drawbacks or merits are discussed below. In further sections, a topology is proposed which add on the key features discussed and integrates it. 1.2.1.1. Converter topologies and its challenges Several TPC topologies have been proposed in the literature which integrate both RESs and ESDs systems in a single converter circuit with a lesser number of switches compared to conventional designs [12][23]. Non-isolated TPCs are found to have fewer components, compact size, more efficient and less costly for LVDCNG applications as compared to conventional two-port converters. TPCs normally provide provisions to: (i) attain maximum power point tracking (MPPT), (ii) control charging/discharging of battery, or (iii) regulate load/bus voltage. A methodology to embed ESDs within conventional non-isolated dc-dc converters was proposed in [13]-[16] (Fig. 1.2.) but the voltage gain was low (similar to the conventional converters). Dual-Input Single-Output (DISO) and Single-Input Dual-Output (SIDO) dcdc converter were also synthesized from the conventional dc-dc converters but they did not have bi-directional power flow capability required for the charging/discharging of ESDs [20]. High voltage gain TPCs having coupled inductors were proposed but these had issues like magnetic leakage, switching surges, and saturation of a core with bulky size [16] (Fig. 1.3.). One major shortcoming associated with non-isolated TPCs is limited power flow options caused due to sharing of switches and components during different operational modes. This can be overcome by using more number of switches, but this also increases the complexity of control circuits. Also, many of the TPC converters topologies proposed 3 in various research papers do not focus on the current reversal feature on the load side [14][17] (Fig. 1.4). Hence, power flow from current reversible loads (eg. DCNG) to bidirectional feature devices (eg batteries) is not possible using those topologies. Few solution to this problem have been proposed in the literature. A bidirectional multiphase converter [18] was proposed which integrates multiple bidirectional elements for electric vehicles (EV) applications. One limitation of this solution proposed was that it required one coupled inductor for each of the bidirectional element used in the topology. Another bidirectional dc-dc converter capable of having two bidirectional elements for electric vehicle applications was reported in the literature, however it required four power switches, three bidirectional power switches, two inductors, and two capacitors [20] (Fig. 1.5). Some TPCs topologies have been reported in the literature which integrated one unidirectional and two bidirectional elements. TPC topology proposed by Cheng et al [21] has used four switches, four diodes, one inductor and two capacitors for integration of one unidirectional and two bidirectional elements. This converter had bidirectional capabilities for LVDCNG and battery but it also increased number of switching elements to eight. Another such TPC proposed by Zolfi and Ajami [22] was reported in literature which integrates two bidirectional elements with an unidirectional element, though it had higher number of components used. Topology proposed used uncoupled inductor, five switches, five diodes and two capacitors to obtain power flow among the three ports. Kumar D, Saxena AR [23] (Fig. 1.6.) proposed a topology with current reversal feature on load side. This topology only had four switches one inductor per ESD and one capacitor, hence is much simpler control complexity. Though one drawback of said topology was low voltage gain as it only single inductor on input side. Based on the above explanation, it is surmised that TPCs with the ability to incorporate more than one bidirectional element are needed to manage electricity between PV panels, EV batteries, and the LVDDS grid. Some major converters and their features have been summarized below in Table 1.1. 4 D1 iC I0 C RL D2 i batt V batt iL S2 Vi S1 Fig. 1.2. Battery-integrated DC-DC converter [13] + Source 1 - Q1 Q3 L1 S1 S3 C1 TR + Load 1 - S6 S5 L2 + Source 2 - C2 C Q2 Q4 S2 S4 Fig. 1.3. Multi-port DC-DC converter [16] 5 + Load 2 - L1 S1 S2 Dpv D1 D2 L2 Load Cpv C0 S4 PV Ba Cba Fig. 1.4. Non-isolated TPC for standalone RES [17] Q2 Q1 L1 DC Bus + SES1 S CB SES2 CH CES1 VES1 L2 CES2 VES2 - Q4 Q3 Fig. 1.5. Bidirectional DC/DC converter with dual-battery energy storage [20] S4 L2 + Vb L1 C0 DC Bus S3 ipv S2 - PV Vpv S1 Fig. 1.6. Battery integrated TPC [23] 6 Table 1.1. Characteristics of various converter topologies present in literature. Topology No. of switches No. of diodes No. of capacitors/inductors [13] 2 2 2 Features [16] 10 Nil 6 [17] 4 2 6 [20] 4 3 6 [23] 4 Nil 2 Simple Construction and switching Integrated battery with both charging and discharging feature Low DC Voltage gain High Voltage Gain Isolated TPC, requires transformer, more circuit elements, more costly, bigger size May suffer from magnetic leakage, switching surges, saturation of core etc. Low gain Required two inductor hence bulky Do not have current reversal feature on load side Integrates two bidirectional ESDs Requires four power switches, three bidirectional switches, two inductors and two capacitors Only four switches two inductor and a capacitor Much simpler control complexity Current Reversal feature on laod side Low voltage gain 1.2.2. Charge Equalization Techniques and its challenges One solution proposed to the cell imbalance was to obtain charge equalization was to use a flyback converter to transfer excess charge from highest SoC cells to lowest SoC cells [25]. But the drawback of this method is that it needs the cells circuit to be reconfigured [26] which increases no. of switches and hence increases 7 complexity. Similar drawbacks are observed where the solution proposed needs an additional redundant battery connected to a cell [27]. The number of two-stage charge equalization [28]-[29] methods has also been proposed, but these need two different control schemes for each stage, and cannot obtain charge equalization while on-load (charging/discharging) conditions. Equalization strategy based on fuzzy logic control have also been proposed but requires two inductor for the Cuk circuit it was adopted for [30]. Some papers proposed the BMS system where energy is directly transferred between high SoC & low SoC elements via an inductor [31]-[33]. These were found to have lesser switches and components compared to other equalization schemes, lesser control complexity, and obtained results in any configuration and in good time. Some equalization technique has also been reported in the literature which works for a string of cells connected in parallel, but these were developed only for a one dimensional string [34][35]. Some cell equalization techniques proposed in literature and their features have been summarized in Table 1.2. IS11 BS11 D2 D1 Undercharged IS12 B1 BS12 S1 IS13 S2 IS21 BS22 V ref IS22 B2 Pulses BS22 Controller IS23 IS31 BS31 IS32 B3 IS33 BS32 IS41 BS41 IS42 B4 BS42 IS43 + - Fig. 1.7. Flyback Converter for Active Charge Equalization [25] 8 B1 Be B2 LOAD/ SOURCE B3 Ic Id B4 BMS Fig. 1.8. Active Battery Equalization Method Based On Redundant Battery [27] I1 V1 I2 V2 DCDC 1 + DCDC 2 V Bus Controller T units Battery 2 V units Battery 1 I units D1 ~ Dn In Vn Battery Module - Battery n g DCDC n Fig. 1.9. Battery Management System with Two-Stage Equalization [28] 9 DC-DC (2-4W) Switch Module 1 Module 1 Switch Module 2 DC-DC Converter (10-20W) DC-DC (2-4W) Switch Module n Second Stage First Stage Module 2 Module n Battery Module Selection Switches Two Stage DC-DC Converter Fig. 1.10. A Modularized Two-Stage Charge Equalizer [29] Low Energy Side S1 S2 B1 S4 S3 B2 B3 B4 High Energy Side L1 L2 C1 Discahrge Port D Q1 Charge Port Fuzzy Logic Control Fig. 1.11. Equalization strategy based on fuzzy logic control [30] 10 Pack +v S8 S1 B1 S2 S7 B2 S6 S3 B3 S5 S4 GND Ieq L Fig. 1.12. ACE for a series string of cells [33] Bidirectional Converter R2 R2 R2 R1 R1 R1 R1 B1 B2 Bn Battery Management System Fig. 1.13. Dynamic Resistance Battery Equalization [35] 11 DC Table 1.2. Characteristics of various charge equalization techniques present in literature. Topology Features [25] Required transformer, hence bulky Circuits needs to be reconfigured, more switches and hence more complex switching technique [27] Reconfiguration needed hence more complex controlling Required an additional redundant battery connected to a cell [28] Obtain Charge equalization in two-stage conversion process. Can not obtain equalization during on-load condition Needs high number of circuit elements, hence complex control scheme Can not obtain charge equalization while on-load Obtain equalization in two stages [29] [30] [33] [35] Lesser equalization time Requires cuk converter and hence two inductor and a capacitor to operate Obtainable for series string of cells only Much simpler technique Equalization obtainable on both on-load and off-load conditions Can obtain equalization of a single series string of cells Uses concept of Self Equalization of batteries Can obtain equalization of batteries connected parallel in an 1-D array only 1.3. Research Gap In the literature presented, some shortcomings which we came across are described as follows: Many converter topologies have low voltage gain, especially in high duty ratios Needs high number of circuit elements, hence switching schemes are complex Current reversal feature on load side can be further explored Charge equalization techniques are available for 1-D array of cells only i.e. either a series string or a parallel string. 1.4. Research Objective Objective of this thesis are: Analyzing the existing technologies available in DC-Nanogrids Analyzing different topologies available for Multi-Port Networks and their specifications 12 Formulate a novel Three-Port Converter which interfaces battery management system in its topology Performing MPPT and Voltage regulation, along with the current reversibility feature on load side for the proposed converter Formulate a charge equalization technique for a ‘m×n’ stack 1.5. Publications A research paper titled, “A Reconfigurable DC-DC Converter with Active Battery Charge Equalization for Power Management of Residential DC Nano-Grids”, has been communicated to the Journal of Energy Storage A research paper titled, “Active Charge Equalization of Cells connected in SeriesParallel configuration under charging, discharging or isolated condition”, is under preparation for communication in an International Conference. 1.6. Organization of Thesis Chapter 1 gives an overview for the thesis. The existing three-port converter topologies and charge equalization technique have been explained. Chapter 2 discusses the photovoltaic systems, modeling of photovoltaic cell, its characteristics, Maximum Power Point Tracking algorithms, DC Grids and Conventional Bidirectional DC-DC converter. In Chapter 3, the proposed battery integrated reconfigurable port bidirectional DC-DC converter have been analyzed. Converter configuration, different scenarios of operation, steady state analysis and results obtained have been discussed. In Chapter 4, the proposed charge equalization technique has been presented. The series equalization technique and parallel equalization technique has been explained and effect of duty ratio on equalization time have been analyzed. Lastly results obtained have been discussed. In Chapter 5, Conclusion and future scope for the project have been presented. 13 Chapter-2 Solar Photovoltaic Systems Solar photovoltaic (PV) systems have grown in popularity as a way of distributed generation during the previous decade. This chapter presents an overview on solar photovoltaic systems, single diode model of PV-cell, characteristics of pv cell, MPPT algorithms. This chapter also gives an overview on DC Grids and Conventional Bidirectional DC-Dc converters. 2.1. Solar Photovoltaic Systems In recent times, solar photovoltaic systems have been emerged as one of the most popular source of renewable energy. It is in practically limitless supply, readily available, causes virtually no pollution and is a clean source of energy. A pv cell works on the fundamental of photoelectric effect. A pv cell has two layer, a electron excess layer and a electron deficient layer. Electron excess layer is made to be exposed to the sunlight. When sunlight interacts with pv cell, the energy from the photons causes the electrons from the excess layer to become free and these electrons flows from negative layer to the positive layer. This whole process produces the electricity. 14 2.1.1. Single diode model of a PV cell Single diode model is one of the most used model for pv cell because of its simplicity and fair accuracy. A simplified single diode model is shown in Fig. 2.1. Rse Ipv Id Iph D Rsh Vpv Fig. 2.1. Single diode model of pv cell Equation for PV current Ipv is given by the following expression: Ipv = Iph – Id [exp ( Vpv.Ipv.Rse Vpv+I.Rse a Rsh ) -1] – ( ) where Ipv = Output PV current Iph = Photon current generated Id = Leakage current of Diode Vpv = Output PV Voltage Rse = PV cell series resistance Rsh = PV cell shunt resistance a = Ideality factor of diode 15 …(2.1) 2.1.2. Characteristics of PV cell Photovoltaic cell are DC current sources. They practically acts as a constant current source for varying solar panel voltages until a breakdown voltage. Increasing voltage beyond that value causes current to suddenly drop to zero. These characteristics between panel voltage and current is know as I-V characteristics of a pv cell. These characteristics varies when solar irradiance and temperature is varied. On increasing solar irradiance S, the value of constant Ipv increases but the breakdown voltage remains the same for the cell. Similarly, on increasing temperature, constant current Ipv does not change but the breakdown occurs more easily and hence breakdown voltage decreases. These are shown in Fig. 2.2.(a)-(b). Similarly the characteristic of output voltage on varying pv voltage is known as P-V characteristics. On increasing voltage Vpv the output power increases linearly until the maximum power point (MPP) is obtained. Increasing the Vpv further causes the output power to fall sharply. The P-V curve is also effected by varying solar irradiance and temperature. On increasing solar irradiance, the size of P-V curve is increased and hence MPP is shifted to a larger value. On increasing temperature, the P-V curve MPP is shifted to a lower range as breakdown occurs more easily. These are shown in Fig. 2.2.(c)-(d). (a) 16 (b) (c) (d) Fig. 2.2. (a) I-V Charateristic of pv cell under different solar irradiance (b) I-V Charateristic of pv cell under different temperature (c) P-V Charateristic of pv cell under different solar irradiance (d) P-V Charateristic of pv cell under different temperature 17 2.1.3. MPPT Algorithms The operating point of a photovoltaic panel does not necessarily coincide with MPP since the I-V and P-V characteristics of the solar panel are nonlinear, and the power output depends on ambient factors such as cell temperature and sun irradiation. Hence, it has become critical to develop an algorithm to track the maximum power point of pv cell to extract maximum power possible. This process of tracking the MPP is known as Maximum Power Point Tracking (MPPT). Two MPPT algorithms are generally widely used, Perturb and observe algorithm and Incremental conductance algorithm. 2.1.3.1. Perturb and Observe method Perturb and observe method is simplest MPPT algorithm available and hence is widely used. In this method, the voltage is adjusted by a small amount and the movement of the output power is observed. If power is increased, further adjustment in pv voltage is made so that the new power point moves in the same direction. If the power is decreased, adjustment are done such that the power point moves in opposite direction. Major drawback of this method is that it tends to be much slower method to obtain MPPT. The flowchart for perturb and observe method is given in Fig. 2.3. This method was simulated and result for MPPT are shown in Fig. 2.4. Start Measure Vp[n] & Ip[n] Calculate Power Pp[n] = Vp[n]*Ip[n] Yes P[n]-P[n-1] =0 No No P[n] - P[n-1]>0 Yes D[n]=D[n-1] Delta d Vp[n]-Vp[n-1] >0 Yes No No D[n]=D[n-1]+ Delta d Vp[n]-Vp[n-1] >0 D[n]=D[n-1]Delta d Return Fig. 2.3. Flowchart of Perturb and observe algorithm 18 Yes D[n]=D[n-1] +Delta d MPPActual Po 2000 1500 1000 Changes i n Solar Irradiance (S ) 500 0 0 0.2 0.4 0.6 0.8 1 Time (s) Fig. 2.4. MPPT using boost converter using P&O algorithm under varying solar irradiance 2.1.3.2. Incremental Conductance Incremental conductance is another popular MPPT algorithm. It is much faster that P&O algorithm, however is much more complex too. The flowchart for the Incremental conductance is shown in Fig.2.5. MPPT was obtained using this algorithm and is shown in Fig.2.6. Start Measure Vp[n] & Ip[n] No Yes Delta V = 0 Yes Yes dI/dV = -I/V Delta I = 0 No Yes D=D+ Delta d dI/dV > -I/V No No No Delta I > 0 D=DDelta d D=DDelta d Return Fig. 2.5. Flowchart of Incremental conductance algorithm 19 Yes D=D+ Delta d ActualMPP MPPT 2000 1500 Changes in Solar Irradiance ( S) 1000 500 0 0 0.1 0.2 Time (s) 0.3 0.4 Fig. 2.6. MPPT using cuk converter Incremental conductance algorithm under varying solar irradiance 2.2. DC Grids For PV applications, there are primarily two types of grids: On-grid pv systems: Solar power systems generate electricity and are directly linked to the utility power grid. These systems transfer surplus electricity generated by solar panels to the utility grid, and users are reimbursed for the extra power supplied back, making them a passive source of income. Standalone off-grid PV systems: Off-grid systems operate independently of the power grid, but feature batteries that can store the solar energy generated by the system. These systems are self-sustaining and can power essential loads in places where there is no power grid. These kind of grids are etremely useful in rural and distant regions. Distributed Grids and distributed energy generation employing RES such as PV cells, wind, and FC, among others, are potential solutions to fulfil rising power demand. As the number of DC loads in a system grows, it becomes more and more appropriate to send power to the load via RES since the electricity generated by them is DC in nature. However, because to its intermittent nature, RES cannot meet load demand on their own. As a result, Energy Storage Devices (ESDs) such as ultra capacitors, battery banks, and so on are 20 frequently incorporated to maintain load supply even when RES is unable to generate power. 2.3. Conventional Bidirectional DC-DC A DC-DC converter may be used to achieve Maximum Power Point Tracking to ensure maximum power is harnessed by PV cells (MPPT). MPPT is done by manipulating switching of DC-DC converters. As thesis aims to propose a converter topology which have reverse current capability on the load side, firstly a simple bidirectional DC-DC converter was first simulated and results were obtained. These are shown in Fig. 2.7. P1 P2 200 Source 1 recieves Power Source 2 delivers Power 100 Source 1 delivers Power Source 2 recieves Power 0 0.49 0.5 Time (s) 0.51 Fig. 2.7. Conventional DC-DC bidirectional converter power output 21 Chapter-3 Battery Integrated Reconfigurable Port Bidirectional DCDC Converter (RPBiC) This chapter focusses on the DC-DC converter side of the project. The circuit configuration and its features are given in section 3.1 and converter detail operation is explained in section 3.2. The five modes of power flow operation obtained under the proposed topology and converter steady state analysis is given in section 3.3. Finally results are given in section 3.4. 3.1. Circuit Configuration The circuit diagram of the proposed reconfigurable port bi-directional dc-dc converter (RPBiC) with provision for active charge equalization is shown in Fig. 3.1. Here, battery stack with active charge equalizer is embedded between the switches S1, S2 and S3, S4. This provides pulse charging and discharging of the battery which helps in increasing its life-time [36]-[37]. This battery stack uses charge equalization technique which are explained in detail in chapter 4. The converter has two inductors (L1 and L2) at the input-side which are alternately connected in series/parallel using diodes Dd1, Dd2, Dd3 to attain high voltage gain. Inductor (L3) connected in series with the battery stack allows battery charging from the dc bus. The capacitor connected at the dc bus side filters out the ripples. 22 DCbus IL2 L2, rL2 Dd1 Dd2 L1, rL1 + S4 S3 IL1 L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx PV Panel(s) C0, rC0 Vbus IB Cin, rC,in S1 Fig 3.1. Circuit configuration of RPBiC The key features of this converter are: (i) high voltage gain, (ii) pulse charging/discharging of battery stack, (iii) reconfigurable port, and (iv) active state-of-charge (SoC) equalization of battery stack (v) current reversible feature on load side. Depending upon the source power generation and load power demand the converter automatically reconfigures itself to operate as single-input dual-output (SIDO), Dual-input single-output (DISO), single-input single-output (SISO). While operating as SISO converter, the power flow can be either from solar PV to dc bus, battery stack to dc bus, or dc bus to battery. While operating as SIDO or DISO the battery stack can be charged and discharged, respectively simultaneously feeding power to the load. Active charge equalization, of battery stack, can be done in all the operating modes of the converter. 3.2. Converter Operation The converter operation in each operating mode is decided by the switching sequence of switches S1, S2, S3, and S4 and their duty ratios D1, D2, D3, and D4, respectively. The converter operation for five different power flow scenarios is described below wherein following notations are followed to represent the power flow patch ‘P’ is for solar PV, ‘B’ is for battery, ‘G’ is for dc grid. 3.2.1. Solar PV to Battery and DC Bus (P2BG): The converter operates in this scenario when the load demand is less than the power generated by the PV source. Here, converter configures itself as single-input dual-output converter (SIDO) and excess power is used to charge the battery. The duty ratio of switch S1 23 is maintained greater that S2 (𝐷1>𝐷2) while switches S3 and S4 are off (𝐷3=𝐷4=0). The switching waveform for P2BG scenario is shown in Fig 3.2. The converter exhibits five modes as discussed below. D1 D2 Iin IB 10 5 Mode 2 Mode 4 Mode 1 Mode 5 0 Mode 3 -5 D2Ts DxTs D1Ts DyTs Ts Fig. 3.2. Switching waveform for P2BG scenario Mode-1: This mode starts when both the switches 𝑆1 and 𝑆2 are turned on at time t = t0. Diodes Dd1 and 𝐷𝑑3 conduct and connect both the inductors 𝐿1 and 𝐿2 in parallel. Inductor currents 𝑖𝐿1 and 𝑖𝐿2 increase with slope 𝑚𝐿11 = 𝑉𝑝𝑣/𝐿1 and 𝑚𝐿21 = 𝑉𝑝𝑣/𝐿2 respectively and stores energy. Capacitor 𝐶0 discharges and supply power to the load connected with the DC bus. The battery is in an idle state. The equivalent circuit is shown in Fig 3.3. (a). Mode-2: Mode-2 starts when switch 𝑆2 is turned off at t=𝐷2𝑇𝑠 as 𝐷2 < 𝐷1. Diodes 𝐷𝑑1 and 𝐷𝑑3 gets reversed biased while diode 𝐷𝑑2 starts conducting thereby connecting inductors 𝐿1 and 𝐿2 in series. This forces the body diode of S3 to conduct. As S1 is already ‘on’ the current flows into the positive terminal of battery stack, thereby charging it. The body diode of S 4 also conducts and hence power is simultaneously fed to the dc bus. Inductor 𝐿1 and 𝐿2 discharges and hence Input current 𝑖𝑖𝑛(= 𝑖𝐿1 = 𝑖𝐿2) starts to decrease with slope of 𝑚𝑖𝑛2 = 𝑚𝐿12 = 𝑚𝐿22 = (𝑉𝐵𝑢𝑠−𝑉𝑝𝑣)/(𝐿1+𝐿2). Inductor current 𝑖𝐿3 and hence Battery current 𝑖𝐵 starts increasing with the slope of 𝑚𝐿32 = (𝑉𝐵𝑢𝑠−𝑉𝐵)/𝐿3 and charging the battery. This mode continues till 𝑖𝑖𝑛=𝑖𝐿3 at t=𝑡2 = 𝐷𝑥𝑇𝑠. The circuit operation in this mode is shown in Fig 3.3. (b). 24 Mode-3: Mode 3 starts when switch S2 turns off at t = t2 = DxTs. The body diode of S4 becomes reverse biased and turns off, resulting PV panel and battery stack comes in series. The capacitor 𝐶0 discharges to supply power to the DC bus in this mode. Inductor current 𝑖𝐿3 𝑚𝐿3 = (𝑉𝑝𝑣 − 𝑉𝐵)/(𝐿𝑖𝑛 + 𝐿3), where 𝐿𝑖𝑛 is equivalent increases with slope inductance at input side. This mode continues until 𝑆1 is turned off at t=𝑡3 = 𝐷1𝑇𝑠. The circuit operation in this mode is shown in Fig 3.3. (c). Mode-4: Mode 4 starts when switch S1 is turned off at t = t3 = D1Ts. The body diode of Switch S2 and S4 becomes forward biased resulting in PV panel and DC grid becoming parallel with each other. Inductor current 𝑖𝐿3 starts decreasing 𝑚𝐿34 = 𝑉𝐵/𝐿3 where 𝐿𝑖𝑛 is the equivalent Inductance in the input side. This mode continues until inductor current 𝑖𝐿3 and battery current 𝑖𝐵 becomes zero at t = 𝑡4 = 𝐷𝑦𝑇𝑠. The circuit operation in this mode is shown in Fig 3.3. (d). Mode-5: Mode 5 starts when inductor current 𝑖𝐿3 and hence Battery Current 𝑖𝐵 becomes zero at t = 𝑡4 = 𝐷𝑦𝑇𝑠. Diodes 𝐷𝑑1 and 𝐷𝑑3 become reversed biased; Diode 𝐷𝑑2 conduct resulting in inductors 𝐿1 and 𝐿2 connecting in series. Inductor currents 𝑖𝐿1 and 𝑖𝐿2 decrease with slope 𝑚𝐿15 = 𝑚𝐿25 = (𝑉𝑝𝑣 − 𝑉𝐵𝑢𝑠)/(𝐿1 + 𝐿2). As Body Diode 𝐷3 is forward biased and on, the battery is in an idle state. The circuit operation in this mode is shown in Fig 3.3. (e). Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 ig + S4 S3 IL1 L1, rL1 L3, rL3 Dd3 + + Battery Stack with SoC Equalizer S2 Ddx C 0, rC0 Vbus IB Cin, rC,in PV Panel(s) ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd2 Dd1 -iC0 C 0, rC0 Vbus iC0 -IB Cin, rC,in PV Panel(s) S1 Battery Stack with SoC Equalizer S2 Ddx S1 - - (b) (a) Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 L1, rL1 L3, rL3 Dd3 + + S2 Ddx Battery Stack with SoC Equalizer PV Panel(s) -IB Cin, rC,in ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd2 ig + S4 S3 IL1 Dd1 C 0, rC0 Vbus S2 Ddx Battery Stack with SoC Equalizer - -iC0 PV Panel(s) S1 -IB Cin, rC,in C0, rC0 Vbus iC0 S1 - - (d) (c) 25 DCbus IL2 L2, rL2 Dd2 Dd1 L1, rL1 ig + S4 S3 IL1 L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx PV Panel(s) IB Cin, rC,in C0, rC0 Vbus iC0 S1 - (e) Fig. 3.3. Modes of operation of power flow from pv solar panel to battery and dc bus. 3.2.2. Solar PV and Battery to DC Bus (PB2G): The converter operates in this scenario when demand of PV Grid is more than the Power generated by PV Panel. Battery stack is also needed to provide power to DC Grid, and hence converter acts in Dual Input Single Output (DISO) state. In this case, the duty ratio of switch S1 is less that of Switch S2 (𝐷1<𝐷2) while switches S3 and S4 are off (𝐷3=𝐷4=0). Switching waveform for PB2G scenario is shown in Fig 3.4. The converter exhibits five modes where converter operation is described as follows. D1 D2 Iin IB 15 Mode 2 10 5 Mode 4 Mode 1 Mode 3 Mode 5 0 D 1 Ts D x Ts D 2 Ts D y Ts Ts Fig. 3.4. Switching waveform for PB2G scenario 26 Depending on voltages 𝑉𝑏𝑢𝑠, 𝑉𝑝𝑣 and 𝑉𝐵 input inductors 𝐿1 and 𝐿2 can connect in series or parallel. (a) If 𝑉𝐵𝑢𝑠 > 𝑉𝑝𝑣 + 𝑉𝐵, Diodes 𝐷𝑑1, and 𝐷𝑑3 are reversed biased, Diode 𝐷𝑑2 start conducting and bring inductor 𝐿1 and 𝐿2 in series. Here Lin = L1+L2. (b) If 𝑉𝐵𝑢𝑠 < 𝑉𝑝𝑣 + 𝑉𝐵, Diodes 𝐷𝑑1, and 𝐷𝑑3 are forward biased, Diode 𝐷𝑑2 is reverse biased and hence inductor 𝐿1 and 𝐿2 are in parallel. Here Lin = L1||L2. Mode-1: This mode works similarly to mode 1 of P2BG. The only difference is that this mode ends when Switch S1 turns off at t = D1Ts as D1<D2 in this case. The equivalent circuit is shown in Fig 3.5.(a). Mode-2: Mode 2 starts when switches 𝑆1 is turned off at t = D1Ts. The body diode of switches S3 and S4 are forced to conduct. As S2 is already ‘on’ the current flows into the negative terminal of the battery stack, hence discharging the battery via Inductor 𝐿3. The battery stack along with PV panel provide power to the DC Grid. Input current 𝑖𝑖𝑛 starts to decrease and Inductor current 𝑖𝐿3 starts increasing with slope 𝑚𝐿32 = 𝑉𝐵/𝐿3. This mode continues until input current becomes equal to inductor current iL3 (𝑖𝑖𝑛 = 𝑖𝐿3) at t = t2 = DxTs. The equivalent circuit is shown in Fig 3.5.(b). If 𝑉𝐵𝑢𝑠 > 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 in series (Fig 3.5.b.i). If 𝑉𝐵𝑢𝑠 < 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 are connected in parallel (Fig 3.5.(b).ii). Mode-3: Mode 3 starts when 𝑖𝑖𝑛 = 𝑖𝐿3 at t = t2 = DxTs. The body Diode of Switch S3 becomes reverse biased and stops conducting, resulting in the PV panel, Battery, and DC grid becoming in series connection. As battery stack and PV panel are in series, Input current 𝑖𝑖𝑛 and Inductor current 𝑖𝐿3 are equal (iin = iL3) and change with the slope of 𝑚𝐿3 = (𝑉𝑝𝑣 + 𝑉𝐵 − 𝑉𝐵𝑢𝑠)/(𝐿𝑖𝑛 + 𝐿3), where 𝐿𝑖𝑛 is equivalent Inductance in input side. This mode continues until Switch 𝑆2 is turned off at t = t3 = D2Ts. The equivalent circuit is shown in Fig 3.5.(c). If 𝑉𝐵𝑢𝑠 > 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 in series (Fig 3.5.c.i). If 𝑉𝐵𝑢𝑠 < 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 are connected in parallel (Fig 3.5.c.ii). Mode-4: Mode 4 starts when Switch S2 turns off at t = t3 = D2Ts. The body Diode of switch S1 becomes forward biased and starts conducting, making PV panel and Battery stack parallel to DC grid. Input current 𝑖𝑖𝑛 and inductor current 𝑖𝐿3 starts decreasing with slope 𝑚𝑖𝑛4 = (𝑉𝑝𝑣 − 𝑉𝐵𝑢𝑠)/𝐿𝑖𝑛, and 𝑚𝐿34 = (𝑉𝐵 − 𝑉𝐵𝑢𝑠)/𝐿3 respectively where 𝐿𝑖𝑛 is the equivalent inductance in input side. This mode continues until inductor current iL3 and Battery current iB 27 becomes zero at t = t4 = DyTs. The equivalent circuit is shown in Fig 3.5.(d). If 𝑉𝐵𝑢𝑠 > 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 in series (Fig 3.5.d.i). If 𝑉𝐵𝑢𝑠 < 𝑉𝑝𝑣 + 𝑉𝐵, input inductor 𝐿1 and 𝐿2 are connected in parallel (Fig 3.5.d.ii). Mode-5: This mode works similarly to mode 5 of P2VG. The equivalent circuit is shown in Fig 3.5.(e). IL2 L2, rL2 Dd1 Dd2 L1, rL1 S4 S3 IL1 DCbus Dd1 ig + IL1 L1, rL1 L3, rL3 Dd3 DCbus I L2 L2, rL2 Dd2 L3, rL3 + + Battery Stack with SoC Equalizer S2 Ddx C0, rC0 Vbus Battery Stack with SoC Equalizer S2 Ddx IB Cin, rC,in C0, rC0 Vbus - PV Panel(s) ig + S4 S3 Dd3 -iC0 Cin, rC,in PV Panel(s) S1 iC0 IB S1 - - (b.i) (a) Dd1 DCbus IL2 L2, rL2 S3 IL1 L1, rL1 Dd2 ig + S4 L1, rL1 + C0, rC0 Vbus - Battery Stack with SoC Equalizer S2 Ddx C0, rC0 Vbus iC0 IB Cin, rC,in PV Panel(s) L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd1 Dd2 Cin, rC,in PV Panel(s) S1 iC0 IB S1 - - (c.i) (b.ii) Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 ig + S4 S3 IL1 Dd1 L1, rL1 L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx PV Panel(s) IB Cin, rC,in ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd2 + C0, rC0 Vbus Battery Stack with SoC Equalizer S2 Ddx iC0 PV Panel(s) S1 IB Cin, rC,in C0, rC0 Vbus iC0 S1 - - (d.i) (c.ii) 28 d1 Dd2 DCbus L2, rL2 I D d1 L1, rL1 ig + S4 S3 IL1 Dd2 L2 L1, rL1 L3, rL3 Dd3 + + S2 Ddx Battery Stack with SoC Equalizer C 0, rC0 Vbus S2 Ddx Cin, rC,in C0, rC0 Vbus IB iC0 IB Battery Stack with SoC Equalizer - PV Panel(s) ig + S4 S3 IL1 L3, rL3 Dd3 DCbus I L2, rL2 D L2 Cin, rC,in PV Panel(s) S1 iC0 S1 - - (d.ii) (e) Fig. 3.5. Modes of operation of power flow from PV Solar panel and Battery to DC Bus. 3.2.3. Solar PV to DC Bus (P2G): The converter operates in this scenario when the demand of PV Grid is equal to the power generated by PV Panel. Battery stack is isolated in this case as they are not required, and hence converter acts in Single Input Single Output state. In this case, the duty ratio of switch S1 is same as that of Switch S2 (𝐷1=𝐷2) while switches S3 and S4 are off (𝐷3=𝐷4=0). The converter exhibits two modes during this case. The operation of these modes is similar to the Mode-I and Mode-IV of P2BG case. The equivalent circuits are shown in Fig. 3.6. (a) and Fig. 3.6. (b). Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 ig + S4 S3 IL1 Dd1 L1, rL1 L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx PV Panel(s) IB Cin, rC,in ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd2 + C0, rC0 Vbus Battery Stack with SoC Equalizer S2 Ddx -iC0 PV Panel(s) S1 IB Cin, rC,in C0, rC0 Vbus iC0 S1 - - (a) (b) Fig. 3.6. Modes of operation of power flow from pv solar panel to dc bus. 3.2.4. Battery to DC Bus (B2G): The converter operates in this scenario when PV Grid is unable to supply power (No solar irradiance) and there is power demand in DC Grid. As PV panel output is unavailable, input diodes DD1-DD3 are off and iin=0. The battery stack is used to supply power to the DC Grid. Here, the converter works as a simple boost converter working in DCM mode. Converter 29 configures itself as a single-input single-output converter in this case (SISO). Switching waveform for this scenario will be similar to a simple boost converter working in DCM mode. In this case, switch S1 and S4 are kept off (D1 = D4 = 0) while switches S2 and S3 are provided with the same duty ratio (𝐷2=𝐷3). The converter exhibits three modes where converter operation is described as follows. The equivalent circuit during each mode is given in Fig. 3.7. (a)-(c). Mode-1: This mode starts when both Switches 𝑆2 and 𝑆3 are turned on at time t = t0. Inductor 𝐿3 gets charged by the battery stack and inductor current 𝑖𝐿3 increase with the slope of 𝑉𝐵/𝐿3. Capacitor 𝐶0 discharges and supply power to the loads connected to the DC grid. This mode ends when Switch 𝑆2 and 𝑆3 are turned off at t = t1 = D2Ts. The equivalent circuit is shown in 3.7. (a). Mode-2: Mode 2 starts when Switch 𝑆2 and 𝑆3 are turned off at t = t1 = D2Ts. The body diode of the switches S1 and S4 are forced to turn on and conduct, bringing battery parallel to DC bus. Inductor 𝐿3 discharges with slope (𝑉𝐵 − 𝑉𝐵𝑢𝑠)/𝐿3, discharging battery. This mode ends when 𝐿3 completely discharges and 𝑖𝐿3 becomes zero at t = t2 = DxTs. The equivalent circuit is shown in 3.7. (b). Mode-3: Mode 3 starts at t = t2 when iL3 becomes zero. The body diode of the switch S1 and S4 stops conducting, disconnecting the battery stack. Capacitor 𝐶0 discharges and supply power to the DC grid. This mode ends when Switch S2 and S3 are turned on at t = Ts. The equivalent circuit is shown in 3.7. (c). d1 Dd2 DCbus L2, rL2 I D d1 S3 IL1 L1, rL1 ig + S4 S2 D dx PV Panel(s) IB Cin, rC,in S3 L1, rL1 + Battery Stack with SoC Equalizer Dd2 L2 IL1 L3, rL3 Dd3 DCbus I L2, rL2 D L2 ig + S4 L3, rL3 Dd3 + C0, rC0 Vbus S2 Ddx Battery Stack with SoC Equalizer - -iC0 S1 PV Panel(s) - IB Cin, rC,in C 0, rC0 Vbus iC0 S1 - (a) (b) 30 Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 ig + S4 S3 IL1 L3, rL3 Dd3 + S2 Ddx Battery Stack with SoC Equalizer PV Panel(s) IB Cin, rC,in C0, rC0 Vbus -iC0 S1 - (c) Fig. 3.7. Modes of operation of power flow from battery to dc bus. 3.2.5 DC Bus to Battery (G2B): The converter operates in this scenario when PV Grid is unable to supply power (No solar irradiance) and there is excess power present in DC Grid. As PV panel output is unavailable, input diodes DD1-DD3 are off and iin=0. The battery stack is charged using the excess power of the DC Grid. Here, the converter works as a simple buck converter working in DCM mode. Converter configures itself as a single-input single-output converter in this case (SISO). Switching waveform for this scenario will be similar to a simple buck converter working in DCM mode. In this case, switch S1 and S4 are provided with the same duty ratio (𝐷1=𝐷4) while switches S2 and S3 are kept off (D2 = D3 = 0). The converter exhibits three modes where converter operation is described as follows. The equivalent circuit during each sub-mode is given in Fig. 3.8. (a)-(c). Mode-1: This mode starts when both Switches 𝑆1 and 𝑆4 are turned on at time t = t0, resulting in bringing DC grid parallel to battery Stack. DC Grid and Battery Stack are connected via inductor L3. Inductor current 𝑖𝐿3 flows into the positive terminal of Battery Stack, charging it. This mode ends when Switch 𝑆1 and 𝑆4 are turned off at t = t1 = D1Ts. The equivalent circuit is shown in Fig. 3.8. (a). Mode-2: This mode starts when Switch 𝑆1 and 𝑆4 are turned off at t = t1 = D1Ts. The body diode of Switches S2 and S3 are forced to conduct, discharging inductor L3 with slope 𝑉𝐵/𝐿3, charging the battery. This mode ends when 𝐿3 completely discharges and 𝑖𝐿3 becomes zero at t = t2 = DxTs. The equivalent circuit is shown in Fig. 3.8. (b). 31 Mode-3: This mode starts when inductor current iL3 becomes zero at t = t2 = DxTs. The body diode of Switches S2 and S3 stops conducting, making the battery isolated. This mode ends when the switches S1 and S4 are turned on at t = Ts. The equivalent circuit is shown in Fig. 3.8. (c). DCbus IL2 L2, rL2 Dd2 Dd1 L1, rL1 ig + S4 S3 IL1 L1, rL1 L3, rL3 Dd3 + S2 Ddx + Battery Stack with SoC Equalizer C0, rC0 Vbus PV Panel(s) S2 Ddx Battery Stack with SoC Equalizer C0, rC0 Vbus - -iC0 -IB Cin, rC,in ig + S4 S3 IL1 L3, rL3 Dd3 DCbus IL2 L2, rL2 Dd2 Dd1 Cin, rC,in PV Panel(s) S1 iC0 -IB S1 - - (b) (a) Dd1 DCbus IL2 L2, rL2 Dd2 L1, rL1 ig + S4 S3 IL1 L3, rL3 Dd3 + Battery Stack with SoC Equalizer S2 Ddx IB Cin, rC,in PV Panel(s) C0, rC0 Vbus iC0 S1 - (c) Fig. 3.8. Modes of operation of power flow from Battery to DC Bus. 3.3 Converter Steady-State Analysis Let input voltage of PV panel be Vpv, output Voltage of DC bus be Vg, Battery Voltage be Vb, D1, D2, Dx and Dy represent same as discussed above. 𝐿1 ′ Let 𝐿1 = 𝐿 = 𝑝 𝐿1.𝐿2 𝐿1+𝐿2 ; 𝐿1+𝐿2 𝐿2 ′ ; 𝐿2 = 𝐿1+𝐿2 𝐿𝑝 ; 𝐿1 ′′ = 𝐿 ′= 𝑝 𝐿𝑝+𝐿3 ; and 𝐿 𝐿1 𝐿1+𝐿2+𝐿3 3𝑝 ′ = 32 ; 𝐿2 ′′ = 𝐿3 𝐿𝑝+𝐿3 𝐿2 𝐿1+𝐿2+𝐿3 ; 𝐿3 ′′ = 𝐿3 𝐿1+𝐿2+𝐿3 … (3.3.1) ; Scenario-1: P2BG Applying Volt-Second Balance across inductor L1 D2Vpv + (Dx-D2)(Vpv-Vg)L1’ + (D1-Dx)(Vpv-Vb)L 1’’ + (Dy-D1)(Vpv-Vg)L 1’ + (1-Dy)(Vpv-Vg)L 1’ = 0 … (3.3.2) Applying Volt-Second Balance across inductor L2 D2Vpv + (Dx-D2)(Vpv-Vg)L 2’ + (D1-Dx)(Vpv-Vb)L 2’’ + (Dy-D1)(Vpv-Vg)L 2’ + (1-Dy)(Vpv-Vg)L 2’ = 0 … (3.3.3) Similarly applying Volt-Second Balance across inductor L3 (Dx-D2)(Vb-Vg) + (D1-Dx)(Vpv-Vb)L3’’ + (Dy-D1)Vb = 0 … (3.3.4) Solving and rearranging these equations results in: 𝑉 = 𝑔 (𝐷2 𝑉𝑝𝑣 ) + (𝐷𝑥 − 𝐷2 )𝑉𝑝𝑣 𝐿′ + (𝐷1 − 𝐷𝑥 )(𝑉𝑝𝑣 − 𝑉𝑏 )𝐿′′ + (𝐷𝑦 − 𝐷1 )𝑉𝑝𝑣 𝐿′ + (1 − 𝐷𝑦 )𝑉𝑝𝑣 𝐿′ 1 1 1 1 (𝐷𝑥 − 𝐷2)𝐿′ + (𝐷1 − 𝐷𝑥)𝐿′′ + (𝐷𝑦 − 𝐷1)𝐿′ + (1 − 𝐷𝑦)𝐿′ 1 𝑉 = 𝑝𝑣 1 1 1 (𝐷𝑥 − 𝐷2 )𝑉𝑔 𝐿′2 + (𝐷1 − 𝐷𝑥 )𝑉𝑏 𝐿′′ + (𝐷𝑦 − 𝐷1 )𝑉𝑔 𝐿′ + (1 − 𝐷𝑦 )𝑉𝑔 𝐿′ 2 2 2 𝐷2 + (𝐷𝑥 − 𝐷2)𝐿′ + (𝐷1 − 𝐷𝑥)𝐿′′ + (𝐷𝑦 − 𝐷1)𝐿′ + (1 − 𝐷𝑦)𝐿′ 2 2 2 2 And 𝐷𝑦 = (𝐷2 − 𝐷𝑥 )(𝑉𝑏 − 𝑉𝑔 ) + (𝐷1 − 𝐷𝑥 )(𝑉𝑏 − 𝑉𝑝𝑣 )𝐿′′3 + 𝐷1 𝑉𝑏 𝑉𝑏 … (3.3.5) Scenario-2: PB2G Case (i) : if Vg > Vpv+Vb Applying Volt-Second Balance across inductor L1 D1Vpv + (Dx-D1)(Vpv-Vg) + (D2-Dx)(Vpv+Vb-Vg)L ’’ + (Dy-D2)(Vpv-Vg)L ’ + (1-Dy)(Vpv-Vg)L ’ = 0 1 1 1 … (3.3.6) 33 Applying Volt-Second balance across inductor L2 D1Vpv + (Dx-D1)(Vpv-Vg)L2’ + (D2-Dx)(Vpv+Vb-Vg)L 2’’+ (Dy-D2)(Vpv-Vg)L 2’ + (1-Dy)(Vpv-Vg)L 2’ = 0 … (3.3.7) Applying Volt-Second balance across inductor L3 (Dx-D1)Vb + (D2-Dx)(Vpv-Vb- Vg)L3’’ + (Dy-D2)(Vb-Vg) = 0 … (3.3.8) Solving and rearranging these equations results in: 𝑉 = 𝑔 (𝐷1 𝑉𝑝𝑣 ) + (𝐷𝑥 − 𝐷1 )𝑉𝑝𝑣 𝐿′ + (𝐷2 − 𝐷𝑥 )(𝑉𝑝𝑣 + 𝑉𝑏 )𝐿′′ + (𝐷𝑦 − 𝐷2 )𝑉𝑝𝑣 𝐿′ + (1 − 𝐷𝑦 )𝑉𝑝𝑣 𝐿′ 1 1 1 1 (𝐷𝑥 − 𝐷1)𝐿′ + (𝐷2 − 𝐷𝑥)𝐿′′ + (𝐷𝑦 − 𝐷2)𝐿′ + (1 − 𝐷𝑦)𝐿′ 1 𝑉 = 𝑝𝑣 1 1 1 (𝐷𝑥 − 𝐷1 )𝑉𝑔 𝐿′2 + (𝐷2 − 𝐷𝑥 )(𝑉𝑔 − 𝑉𝑏 )𝐿′′ + (𝐷𝑦 − 𝐷2 )𝑉𝑔 𝐿′ + (1 − 𝐷𝑦 )𝑉𝑔 𝐿′ 2 2 2 𝐷1 + (𝐷𝑥 − 𝐷1)𝐿′ + (𝐷2 − 𝐷𝑥)𝐿′′ + (𝐷𝑦 − 𝐷2)𝐿′ + (1 − 𝐷𝑦)𝐿′ 2 2 2 2 And 𝐷𝑦 = (𝐷1 − 𝐷𝑥 )𝑉𝑏 + (𝐷2 − 𝐷𝑥 )(𝑉𝑔 + 𝑉𝑏 − 𝑉𝑝𝑣 )𝐿′′3 + 𝐷2 (𝑉𝑏 − 𝑉𝑔 ) 𝑉𝑏 − 𝑉𝑔 … (3.3.9) Case (ii) : if Vg < Vpv+Vb Applying Volt-Second Balance across inductor L1 D1Vpv + (Dx-D1)(Vpv-Vg) + (D2-Dx)(Vpv+Vb-Vg)L p’ + (Dy-D2)(Vpv-Vg) + (1-Dy)(Vpv-Vg)L 1’ = 0 … (3.3.10) Applying Volt-Second balance across inductor L2 D1Vpv + (Dx-D1)(Vpv-Vg) + (D2-Dx)(Vpv+Vb-Vg)L p’+ (Dy-D2)(Vpv-Vg) + (1-Dy)(Vpv-Vg)L 2’ = 0 … (3.3.11) 34 Applying Volt-Second balance across inductor L3 (Dx-D1)Vb + (D2-Dx)(Vpv+Vb-Vg)L3p’ + (Dy-D2)(Vb-Vg) = 0 … (3.3.12) Solving and rearranging these equations results in: (𝐷1 𝑉𝑝𝑣 ) + (𝐷𝑥 − 𝐷1 )𝑉𝑝𝑣 + (𝐷2 − 𝐷𝑥 )(𝑉𝑝𝑣 + 𝑉𝑏 )𝐿′ + (𝐷𝑦 − 𝐷2 )𝑉𝑝𝑣 + (1 − 𝐷𝑦 )𝑉𝑝𝑣 𝐿′ 𝑝 1 𝑉𝑔 = (𝐷𝑥 − 𝐷1) + (𝐷2 − 𝐷𝑥)𝐿′ + (𝐷𝑦 − 𝐷2) + (1 − 𝐷𝑦)𝐿′ 𝑝 1 (𝐷𝑥 − 𝐷1 )𝑉𝑔 + (𝐷2 − 𝐷𝑥 )(𝑉𝑔 − 𝑉𝑏 )𝐿′ + (𝐷𝑦 − 𝐷2 )𝑉𝑔 + (1 − 𝐷𝑦 )𝑉𝑔 𝐿′ 𝑝 2 𝑉𝑝𝑣 = 𝐷1 + (𝐷𝑥 − 𝐷1) + (𝐷2 − 𝐷𝑥)𝐿′ + (𝐷𝑦 − 𝐷2) + (1 − 𝐷𝑦)𝐿′ 𝑝 2 And 𝐷𝑦 = (𝐷1 − 𝐷𝑥 )𝑉𝑏 + (𝐷2 − 𝐷𝑥 )(𝑉𝑔 − 𝑉𝑏 − 𝑉𝑝𝑣 )𝐿′3𝑝 + 𝐷2 (𝑉𝑏 − 𝑉𝑔 ) 𝑉𝑏 − 𝑉𝑔 … (3.3.13) Scenario-3: P2G As here D1 = D2; It is simply denoted as D Applying Volt-Second Balance across inductor L1 DVpv + (1-D)(Vpv-Vg)L1’ = 0 … (3.3.14) Applying Volt-Second Balance across inductor L2 … (3.3.15) DVpv + (1-D)(Vpv-Vg)L2’ = 0 𝑉 1 𝑉𝑝 1−𝐷 Solving these equations results in 𝑔 = … (3.3.16); which is the same as a conventional boost converter, which is in accordance with the expected result as the converter was expected to work as a conventional boost converter in this scenario. 35 Scenario-4: B2G Here converter works as a simple boost converter working in DCM mode, hence the relationship between grid voltage/current and battery voltage/ current can simply be given as 𝑉𝑔 = 𝑉𝑏 𝐼𝑏 = 1 + √1 + 𝐼𝑔 4𝐷2 𝐾 2 … (3.3.16) Where = 2𝐿3𝑓𝑠 𝑅𝐿 ; condition for DCM is K < Kcrit where Kcrit = D(1-D)2 Scenario-5: G2B Here converter works as a simple buck converter working in DCM mode, hence the relationship between grid voltage/current and battery voltage/ current can simply be given as 𝑉𝑏 𝑉𝑔 = 𝐼𝑔 = 𝐼𝑏 2 1 + √1 + 4𝐷2 𝐾 … (3.3.17) condition for DCM is K < Kcrit where Kcrit = (1-D) 3.4 Results and Discussion The converter topology developed was simulated using MATLAB/SIMULINK and the results were rectified and found to be satisfactory. The design parameters of the converter are shown in Table 3.1. The Load voltage was successfully regulated at 48 V, and MPPT was obtained as shown in Fig 3.9. and Fig 3.10. 36 Table 3.1. Converter Topology Parameters Parameters Values PV MPP 183 W at 1000 W/m2 corresponding to 145 W at 750 W/m2 Solar irradiance 198 W at 1250 W/m2 Battery 3 Li-ion battery of 7.2 V nominal voltage each Inductors/Capacitors 4mH and 10000uF respectively Switching 50 KHz Frequency Solar irradiance value was varied linearly from a minimum of 750 W/m2 to a maximum of 1250 W/m2. PV panel output obtained verified the correctness of Maximum Power Point Tracking. Load voltage was regulated at 48V. Under varying solar irradiance, the desired voltage regulation was obtained with satisfactory accuracy. Results for MPPT and Load Voltage regulation is shown in Fig. 3.9. (b) and (c) respectively. Similarly solar irradiance was also varied in step fashion and MPPT and Voltage regulation was observed. This result is shown in Fig 3.10. (b) and (c) respectively. (b) (a) 37 (c) Fig 3.9. (a) Constantly varying Solar irradiance function (b) Voltage regulation (c) PV panel output. (b) (a) (c) Fig 3.10. (a) Step-wise varying Solar irradiance function (b) Voltage regulation (c) PV panel output. 38 The proposed converter was also able to switch in the 5 power flow scenarios of operation as shown in Fig 3.11. 180 (a) PV Panel Output (W) 160 140 120 100 80 60 40 20 0 5 10 15 20 25 35 30 40 45 50 Time (s) 150 Battery Power Output (W) (b) 100 50 0 Battery Power Output (W) -50 P2BG PB2G P2G B2G B2V -100 -150 0 5 10 15 20 25 30 35 40 45 50 Time (s) 150 DC Grid Power (W) (c) 100 50 0 5 10 15 20 25 30 35 40 45 50 Time (s) Fig 3.11. 5 Power flow scenarios of the proposed converter (a) PV panel output (b) Battery power output (c) DC grid output. 39 Chapter-4 Active Charge Equalization Technique In this chapter, a new active charge equalization technique is proposed by modifying existing technique in such a way that it retains the benefits and simplicity of different techniques while overcoming their shortcomings. The proposed charge equalization technique is able to obtain charge equalization of any 2-d arrays of cells. The technique used to equalize a series string is explained in section 4.1. Section 4.2 gives the analysis on effect of duty cycle on equalization time. Section 4.3 extends the technique to be able to perform charge equalization of parallel array. Finally results for the charge equalization technique is given in section 4.4. 4.1. Charge Equalization of a Series Connected String of Cells The circuit configuration of the active SoC equalization scheme for a string of series connected batteries is shown in Fig. 4.1. The fundamental idea is to use a non-dissipative element to transfer energy from stronger cells to weaker cells to achieve charge equalization. We used one inductor to exchange energy among all the cells, hence reducing no. of additional components required. To evaluate the charge equalization scheme, let us determine the maximum SoC cell and minimum SoC cell, let them be VSoCmax and VSoCmin respectively. 40 Pack +v S8 S1 B1 S2 S7 B2 S6 S3 B3 S5 S4 GND Ieq L Fig. 4.1. Active charge balancing of three cells BMS [33]. First, we need to measure SOCs of all cells in the series battery packs. This can be calculated using The Coulomb Counting method. The coulomb counting method is the most common technique for calculating the SOC. The current SOC is calculated by the formula given as 𝑆𝑂𝐶 = 𝑆𝑂𝐶(𝑡 ) + 0 1 𝑡0+ 𝑐 ∫ (𝐼 𝑏 −𝐼 𝑙𝑜𝑠𝑠)𝑑𝑡 𝐶𝑟𝑎𝑡𝑒𝑑 𝑡0 …(4.1.1) Where 𝑆𝑂𝐶(𝑡0) is the initial SOC of the cell is during observation, 𝐶𝑟𝑎𝑡𝑒𝑑 is the rated capacity, 𝐼𝑏 is the battery current and 𝐼𝑙𝑜𝑠𝑠 is the current consumed by the loss reactions. The method calculated the capacity and SOC by simply calculating total charge transfer in or out of the cell. The accuracy of the method primarily depends on the estimation of the initial SOC. This is estimated from the operating condition and open-circuit voltage of the cell and the datasheet provided by the manufacturer. The next step is to find the maximum SoC cell and the minimum SoC cell among the series string. Let them be VSoCmax & VSoCmin respectively. To obtain equalization, the excess charge needs to be transfered from VSoCmax to VSoCmin. This process is divided into two switching cycles, Discharging Cycle and the Charging Cycle. The switching control scheme determines which cell would be charged or discharged. This is explained in Fig 4.2. 41 M8 M1 V1 M6 M3 V3 I I M2 M7 M4 M5 L L (b) (a) Fig 4.2. (a) Discharging of battery (b) Charging of battery with the proposed switching scheme (i) Discharging Cycle: Fig 4.2 (a) represents the discharging operation of the highest SoC cell of the stack. In this case, the MOSFET S1 and S3 are turned on and S2 and S4 are turned off, so that the cell could transfer the charge to the inductor L. (ii) Charging Cycle: Fig 4.2 (b) represents the charging operation of the lowest SoC cell of the stack. In this case, the MOSFET S2 and S4 are turned on and S1 and S3 are turned off, so that the energy stored in the inductor L could be transferred to the cell. Let us consider V1 to be the Highest SoC cell (𝑉𝑆𝑂𝐶𝑚𝑎𝑥) that needs to transfer energy to the Lowest SoC cell (𝑉𝑆𝑂𝐶𝑚𝑖𝑛) let’s say V3. To discharge V1, Switch S7 and S1 need to be turned on in the first half cycle. When they are turned on, the inductor charges and its current increase from i′L2 to i′L1, SoC 1, and the Voltage of battery V1 decreases linearly from Vb1. This action stores energy from Battery V1 to Inductor L. In the second cycle, we need to charge V3. Switch S4 and S6 are turned on and the inductor discharges and its current reduce from i′L1 to i′L2, SoC 3, and the Voltage of the battery V3 increases linearly from Vb3. This action transferred stored energy from Inductor L to Battery V3. The timing diagram for the process is shown in Fig 4.1.3. The combined effect of these two cycles is that Vmax is transferring its excess charge to Vmin, hence moving towards equalization. After these two cycles again cells corresponding to 𝑆𝑂𝐶𝑚𝑎𝑥 and 𝑆𝑂𝐶𝑚𝑖𝑛 are found out and again these two cycles are repeated for the corresponding cells till equalization is obtained. 42 Pulses from MC Pulses from MC MOSFET 4 & 6 ON MOSFET 4 & 6 ON Battery 1 Voltage IL1 IL2 Vb1 Vb Battery 3 Voltage IL MOSFET 1 & 7 ON MOSFET 1 & 7 ON Vb Vb3 t1 t2 t3 t4 Fig. 4.3. The timing diagram for the power transfer from Battery 1 to Battery 3. In the current example, as V1 is continually discharged, at a certain point difference of SoC of V1 (𝑆𝑜𝐶1) and V2 (𝑆𝑜𝐶2) will be less than tolerance value (lets say 0.001). Here V1 and V2 are said to be equalized. Now from the next cycles, lets say 𝑆𝑜𝐶1 is greater than 𝑆𝑜𝐶2 by a very small difference so V1 will be considered cell corresponding to max SoC and will be discharged to charge the lowest SoC cell. As V1 is discharged, from the next cycle 𝑆𝑜𝐶2 will be greater than 𝑆𝑜𝐶1 by a very small difference and hence V2 will be considered cell corresponding to max SoC and will be discharged to charge the lowest SoC cell. As V1 and V2 are taking turns getting discharged, these two are effectively discharging together to charge the lowest SoC cell and hence remain equalized with each other. This process is repeated till all cells get equalized (having difference less than tolerance value). Flowchart for the whole process is explained in Fig 4.4. 43 Start Calculate SOC of all the cells Calculate SOCmax and SOCmin from all the cells Open all Equalization switch Yes SOCmax and SOCmin within tolerance (equilized) No Transfer charge from SOCmax cell to inductor in the first half by switching appropriate switches Transfer charge from inductor to the SOCmin cell in the second half by switching appropriate switches Fig 4.4. Flowchart of active charge equalization technique used. 4.2. Effects of Duty Ratio on the Charge Equalization Time Let the whole charging and discharging cycle be of switching time period 𝑇𝑠 or frequency 𝑓𝑠. Let D be the ratio of discharging time and the whole switching time period; and D’ be the ratio of charging time and the whole switching time period. It can be easily observed that D=1D’. Let us assume that the inductor L is working in CCM to maximize the equalization current of the batteries for optimal utilization. If we observe in Fig 4.2 (a), When inductor L is getting charged, the current flowing through the circuit is given by the formula 𝑉.𝑡 …(4.2.1) 𝐼𝐿1 = 𝐼𝑚𝑖𝑛 + 𝐿 where 𝐼𝑚𝑖𝑛 is the current at the instant when discharging starts and t is the time since discharging of the inductor and t<D.𝑇𝑠 Value of D determined the time given to the highest SoC battery to discharge and transfer the excess charge. This determined the max value of Equalization current 𝐼𝑒𝑞. Higher the value of D, higher the 𝐼𝑒𝑞 and hence lesser the equalization time. Similarly, if we observe Fig 4.2. (b), When an inductor is getting discharged, the current flowing through the circuit is given by the formula 𝑉.𝑡′ …(4.2.2) 𝐼𝐿2 = 𝐼𝑚𝑎𝑥 − 𝐿 44 where 𝐼𝑚𝑎𝑥 is the current at the instant when charging starts and t is the time since charging of inductor and t’<D’.𝑇𝑠 Value of D’ determined the time given to the lowest SoC battery to charge. This determines the value of Equalized SoC. Higher the value of D’, the higher the Equalized SoC and Equalized Voltage of the battery system but it also increases the equalization time. It can be observed that the major limiting factor on Equalization current, and hence the Equalization time of the batteries will be the maximum value of 𝐼𝑚𝑎𝑥 we can safely pass in the circuit and its current carrying capacity. Active charge equalization time and Equalizing Current under various values of D and D’ is shown in Fig 4.7. For optimal use the value of D and D’ needs to be selected depending on the current capacity of the battery, converter operation frequency, and circuit it is designed to operate on. Values should be chosen such that 𝐼𝑚𝑎𝑥 equals the current capacity and the inductor should be working in CCM if possible. Value of 𝐼𝑚𝑎𝑥 is given by the formula: 𝐼𝑚𝑎𝑥 = 𝐼𝑚𝑖𝑛 + 𝑉.𝐷 …(4.2.3) 𝑓𝑠.𝐿 For Boundary CCM condition 𝐼𝑚𝑖𝑛 = 0, hence, 𝐼𝑚𝑎𝑥 = 𝐼𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑦 = 𝑉.𝐷 …(4.2.4) 𝑓𝑠.𝐿 4.3. Parallel Equalization and Complete Equalization Topology Now using this, we designed for equalization of a 2x2 battery stack. Two parallel battery stacks are independently designed to achieve active charge equalization, as well as made to achieve equalization in the parallel stack using Balancing Resistance Technique [34][35]. The Balancing Impedance used to achieve equalization between parallel strings needs to be greater than the impedance of the battery cells used [35]. Although, only 2×2 battery stack is considered here the proposed scheme can be extended for ‘n×m’ stack. Here the individual strings of cell are being balanced individually. Simultaneously there is transfer of energy between parallel strings of cells as it is connected by equalization impedance greater than the impedance of the battery cells used[35]. This along with selfbalancing of parallel-connected cells further aids the cell balancing process. The complete Active Equalization Circuit used is shown in Fig 4.5. 45 Pack +ve terminal Parallel Balancing V1 S15 S11 S26 S12 S25 S22 V2 V4 S14 S13 Ieq S21 V3 L Balancing Impedance (Zb > Rbattery) Pack -ve terminal S24 S23 Ieq L Fig 4.5. Complete active charge equalization circuit used. The advantage of this Active Charge Equalization method is that 1. It needs a much less number of switches compared to other existing techniques 2. Fewer components and fewer switches make the control scheme much simpler. 3. Charge equalization can be done both while the battery is on-load (charging or discharging) and off-load (isolated) and can be easily extended to any number of cells either in series or parallel or both. 4. No need of sorting batteries according to SoCs, will work in any SoC order. 4.4 Results and Discussion The RPBiC topology discussed in chapter 3 has been used to obtain various loading scenarios for the battery stack (charging, discharging and isolated condition). First the charge equalization of a single series string of cells was obtained. Topology also was able to seamlessly transition BMS state from charging to discharging to idle as required. Active charge equalization was obtained under varying conditions and found to be satisfactory as shown in Fig 4.6. Time taken for the cells to obtain Charge equalization came out to be ~ 2000sec (~33 min) during the charging/ discharging condition or isolated condition of BMS and transition seamlessly between states. 46 Series Balancing 2 Series Balancing 1 S16 (a) (b) (c) 47 (d) Fig 4.6. Active charge equalization obtained under (a) Charging (b) Discharging (c) Isolated condition (d) Condition changing from discharging to charging to again discharging. Also as discussed in the section 4.2, the value of D and D’ governs the equalization time, magnitude of equalization current and equalized voltage. String of cells having SoC1 = 38%, SoC2 = 42% and SoC3 = 40% with D = 0.3 and D’ = 0.7 was not able to reach equalization in 1000 seconds. Same cell setup was able to reach at t~750 seconds when value of D = D’ = 0.5 was used. Similarly, same setup was able to obtain equalization at t~133 seconds when value of D is further increased to D = 0.75 and D’ = 0.25. These observations are shown in Fig. 4.7. (a)-(c). (a.i) 48 (a.ii) (b.i) (b.ii) 49 (c.i) (c.ii) Fig 4.7. Charge equalization and equalization current under D-D’ ratio of (a) 30-70 (b) 50-50 (c) 70-30. Similarly charge equalization was extended for two parallel strings and results were obtained during both charging, discharging and isolated conditions as shown in Fig 4.8. It can be observed that the SoCs of individual strings are further approaching to an equilibrium point, they are said to be equalizing. 50 (a) (b) (c) Fig 4.8. Charge equalization of a 2x2 battery stack obtained under (a) Charging (b) Discharging (c) Isolated condition 51 Chapter-5 Conclusion and Future Scope 5.1. Conclusion It can be concluded that a new Reconfigurable Port Bi-directional Battery integrated DC-DC converter topology with active charge equalization was developed in this project following. The new topology and it’s analysis have been described in detail. These include the configuration, working principle and analysis of both the converter and charge equalization technique. The proposed topology was simulated in MATLAB Simulink software to obtain satisfactory results. 5.2. Future Scope Some future scope for the project is optimization of the requirement of three inductors for high voltage gain to reduce device count. Also the proposed charge equalization topology can be further optimized to obtain charge equalization ever faster. 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Choi, Dynamic Resistance Battery Equalization for Capacity Optimization of ParallelConnected Cells, 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia), 2019, pp. 1-6, https://doi.org/10.23919/ICPE2019-ECCEAsia42246.2019.8797006. [36] Gabriele Panzeri, Luigi Piegari, Marco Faifer, Luca Magagnin, A pulsed discharge system with an intermitting partial charge for improved battery efficiency, Journal of Energy Storage, Volume 36, 2021, 102367, ISSN 2352-152X, https://doi.org/10.1016/j.est.2021.102367. [37] Huazhen Fang, Christopher Depcik, Vadim Lvovich, Optimal pulse-modulated Lithium-ion battery charging: Algorithms and simulation, Journal of Energy Storage, Volume https://doi.org/10.1016/j.est.2017.11.007 55 15, 2018, Pages 359-367, ISSN 2352-152X, Biography Siddhartha Suyal was born in Mayur Vihar, Delhi, India in January 1995. He received his B.Tech degree in Electrical and Electronics Engineering in 2016 from National Institute of Technology Hamirpur, Himachal Pradesh. He is currently pursuing his M.Tech Degree in Power Electronics and Drives from National Institute of Technology Delhi. His research interests includes power electronics, dc-dc converters, renewable energy integration and battery management systems. Email address: sidsuyal12288@gmail.com Contact number: +91-9582513237 Permanent Address: 85-D, Pocket 6, M.I.G. Flats, Mayur Vihar Phase-3, Delhi. Pincode-110096 56
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