2024 Dec 10
Final Exam
ECET 227
Final Exercise
Fall 2024
Total Points: 181
Total: 178 pts
____________
name & PUID
You must write your name and PUID to receive any credit for the exam.
You must show all of your work and include units in all appropriate places to receive ANY credit for an
answer: 1. write the equation, 2. replace with numbers, and 3. then write the answer, 4. with units.
Pay attention to the order of variables and units, as they may play a role in the answer
1. Rectifiers (21 pts)
Prob 1 (18 pts)
Given: VRMS Pri = 15.5 V; fPri = 52 Hz; Phase shift = 45°; nPri = 10; nSec = 15; C = 100 µF; RLoad = 1.1 kΩ
turns
10
15
Node A
5
7.5 Node B
5
7.5
Node D
Node E
1N60
RLoad
Node C
1N60
Node F
Figure 1. Rectifier Circuit
a. [5 pts] Carefully sketch the waveshape of the voltage between Node A & F: VAF, and Node F & D:
VFD. The graph should include labeled horizontal and vertical axis, show waveform for two periods, and
scalars (values) on both axis (i.e. time and voltage magnitude).
V (V)
Vmax = 32.2305 V
VFD
Vmin = 29.4131 V
t (s)
VAF
Period = 9.6 ms
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2024 Dec 10
Final Exam
b. [2 pts] Find transformer ratio.
Even though n_pri is 10, but you’re only using
half of it, or 5 windings
n = __________
n = n_pri / n_sec = 5 : 15 = 1/3
c. [3 pts] Find RMS voltage drop between Node A and F.
VAF RMS = __________
VAF_RMS = VAB_RMS = VPri_RMS * ½ * 1/n = 23.25 VRMS
d. [3 pts] Find the Vpeak between Node F and D.
VFD p = __________
VFE p = VAF_RMS * sqrt (2) – V1N60 Diode Forward = 23.25 * sqrt(2) – 0.65 = 32.2305 V
Per datasheet, with ~30 mA current, forward
voltage is 0.65 V
e. [3 pts] Find the peak current between Node F and D (ignore iC).
IFD p = __________
IFE p = VFE p / RLoad = 32.2305 / 1.1k = 29.3 mA
f.
[2 pts] What is the period of the signal between Node F and D?
TFD = __________
fSec = fPri * 2 = 104 Hz
TFE = 1 / fSec = 9.6 ms
g. [3 pts] Find the minimum voltage between Node F and D.
VFD DC = __________
(VFE_min = VFE p * (1 – T_FE / (R * C)) = 32.2305 * (1 – 9.6ms / (1.1k * 100 µF)) = 29.4131 V)
Problem removed from the exam because of ambiguous wording
(asking for minimum and DC voltage)
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2024 Dec 10
Final Exam
2. Waveshape Design (30 pts)
a. [15 pts] Complete the design from Figure 2 that will take the input square wave and produce desired
output across the load resistor.
Complete the schematic. Show all of your work and indicate all component values.
Input
100 V
Output
50 V
0V
-50 V
0V
f = 10 kHz
R1 = 8 kΩ
R2 = 6 kΩ
R3 = 2 kΩ
Figure 2. Design circuit
f = 10 kHz → T = 100 µs; T/2 = 50 µs
R_eq = R1 || (R2 + R3) = 4 kΩ
5 * C * R_eq >> T/2
𝑻⁄ 𝟐
𝟓𝟎 µ𝐬
𝑪 ≫ 𝟓𝑹 = 𝟓∗𝟒 𝐤Ω = 𝟐. 𝟓 𝒏𝑭
𝒆𝒒
→
C = 500 nF
100 V
10 kHz
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2024 Dec 10
Final Exam
b. [15 pts] Complete the design from Figure 3 that will take the input square wave and produce desired
output across the load resistor. Complete the schematic. Show all of your work and indicate all
component values.
Input
5VV
50
550Ω
0V
0V
Output
output
1 ms
0V
15 kΩ
2.5 ms
33 k
2.5 ms
1 ms
Figure 3. Design circuit
To make R evenly above R_supply and below R_load
(which means that it also equals R_tot (R||R_load)+R_supply):
𝑹 = √𝟓 ∗ 𝟏𝟓𝒌 = 𝟐𝟕𝟒 Ω
C will fully react when: 5RC = T/2
C = T / 10R = 2.5e-3 / (10*274) = 912 nF
50 V
400 kHz
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-5
-50VV
2024 Dec 10
Final Exam
3. Transistor Switches (total 65 pts)
V1 = 10 V; V2 = 0 V; VCC = 10 V; RMotor = 12 Ω;
10V
10V
G
10V G
OFF
S P-type
10V
Node A
10V
0V G
0V
OFF D
G
OFF
S
0V Node C
P-type
D
N-type
0V
ON
0V
10V
D
N-type
Node B
S
Figure 4. Switch Circuit
a. [4 pts] Label all terminals of all Qs and Ds in Figure 4: = __________
see figure
b. [4 pts] Label all types of all Qs in Figure 4: = __________
see figure
c. [3 pts] Voltage between Gate and Source of Q1 is: VQ1 GS = __________
VQ1 GS = 10 - 0 = 10 V
d. [2 pts] State of Q1 is: __________
Q1 is ON
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0V
10VG
10V
ON
P-type
D
S
D
G
S
OFF
N-type
G
10V
P-type
D
ON D
0V
S
S
D
G
N-type
0V OFF S
OFF
2024 Dec 10
Final Exam
e. [3 pts] Voltage between Gate and Source of Q 2 is: VQ2 GS = __________
VQ2 GS = 10 - 10 = 0 V
f. [2 pts] State of Q2 is: __________
Q2 is OFF
g. [3 pts] Voltage between Gate and Source of Q3 is: VQ3 GS = __________
VQ3 GS = 0 - 0 = 0 V
h. [2 pts] State of Q3 is: __________
Q3 is OFF
i. [3 pts] Voltage between Gate and Source of Q 4 is: VQ4 GS = __________
VQ4 GS = 0 - 10 = -10 V
j. [2 pts] State of Q4 is: __________
Q4 is ON
k. [4 pts] Voltage at Node A: VNode A = __________
VNode A = 10 V
Q4 is ON, hence R_Q4_ON = ~0 ohm, and V_node_A = Vcc
l. [4 pts] Voltage at Node B: VNode B = __________
VNode B = 0 V
Q1 is ON, hence R_Q1_ON = ~0 ohm, and V_node_B = GND
m. [3 pts] Voltage between Gate and Source of Q5 is: VQ5 GS = __________
VQ5 GS = 10 - 0 = 10 V
n. [2 pts] State of Q5 is: __________
Q5 is ON
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Final Exam
o. [3 pts] Voltage between Gate and Source of Q6 is: VQ1 GS = __________
VQ6 GS = 0 - 0 = 0 V
p. [2 pts] State of Q6 is: __________
Q1 is OFF
q. [3 pts] Voltage between Gate and Source of Q8 is: VQ8 GS = __________
VQ8 GS = 10 - 10 = 0 V
r. [2 pts] State of Q8 is: __________
Q1 is OFF
s. [3 pts] Voltage between Gate and Source of Q 7 is: VQ7 GS = __________
VQ7 GS = 0 - 0 = 0 V
t. [2 pts] State of Q7 is: __________
Q7 is OFF
u. [4 pts] Voltage at Node C: VNode C = __________
VNode C = 0 V
Q5 is ON, hence R_Q5_ON = ~0 ohm, and V_node_C = GND
v. [3 pts] Current through Motor is: IMotor = __________
IMotor = 0 A
w. [2 pts] State of Motor is = __________
Motor is OFF
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2024 Dec 10
Final Exam
4. DC-DC Regulators (total 40 pts)
a. [15 pts] Draw a basic design of a discrete buck regulator. When PWM is OFF, indicate the state of Q
and D, whether L and C are charging or discharging, and major path of the load current. Mark voltage
polarities on all of the elements. Draw PWM, Q / D and load voltages, indicating approximate values.
OFF
~8.9V
~8.9V
~-0.5V
~8.9V
0V
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2024 Dec 10
Final Exam
b. [15 pts] Draw a basic design of a discrete boost regulator. When PWM is ON, indicate the state of Q
and D, whether L and C are charging or discharging, and major path of the load current. Mark voltage
polarities on all of the elements. Draw PWM, Q / D and load voltages, indicating approximate values.
OFF
ON
~12V
~12V
0V
12V
0V
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2024 Dec 10
Final Exam
A discrete buck regulator has an input voltage of 12 Vdc, and produces a load voltage of 5 Vdc into a 10
Ω load. Its switch is driven at 100 kHz. The inductor is 220 µH and capacitor is 330 µF.
c. [2 pts] Calculate load duty cycle DLoad = __________
D = Vload / EEnreg = 5 Vdc / 12 Vdc = 42%
d. [2 pts] Calculate on time ∆t = __________
T = 1 / f = 1 / 100 kHz = 10 µs
∆t = D * T = 0.42 * 10 µs = 4.2 µs
e. [2 pts] Calculate ripple current ∆i = __________
∆i = (VL * ∆t) / L = ((12 V – 5 V) * 4.2 µs) / 220 µH = 134 mApp
f. [2 pts] Calculate average inductor current idc L = __________
idc L = idc Load = VLoad / RLoad = 5 Vdc / 10 Ω = 500 mAdc
h. [2 pts] Calculate peak inductor current ip L = __________
ip L = idc L + 0.5 * ∆i = 500 mAdc + 0.5 * 134 mApp = 567 mAp
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Final Exam
5. PWM & Class D Amplifier (25 pts)
C
A
E3
+E
supply
E
G
E1, E2
high-side
MOS
low level
music
pulse
width
mod
MOS
driver
filter
loud
music
low-side
MOS
B
D
F
Figure 5. Class D Amplifier
a. [6 pts] Carefully draw the circuits of the “PWM” and “bandpass filter” blocks in Figure 5. Label all
components, provide part numbers and their approximate values (ie., what value of R, C you would use):
(200-500 pF)
(2-10 kΩ)
(2-10 kΩ)
(1-6 kΩ)
Approximate
values
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Final Exam
CCouple
LOutput
(100-400 μH)
(200-500 μF)
COutput
RSpeaker
(200-500 pF)
b. [3 pts] In figure below, identify cutoff frequency:
(4-8 Ω)
~40 kHz
fcutoff = __________
0
Gain (dB)
-1
-2
-3
-4
104
103
Frequency (Hz)
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~4*104 Hz
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2024 Dec 10
Final Exam
c. [2 pts] In figure above (Prob 5b), identify (circle appropriate) filter type:
High Pass Filter
Low Pass Filter
Bandpass Filter
For LRC filter in Figure 5 (and Prob 5b), given: VIN = 62 mV; VOUT = 16 V; RSpeaker = 8 Ω; lower cutoff
fLow = 15 Hz, higher cutoff fHigh = fcutoff (Prob 5b);
d. [2 pts] Gain:
AV = __________
AV = VOUT / VIN = 16 / 62m = 258.0645
e. [2 pts] Gain in dB:
dB: = __________
dB = 20 * log10 (AV) = 48.2346 dB
f.
[3 pts] Coupling capacitor:
CCouple = __________
CCouple = 1 / (2 * π * RSpeaker * fLow) = 1 / (2 * 3.14159 * 8 * 15) = 1.3e-03 = 1.3 mF
g. [4 pts] Output capacitor:
COutput = __________
X = RSpeaker * sqrt (2) = 8 * sqrt(2) = 11.3137
COUT = 1 / (2 * π * fHigh * X) = 1 / (2 * 3.14159 * 40k * 11.3137) = 3.5169e-07 = 351.69 nF
h. [3 pts] Output Inductor:
LOutput = __________
LOUT = X / (2 * π * fHigh) = 11.3137 / (2 * 3.14159 * 40k) = 4.5016e-05 = 45.016 μH
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Final Exam
Bonus: Transients & Clippers (total 10 pts)
C
A
D
B
E
Figure 6. RC Circuit: E = 5.1 V; f = 650 Hz; VD ON = 0.65 V; R1 = 50 Ω; R2 = 15 kΩ; R3 = 2.5 kΩ;
R4 = 5 kΩ; RLoad = 7 kΩ; C1 = C2 = 5e-8 F; C3 = 20 nF; C4 = 30 nF
Draw VAE, VAC, VCE , VDE waveforms. Make sure you label horizontal and vertical axis, indicating max
and min (noticeable) values on both axis.
V (V)
+5.1 V
+5.1 V
VAC
t (s)
VCE
1.5 ms
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-5.1 V
2024 Dec 10
Final Exam
V (V)
+5.1 V
VAE
541 μs
ms
t (s)
VDE
-4.356 V (~5.1-0.65=4.4 V)
1 / Req = 1 / (R2 + R3) + 1 / R4 + 1 / R_load
Req = 2.5 kOhm
1 / Ceq12 = 1 / C1 + 1 / C2 (25nF)
1 / Ceq34 = 1 / C3 + 1 / C4 (12nF)
Ceq = Ceq12 + Ceq34 = 25 nF + 12 nF = 37 nF
Tau = Req * Ceq = 2.5 kOhm * 37 nF = 92.5 us
5 Tau = 462.5 us
f = 650 Hz → T = 1.54 ms
T/2 = 769 us
Since T/2 > 5Tau, the circuit DOES have enough time to react
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Final Exam
Appendix
Problem 1
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