Mixed-Signal/RF PDK Checklist
Foundry - TSMC
Process – 0.18um MM/RF
PDK Revision – Version 1.3D, 1/06/06
Page 1 of 2
PDK Support Contact
E-mail pdk@tsmc.com
Foundry Process Documents
Document
Design Manual
(Devices)
Electrical Parameters
Design Layout Rules
Spice Model
RF
Parameters/Modeling
Noise Model
Matching Models
Document Number & Title
Section Revision
Date
T-018-MM-SP-001
T-018-MM-SP-002
1.3
2.0
09/16/2004
04/06/2004
T-018-LO-DR-001
T-018-MM-DR-001
T-018-MM-SP-001
T-018-MM-SP-002
2.5
1.3
1.3
2.0
04/23/2004
03/04/2004
09/16/2004
04/06/2004
T-018-MM-SP-001
1.3
09/16/2004
T-018-MM-DR-001-U1
T-018-MM-DR-001-C1
T-018-LO-DR-001-C1
T-018-MM-SP-001-U1
T-018-MM-SP-001-C1
T-018-MM-SP-001-V1
T-018-MM-SP-001-X1
Included in techfile
1.3b
1.3a
2.5b
1.3e
1.3b
1.3a
1.3a
05/27/2004
03/04/2004
08/06/2004
01/06/2006
01/03/2006
10/27/2004
10/27/2004
ESD Guidelines
DRC
LVS
Parasitic Extraction
Layer Map
EDA Tools Supported and Verified for Use with this PDK
Type
Schematic
Vendor and Tool
Version
Cadence Design Systems, Inc / Composer
5.0.33.500.3
Cadence Design Systems, Inc / Analog Design
5.0.33.500.3
Simulation Control
Environment
Circuit Simulator (A) Cadence Design Systems, Inc / Spectre
5.0.33.500.3
Circuit Simulator (B) Synopsys / Hspice – HspiceS
2005.03
Circuit Simulator (C) Agilent / ADS
RFDE 2003c
Circuit Simulator (D)
Layout Editor
Cadence Design Systems, Inc / Virtuoso VirtuosoXL 5.0.33.500.3
DRC Checker
Cadence Design Systems, Inc / Assura
3.1.4
Mentor Graphics Corporation, Inc / Calibre
v2005.4_8.13
LVS Checker
Cadence Design Systems, Inc / Assura
3.1.4
Form Version 1.3C, 03/24/05
Version Date
12/08/2003
12/08/2003
12/08/2003
12/08/2003
05/04/2005
05/04/2005
Parasitic Extractor
Mentor Graphics Corporation, Inc / Calibre
Cadence Design Systems, Inc / Assura
Mentor Graphics Corporation, Inc / Calibre
Analysis Tools
Form Version 1.3C, 03/24/05
v2005.4_8.13
3.1.4
v2005.4_8.13
05/04/2005
Mixed-Signal/RF PDK Checklist
GDS
P-Params
Sim-Test-A
Sim-Test-B
Sim-Test-C
DRC Test
LVS Test
Pcell Test
X
X
X
X
X
X
X
X
X
X
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X
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X
X
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
7
7
7
7
7
7
6
6
X
X
X
X
X
X
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X
X
X
X
X
X
X
4
4
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
7
6
6
X
X
X
X
X
X
X
X
X
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X
X
X
X
X
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X
3
3
3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
X
X
X
X
X
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X
X
X
X
X
2
2
X
X
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X
X
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X
X
X
X
X
X
X
2
2
X
X
X
X
X
X
X
X
X
X
X
X
Form Version 1.3C, 03/24/05
Sim-Test-D
SDL Net
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Sim-Net-D
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Stat Mod
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HF Noise
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1/f Noise
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Spice-Mod
LVS Net
dioden
dioden3v
Sim-Net-C
Diode
1
1
1
Sim-Net-B
npn
vpnp
vpnp3
Sim-Net-A
BJT
Symbol
nmos2v
nmos2v_mis
nmos2vdnw
nmos3v
nmos3v_mis
nmos3vdnw
nmosmvt2v
nmosmvt3v
nmosnvt2v
nmosnvt3v
pmos2v
pmos2v_mis
pmos3v
pmos3v_mis
pmosmvt2v
rfnmos2v
rfnmos2v_mis
rfnmos3v
rfnmos3v_mis
rfpmos2v
rfpmos2v_mis
rfpmos2v_nw
rfpmos2v_nw_
mis
rfpmos3v
rfpmos3v_mis
rfpmos3v_nw
rfpmos3v_nw_
mis
Terminals
Device
Name
MOS
Comment
Device
Type
Foundry - TSMC
Process – 0.18um MM/RF
PDK Revision – Version 1.3D, 1/06/06
Page 2 of 2
diodenw
diodenw3v
diodep
diodep3v
2
2
2
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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X
X
X
X
X
2
2
2
2
X
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X
X
X
X
X
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X
X
X
X
X
X
X
X
X
X
X
X
X
X
CAP
mimcap
mimcap_rf
nmoscap
pmoscap
2
3
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
6
14
14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RES
rm1
rm2
rm3
rm4
rm5
rmt
rnhpoly
rnlplus
rnlpoly
rnplus
rnwell
rnwod
rphpoly
rphpoly_rf
rphripoly
rphripoly_rf
rplplus
rplpoly
rplpoly_rf
rpplus
2
2
2
2
2
2
2
3
2
3
2
3
2
3
2
3
3
2
3
3
X
X
X
X
X
X
X
X
X
X
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X
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X
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X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
5
5
5
5
5
9
9
9
9
9
9
9
7
9
7
9
9
6
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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X
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X
X
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X
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X
X
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X
X
X
X
Special
dio_dnwpsub
dio_pwdnw
diodesd3v
lcPad
2
2
2
2
2
2
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
dnwcon
3
2
X
X
X
X
nwcon
psubcon
pwcon
3
3
3
2
2
2
X
X
X
X
X
X
X
X
X
X
X
X
3
3
3
2
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SubNet
Works
VAR
jvar
mos_var
mos_var33
mos_var_b
mos_var_b3
X
Form Version 1.3C, 03/24/05
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
6
6
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IND
ind_std
ind_sym
ind_sym_ct
3
3
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
4
4
X
X
X
X
X
X
X
X
X
Comments
1. The pnp/vpnp/vpnp3 cells don’t have the layout view. It will be automatically generated during the schematic
driven layout procedures.
2. This PDK only provide front-end information for these devices. Users have to provide the layouts and set
those parameters manually depending on the layouts.
3. This PDK only provide front-end information for these devices. These devices are designed for designers to
take the RC substrate network effect into consideration during the design phase. Users have to prepare the
corresponding models for those devices and incorporate them into TSMC’s spice model before running the
simulation.
Form Version 1.3C, 03/24/05
X
X
X
X
X
X
X
X
X