Chapter 6
Memory Organization
1
The Overview of Memory Unit
• A memory unit is a collection of storage cells together
with associated circuits needed to transfer information in
and out of storage.
• The memory stores binary information in groups of bits
called words.
• A word in memory is an entity of bits that move in and
out of storage as a unit.
• A memory word may represent a number, an instruction
code, one or more alphanumeric characters, or any
other binary-coded information.
• Most computer memories use words whose number of
bits is a multiple of 8, 16-bit word contains two bytes
2
and a 32-bit word is made up of four bytes.
The Overview of Memory Unit, … cont’
• The internal structure of a memory unit is specified by the
number of words it contains and the number of bits in
each word.
• Special input lines called address lines select one
particular word.
• Each word in memory is assigned an identification
number, called an address.
• The address is starting from 0 and continuing with 1,2,3,
up to 2k – 1 where k is the number of address lines.
• The selection of a specific word inside the memory is
done by applying the k-bit binary address to the address
lines.
3
The Overview of Memory Unit, … cont’
• A decoder inside the memory accepts the address and
opens the paths needed to select the bits of the specified
word.
• Computer memories may range from 1024 words,
requiring an address of 10 bits, to 232 words, requiring 32
address bits.
• It is customary to refer to the number of words (bytes) in
a memory with one of the letters: K (kilo),M (mega), or G
(giga).
• K is equal to 210,M is equal to 220 , and G is equal to 230.
• Thus 64K = 216, 2M = 221, and 4G = 232.
• Two major types of memories are used in computer
system: RAM and ROM.
4
MEMORY HIERARCHY
Memory Hierarchy is to obtain the highest possible access speed
while minimizing the total cost of the memory system
Increase in
capacity and
access time
Increase in
cost per bit.
5
Main memory
• It stores data and program during computer
program operation.
• It uses semiconductors technology hence known
as semiconductor memory.
• Central storage unit in a computer system
• Large memory
• Types:
– RAM (Random access memory)
– ROM (Read only memory)
6
Main memory, … cont’
• Memory Connection to CPU
– RAM and ROM chips are connected to a CPU through
the data and address buses.
– The low-order lines in the address bus select the byte
within the chips and other lines in the address bus select a
particular chip through its chip select inputs.
• Most of the main memory in a general-purpose
computer is made up of RAM integrated circuit chips.
• Originally, RAM was used to designate a read/write
memory to distinguish it from a read-only memory.
• Among other things, the ROM portion of main
memory is needed for storing an initial program
called a bootstrap loader or known as BIOS.
7
Cache
• Small amount of fast memory.
• Sits between normal main memory and CPU
• May be located on CPU chip or module
– An entire blocks of data is copied from memory to the
cache because the principle of locality tells us that
once a byte is accessed, it is likely that a nearby data
element will be needed soon.
8
Cache operation - overview
• CPU requests contents of memory location;
• Check cache for this data;
• If present, get from cache (fast);
• If not present, read required block from main
memory and load to cache;
• Then deliver from cache to CPU;
• Cache includes tags to identify which block of
main memory is in each cache slot;
• See fig. in next slide.
9
Cache/Main Memory
Structure:
10
Hit and miss in Cache
• Based on above procedure, we have terminologies
with a cache as follows:
– It is said hit when data is found at a given memory level.
– Also said miss when data is not found.
– The hit rate is the percentage of time data is found at a
given memory level.
– The miss rate is the percentage of time it is not.
– The hit time is the time required to access data at a given
memory level.
– The miss penalty is the time required to process a miss,
including the time that it takes to replace a block of
memory plus the time it takes to deliver the data to the
processor.
• See cache read operation diagram in next slide .. ->
11
Cache Design
• If memory contains 2n addressable words:
– Memory can be broken up into blocks with K words per
block; number of blocks = 2n / K
– Cache consists of C lines or slots, each can contain of K
words from memory blocks; C << M; for M number of
blocks in main memory.
Memory
Cache
C
Line 0
Line 1
…
Line C-1
M
Block 0
Block 1
…
Block (2n/K)-1
12
Cache Design, … cont’
• How to map blocks of memory to lines in the
cache?
• We need the following to perform mapping:
– Size
– Mapping Function
– Replacement
Algorithm
– Write Policy
– Block Size
– Number of Caches
• Each explained next… ->
13
Cache Address: Logical/ Physical
(a) Logical cache
(b) Physical cache
14
Cache size:
• We would like the size of the cache to be small enough so that
the overall average cost per bit is close to that of main memory
alone;
and
• large enough so that the overall average access time is close to
that of the cache alone.
• There are several other motivations for minimizing cache size.
• The larger the cache, the larger the number of gates involved in
addressing the cache.
• The result is that large caches tend to be slightly slower than
small ones—even when built with the same integrated circuit
technology and put in the same place on chip and circuit board.
• The available chip and board area also limits cache size.
• Because the performance of the cache is very sensitive to the
nature of the workload, it is impossible to arrive at a single
“optimum” cache size.
15
Mapping Function
• Suppose we have the following configuration:
– Word size of 1 byte;
– Cache of 16 bytes;
– Cache line / Block size is 2 bytes i.e. cache is 16/2
= 8 (23) lines of 2 bytes per line, will need 8 addresses
for a block in the cache;
– Main memory of 64 bytes • 6 bit address needed to reference 64 bytes (26= 64);
• 64 bytes / 2 bytes-per-block  32 Memory Blocks;
– Somehow we have to map the 32 memory
blocks to the 8 lines in the cache.
– Multiple memory blocks will have to map to the
same line in the cache.
16
Direct Mapping
• Simplest mapping technique - each block of main
memory maps to only one cache line, i.e. if a
block is in cache, it must be in one specific place.
• Formula to map a memory block to a cache line:
=> i = j mod c
• i=Cache Line Number;
• j=Main Memory Block Number;
• c=Number of Lines in Cache;
– i.e. we divide the memory block by the number of
cache lines and the remainder is the cache line
address.
17
Direct Mapping with C=4
• Shrinking our example to a cache line size of 4
slots (each slot/line/block still contains 4 words):
– Cache Line
•0
•1
•2
•3
Memory Block Held
0, 4, 8, …
1, 5, 9, …
2, 6, 10, …
3, 7, 11, …
18
Direct-Mapped Cache
Cache 4 Byte Direct
Memory
Index Mapped Cache
Address Memory
0
0
1
1
2
2
3
3
4
5
6
7
8
• Cache Location 0 can be
9
A
occupied
by
data
from:
B
C
– Memory location 0, 4, 8, ...
D
– In general: any memory location
E
19
F
that is multiple of 4
Direct Mapping Address Structure
• Address is in three parts:
– Least Significant w bits identify unique word within a
cache line.
• w must be enough bits to address a specific word in a cache
line; e.g. if 4 words per cache line, then we need 2 bits for w.
– Next Significant s bits specify which line this address
maps into.
• s must be enough bits to address a specific line in the cache;
e.g. if 16 cache lines, then we need 4 bits for s.
– Remaining t bits used as a tag to identify the memory
block.
Tag t
Line or Slot s
Word w
2
4
2
8 bit address
20
Simplest Cache: Direct Mapped
Block
Address
0000two0
1
2
3
0100two4
5
6
7
1000two8
9
10
11
1100two12
13
14
15
21
Memory
Cache
Index
4-Block Direct
Mapped Cache
0
1
2
3
• Block Size = 32/64 Bytes
• Cache Block 0 can be
occupied by data from:
Memory block 0, 4, 8, 12
- Cache Block 1 can be
occupied by data from:
Memory block 1, 5, 9, 13
1999 ©UCB
Simplest Cache: Direct Mapped
Block
Address
0
1
0010 2
3
4
5
0110 6
7
8
9
1010 10
11
12
13
1110 14
15
Main
Memory
Cache
Index
4-Block Direct
Mapped Cache
0
1
2
3
Memory block address
tag
index
° index determines block in cache
° index = (address) mod (# blocks)
° If number of cache blocks is
power of 2, then cache index is
just the lower n bits of memory
address [ n = log2(# blocks) ]
Simplest Cache: Direct Mapped w/Tag
Block
Address
0
1
0010 2
3
4
5
0110 6
7
8
9
1010 10
11
12
13
1110 14
15
23
Main
Memory
Direct Mapped Cache
cache
index
0
1
2
3
data
tag
11
° tag determines which memory
block occupies cache block;
° tag bits = lefthand bits of address
° hit: cache tag field = tag bits of
address
° miss: tag field  tag bits of addr.
1999 ©UCB
Associative Mapping
• A main memory block can load into any line of
cache.
• Memory address is interpreted as tag and word.
• Tag uniquely identifies block of memory.
• Every line’s tag is examined for a match.
• Cache searching gets expensive.
27
Associative mapping
• A fully associative mapping scheme can overcome the
problems of the direct mapping scheme.
– A main memory block can load into any line of cache;
– Memory address is interpreted as tag and word;
– Tag uniquely identifies block of memory;
– Every line’s tag is examined for a match;
– Also need a Dirty and Valid bit;
• But Cache searching gets expensive!
– Ideally need circuitry that can simultaneously examine all tags
for a match;
– Lots of circuitry needed, high cost;
• Need replacement policies now that anything can get
thrown out of the cache (will look at this shortly).
28
Associative Mapping from Cache to Main Memory
29
Associative
Mapping
Example
Set Associative Mapping
• Cache is divided into a number of sets
• Each set contains a number of lines
• A given block maps to any line in a given set
– e.g. Block B can be in any line of set i
• e.g. 2 lines per set
– 2 way associative mapping
– A given block can be in one of 2 lines in only one set
31
Set Associative Mapping: Example
• 13 bit set number
• Block number in main memory is modulo 213
• 000000, 00A000, 00B000, 00C000 … map to same
set.
32
Mapping From Main Memory to Cache:
v Associative
33
34
Types of External Memory
• Magnetic Disk
– RAID
– Removable
• Optical
– CD-ROM
– CD-Recordable (CD-R)
– CD-R/W
– DVD
• Magnetic Tape
35
Magnetic Disk
• Disk substrate coated with magnetizable material
(iron oxide…rust)
• Substrate used to be aluminium
• Now glass
– Improved surface uniformity
• Increases reliability
– Reduction in surface defects
• Reduced read/write errors
– Lower flight heights (See later)
– Better stiffness
– Better shock/damage resistance
36
Magnetic Disk
37
Read and Write Mechanisms
•
•
•
•
Recording & retrieval via conductive coil called a head
May be single read/write head or separate ones
During read/write, head is stationary, platter rotates
Write
– Current through coil produces magnetic field
– Pulses sent to head
– Magnetic pattern recorded on surface below
• Read (traditional)
– Magnetic field moving relative to coil produces current
– Coil is the same for read and write
• Read (contemporary)
– Separate read head, close to write head
– Partially shielded magneto resistive (MR) sensor
– Electrical resistance depends on direction of magnetic field
– High frequency operation - Higher storage density and speed
38
Data Organization and Formatting
• Concentric rings or tracks
– Gaps between tracks
– Reduce gap to increase capacity
– Same number of bits per track (variable packing
density)
– Constant angular velocity
• Tracks divided into sectors
• Minimum block size is one sector
• May have more than one sector per block
39
Disk Data Layout
40
Fixed/Movable Head Disk
• Fixed head
– One read write head per track
– Heads mounted on fixed ridged arm
• Movable head
– One read write head per side
– Mounted on a movable arm
41
Removable or Not
• Removable disk
– Can be removed from drive and replaced with
another disk
– Provides unlimited storage capacity
– Easy data transfer between systems
• Nonremovable disk
– Permanently mounted in the drive
42
Multiple Platter
• One head per side
• Heads are joined and aligned
• Aligned tracks on each platter form cylinders
• Data is striped by cylinder
– reduces head movement
– Increases speed (transfer rate)
43
Multiple Platters
44
RAID
• Redundant Array of Independent Disks
• Redundant Array of Inexpensive Disks
• 6 levels in common use
• Not a hierarchy
• Set of physical disks viewed as single logical drive
by O/S
• Data distributed across physical drives
• Can use redundant capacity to store parity
information
45
RAID 0
• No redundancy
• Data striped across all disks
• Round Robin striping
• Increase speed
– Multiple data requests probably not on same disk
– Disks seek in parallel
– A set of data is likely to be striped across multiple
disks
46
RAID 1
• Mirrored Disks
• Data is striped across disks
• 2 copies of each stripe on separate disks
• Read from either
• Write to both
• Recovery is simple
– Swap faulty disk & re-mirror
– No down time
• Expensive
47
RAID 2
• Disks are synchronized
• Very small stripes
– Often single byte/word
• Error correction calculated across corresponding
bits on disks
• Multiple parity disks store Hamming code error
correction in corresponding positions
• Lots of redundancy
– Expensive
– Not used
48
RAID 3
• Similar to RAID 2
• Only one redundant disk, no matter how large
the array
• Simple parity bit for each set of corresponding
bits
• Data on failed drive can be reconstructed from
surviving data and parity info
• Very high transfer rates
49
RAID 4
• Each disk operates independently
• Good for high I/O request rate
• Large stripes
• Bit by bit parity calculated across stripes on
each disk
• Parity stored on parity disk
50
RAID 5
• Like RAID 4
• Parity striped across all disks
• Round robin allocation for parity stripe
• Avoids RAID 4 bottleneck at parity disk
• Commonly used in network servers
• N.B. DOES NOT MEAN 5 DISKS!!!!!
51
RAID 6
• Two parity calculations
• Stored in separate blocks on different disks
• User requirement of N disks needs N+2
• High data availability
– Three disks need to fail for data loss
– Significant write penalty
52
53
RAID 0, 1, 2
54
RAID 3 & 4
55
RAID 5 & 6
56
Data Mapping For RAID 0
57
Optical Storage CD-ROM
• Originally for audio
• 650Mbytes giving over 70 minutes audio
• Polycarbonate coated with highly reflective
coat, usually aluminium
• Data stored as pits
• Read by reflecting laser
• Constant packing density
• Constant linear velocity
58
Magnetic Tape
• Serial access
• Slow
• Very cheap
• Backup and archive
• Linear Tape-Open (LTO) Tape Drives
– Developed late 1990s
– Open source alternative to proprietary tape
systems
59
Magnetic tape/ cassette recorder
60