Chapter 2-3
Real-Mode Software
Architecture and Programming
of Intel Architecture-32
Processors
ECE3166 Advanced Microprocessors
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Real-Addressed Mode
• 80286, 80386, 80486 and Pentium processors can operate in
either real-addressed mode or protected-addressed mode.
• Following the system reset, 80286, 80386DX are initialized in
real-mode:
➢ While in real mode, they operate like a high-performance
8086/8088 (e.g., 16-MHz 80386 is 10x faster than 5-MHz 8086).
➢ They can execute what is called the base instruction set, which is
object code compatible with 8086/8088.
➢ In this mode, the address space is limited to 1 MB using the
lower order address lines A0-A19 (the high address line A20-A31
are inactive).
➢ The segmented memory addressing mechanism of the 8086 is
retained, with each segment limited to 64 KB.
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Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Protected-addressed Mode
• This mode offers enhanced system-level features.
• All instructions and features are available.
• It also includes new instructions to support multitasking
operating system
• Other differences between protected mode and real mode
from a programmer’s viewpoint are:
➢ The increased memory space (larger memory space in
protected mode).
➢ A differing addressing mechanism.
➢ Protection level (higher protection level in protected
mode).
3
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
80286 Microprocessor Family
• Introduced by Intel in 1982.
• 16-bit architecture microprocessor, and almost
identical to 8086/8088.
• Addressed a 16MB memory.
• Additional pipelining to provide higher performance.
• Enhanced with new instructions.
• Address and data buses are demultiplexed to simplify
system design.
4
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Internal Architecture of 80286
4 independent
processing units:
 bus unit (BU)
 instruction unit (IU)
 execution unit
(EU)
 address unit (AU) 5
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Real-Mode Software Model of 80286
• In real mode, the 80286 operates
like a high performance 8086:
10-MHz 80286 is 7x faster than
10-MHz 8086.
• 80286 has 15 internal registers,
where 14 of them are identical to
8086.
• The address and data buses are
demultiplexed (16-bit data bus
and 24-bit address bus).
• A new register, the machine
status word register (MSW).
• The only active bit in MSW in the
real mode is the protected mode
enable (PE), which is used to
switch it from real to protected
mode.
0000016
8088/8086 MPU
IP
Code segment
(64kbytes)
CS
DS
SS
ES
AH AL
BH BL
CH CL
DH DL
External
memory address
space
000016
Data segment
(64kbytes)
Input/output
address space
AX
BX
CX
DX
Stack segment
(64kbytes)
SP
BP
SI
FFFF16
Extra segment
(64kbytes)
DI
SR
MSW
FFFFF16
6
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
80386 Microprocessor Family
• In 1985, Intel announced the 80386DX, which is a 32-bit uP
and a logical extension of the Intel 80286.
• It provides on-chip memory-management facilities include
address translation registers, advanced multitasking
hardware, a protection mechanism, and paged virtual
memory.
• It includes separate 32-bit internal and external data paths
along with eight general-purpose 32-bit registers.
• It can handle 8, 16 and 32-bit data types.
• It has separate 32-bit data and address pins and generates a
32-bit physical address.
• The 80386 can directly address up to 4GB of physical memory
and 64TB of virtual memory.
Note: iAPX432 is Intel first 32-bit microprocessor released in 1981
7
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Continue …
• The 80386 can be operated from 12.5, 16, 20, 25 or 33-MHz
clock.
• The 80386 is designed using high-speed CHMOS III
technology.
• The 80386 is highly pipelined and can perform instruction
fetching, decoding and memory management functions in
parallel.
• The on-chip memory management and protection hardware
translates logical addresses to physical addresses and provides
the protection rules required in a multitasking environment.
8
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Internal Architecture of 80386DX
• The 80386 includes 6 functional units that operate in parallel for pipelined
processing: Fetching, decoding, execution, memory management and bus
access for several instructions are performed simultaneously.
Bus Control
3-Input
Adder
Adder
Request
Prioritizer
32
34
32
Descriptor
Registers
Effective address bus
32
Page cache
Protection
Test Unit
Multiply /
Divide
Status Flags
Register File
ALU
Decode and
Sequencing
Control ROM
ALU Control
Control
Displacement
Barrel
shifter,
Adder
Internal control bus
Control and
Attribute
PLA
Linear address bus
bus
Limit and
Attribute
PLA
Prefetcher /
Limit
Checker
Instruction
Decoder
3-Decoded
instruction
Queue
Instruction
Predecode
Code
Stream
32-bit
Code fetch / Page table fetch
Effective address bus
32
16 Byte
Code Queue
HOLD, INTR, NMI
ERROR, BUSY
RESET, HLDA
Control
Paging Unit
Physical address bus
Segmentation Unit
Address
Driver
BE0# - BE3#,
A2 – A31
Pipeline /
Bus Size
Control
M/IO#, D/C#,
W/R#, LOCK#,
ADS#, NA#,
BS16#, READY#
MUX /
Transceivers
D0 – D31
80386
Instruction
Prefecher
Dedicated ALU bus
32
9
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Segmentation Unit
Paging Unit
Bus Control
3-Input
Adder
Adder
Request
Prioritizer
32
34
32
Descriptor
Registers
Effective address bus
32
Page cache
Multiply /
Divide
bus
Decode and
Sequencing
Status Flags
Register File
ALU
Control ROM
ALU Control
Control
EXECUTION
UNIT
Displacement
Internal control bus
Barrel
shifter,
Adder
Control and
Attribute
PLA
Linear address bus
Limit and
Attribute
PLA
Prefetcher /
Limit
Checker
Instruction
Decoder
3-Decoded
instruction
Queue
Instruction
Predecode
Code
Stream
32-bit
HOLD, INTR, NMI
ERROR, BUSY
RESET, HLDA
Control
Effective address bus
Physical address bus
SEGMENT
UNIT
Protection
Test Unit
Part 3
PAGING
UNIT
Code fetch / Page table fetch
Chapter 2
32
Address
Driver
BE0# - BE3#,
A2 – A31
Pipeline /
Bus Size
Control
M/IO#, D/C#,
W/R#, LOCK#,
ADS#, NA#,
BS16#, READY#
MUX /
Transceivers
D0 – D31
BUS
UNIT
80386
16 Byte
Code Queue
Instruction
Prefecher
Dedicated ALU bus
DECODE UNIT
32
PREFETCH
UNIT
10
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Block Diagram
Segmen
-tation
Unit
Execution
Unit
Decode Unit
Paging
Unit
Bus
Unit
Prefetch
Unit
11
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Functional Units
• Bus unit
➢ Interfaces between the 80386 with memory and I/O.
➢ It provides a 32-bit data bus, a 32-bit address bus and the
signals needed to control transfers over the bus (8-bit, 16-bit
and 32-bit data transfers are supported).
➢ These buses are demultiplexed like those of the 80286 i.e. the
80386DX has separate pins for its address and data bus lines.
The demultiplexing of address and data results in higher
performance and easier hardware design.
• Prefetch unit
➢ Implements a mechanism known as instruction stream queue.
➢ The unit prefetches instructions when the bus interface unit is
not executing bus cycles. It then stores them in a 16-byte
instruction queue for decoding by the instruction decode unit.
12
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Continue …
• Decode unit
➢ Translates instructions from the instruction queue (reads
machine code instructions from the output side of the prefetch
queue and decodes them into the microcode instruction format
used by the execution unit).
➢ The decoded instructions are then stored in an instruction queue
(FIFO) for processing by the execution unit.
• Execution unit
➢ Processes the instructions from the instruction queue. Contains:
Control unit : contains microcode and parallel hardware for fast
multiply, divide and effective address calculation.
Data unit : includes an ALU, 8 general-purpose registers and a 64-bit
barrel shifters for performing multiple bit shifts in one clock.
Protection test unit: checks for segmentation violations under the
control of the microcode.
13
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Continue …
• Segmentation unit
➢ Contains dedicated hardware for performing high-speed address
calculations, logical-to-linear address translation and protection
checks.
• Paging unit
➢ Implements the protected mode paging model of the 80386DX’s
memory management.
➢ It contains the translation-lookaside-buffer (TLB) that store the
recently used page directory and page table entries.
14
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Real-Mode Software Model of 80386
• 80386DX includes 6 16-bit registers and 24 32-bit registers.
• The registers (or part of registers) that are important to real-mode
application are highlighted
➢ Nine of them – the data registers (EAX, EBX, ECX and EDX), the pointer
registers (EBP and ESP), the index registers (ESI and EDI) and the flag
registers (FLAGS) – 32-bit length.
➢ The instruction pointer (IP) and segment registers (CS, DS, SS and ES)
are of 16-bit length.
• Several new registers are
➢ 2 more data segment registers FS and GS
➢ control register zero (CR0). The 5 least significant bits of this register
are MSW.
• Since it has 6 segment registers, not 4 as in the 8086 and 80286, 6
64KB segments are active at a time (384KB)
• 64KB for code, 64KB for stack, 256KB for data
15
0000016
80386 MPU
31
16 15
0
IP
15
Code segment
(CS)
(64kbytes)
0
CS
DS
SS
ES
FS
GS
31
EAX
EBX
ECX
EDX
ESP
EBP
ESI
EDI
16 15
87
AH AL
BH BL
CH CL
DH DL
External
memory address
space
000016
Data segment
(DS)
(64kbytes)
Input/output
address space
0
AX
BX
CX
DX
Stack segment
(SS)
(64kbytes)
FFFF16
SP
BP
SI
DI
Extra segment
(ES)
(64kbytes)
Flags
CR0
CR1
CR2
CR3
Data segment
(FS)
(64kbytes)
DR0
DR1
DR2
DR3
DR4
Data segment
(GS)
(64kbytes)
DR5
DR6
DR7
TR6
TR7
FFFFF16
16
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
The 80486 Microprocessor Family
• In 1989, Intel announced the 2nd generation 32-bit uP, the 80486 family,
the first product is the 80486DX.
• The 80486DX is the first member of 80x86 family with a high
performance reduced-instruction-set-computer (RISC) integer code, it is
best described as complex reduced-instruction-set-computer (CRISC).
• Among the major changes that greatly improved the performance:
i. On-chip floating-point math processor (the 80486SX does not have).
ii. On-chip code and data cache memory.
iii. Enhancement of the coding of instructions in the control ROM, so that the
execution speed of most instructions can be done in just 1 clock cycle.
iv. Code queue in the prefetch unit has been doubled to 216bytes = 32 bytes
(more instructions to be held on-chip ready for decode and execution).
v. Translation lookaside buffer (TLB) in paging unit uses an improved algorithm.
vi. Improvement on bus interface unit further speed-up the processing
operation.
17
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Internal Architecture of 80486
18
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Real-Mode Software Model of 80486
• The 80486 has essentially the
same internal registers as the
80386, except:
➢ In the control register 0 (CR0),
besides PE bit (which is used to
switch it from real to protected
mode), two other bits, caches
disable (CD) and not writethrough (NW), are active (they
are used to enable and configure
the operation of the on-chip
cache memory).
➢ the 80486 DX has more registers
in its real-mode model to
support the operation of the
floating-point coprocessor
80486 MPU
31
16 15
0
15
0
IP
CS
DS
SS
ES
FS
GS
31
EAX
EBX
ECX
EDX
ESP
EBP
ESI
EDI
16 15
87
AH AL
BH BL
CH CL
DH DL
0
AX
BX
CX
DX
SP
BP
SI
DI
Flags
CR0
CR1
CR2
CR3
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TR3
TR4
TR5
TR6
TR7
19
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Pentium Microprocessor Family
• Pentium was introduced in 1993.
• Its 32-bit architecture is enhanced with a 64-bit external data
bus and a variety of internal data paths that are 64 bits, 128
bits, or 256 bits wide.
• Among the major changes that greatly improved the
performance:
➢ An advanced superscalar pipelined internal architecture (has more
than 1 execution unit).
➢ Each execution unit has its own ALU, address generation circuitry and data
cache interface.
➢ They are identified as the U pipeline and the V pipeline.
➢ This parallel processing gives Pentium the ability to execute more than 1
instruction per clock cycle.
➢ Independent code and data caches.
➢ High-performance floating-point unit (employs faster hardwired,
instead of microcoded)
20
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Internal Architecture of Pentium
21
Chapter 2
Section 1: Internal Architecture and Real-Mode Software Architecture of the Intel x86 Microprocessors.
Part 3
Status Register (EFLAGS)
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
ID
VIP
VIF
AC
VM
RF
0
NT
IOPL
IOPL
OF
DF
IF
TF
SF
ZF
0
AF
0
PF
1
CF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
• The lower 16 bits, called FLAGS or SR, are used in 8086/8088.
• The new flags (system flags) are:
➢ Identification Flag (ID) [Pentium+]: To indicate that the MPU supports the CPUID instruction
➢ Virtual Interrupt Pending Flag (VIP) [Pentium+]: Together with VIF, enables each application
program in multitasking environment to have virtualized versions of the system's IF
➢ Virtual Interrupt Flag (VIF) [Pentium+]: A virtual image of the IF flag used with VIP
➢ Alignment Check Flag (AC) [486+]: Setting this flag and the AM bit in CR0 enables alignment
checking on memory references
➢ Virtual Mode Flag (VM) [386+]: Set this bit to enable the MPU operate in virtual 8086 mode
➢ Resume Flag (RF) [386+]: Set it to temporarily disable debug faults so that an instruction can
be restarted after a debug fault without immediately causing another debug fault
➢ Nested Task Flag (NT) [286+]: When it is set indicates that the currently executing task is
nested within another task and has a valid link to the previous task
➢ Input/Output Privilege Level Flags (IOPL) [286+]: The IOPL encoded values (0,1,2,3) indicate
the numerically maximum current privilege level permitted to access I/O address space
22