Analog Integrated Circuits and Signal Processing, 34, 265–269, 2003
C 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.
High-Speed High-Precision CMOS Current Conveyor
B. CALVO∗ , S. CELMA, P. A. MARTÍNEZ AND M. T. SANZ
Grupo de Diseño Electrónico, Facultad de Ciencias at the Universidad de Zaragoza, Zaragoza, Spain Fax: +34 976 762143
E-mail: uelec@posta.unizar.es
Abstract. In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel highperformance voltage follower topology is proposed. Post-layout simulation results from a 0.8 µm design supplied
at 3.3 V show very low resistance at node X (< 50 ), high frequency operation (∼100 MHz), high precision in
the voltage and current transference and reduced offset. As application examples, a V-I converter and a current
feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than
±100 V/µs.
Key Words: CMOS analogue circuits, current conveyor, current-mode signal processing, current feedback
operational amplifier
1.
Introduction
The second generation current conveyor (CCII) is a
versatile analogue component widely used as an elementary cell in applications of signal processing and as
a basic building block in universal active elements [1].
Basically, an ideal CCII is a three terminal device
(X, Y, Z) composed of a voltage follower—between
terminals Y and X− and a positive (CCII+ ) or a negative (CCII− ) current follower—between terminals X
and Z−. In practice, CCII implementations should simultaneously exhibit low gain and low DC errors, high
linearity and wide frequency response. To this end, a reduced input resistance at node X is usually required [2].
The first implementations of CCII were realised
in bipolar technology [3]. Today, operation over the
hundred megahertz range and slew-rate levels better
than 1000 V/µs can be achieved by means of classAB topologies fabricated with modern complementary
bipolar processes. Recently, several innovative CMOS
CCII realisations have been reported aiming to prove
that CMOS is also a viable technology for the implementation of a high performance current conveyor.
The difference between them lies mainly in the diverse
∗ Address correspondence to: Belen Calvo. Área de Electrónica,
Dept. Ingenierı́a Electrónica y Comunicaciones, Facultad de Ciencias, Universidad de Zaragoza, Pedro Cerbuna 12, Zaragoza,
E-50009 (Spain), Tel.: +34 976 761000, ext. 3427, Fax:
+34 976 762143. E-mail: becalvo@posta.unizar.es
input voltage buffer topologies used. When improving
the features of the CMOS version an unavoidable dichotomy arises: high precision or high speed.
High-precision voltage transference can be obtained
by using negative feedback closed-loop schemes such
as a differential pair. Nevertheless, these architectures
exhibit a limited bandwidth, comparable to that of a
conventional op-amp. For instance, a tracking error
lower than 1% within an input range of ±0.3 V has
been obtained for a ±1.5 V circuit over a bandwidth of
10 MHz [4].
To obtain higher frequency operation and better dynamic behaviour open-loop structures must be used,
such as those based on the translinear principle. Additionally, the use of class-AB configurations increases
slew-rate. Open-loop structures, however, are very sensitive to the body effect in single-well technologies
and, consequently, high offset voltage (up to 0.4 V)
and high gain error (almost 20%) are exhibited. On the
other hand, if not reduced through feedback schemes,
they also present a relatively high resistance at node X ,
which further degrades the voltage transfer precision [5].
In this paper we propose a new high-performance
class-AB CCII+ topology. It exploits a new openloop voltage buffer architecture in a standard CMOS
technology which presents a high speed performance
while providing a precision in the voltage transference
almost as high as the closed-loop counterparts.
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Calvo et al.
2.
Circuit Description
where gmi represents the transconductance of transistor Mi .
In order to guarantee stability, the following necessary condition must be fulfilled
The proposed voltage follower is based on the conceptual scheme shown in Fig. 1. This circuit consists of a
complementary source follower cascade, M1,2 , and two
complementary level shifters, M1,2 . In this way, the offset voltage is efficiently cancelled and body effect neutralisation occurs if identical transistors M1,2 = M1,2
are used. Further, the positive feedback path implemented by the simple current mirror M3,4 reduces the
output resistance [6], which is given by
RX ≈
1
gm4
−
gm2 gm1 · gm3
gm1 gm3
1
·
>
gm2 gm4
1 + gm2 · R X load
where RX load represents the load resistance at node X .
It is worthy noting that this stability condition is automatically fulfilled for any positive value of R X .
Note that the use of this feedback scheme is not possible in single source follower based structures since
there is a coupling between terminal impedances.
Figure 2 shows the proposed class-AB CCII+ ,
where M3,4 (M7,8 ) form the complementary source
follower cascade and their respective level shifters
are implemented with M1,2 (M5,6 ). Transistors M9,10,17
(M11,12,18 ) constitute the positive feedback path
sampling the output current of M7 (M8 ) and adjusting
the bias current of M4 (M3 ).
The output current stage is realised by means of
a high-swing high-impedance cascode current mirror [7]. Transistors M13,14 (M15,16 ) reproduce at node Z
the current flowing from node X . In this way high
output impedance and low voltage headroom can be
simultaneously achieved. Some authors have recently
proposed a solution based on a two long tail feedbackstabilized structure needing several precise current
sources to avoid the current mirror input dominant
pole [8]. The current transference bandwidth is then
(1)
Fig. 1. Scheme of the improved class-A voltage follower.
Vdd
M9
M17
M20
M19
M10
M22 M23
M1
M3
M5
M7
M2
M4
M6
M8
M11
M27
M14
X
Y
M28
M24
M13
M21
50uA
(2)
M25
Z
M15
M26
M12
M18
Vss
Fig. 2. Class-AB CCII+ with improved voltage follower.
M16
High-Speed High-Precision CMOS Current Conveyor
increased but in contrast complex and hungry structures must be used.
267
Rx load = 1k
–60
Rx load = 5k
Simulation Results
Iz/Vy (dB)
The conveyor shown in Fig. 2 has been laid out and
simulated using a standard 3.3 V 0.8 µm process. The
main performances are summarised in Table 1. We have
to mention that the reduced power supply voltage imposes a severe limitation of the output voltage range.
Although our aim has not been to design competitive
low-voltage current conveyor, the proposed structure is
able to provide good performance even with a supply
as low as 3.3 V.
To test the feasibility of the proposed CCII+ some
basic applications have been simulated. Figure 3 shows
the frequency response of a V-I converter implemented
with the proposed class-AB conveyor for different values of the load resistance at node X .
A current feedback operational amplifier (CFOA)
has also been designed based on this structure and followed by a conventional class-AB voltage buffer. Notice that the precision requirements of this buffer can
be relaxed due to its operation in closed-loop.
A very useful property of the CFOA is that there
is no gain-bandwidth trade-off, a fact only if the resistance at node X has a low value [9]. Figure 4 shows
the almost constant bandwidth obtained for an inverting gain configuration with compensating capacitance
CC = 0.7 pF.
Another important advantage of the CFOA is its very
high slew-rate when class-AB structures are used. For
the same compensating capacitance, results better than
±100 V/µs have been obtained for both inverting and
VY
–100
CCII+
Z
Y
X
IZ
RZ
RX
–120
1E+0
1E+3
1E+6
frequency (Hz)
1E+9
Fig. 3. Frequency response of the V-I converter.
RF
100
R1
VS
X
Y
CFOA
Z
VO
CC
10
0
–5
gain (V/V)
–10
Fig. 4. Bandwidth vs. gain for an inverting stage (R1 = 9 k, 1.8 k,
900 ; R F = 9 k): ■ without reduction of R X , ▲ with reduction
of R X .
Table 1. Summary of CCII+ performance.
Technology
Supply voltage (Vdd − Vss )
Quiescent power
X Resistance
Y Impedance
Z Impedance
Input offset voltage
Input offset current
DC Gain VX /VY (R X = 10 k)
DC Gain I Z /I X (R Z = 10 k)
Voltage transference BW
Current transference BW
DR VX (THD = −60 dB @ 100 kHz)
Rx load = 10k
–80
BW (MHz)
3.
0.8 µm CMOS
+3.3 V
2.24 mW
42 174 k//1.23 pF
2.24 M//0.21 pF
0.2 mV
50.2 nA
0.953
0.998
87 MHz
70 MHz
65 dB
non-inverting configurations, which are high enough
for many applications.
4.
Conclusions
A new class-AB CMOS current conveyor has been proposed which meets as main characteristics very low
resistance at node X , high speed operation and high
precision in voltage and current transference. The circuit exhibits a better trade-off of precision, speed and
consumption than other previously reported structures.
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Calvo et al.
Its performance has been validated realising a V-I
converter and a CFOA. Post-layout simulation results
indicate that the presented structure could be a preferential choice in applications where precision and speed
must be combined.
then she has been with the Grupo de Diseño Electrónico
at the Department of Electronic Engineering and Communications at the University of Zaragoza. She is currently working towards the Ph.D. degree. Her research
interests are in the areas of analog design and integrated
circuits.
Acknowledgment
This work has been partially supported by the
DGA (P078/2001), CICYT (TIC99-0977) and MECD
(AP99-25166272).
References
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74(1), pp. 93–100, 1993.
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7. Säckinger, E. and Guggenbühl, W., “A high-swing, highimpedance MOS cascode circuit.” IEEE J. Solid-State Circuits
25(1), pp. 289–298, 1990.
8. Ismail, A. M. and Soliman, A. M., “Novel CMOS current feedback op-amp realization suitable for high frequency applications.”
IEEE Transactions on Circuits and Systems-I 47(6), pp. 918–921,
2000.
9. Franco, S., “Current feedback amplifiers.” In: J. Williams (ed.),
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1991.
Belén Calvo received the B.Sc. degree in Physics
from the University of Zaragoza, Spain in 1999. Since
Santiago Celma was born in Zaragoza, Spain. He
received the B.Sc. degree in 1987, the M.S. degree in
1989 and the Ph. D. degree in 1993, all in physics
from University of Zaragoza, Spain. Currently, he is
an associate professor in the Department of Electronic Engineering and Communications at University
of Zaragoza. His research interests include circuit theory, mixed-signal integrated circuits and instrumentation.
Pedro A. Martı́nez was born in Zaragoza, Spain.
He received the B.Sc. degree in 1971 and the Ph.D.
degree in 1974 both in Physics from the University of
Zaragoza. Since 1971 he has been with the Department
of Electronic Engineering and Communications at the
University of Zaragoza where he is Professor. His research interest lies in the area of solid-state circuits,
including analog IC design, non-linear networks, modelling of analog integrated circuits and current-mode
signal processing.
High-Speed High-Precision CMOS Current Conveyor
269
1999. She is a member of the Electronic Design Group
at the Department of Electronic Engineering and Communications at the University of Zaragoza and she is
working towards the Ph.D. degree at present. Her research interests include analog IC design and on-chip
programmable circuits.
Maria Teresa Sanz received the B.Sc. degree in
Physics from the University of Zaragoza, Spain in