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BJT AC Analysis
Chapter 5
Ch.5 Summary
BJT Transistor Modeling
A model is an equivalent circuit that represents
the AC characteristics of the transistor.
A model uses circuit elements that approximate
the behavior of the transistor.
There are two models commonly used in small
signal AC analysis of a transistor:
re model
Hybrid equivalent model
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Ch.5 Summary
The re Transistor Model
BJTs are basically current-controlled devices; therefore
the re model uses a diode and a current source to
duplicate the behavior of the transistor.
One disadvantage to this model is its sensitivity to the
DC level. This model is designed for specific circuit
conditions.
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Ch.5 Summary
Common-Emitter Configuration
The diode re model
can be replaced by
the resistor re.
Ie    1 I b   I b
re 
26 mV
IE
IE : DC emitter current
re: AC diode resistance
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Ch.5 Summary
Common-Emitter Configuration
Input impedance:
Output impedance:
Zo  ro  
Voltage gain:
Current gain:
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Ch.5 Summary
Common-Base Configuration
Input impedance:
Output impedance:
Voltage gain:
Current gain:
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Ch.5 Summary
Common-Collector Configuration
Input impedance:
Output impedance:
Voltage gain:
Current gain:
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For the common-collector configuration,
the model defined for the commonemitter Configuration is normally
applied rather than defining a model for
the common-collector configuration.
In subsequent sections, a number of
common collector configurations will be
investigated and the impact of using the
same model will become quite
apparent.
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Ch.5 Summary
The Hybrid Equivalent Model
Hybrid parameters are developed and used for modeling the
transistor. These parameters can be found on a transistor’s
specification sheet:
hi = input resistance
hr = reverse transfer voltage ratio (Vi/Vo)  0
hf = forward transfer current ratio (Io/Ii)
ho = output conductance
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Ch.5 Summary
Simplified General h-Parameter Model
hi = input resistance
hf = forward transfer current ratio (Io/Ii)
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Ch.5 Summary
re vs. h-Parameter Model
Common-Emitter
hie  βre
hfe  βac
Common-Base
hib  re
hfb  α  1
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Ch.5 Summary
The Hybrid  Model
The hybrid pi model is most useful for analysis
of high-frequency transistor applications.
At lower frequencies the hybrid pi model closely
approximate the re parameters, and can be
replaced by them.
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Ch.5 Summary
Common-Emitter Fixed-Bias
Configuration
The input is applied to the base
The output is taken from the
collector
High input impedance
Low output impedance
High voltage and current gain
Phase shift between input and
output is 180
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Ch.5 Summary
Common-Emitter
Fixed-Bias
Configuration
AC equivalent
re,model
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Ch.5 Summary
Common-Emitter
Fixed-Bias
Calculations
Input
Output
Z i  RB||β|e
Z i  βre RB 10 βre
Zo  RC||rO
Vo
(R ||r )
 C o
Vi
re
Av  
RC
re
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Current gain
Ai   AV
Zo  RC ro 10RC
Av 
Voltage gain:
Current gain:
I
βRB ro
Ai  o 
I i (ro  RC )(RB  βre )
Ai  β ro 10 RC , RB 10 βre
Zi
RC
ro 10 RC
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Ch.5 Summary
By passed Common-Emitter VoltageDivider Bias
re model requires you to
determine , re, and ro.
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Ch.5 Summary
Current gain
Common-Emitter
Voltage-Divider Bias
Calculations
I
 R ro
Ai  o 
I i (ro  RC )(R    re )
I
R 
Ai  o 
r 10R
I i R    re o C
Input impedance
Output impedance
R   R1 || R2
Zi  R  || βre
Zo  RC || ro
Zo  RC ro 10RC
I
Ai  o   ro 10RC , R 10 re
Ii
Current gain from Av
Ai   Av
Zi
RC
Voltage gain
Av 
Vo  RC || ro

Vi
re
Av 
Vo
R
  C ro 10RC
Vi
re
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Ch.5 Summary
Common-Emitter Emitter-Bias
Configuration(Un-bypassed)
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Ch.5 Summary
Impedance Calculations
Input impedance:
Zi  RB || Zb
Zb  re  (   1)RE
Zb  (re  RE )
Z b   RE
Output impedance:
Zo  RC
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Ch.5 Summary
Gain Calculations
Voltage gain:
Av 
Vo
R
 C
Vi
Zb
Av 
Vo
RC

Z (r  R )
Vi
re  RE b e E
Av 
Vo
R
  C Z b   RE
Vi
RE
Current gain:
I
 RB
Ai  o 
I i RB  Z b
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Current gain from Av:
Ai   Av
Zi
RC
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Ch.5 Summary
Emitter-Follower Configuration( common collector)
This is also known as the common-collector configuration.
The input is applied to the base and the output is taken from the emitter.
There is no phase shift between input and output.
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Ch.5 Summary
Impedance
Calculations
Input impedance:
Zi  RB ||Z b
Zb  βre  (β  1)RE
Zb  β(re  RE )
Zb  βRE
Output impedance:
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Zo  RE||re
Zo  re RE re
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Ch.5 Summary
Gain Calculations
Voltage gain:
Av 
Vo
RE

Vi RE  re
Av 
Vo
 1 RE re , RE  re RE
Vi
Current gain:
Ai  
βRB
RB  Z b
Current gain from voltage gain:
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Ai   Av
Zi
RE
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Ch.5 Summary
Common-Base Configuration
The input is applied to the emitter
The output is taken from the
collector
Low input impedance.
High output impedance
Current gain less than unity
Very high voltage gain
No phase shift between input
and output
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Ch.5 Summary
Calculations
Input impedance:
Zi  RE || re
Output impedance:
Zo  RC
Voltage gain:
Av 
Vo RC RC


Vi
re
re
Current gain:
I
Ai  o    1
Ii
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Ch.5 Summary
Common-Emitter Collector Feedback
Configuration
• A variation of the common-emitter fixed-bias configuration
• Input is applied to the base
• Output is taken from the collector
• There is a 180 phase shift between the input and output
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Ch.5 Summary
Calculations
Input impedance:
Output impedance:
Voltage gain: Av 
Zi 
re
1 RC

β RF
Zo  RC || RF
Vo
R
 C
Vi
re
Current gain:
Ai 
Io
βRF

Ii
RF  βRC
Ai 
Io
R
 F
Ii
RC
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Ch.5 Summary
Two-Port Systems Approach
With Vi set to 0 V:
ZTh  Zo  Ro
The voltage across
the open terminals is:
ETh  AvNLVi
where AvNL is the noload voltage gain
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Ch.5 Summary
Effect of Load Impedance on Gain
This model can be applied
to any current- or voltagecontrolled amplifier.
Adding a load reduces the
gain of the amplifier:
Av 
Vo
RL

AvNL
Vi RL  Ro
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Zi
Ai   Av
RL
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Ch.5 Summary
Effect of Source Impedance on Gain
The amplitude of the
applied signal that
reaches the input of
the amplifier is:
Vi 
RiVs
Ri  Rs
The internal resistance of the signal source reduces the overall
gain:
Avs 
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Vo
Ri

AvNL
Vs Ri  Rs
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Ch.5 Summary
Combined Effects of RS and RL on
Voltage Gain
Effects of RL:
Av 
Vo RL AvNL

Vi RL  Ro
Ai   Av
Ri
RL
Avs 
Effects of RL and RS:
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Vo
Ri
RL

AvNL
Vs Ri  Rs RL  Ro
Ais   Avs
Rs  R i
RL
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Ch.5 Summary
Cascaded Systems
• The output of one amplifier is the input to the next
amplifier
• The overall voltage gain is determined by the product of
gains of the individual stages
• The DC bias circuits are isolated from each other by the
coupling capacitors
• The DC calculations are independent of the cascading
• The AC calculations for gain and impedance are
interdependent
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Cascaded Systems
The total gain of the system is then determined by the product of the individual
gains as follows:
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Ch.5 Summary
R-C Coupled BJT Amplifiers
Voltage gain:
Av 1 
RC || R1 || R2 ||  Re
re
Av 2 
RC
re
Av  Av 1Av 2
Input impedance,
first stage:
Zi  R1 || R2 || Re
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Output impedance,
second stage:
Zo  RC
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Ch.5 Summary
Cascode Connection
This example is a CE–CB
combination. This arrangement
provides high input impedance
but a low voltage gain.
The low voltage gain of the
input stage reduces the Miller
input capacitance, making this
combination suitable for highfrequency applications.
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APPROXIMATE HYBRID EQUIVALENT CIRCUIT
Fixed-Bias
Input impedance:
Zi  RB || hie
Output impedance:
Zo  RC || 1/ hoe
Voltage gain:
Av 
Vo
h R || 1/ ho e 
  fe C
Vi
hie
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Current gain:
I
Ai  o  hfe
Ii
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Ch.5 Summary
Voltage-Divider Configuration
Input impedance:
Zi  R  || hie
Output impedance:
Zo  RC
Voltage gain:
gain
Av  
Current gain:
Ai  
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hfe RC || 1/hoe 
hie
hfe R 
R   hie
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Ch.5 Summary
Emitter-Follower Configuration
Input impedance:
Zb  hfe RE
Z b  h fe R E
Zi  Ro || Zb
Z i  R o || Z b
Output impedance:
Zo  RE ||
hie
hfe
Voltage gain:
Av 
Vo
RE

Vi RE  hie / hfe
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Ai 
Current gain:
hfe RB
RB  Z b
Ai   Av
Zi
RE
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Ch.5 Summary
Common-Base Configuration
Input impedance:
Zi  RE || hib
Output impedance:
Zo  RC
Voltage gain:
Av 
Vo
h R
  fb C
Vi
hib
Current gain:
I
Ai  o  hfb  1
Ii
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Ch.5 Summary
Troubleshooting
Check the DC bias voltages
 If not correct, check power supply, resistors,
transistor. Also check the coupling capacitor
between amplifier stages.
Check the AC voltages
 If not correct check transistor, capacitors and
the loading effect of the next stage.
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