ECS Journal of Solid
State Science and
Technology
You may also like
Review—Critical Analysis of CNTFET-Based
Electronic Circuits Design
To cite this article: R. Marani and A. G. Perri 2023 ECS J. Solid State Sci. Technol. 12 051005
View the article online for updates and enhancements.
- Low-power and robust ternary SRAM cell
with improved noise margin in CNTFET
technology
Shams ul Haq, Erfan Abbasian, Tabassum
Khurshid et al.
- A Compact Model for Carbon Nanotube
Field Effect Transistors Incorporating
Temperature Effects and Application for
Operational Amplifier Design
Yajie Zou, Hongwei Liu, Yiying Liu et al.
- Application of S-Relu activation function
and adaptive dual-threshold noise
reduction in fault diagnosis of RV reducer
rolling bearings
Linlin Xue, Yukun Huang, Chenglong
Wang et al.
This content was downloaded from IP address 14.139.171.122 on 12/06/2025 at 10:31
ECS Journal of Solid State Science and Technology, 2023 12 051005
2162-8777/2023/12(5)/051005/15/$40.00 © 2023 The Electrochemical Society (“ECS”). Published on behalf of ECS by IOP Publishing Limited
Review—Critical Analysis of CNTFET-Based Electronic Circuits
Design
R. Marani1
and A. G. Perri2,z
1
National Research Council of Italy (CNR), Institute of Intelligent Industrial Technologies and Systems for Advanced
Manufacturing (STIIMA), Bari, 70126, Italy
2
Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari,
70125, Italy
In this review we present many design of CNTFET-based circuits, already proposed by us and here critically examined. For some
of these, we compare the performance of proposed circuits both in CNTFET and CMOS technology. For CNTFET model, we use a
compact, semi-empirical model, already proposed by us and briefly recalled, while, for the MOSFET model, we use the BSIM4 one
of ADS library. Moreover in some design examples we compare our results with those obtained using the Stanford model. All
simulations are carried out using the software Advanced Design System (ADS), which is compatible with the Verilog-A
programming language.
© 2023 The Electrochemical Society (“ECS”). Published on behalf of ECS by IOP Publishing Limited. [DOI: 10.1149/2162-8777/
acd65d]
Manuscript submitted March 20, 2023; revised manuscript received April 30, 2023. Published May 25, 2023.
We have been dealing with Carbon NanoTubes (CNTs)1 and
Carbon NanoTube Field Effect Transistors (CNTFETs)2–11 for many
years now. In particular we have studied extensively MOSFET-like
CNTFET for high-performance and low-power memory
designs.12–22
In this review we present many design of CNTFET-based
circuits, already proposed by us and here critically examined.
For some of these, we compare the performance of proposed
circuits both in CNTFET and CMOS technology.
For CNTFET model, we use a compact, semi-empirical model,
already proposed by us2,3 and briefly recalled, while, for the
MOSFET model, we use the BSIM4 one of ADS library. BSIM
(Berkeley Short-channel IGFET Model)23 refers to a family of
MOSFETs for integrated circuit design.
Moreover in some design examples we compare our results with
those obtained using the Stanford model.24,25
All simulations are carried out using the software Advanced
Design System (ADS), which is compatible with the Verilog-A
programming language.26
The presentation is organized as follows. At first we present a
brief review of the considered models.
Then we review many design, discussing critically the obtained
results, together with the conclusions and future developments.
A Brief Review of Models Used
An exhaustive description of our CNTFET model is in our
Refs. 2, 3 and therefore the reader is requested to consult them.
The model, based on the hypothesis of ballistic transport, makes
reference to Ref. 27 and on the following improvements introduced
in Refs. 28, 29 to solve some numerical problems of the original paper.27
In this section we just describe the main equations on which our
I—V model is based.
The total drain current IDS in our model has been expressed as
in:30
IDS =
4qkT
∑ [ln (1 + exp ξSp) − ln (1 + exp ξDp)]
h
p
[1]
where k is the Boltzmann constant, T is the absolute temperature, h
is the Planck constant, p is the number of sub-bands, while ξSp and
ξDp have the following expressions:
z
E-mail: annagina.perri@poliba.it
ξSp =
qVCNT −E Cp
kT
and ξDp =
qVCNT −E Cp −qVDS
kT
[2]
being ECp the sub-bands conduction minima, VDS the drain-source
voltage and VCNT the surface potential.
In (7) we have proposed, in order to evaluate VCNT, the following
approximation:
VCNT =
⎧ VGS for VGS < E C
⎪
q
⎨
EC ⎞
EC
⎛
⎪ VGS − α VGS − q for VGS ⩾ q
⎝
⎠
⎩
⎜
[3]
⎟
where EC is the conduction band minimum for the first sub-band and
α is a parameter depending on VDS voltage, CNTFET diameter and
gate oxide capacitance Cox.7,8
Regarding the C-V model, an exhaustive description of our C-V
model is widely described in Refs. 7, 8 and therefore the reader is
requested to consult these references, in which the following
expressions of quantum capacitances CGD and CGS are explained:
∂ξ
∂n
∂n
∂V
⎧C = q
∑ Dp = q ∑ Dp Dp CNT
GD
⎪
∂
V
∂
ξ
∂
V
∂VGS
GS
CNT
⎪
Dp
p
p
⎨
∂n Sp
∂n Sp ∂ξSp ∂VCNT
= q∑
⎪ C GS = q ∑
∂
V
∂ξSp ∂VCNT ∂VGS
⎪
GS
p
p
⎩
[4 ]
In order to simulate correctly the CNTFET behaviour, we needed
to estimate parasitic capacitances and inductances as well as the
drain and source contact resistances.
We have achieved this goal using an empirical method exhaustively described in Refs. 2, 3, where we explained that VFB, RD, RS
have been determined by a best-fit procedure between the measured
and simulated values of I—V characteristics of the device, while the
quantum capacitances have been computed from the charge in the
channel. In this way all elements of the CNTFET equivalent circuit,
shown in Fig. 1, are determined.
It is similar to a common MOSFET model and is characterized
by the generator VFB, for accounting the flat band voltage, the
quantum capacitances CGS and CGD, the inductances of the CNT
Ldrain and Lsource and the resistors Rdrain and Rsource, in which the
parasitic effect due to the electrodes are also included.
Other authors31,32 have then assumed these parameters fixed to
constant and typical values (i.e. VFB = 0 V31 and RD = RS = 25 kΩ32),
thus losing the dependence on the CNT diameter.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 1. Equivalent circuit of a n-type CNTFET.
Figure 2. C-S amplifier based on CNTFET.
Regards to the CNT quantum inductance, as shown in Fig. 1, we
have assumed constant and equal to 4 pH nm−1, which we have
splitted up into two inductances of 2 pH nm−1, while the classical
self-inductance, as it is known,31 can be ignored.
As already said, for the MOSFET model we use the BSIM4
model of ADS library.
BSIM (Berkeley Short-channel IGFET Model)23 refers to a
family of MOSFETs for integrated circuit design. In this work
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 3. C-S amplifier with MOSFET in 32 nm technology.
Table I. Parameter values.
Device
MOSFET 32 nm
CNTFET
VG
0.5 V
0.5 V
VD
1V
1V
BSIM4 has been used for the 32 nm technology nodes. The
MOSFET parameters for BSIM4 model were obtained by
Predictive Technology Model (PTM) web site from the
Nanoscale Integration and Modelling Group of Arizona State
University. In particular the MOSFET parameters, obtained using
an evolution of previous Berkeley Predictive Technology Model
(BPTM), have been improved by us through parametric simulations
to obtain performance of the MOSFET model comparable to the
CNTFET one.
As in some design examples we will compare our results with
those obtained using the Stanford model,24,25 we also make a brief
recall of this model,
The Stanford-Source Virtual Carbon Nanotube Field-Effect
Transistor model (VS-CNFET) is a semi-empirical model that describes
the current-voltage (I-V) and capacitance-voltage (C-V) characteristics
ID
16.3 μA
6.8 μA
ro
gm
−1
0.178 mA V
0.035 mA V−1
9.6 kΩ
200 kΩ
in a short-channel metal-oxide-semiconductor field-effect transistor
(MOSFET) with carbon nanotubes as the channel material.
In particular the VS-CNFET model is based on the semiempirical virtual source concept calibrated to experimental data.
The intrinsic drain current and terminal charges are based on the
virtual source (VS) model, with the virtual source velocity extracted
from experimental data for different channel lengths (ranging from
3-um down to 15-nm).
Moreover, the VS-CNFET model takes to account the following
parasitic effects:
1. Direct source-to-drain and band-to-band tunnelling current
calibrated by numerical simulations;
2. Metal-to-CNT contact resistances calibrated by experimental
data;
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 4. Simulation results for the C-S amplifier with CNTFET: (a) voltage gain; (b) output resistance; (c) frequency response.
3. Parasitic capacitance including gate-to-CNT fringe capacitances
and gate-to-contact coupling capacitances.
The inputs to the VS-CNFET model are the physical device
design including device dimensions, CNT diameter, gate oxide
thickness, etc.
Critical Review of CNTFET-Based Circuit Design:
Experimental Set-Up and Methodology
Design of a common source amplifier in CNTFET and
MOSFET technology.—In this section we review the performances
of a common source (C-S) amplifier realized both with a CNTFET
and then with a MOSFET. The circuital configurations are shown in
Fig. 2 and Fig. 3 respectively.
In particular we compare the values obtained from the simulations with those obtained by theoretical calculation using the
following formulas:33
rR
rR
AV = −g m ⎛ o D ⎞ and R OUT = o D
+
r
R
r
D⎠
o + RD
⎝ o
⎜
⎟
[5]
As the gate is isolated, the input resistance of the stage is infinite
(RIN ≅ ∞). Moreover RD = RLOAD.
The analysis of the previous circuits have been obtained used the
parameters reported in Table I.
The simulation results are shown in Fig. 4 and Fig. 5.
In Table II we compare the values obtained from the simulations
with those obtained by theoretical calculations.33
It is clear that the use of a CNTFET rather than a MOSFET
improves the performance of a common source amplifier.
In fact, for equal gains, there is a halving of the current and a widening
of the pass band of about 1.2 THz, being the MOSFET cut-off frequency
fc = 316 GHz and the CNTFET cut-off frequency fc = 1.5 THz.
Design of a common drain amplifier in CNTFET and
MOSFET technology.—In this section we compare the performances of a common drain (C-D) amplifier realized both with a
MOSFET and then with a CNTFET.
In particular we compared the values obtained from the simulations with those obtained by theoretical calculation using the
following formulas:33
AV =
g m (ro//R S)
1
and R OUT = ro//R S//⎛⎜ ⎞⎟
1 + g m (ro//R S)
g
⎝ m⎠
[6]
Also in this case, as the gate is isolated, the input resistance of the
stage is infinite (RIN ≅ ∞). Moreover RS = RLOAD.
The analysis have been obtained used the parameters reported in
Table III.
The design technique is the same previously examined for a C-S
amplifier and therefore, in order to avoid overloading the discussion,
we limit ourselves to report in Table IV the values obtained from the
simulations with those obtained by theoretical calculations.33
It is useful to point out that in the theoretical calculations made
for the MOSFET configuration, it was possible to neglect the
source resistance (RS = 1000 KΩ) in parallel with the MOSFET
output resistance (ro = 9.6 KΩ) being RS much greater than ro.
Moreover, also for a C-D amplifier we have a pass band of
525 GHz for MOSFET configuration and 14.4 THz for CNTFET
configuration.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 5. Simulation results for the C-S amplifier with 32 nm MOSFET: (a) voltage gain; (b) output resistance; (c) frequency response.
Table II. Theoretical and simulated values of AV and ROUT.
MOSFET 32 nm
AV
ROUT
CNTFET
Theoretical
values
Simulated
values
Theoretical
values
Simulated
values
−1.15
6.48 kΩ
−1.48
14.35 kΩ
−1.16
33.34 kΩ
−1.41
37.45 kΩ
Table III. Parameter values.
Device
MOSFET 32 nm
CNTFET
VG
1.5 V
1.5 V
VD
ID
−1
1.45 μA
1.18 μA
3V
3V
ro
gm
0.053 mA V
0.035 mA V−1
9.6 kΩ
200 kΩ
Table IV. Theoretical and simulated values of AV and ROUT.
MOSFET 32 nm
AV
ROUT
CNTFET
Theoretical values
Simulated values
Theoretical values
Simulated values
0.34
6.2 kΩ
0.66
1.7 kΩ
0.85
24 kΩ
0.79
21.6 kΩ
Design of a basic current mirror in CNTFET and MOSFET
technology.—In this section we review the design of a basic current
mirror both in CNTFET and MOSFET technology, already proposed
by us14 but here critically examined.
The CNTFETs in any proposed simulation have a diameter of
15 nm and a channel length of 32 nm.
Figure 6 shows a basic current mirror, where a current sink is
based on n-type C-CNTFET.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 6. Basic current mirror circuit with a n-type CNTFET.
Figure 7. Reference current vs VDD in a n-type basic current mirror.
The IREF reference current of 10 μA is provided by an ideal
current supply on the left branch of the circuit. This current imposes
the quiescent point of M1 in saturation region and provides the bias
voltage on gate M2, which must faithfully follow the IREF as long as
output voltage VDD ⩾ VT, the voltage required to switch M2 on.
The drain voltage of M2 is swept in order to evaluate how well
the output current replicate an ideal current supply. The expected
current value comes out from the general I-V characteristic of a FET
device in saturation region, which is generally given by the
following relation:33
I out = k′(VG − VT ) 2 (1 + λVDD)
[7]
where VT is the threshold voltage and k′ is a technology related
constant depends by particular dimensional and construction
features. Presence of λVDD term calls out the second order effect
of channel modulation, where λ is the channel length modulation
constant. This unwanted phenomenon affects the behaviour of
current mirror as non-ideal current supply on account of drain
bias. Since M1 is a technologically equal device to M2, reference
current should be mirrored as expected.
Afterwards the two n-type C-CNTFETs are substituted with an
NMOS pair formed by devices with different sizes in order to
compare MOSFET technology performances with CNTFET ones.
The IOUT values are shown in Fig. 7 where a comparison with
MOSFETs having different channel length L and constant aspect
ratio, W/L = 2, is illustrated.
The simulation underlines that n-type CNTFET works better then
MOSFETs of larger size in current replication in a basic current
mirror. This feature can be better appreciate in Fig. 8, where error in
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 8. Relative error |IOUT-IREF| in current replication of a n-type basic current mirror.
current replication given by |IOUT-IREF| is shown. However, NMOS
shows a lower threshold voltage that allows to keep easier the device
in saturation region, when current mirror function begins to operate.
Another feature we would to analyze is the output resistance
ROUT seen from the M2 drain to ground (ideal case is ROUT tending
to ∞). For the proposed mirror ROUT is given by:
R out =
1 + λVDD
1
≅
λI out
λI out
[8]
where IOUT in saturation region is given by Eq. 7. Therefore, ROUT is
a sensitive quantity to the variation of M2 drain-source voltage. In
effect it exhibits its maximum value as long as IOUT is maximally
consistent with respect of VDD changes.
The trend of ROUT due to VDD changes is shown in Fig. 9.
We notice that n-type CNTFET-based basic mirror behaves
better than NMOS one because of the larger CNTFET small-signal
output resistance seen from drain to source. A resistance value of
5.2 MΩ is achieved by n-CNTFET compared to the 890 kΩ of the
longer NMOS proposed in simulation. Overall we observe that ntype CNTFET mirror obtained resistance exceeds about five times
the performance related to MOS devices with channel length of
about two orders of magnitude higher.
This simulation is repeated choosing pairs of NMOS with L = 5
μm, characterized by the best shown simulated performances, and
changing the MOSFET device aspect ratio in order to increase
channel width W, and MOSFET trans-conductance given by:33
gm =
2k′
W
∣ I out ∣(1 + λVDD)
L
[9]
where kn′ = μn Coss′ depends of the depth of the thin oxide. As
Eq. 9 indicates, an increment of aspect ratio W/L corresponds to a
slowly increment of the device trans-conductance. This means that
for larger MOSFETs a lower driving source-gate voltage is allowed
for achieve the 10 μA of reference current, then the same for the
replication in case of equal devices in mirror.
In Figs. 10, 11 and 12 we have reported the results of our
simulations.
As we can see NMOS current mirrors provide better performances in terms of current replication error and output resistance,
for lower values of W/L. In spite of this analysis we can assume the
n-type C-CNTFET behaviour in current mirror similar to behaviours
of NMOS with channel length of the order of μm with a very low
W/L.
In Ref. 14 we have designed the basic current mirror, involving
also the p-type configuration, and the obtained results are illustrated
in Table V, in which we show the results for also cascode current
mirror design, widely described in Ref. 14.
These simulations allow us to critically underline the following
considerations:
• N-type CNTFET performances largely surpass NMOS outcomes when n-channel length does not exceed 5 μm in basic current
mirror, because of output resistance exceeds about five times the
performance related to NMOS devices with channel length of about
two orders of magnitude higher;
• N-type CNTFET behaviour in current mirror is similar to
behaviour of NMOS with channel length of the order of the μm with
a very low aspect ratio;
• MOSFETs generally show a lower threshold voltage that
allows to keep easier then CNTFETs the saturation region, when
current mirror function begins to operate;
• Performance in p-type basic current mirrors are comparable as
long as p-channel length does not exceed 5 μm, so there is minor
benefit in the implementation of p-type CNTFET current mirror;
• There is not an evident convenience in terms of performances
for the implementation of cascode current mirror topology with
CNTFETs in place of MOSFET with channel length of some
hundreds of nanometers, especially for the p-type topology.
Design of a differential amplifier: comparative analysis of
CNTFET models.—In Fig. 13 we show a differential amplifier
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 9. Output resistance of a n-type basic current mirror.
Figure 10. IOUT vs VDD in n-type basic current mirror for different W/L values.
with symmetric supplies, the positive VDD = 2 V the negative -VDD
= −2V (named MinusVDD.34
We use five CNTFET, X1 X2 X3 X4 X5, each made by a single
carbon nanotube channel with indices (19, 0) and length 25 nm. These
values derive from a previous analysis,35 where we observed that short
tubes gives the best performance at high frequency. In order to
simulate the output load, both drain of the differential pair are directly
coupled to gate input of a differential pair complementary to the one in
Fig. 13, i.e. obtained swapping position of differential pair and a
current generator, and swapping N devices with P devices.
We ignore the embedding parasitic element, since these would
cut down the gain at higher frequencies and cover differences
between models.
As the Stanford model includes voltage independent capacitances, presumably for terminal pads, we measured values of these
capacitances from simulation of a bare CNTFET obtaining a 2.19 aF
capacitance between gate and source, and a 1.44 aF capacitance
between drain an source.
To make comparison more balanced we add two capacitor to our
model with these values.
We consider first the polarizations: in Fig. 14 we show the drain
current of the differential pair, our model foresees lower current,
from 30% less at VDD = 1 V to 15% less at VDD = 2 V.
Vds for the differential pair is lower, while the Vds of the current
source is higher, the difference being about 0.1 V.
In Fig. 15 the differential voltage gain of the proposed circuit at
low frequencies, below 1 GHz, foreseen by our model is 21.2 dB,
while Stanford model is 0.7 dB lower.
For the 3 dB cut frequencies, values are 34 GHz for our model
and 12% higher, 38 GHz, for Stanford model. On the tail of the
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 11. Relative error |IOUT-IREF| vs VDD in n-type basic current mirror for different W/L values.
Figure 12. Output resistance of a n-type basic current mirror for different W/L values.
curve, the 0 dB gain frequency is 0.44 THz for our model and 36%
higher, 0.60 THz for Stanford model.
In Fig. 16 we show the transient analysis for an input differential
sine of Vin = ±1 mV amplitude at 50 GHz, at a frequency above the
3 dB cut frequency since linear simulation foresee 6.57 (16 dB)
voltage gain.
Transient simulation shows a small transient in the form of
decreasing exponential, which appears as a slow derive of the mean
voltage of the signal, its voltage values at first peak of sinusoid is
1.0 mV for our model and 0.8 mV for Stanford one. Distortion is not
negligible and not visible in Fig. 16 since input signal amplitude is
small compared to the harmonic intercept value, that we will show
later.
We present in Fig. 17 the differential input admittance, while in
Fig. 18 the output single ended impedance.
The input differential admittance is dominated by a capacitance
component, our model foresees a value 8 times smaller than the
values from Stanford model for frequencies below 100 GHz.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 15. Differential gain. Colours as for Fig. 14.
Figure 13. Differential circuit using CNTFET.34
Figure 16. Transient output for sinusoidal input. The input differential
signal is in black, the output is in blue for our model and in red for Stanford
model. Input has been multiplied by the gain obtained from linear analysis
using our model. Continuous components have been subtracted.
Figure 17. Differential input admittance, continuous line are real part, while
imaginary parts is represented with a line plus circles. Colours as for Fig. 14.
Figure 14. Drain current of differential pair of Fig. 13, for various supply
voltages. The blue line represent our model results and the red line represent
the Stanford model results.
For the output impedance, the resistive component is dominant at
frequencies below 100 GHz, above this frequency the capacitive
component became dominant. For frequencies below 100 GHz our
model foresee 20% lower real part and 50% lower capacitive part,
above this frequency, our model still gives lower result but relative
differences depends on frequency.
Regards to harmonic distortion, we made a transient simulation
with a differential input signal at 50 GHz, measuring the simulated
output harmonic component for various periods until we see
transient effects disappear. Since transient effect are detectable till
the 5th period, we selected the 40th period to measure the harmonic
components from 2nd to the 5th.
In Table VI we list the ratios of higher harmonic to the first
harmonic.
Simulation description
CNTFET
MOSFET
Mirror
Circuit
Channel
type
Parametric sweep
Relative error in output
current
Maximum output
resistance
Relative error in output
current
Maximum output
resistance
Best
competitor
Basic
Basic
Basic
Cascode
Cascode
Cascode
N
N
P
N
P
P
L (μm) 0.5 ÷ 5
(W/L) 1 ÷ 5
L (μm) 0.5 ÷ 5
L (μm) 0.5 ÷ 5
L (μm) 0.5 ÷ 5
L (nm) 150 ÷ 350
<40%
<40%
<80%
>4%
<9%
<9%
5.2 MΩ
5.2 MΩ
1.2 MΩ
72.9 MΩ
30.5 MΩ
30.5 MΩ
<60%
<50%
<30%
<4%
<1%
<4%
890 kΩ
1.2 MΩ
1.3 MΩ
105.6 MΩ
139.6 MΩ
31.2 MΩ
L = 5 μm
(W/L) = 1
L = 5 μm
L = 5 μm
L = 5 μm
L = 350 nm
ECS Journal of Solid State Science and Technology, 2023 12 051005
Table V. Summary of simulation results.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Table VI. Ratio of the higher harmonic to the fundamental component at 50 GHz. Unreported values are covered by numerical noise.
Harmonics (our model)
Vin
[V]
–3
10
10–4
10–5
10–6
2nd
3rd
–2
1.3810
1.3810–3
1.3810–4
1.3810–5
4th
–3
1.1510
1.1510–5
—
—
Harmonics (Stanford model)
5th
–5
5.4010
5.4010–8
—
—
2nd
–6
2.00 10
2.6610–10
—
—
3rd
–3
9.3110
9.2210–4
9.2210–5
9.2110–6
4th
–4
4.4910
4.4110–4
4.4110–4
—
5th
–5
3.05 10
2.97 10–8
3.0010–11
—
1.90 10–6
1.8510–10
—
—
Table VII. Intercept point for harmonic components at 50 GHz obtained by Table VI.
Harmonics intercept (our model)
Harmonics intercept (Stanford model)
Vin
2nd
3rd
4th
5th
2nd
3rd
4th
5th
[V]
[V]
[V]
[V]
[V]
[V]
[V]
[V]
[V]
10–3
10–4
10–5
10–6
0.0727
0.0725
0.0725
0.0725
0.0295
0.0295
—
—
0.0265
0.0264
—
—
0.0266
0.0248
—
—
0.1074
0.1085
0.1085
0.1085
0.0472
0.0476
0.0476
—
0.0320
0.0323
0.0322
—
0.027
0.027
—
—
Figure 19. Truth table of a Full Adder.
Figure 18. Output impedance, continuous line are for the real part, circles
for imaginary part. Colours as for Fig. 14.
The values for the k-th harmonic distortion relative to the first
harmonic could be easily approximated with the function (Vin/Vk)k-1
from which we could obtain the values of the intercept Vk, that we
present in Table VII.
We observe that obtained values for Vk are almost independent
from Vin as it should be.
Since we have to seek for the lowest Vk value, from Table VII we
obtain an intercept at 25 mV for our model, and at 27 mV for
Stanford model, in both cases due to the 5th harmonic.
If we use Table VI to compare distortion values, we observe that
the worst case is the 3rd harmonic distortion for which our model
foresee a distortion 2.30 times that foreseen by Stanford model. For
the other harmonics the difference is smaller but our model still
predicts larger distortions. We stress that none of the examined
model consider self-heating due to power dissipation.
Definitely the values of gain, between the two considered models,
at various frequencies are comparable, with comparable results for
characteristic frequency point at—3 dB and at gain = 1. The largest
difference between the simulation results comes from the differential
input admittance for which our model foresees a value 8 times smaller.
For distortions, while our model predicts always higher values
for harmonic distortions, we obtained similar results for the
harmonic intercept since this value is due to the 5th harmonic for
which models predict similar results.
Full adder circuit designs in CNTFET and CMOS technology.—
A Full Adder33 adds binary numbers and has three inputs and two
outputs. The two inputs are A and B, and the third input is a carry
input CIN. The output carry is designated as COUT, and the normal
output is designated as SUM.
The truth table of the full adder circuit is shown in Fig. 19.
The circuit of Fig. 20 realizes the function proposed by truth
table, where XOR gate is realized with NAND gates, as the
schematic of Fig. 21.
The simulations to verify the correct mode of operation of the
proposed full adder (realized using NAND and NOT gates) in
CNTFET technology, have been made, doing compromise choice.
As we have widely illustrated in Ref. 36, for a supply voltage of
0.5 V the NAND and NOT gates present a Voltage Transfer
Characteristics (VTC), that allows the correct mode of operation
because there is a clear division between the high logic state and the
low logic state. Therefore we have fixed a supply voltage of 0.5 V.
Assuming Cin = 1 for all simulations, that the reader can see
in Ref. 35, in this review we only critically underline that the limit
for a correct mode of operation is 50 GHz. In fact, with a frequency
of 80 GHz, the output SUM completely loses its meaning.
ECS Journal of Solid State Science and Technology, 2023 12 051005
Figure 20. Full adder schematic.
Table VIII. Writing time values for the two considered models.
Writing time
Our model
Stanford model
Single - supply
Dual - supply
5.24 ps
6.02 ps
6.28 ps
6.28 ps
Table IX. Reading time values for the two considered models for a
single cell.
Figure 21. XOR schematic.
Reading time
Our model
Stanford model
Single - supply
Dual - supply
1.28 ps
1.4 ps
1.26 ps
1.56 ps
Table X. Reading time values for the two considered models for the
designed 16 bit SRAM.
Reading time
Our model
Stanford model
Single - supply
Dual - supply
1.53 ps
1.4 ps
6.76 ps
6.56 ps
Table XI. Static noise margins for the two considered models.
Static noise margins
Single - supply
Dual - supply
Figure 22. 6 T SRAM cell structure in CNTFET technology.37
Regards to a full adder in CMOS technology, in Ref. 36 we have
illustrated that for a supply voltage of 3 V the NAND and NOT gates
present a VTC that allows the correct mode of operation because
there is a better frequency characteristic. Therefore we have fixed a
supply voltage of 3 V.
In this case the limit for a correct mode of operation is 200 MHz.
In fact with a frequency of 333 MHz the output SUM completely
loses its meaning.
Design of a SRAM Cell: comparative analysis of CNTFET
models.—In Ref. 37 we already presented a comparison of CNTFET
models through the design of a SRAM cell, in order to identify the
Our model
Stanford model
NMH = 0.52 V
NML = 0.21 V
NMH = 0.52 V
NML = 0.21 V
NMH = 0.44 V
NML = 0.20 V
NMH = 0.51 V
NML = 0.13 V
one more easily implementable in simulation software. In particular
we considered two models: our model and the Stanford one.
A 6 T SRAM cell structure in CNTFET technology is shown in
Fig. 22.
SRAM consists of four transistors that form two cross coupled
inverters to store one single bit. Two outputs of the cross coupled
inverters denote two stable states “0” and “1”. Two additional access
transistors are added to control the access to the cross coupled
inverters during read and write operations. Therefore, it requires six
transistors to store one memory bit. The word line (WL) acting as
gate voltage controls the access transistors MN1 and MN2 which
ECS Journal of Solid State Science and Technology, 2023 12 051005
Table XII. Static power dissipation for the two considered models.
Static power dissipation
Our model
Stanford model
Single - supply
Dual - supply
0.16 nW
0.17 nW
5.783 nW
1.86 nW
Table XV. Power and rising time values for the designed SRAM 6 T
cell (Supply Voltage = ± 0.3 V and frequency = 2.2 GHz).
Technology
Table XIII. PDP values for the two considered models.
PDP
Our model
Stanford model
Single - supply
Dual - supply
0.72 · 10–16 J
0.96 · 10–16 J
1.84 · 10–16 J
1.62 · 10–16 J
Table XIV. Power and rising time values for the designed SRAM 6 T
cell (Supply Voltage = ±0.5 V and frequency = 2.2 GHz).
Technology
CMOS 45 nm
CNTFET 32 nm
Power (μW)
Rising time (ps)
12.68
0.27
28.8
4.2
connect the outputs of two inverters with two bit lines. These bit
lines are used to read the stored data or write new data in the
memory cell.
In the simulations, widely described in Ref. 37, for all CNTFETs
we have assumed a channel length equal to 32 nm and a transistor
width W equal to 64 nm for MN1, MN2, MN3 and MN4, and equal
to 80 nm for MP5 and MP6, in order to have comparable results with
Refs. 38, 39 All CNFETs use nanotubes as channel, having chirality
(19, 0). In fact the diameter of CNT, dependent on chirality, is
1.49 nm and therefore the threshold voltage of the CNFETs using
(19, 0) CNTs is 0.289 V. These values in Refs. 38, 39 have been
identified as optimal values during read operation of the stored data
or during write operation of new data in the memory cell.
In this review we do not report the simulations, that the reader
can see in Ref. 37, but only the obtained results, described through
the following Tables and here critically analyzed.
In particular from the data reported in Table VIII, it is evident
that both for single and dual-supply, the writing time is nearly the
same for the two models (evaluated as the time needed to reach the
95% of the high-level voltage).
The reading time for the two models is reported in Table IX,
where it is evident that both for single- and dual-supply, for a single
cell, the reading time is nearly the same for both models.
The results for the design of a 16 bit SRAM are reported in
Table X.
The mismatch between the two models is due to the different
loading effect of the unselected cells.
We believe that the reason is the different drain equivalent
capacitance or output resistance of the 15 access-transistors, which
are off.
In Table XI the Static Noise Margins values are reported using
the two considered models, both for single-supply and for dualsupply.
In Table XII the values of static power consumption of the
designed CNTFET SRAM are reported using the two considered
models, both for single- and dual-supply.
It is easy to see that there is a great difference in static power
dissipation for the two models, probably due to the fact that the two
output characteristics of the single CNTFET present the major
differences for high (or null) values of gate voltage, with respect to
Vdd (see Fig. 22). That is the case of the SRAM, in which gate
voltages are either null or equal to Vdd.
CMOS 45 nm
CNTFET 32 nm
Power (μW)
Rising time (ps)
1.44
0.04
35
18.1
Table XVI. Power and rising time values for the designed SRAM 6 T
cell (Supply Voltage = ±0.5 V and frequency = 3.84 GHz).
Technology
CMOS 45 nm
CNTFET 32 nm
Power (μW)
Rising time (ps)
14.4
0.47
28.8
4.2
Table XVII. Power and rising time values for the designed SRAM
6 T cell (Supply Voltage = ±0.3 V and frequency = 3.84 GHz).
Technology
CMOS 45 nm
CNTFET 32 nm
Power (μW)
Rising time (ps)
2
0.082
35
18.2
As we know,33 the Power-Delay Product (PDP) is a figure of
merit of a SRAM correlated with the energy efficiency. It is also
known as Switching Energy and is the product between power
consumption (averaged over a switching event) and the duration of
the switching event. This value, multiplied by the number of
switching events per second, gives the average power consumption
due to switching.
In order to obtain the PDP value, it is necessary to integrate the
power consumption during a writing event, through the current
flowing in the cell.
In Table XIII the values of PDP of the designed CNTFET
SRAM, whose simulations can be seen in Ref. 37, are reported using
the two considered models, both for single- and dual-supply,
obtaining results of the same order of magnitude.
Design of a 6 T SRAM cell structure in CMOS technology.—
Finally, in order to compare the performance of a 6 T SRAM cell in
CNTFET technology with the same in CMOS technology, the
obtained results37 can be summarized through the following
Tables XIV, XV, XVI and XVII.
In order to make the discussion easier, we simply say that the
comparison has shown that CNTFET SRAM has much greater
access times compared to the CMOS technology.
However, the power consumption remains high for CNTFET
because they have a higher load capacity than CMOS.
We observe that the memory cell realized with CNTFET allows
to reach very high working frequencies, always guaranteeing a
reliable and little distorted signal.
Moreover the static analysis of the cell allows the determination
of the logical thresholds, which in CNTFET technology are more
restricted than those obtained in CMOS technology.
Definitely we underline that the design of the SRAM cell in
CMOS technology shows a good operation up to near 4 GHz
frequencies, beyond which the signal undergoes strong alterations,
becoming a first triangular approximation signal.
Conclusions and Future Developments
In this review we presented many design of CNTFET-based
circuits, already proposed by us and here critically examined.
For some of these (C-S and C-D amplifier, basic current mirror,
Full Adder) we compared the performance of circuits both in
ECS Journal of Solid State Science and Technology, 2023 12 051005
CNTFET and CMOS technology, quantitatively highlighting the
differences between the two technologies.
For CNTFET model, we used a compact, semi-empirical model,
already proposed by us and briefly recalled, while, for MOSFET
model, we used the BSIM4 one of ADS library.
In other design examples (differential amplifier, SRAM cell) we
have compared our results with those obtained using the Stanford
model. Also in this case we quantitatively highlighted the differences between the two models.
All simulations have been carried out using the software
Advanced Design System.
Currently we are working to study the effect of temperature and
of noise40,41 in other circuits based on CNTFETs.
Moreover we are analyzing more thoroughly the effects of
parasitic elements of interconnection lines in CNT embedded
integrated circuits42 and the impact of technology on CNTFETbased circuits performance.43
Acknowledgments
This work is dedicated to Mr. Pietro Perri and Mrs. Ida Ruffolo.
ORCID
R. Marani
A. G. Perri
https://orcid.org/0000-0002-5599-903X
https://orcid.org/0000-0003-4949-987X
References
1. R. Marani and A. G. Perri, ECS Trans., 23, 429 (2009).
2. G. Gelao, R. Marani, R. Diana, and A. G. Perri, IEEE Trans. Nanotechnol., 10, 506
(2011).
3. R. Marani and A. G. Perri, Current Nanoscience, 7, 245 (2011).
4. R. Marani and A. G. Perri, Int. J. Electron., 99, 427 (2012).
5. R. Marani, G. Gelao, and A. G. Perri, Current Nanoscience, 8, 556 (2012).
6. R. Marani, G. Gelao, and A. G. Perri, Microelectron. J., 44, 33 (2013).
7. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 5, M1 (2016).
8. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 5, M31 (2016).
9. G. Gelao, R. Marani, L. Pizzulli, and A. G. Perri, Current Nanoscience, 11, 515 (2015).
10. G. Gelao, R. Marani, L. Pizzulli, and A. G. Perri, Current Nanoscience, 11, 770
(2015).
11. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 5, M38 (2016).
12. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 5, M118 (2016).
13. R. Marani, G. Gelao, and A. G. Perri, ECS J. Solid State Sci. Technol., 6, M118
(2017).
14. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 6, M60 (2017).
15. G. Gelao, R. Marani, and A. G. Perri, ECS J. Solid State Sci. Technol., 7, M16
(2018).
16. G. Gelao, R. Marani, and A. G. Perri, ECS J. Solid State Sci. Technol., 7, M41
(2018).
17. R. Marani and A. G. Perri, Current Nanoscience, 15, 471 (2019).
18. G. Gelao, R. Marani, and A. G. Perri, ECS J. Solid State Sci. Technol., 8, M19
(2019).
19. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 9, 031001 (2020).
20. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 11, 031006 (2022).
21. G. Gelao, R. Marani, and A. G. Perri, ECS J. Solid State Sci. Technol., 12, 011004
(2023).
22. R. Marani and A. G. Perri, International Journal of Nanoscience and
Nanotechnology, 19, 9 (2023).
23. University of California (USA) (2020), (http://bsim.berkeley.edu/models/bsim4/,
BSIM Group, Berkeley.
24. C.-S. Lee, E. Pop, A. D. Franklin, W. Haensch, and H.-S. P. Wong, IEEE Trans.
Electron Devices, 62, 3061 (2015).
25. C.-S. Lee, E. Pop, A. D. Franklin, W. Haensch, and H.-S. P. Wong, IEEE Trans.
Electron Devices, 62, 3070 (2015).
26. (2014), Verilog-AMS language reference manual, Version 2.2.
27. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, IEEE Trans. Comput. Aided
Des. Integr. Circuits Syst., 23, 1411 (2004).
28. F. Pregaldiny, C. Lallement, and J. B. Kammerer, International Conference on
Design and Test of Integrated Systems in Nanoscale TechnologyDTIS 2006., Tunis,
p, 34 (2006).
29. F. Prégaldiny, C. Lallement, B. Diange, M. Sallese, and M. Krummenacher,
“Compact modeling of emerging technologies with VHDL-AMS”, ed. S. A. Huss
Advances in Design and Specification Languages for Embedded Systems (Berlin)
(Springer, Netherlands) (2007).
30. S. Datta, “Cambridge studies in semiconductor physics and microelectronic
engineering 3.” Electronic Transport in Mesoscopic Systems (Cambridge,
Cambridge University Press, New York) (1995).
31. P. Avouris, Z. Chen, and V. Perebeinos, Nature Nanotechology, 2, 605 (2007).
32. A. Javey et al., Nature Mater, 1, 241 (2002).
33. A. G. Perri, Fondamenti di Elettronica, (Bari, Italy) (2009).
34. G. Gelao, R. Marani, and A. G. Perri, International Journal of Emerging
Technology and Advanced Engineering, 11, 22 (2021).
35. G. Gelao, R. Marani, and A. G. Perri, ECS J. Solid State Sci. Technol., 10, 061009
(2021).
36. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 7, M108 (2018).
37. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 8, M1 (2019).
38. S. Lin, Y. Kim, F. Lombardi, and Y. J. Lee, Proceedings of 2008 International SoC
Design Conference, (Busan, South Korea) (2008).
39. D. H. Emon, N. Mohammad, and S. M. Mominuzzaman, Proceedings of 7th
International Conference on Electrical and Computer Engineering (Dhaka,
Bangladesh) (2012).
40. R. Marani and A. G. Perri, International Journal of Emerging Technology and
Advanced Engineering, 11, 13 (2021).
41. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 11, 061002 (2022).
42. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 9, 021004 (2020).
43. R. Marani and A. G. Perri, ECS J. Solid State Sci. Technol., 9, 051001 (2020).