CMOS Power Management Circuits and Systems for
Microwatts Energy Harvesting
by
TEH Ying Khai
A Thesis Submitted to
The Hong Kong University of Science and Technology
in Partial Fulfillment of the Requirements for
the Degree of Doctor of Philosophy
in the Department of Electronic and Computer Engineering
May 2015, Hong Kong
i
Authorization
I hereby declare that I am the sole author of the thesis.
I authorize the Hong Kong University of Science and Technology to lend this thesis to
other institutions or individuals for the purpose of scholarly research.
I further authorize the Hong Kong University of Science and Technology to reproduce
the thesis by photocopying or by other means, in total or in part, at the request of other
institutions or individuals for the purpose of scholarly research.
__________________________________________
TEH Ying Khai
May 2015
ii
CMOS Power Management Circuits and Systems for Microwatts Energy Harvesting
by
TEH Ying Khai
This is to certify that I have examined the above PhD thesis
and have found that it is complete and satisfactory in all aspects,
and that any and all revisions required by
the thesis examination committee have been made.
_____________________________________
Prof. Philip K.T. MOK (ECE)
Thesis Supervisor
_____________________________________
Prof. Tianshou ZHAO (MAE)
Chairman, Thesis Examination Committee
_____________________________________
Prof. Wing-Hung KI (ECE)
Thesis Examination Committee
_____________________________________
Prof. Chi-Ying TSUI (ECE)
Thesis Examination Committee
_____________________________________
Prof. Francesco CIUCCI (MAE)
Thesis Examination Committee
_____________________________________
Prof. Ross D. MURCH
Head of Department (ECE)
Department of Electronic and Computer Engineering,
The Hong Kong University of Science and Technology
May 2015
iii
ACKNOWLEDGEMENTS
“If I have seen further it is by standing on the shoulders of giants.”
Sir Isaac Newton
First of all I would like to thank my thesis advisor, Prof. Philip K.T. Mok. Without his
vision, guidance, patience, trust and support, it would be impossible for me to complete my
PhD program.
Secondly I wish to acknowledge Prof. Wing-Hung Ki, Prof. Chi-Ying Tsui, Prof.
Francesco Ciucci, and Prof. Siew-Chong Tan for their willingness to spare their invaluable
time and expertise in reviewing this thesis, and serve in the thesis committee.
Thirdly I would like to express my sincere appreciation to all my professors,
colleagues and friends in HKUST for their consistent technical advice and moral support. In
particular I wish to thank my fellow IPELers, i.e. Dr. Jun Yi, Dr. Chenchang Zhan, Dr.
Edward Ho, Dr. Xiaocheng Jing, Dr. Vincent Chan, Dr. Yan Lu, Dr. Cheng Huang, late Dr.
Yonggen Liu, Mr. Jerry Zhang, Mr. Oliver Lee, Mr. Eric Lai, Mr. Augustus Hu, Mr. Min Tan,
Mr. Lin Cheng, Mr. Fan Yang, Mr. Yuan Gao, Ms. Xun Liu, Mr. Lisong Li, Mr. Jiawei Zheng
and Mr. Junmin Jiang. I also owe special gratitude to Mr. Siu Fai Luk, Mr. Fred Kwok, Mr.
Hi Yin Man, Ms. Wendy Yuen, Ms. Alisa Wong, Ms. Joey On, Ms. Josie Man, ECE eehelp
team and Mr. Erwin Deumens from IMEC for their prompt and warm assistance throughout
my PhD program in HKUST.
Besides, I am grateful that the Hong Kong Research Grant Council has selected me as
one of the inaugural Hong Kong PhD Fellowship recipients. The generous support had
categorically solved my financial worries of pursuing doctoral degree in this Asia’s world
city, which is interesting and vibrant, but high in cost of living nevertheless.
Cliché perhaps, but I must also thank my family, in particular, my better half Ruen
Shan. Their unconditional love, understanding, patience, tolerance, motivation and support
are the quintessential pillars towards the completion of my PhD research.
Finally, I dedicate this work to all great scientists, researchers and engineers before
me. I am nothing but a dwarf standing on top of your shoulders, seeking to navigate the
possibilities of unknown.
iv
TABLE OF CONTENTS
Title Page
i
Authorization Page
ii
Signature Page
iii
Acknowledgements
iv
Table of Contents
v
List of Figures
viii
List of Tables
xiii
Abstract
xiv
Chapter 1
Introduction
1
1.1
Background and Motivation
1
1.2
Research Challenges and Goals
3
1.3
Thesis Contribution
5
1.4
Thesis Organization
6
Chapter 2
Review of Energy Harvesting Sources and Storage
7
2.1
Thermoelectric generator (TEG)
7
2.2
Microbial fuel cell (MFC)
9
2.3
Photovoltaic cell (PVC)
9
2.4
Piezoelectric harvester (PEH)
10
2.5
Summary of Energy Source Characteristics and Classification
11
2.6
High Density Capacitor as Energy Storage
12
Chapter 3
System Architecture and Circuit Blocks
15
3.1
Proposed Multi-Source Stacked Capacitor System
15
3.2
Brief Review of Linear Regulator
19
3.3
Brief Review of Switched-Inductor Converter
20
3.4
Brief Review of Switched-Capacitor Converter
21
3.5
Summary of different DC-DC converter
22
v
Chapter 4
Shunt Regulator and Voltage Supervisor based on Digital Schmitt-Trigger 23
Cell
4.1
Shunt Regulator
23
4.2
Six-transistor Schmitt-Trigger
24
4.3
Voltage Reference and Voltage Monitor
27
4.4
Voltage Supervisor in Piezoelectric Energy Harvesting System
28
4.5
Simulations and Measurements
30
4.5.1
Simulated Schmitt-Trigger hysteresis operation
30
4.5.2
Accelerated cold start-up time with multiple sources
30
4.5.3
Simulated start-up sequence of VREF, VBIAS, VSHUNT and VDD
31
4.5.4
Measurement results from prototype chip
31
4.6
Summary
Chapter 5
32
Pulse Transformer Boost Converter
36
5.1
Low voltage energy source start-up problem
36
5.2
Comparisons with Other Transformer Topologies (Start-up and Efficiency)
37
5.2.1
Start-up and efficiency loss of transformer oscillation mode
38
5.2.2
Efficiency loss after boost converter mode change
39
5.3
Unipolar and Bipolar Continuous Time Operations
41
5.3.1
Output regulation and gate bias changer
47
5.3.2
Bipolar output version of pulse transformer boost converter
50
5.3.3
Potential applications of bipolar supply
50
5.3.4
DTMOS version of pulse transformer boost converter
52
5.4
Discontinuous Time Operations
56
5.5
Continuous Time Maximum Power Point Tracking (MPPT) Techniques
57
5.6
Measurement Results of Different Pulse Transformer Boost Converters
61
5.6.1
Measurement results of unipolar version
61
5.6.2
Measurement results of unipolar-DTMOS version
71
5.6.3
Measurement results of bipolar version
71
5.7
Summary
72
vi
Chapter 6
6.1
Charge Pump for Secondary Power Extraction
77
Concept of Secondary Power Extraction
77
6.1.1
78
Configuration 1: Boost Converter + Shunt Regulator
+ Unipolar Charge Pump
6.1.2
Configuration 2: Boost Converter + Shunt Regulator
80
+ Bipolar Charge Pump
6.1.3
Configuration 3: Boost Converter (DTMOS) + Bipolar Charge Pump
80
only
6.2
Unipolar and Bipolar Charge Pump
81
6.3
Charge Pump Control and Peripheral Circuits
84
6.3.1
Frequency Adjustable Oscillator
84
6.3.2
Unipolar to Bipolar Level Shifter
84
6.3.3
Bi-directionality of Power Flow
85
Simulations and Measurements Results
85
6.4.1
Simulation results of configuration 1
85
6.4.2
Simulation results of configuration 2
86
6.4.3
Measurement results of configuration 3
86
6.4
6.5
Summary
Chapter 7
87
Conclusions
92
7.1
Conclusions
92
7.2
Potential Future Works
93
References
95
Appendix A
Prototypes Photos
107
Appendix B
Biography and List of Publications
109
vii
LIST OF FIGURES
Figure 1.1
IoT devices versus world population growth trend (Cisco IBSG 2011)
1
Figure 2.1
Simplified equivalent circuit model and output characteristics of TEG [18]
8
Figure 2.2
Power and Power density of conventional TEG (TEG-I) and new
8
generation TEG (TEG-II)
Figure 2.3
I-V characteristics of TEG [18] at ΔT = 4 °C, ΔT = 5 °C and MFC
9
Figure 2.4
Simplified equivalent circuit model of PVC and its output characteristics
10
Figure 2.5
Simplified equivalent circuit model of PEH and its output characteristics
11
Figure 2.6
Leakage current versus voltage profiles of the ultrathin capacitor
13
Figure 3.1
Proposed energy harvesting scheme I (Unipolar Outputs)
18
Figure 3.2
Proposed energy harvesting scheme II (Bipolar Outputs)
18
Figure 3.3
Basic working principle of series voltage regulator
19
Figure 3.4
Basic working principle of shunt voltage regulator
19
Figure 3.5
Basic working principle of (a) buck, (b) boost, (c) buck-boost
20
switched-inductor DC-DC converter
Figure 3.6
Basic working principle of switched-capacitor DC-DC converter for
21
(a) step-down, (b) step-up, (c) invert
Figure 4.1
Digital logic based implementation of shunt voltage regulator
24
Figure 4.2
Illustration of Schmitt-Trigger leakage suppression
25
viii
Figure 4.3
(a) 2-T picowatt voltage reference (b) 3-T voltage monitor
27
Figure 4.4
Simulated temperature variation of 2-T picowatt voltage reference
27
Figure 4.5
Simulated line regulation of 2-T picowatt voltage reference
28
Figure 4.6
Piezoelectric harvester output power profile
29
Figure 4.7
Voltage supervisor circuit detects presence of discontinuous-mode
30
energy source and its measured operation waveforms
Figure 4.8
Die photos of shunt regulators
31
Figure 4.9
Schmitt-Trigger DC hysteresis and threshold trip point simulations
32
Figure 4.10
Simulated system cold start-up time required by single source (PEH only)
33
and three sources (PVC+PEH+TEG) system
Figure 4.11
Start-up transient pre-layout simulation without RCOMP (top)
34
post-layout simulation with RCOMP (bottom)
Figure 4.12
Die-to-die measured regulated voltage versus simulation
35
Figure 4.13
Measured operation waveforms when voltage supervisor is (a) dormant,
35
(b) activated due to high DT-source
Figure 5.1
Efficiency graph comparison between two state-of-the-art transformer
37
-based boost converters (LTC3108 and JSSC2012 [55])
Figure 5.2
Simplified schematic of transformer oscillation mode boost converter
38
Figure 5.3
Simplified equivalent circuit of dual-mode transformer-based solution
39
at boost converter mode
ix
Figure 5.4
Proposed boost converter using 1:1 turn ratio pulse transformer
41
Figure 5.5
Conceptual blocks of proposed boost converter
42
Figure 5.6
Proposed boost converter operation waveforms
45
Figure 5.7
Off-state current due to sub-threshold leakage and GIDL effect
46
Figure 5.8
Impedance adjustment principles in boost converter
47
Figure 5.9
Gate bias changer concept to alter boost converter input impedance
49
Figure 5.10
Integration of bipolar output pulse transformer boost converter
51
into the proposed stack capacitors scheme [64]
Figure 5.11
Bipolar output pulse transformer boost converter operation waveforms
52
Figure 5.12
Cross-section of Bulk DTMOS realized with deep N-well isolation
53
and the required CMOS process flow [74]
Figure 5.13
gm-to-Ids ratio of DTMOS and conventional MOS
54
Figure 5.14
Ids versus Vds of DTMOS and conventional MOS
54
Figure 5.15
Bipolar pulse transformer boost converter, cross-section view of
55
DTMOS configuration, and self-start-up free-running boost converter
operation waveforms
Figure 5.16
Piezoelectric Energy Harvesting system architecture
56
Figure 5.17
Discontinuous time operation of pulse transformer boost converter
57
Figure 5.18
Maximum power point tracking algorithm and possible implementations
59
using timing of VX
x
Figure 5.19
Simulation waveforms showing maximum power point operations
60
Figure 5.20
Proposed Boost Converter Die Photo
61
Figure 5.21
Schottky diode I-V characteristics at 25 ºC
64
Figure 5.22
Measured VS, VG, VX node voltage and inductor IL1 current waveforms
65
using LVLT transistor (with the lowest input voltage)
Figure 5.23
Measured VS, VG, VX node voltage and inductor current IL1
66
operation waveforms at non-MPP and MPP state for VGEN = 1.2 V
Figure 5.24
Measured free running switching frequency (without MPPT) using
67
L1 = 10 mH transformer A and L1 = 0.5 mH transformer D
Figure 5.25
Measured free running switching frequency (without MPPT) using
68
L1 = 4 mH transformers (B, C)
Figure 5.26
Measured power efficiency versus different transistors using L1 = 10 mH
68
and L1 = 0.5mH transformers
Figure 5.27
Measured power efficiency versus different transistors using
69
L = 4 mH transformers with 13 pF CIW and 78 pF CIW
Figure 5.28
Measured power efficiency comparisons between 10 mH-LVZT (best)
70
and 0.5 mH-LVZT (worst) combinations with existing transformer
boost converter LTC3108 and JSSC2012 [55]
Figure 5.29
Measured power efficiency of different transistors using L = 10mH
70
transformer versus input voltage VS with RS = 400 Ω
Figure 5.30
Measured DTMOS power efficiency of different transistors using
L = 10 mH transformer versus input voltage VS with RS = 400 Ω
xi
74
Figure 5.31
Measured VX, VY, VG and IL1 waveforms
74
Figure 5.32
Measured VIN, VCS1, IL1 and IL0 waveforms
75
Figure 5.33
Measurements showing (a) Minimum VIN at max VOUT = ±3 V
76
configuration, (b) Minimum VIN at max VOUT = ±2 V configuration,
(c) Minimum VIN at max VOUT = ±1 V configuration, (d) Four level
outputs (±3 V, 2 V, 1 V) at max VOUT = ±3 V configuration
Figure 6.1
1:100 transformer boost converter and unipolar charge pump [79]
79
Figure 6.2
1:1 transformer boost converter and bipolar charge pump [80]
79
Figure 6.3
(a) Cross-coupled charge pump (b) non-overlapped clock generation
83
Figure 6.4
Bipolar cross-coupled charge pump and peripheral circuits
83
Figure 6.5
Maximum power harvestable by charge pump and transformer boost
86
converter self-oscillation period versus TEG voltage
Figure 6.6
Simulated system operations for configuration 1 under varying input
88
voltage
Figure 6.7
Simulated system operations for configuration 2 under varying input
89
voltage
Figure 6.8
Chip micrograph of the fabricated DTMOS boost converter and bipolar
90
charge pump
Figure 6.9
Measured bipolar clock charge pump operations
90
Figure 6.10
Measured output voltage of configuration 3 (without shunt regulator)
91
xii
LIST OF TABLES
Table 1.1
Summaries of Design Requirements and Challenges
4
Table 2.1
Device Characteristics of Different Energy Sources
12
Table 2.2
Classifications of Energy Sources
12
Table 3.1
Summary of different DC-DC converters
22
Table 5.1
Transistor Types Used in Experiments
62
Table 5.2
Transformers Parameters Used in Experiments
63
Table 5.3
Input power, switching frequency at minimum start-up voltage and peak
64
power efficiency for all transformer-transistor combinations
Table 5.4
Performance comparisons with related works
71
Table 5.5
Comparison Table of Proposed Scheme over Existing Multi-Input Source
73
Schemes
Table 6.1
Internal Power Loss Mechanisms of Charge Pumps
xiii
82
CMOS Power Management Circuits and Systems for Microwatts Energy Harvesting
by TEH Ying Khai
Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology
Abstract
In recent years, the Internet of Things (IoT) era is growing in momentum. It is
desirable that all IoT devices are designed to be in-situly energy autonomous via energy
harvesting, since battery replacement in such astronomical scale is laborious and expensive.
This thesis first reviews the state-of-the-art of microwatts energy harvesting sources and
storage capacitors. Based on the electrical characteristics of different energy harvesting
sources and storage capacitors, an integral multi-source energy harvesting scheme is proposed
to power a multi-level supply voltage wireless sensor node at system level. Circuit level
innovation associated with building the proposed system architecture, i.e. linear regulator,
switched-inductor and switched-capacitor converters are then pursued. The circuit prototypes
are implemented on a standard 0.13-µm CMOS process.
A shunt regulator is designed to provide voltage supervision, regulation and overvoltage protection, and balance individual storage capacitor in a stacked-capacitor system.
The core circuit of the shunt regulator is a multi-threshold six-transistor Schmitt-Trigger,
which is conventionally regarded as a digital logic cell that consumes minimal quiescent
power. The measured mean output voltage is 1.118 V and standard deviation is 8 mV.
Conventional transformer-based boost converters commonly used to achieve
autonomous low voltage start-up encounter low efficiency and potential start-up failures when
energy harvesting source with high internal resistance is used. An improved design of
transformer-based boost converter with bipolar output option is proposed to solve the start-up
problem. Circuit techniques to enable maximum power point tracking feature of this boost
converter are also investigated. Minimum start-up voltage of boost converter measured is 21
mV, requiring 5.8 µW of input power to generate 1 V output, with peak efficiency of 74%.
Instead of permitting shunt regulator routes unused power to ground, charge pump is
connected in parallel to the shunt regulator, with the intention to transfer the excess power to
secondary storage capacitor. Internal power loss mechanisms of charge pump circuits which
can be utilized to supplement the shunt regulator are studied. Besides, a bipolar clock driven
cross-coupled charge pump and the associated level shifter circuit are presented. Using thick
oxide transistor, the proposed charge pump can generate up to 6 V output from 300 mV input.
xiv
CHAPTER 1
INTRODUCTION
1.1
Background and Motivation
In near future, it is envisaged that digital sensing, communication, and information
processing capabilities will be ubiquitously embedded into everyday objects, propelling us
into the era of Internet of Things (IoT) [1]. The growth trend of devices connected to internet,
versus the world population is shown in Figure 1.1. By 2020, it is foreseen that there will be
50 billion IoT devices, whereas the world population will stand at 7.6 billion. Cisco predicts
that the IoT’s potential value will be 14.4 trillion US dollars for companies and industries
worldwide in the next decade. Over the next 10 years, this potential value represents an
opportunity for global corporates to increase their profit by 21% [2].
Figure 1.1 IoT devices versus world population growth trend (Cisco IBSG 2011)
Rapid advancement of networking technology and miniaturization of electronic
devices enable interesting applications that connect the internet and physical worlds. In this
1
new paradigm, wireless sensor node (WSN), which is an important member of the IoT family
will collect data, relay the information to each other wirelessly, and can process the
information in distributive manner. Some application examples of the emerging paradigm
include:
1) Environmental monitoring: In Southeast Asia countries such as Indonesia and
Malaysia, illegal deforestation over valuable logs or slash-and-burn agriculture of aboriginals
have caused hazardous environmental problems [3]. Massive wireless sensor nodes can be
installed across rain forests to detect these illegal activities. By relaying the collected data to
internet, the public can monitor the forests over the internet via crowd sourcing effort, instead
of just relying on proactive law enforcement from the authority.
2) Smart healthcare: Many countries in the world are having aging population [4],
particularly developed economies in East Asia such as Hong Kong. Indoor and body sensors
can monitor the health condition of elderly people and properly provide in-time help (e.g.
reminders of missing a dose, warning of high blood pressure and requesting medical
emergency in case of accidental fall).
3) Predictive manufacturing with Big Data [5]: Predictive manufacturing begins with
data acquisition where different types of sensory data are available to acquire such as
acoustics, vibration, pressure, current, voltage and controller data. Vast amount of sensory
data in addition to historical data construct the Big Data in manufacturing, which act as the
inputs into predictive tools and preventive strategies towards near-zero production downtime
and supply-chain transparency.
For the aforementioned applications, enormous numbers of sensor nodes will be
deployed and two major issues will require attention. First, releasing massive number of
batteries since their toxic byproduct [6] will leech into soil and water and cause environmental
disaster. Second, the costs of servicing such sensor nodes as it will also be incredibly
laborious to replace batteries once they are deployed in the field. Therefore, one major
challenge is to design low power sensor node that require minimal battery change
maintenance. This creates a demand for energy harvesting systems which involves in situ
power extraction from the surrounding, voltage conversion and alternative energy storage i.e.
capacitor due to their longer lifespan than batteries.
2
1.2
Research Challenges and Goals
Existing energy autonomous WSN is commonly powered by single energy harvesting
source; with photovoltaic cell (PVC) being the most popular and matured technology.
Nevertheless a single source energy harvesting system is often intermittent and unpredictable
in term of power generated. For example, PVC-powered WSN reported in [7] needs a very
large energy storage capacitor to compensate for the minimal solar power during shady days.
Instead of increasing storage capacitor size, recent research direction such as [8] is to pursue
energy harvesting schemes using multiple energy sources. The standalone non-PVC devices
needed to harness and generate microwatts of electrical power are readily available. For
example the vibrations of a person walking on a bridge via piezoelectric harvester (PEH) [9];
and temperature difference between body temperature and ambient air via thermoelectric
generator (TEG) [10]. These novel miniaturized energy sources are typically fabricated using
state-of-the-art thin film fabrication process which brings energy generation device of higher
power density and smaller physical size than their conventional siblings.
The first key challenge is the design of interfacing power management circuit that
efficiently combines many different sources of energy into one. Combining the power from
variable sources conventionally requires a sophisticated control system as demonstrated in
[8]. The control itself requires additional overhead power, i.e. first sense the availability of
power from each source, then compute and optimize the multi-source time multiplexing.
Another challenge is the limit imposed by the low supply voltages in standard CMOS
technologies. These constrain the output voltage to be within the defined supply voltage. At
higher voltages outside of the nominal range, breakdown mechanisms and hot carrier effects
will be present. Hence the power management circuit must prevent the overvoltage problem.
On the other end of the spectrum, some energy sources have very low input voltage (< 0.2V),
which are lower than transistor threshold voltage. At sub-threshold region, transistors are not
fully turned on and conventional voltage converter topologies are no longer valid or suffer
poor conversion efficiency.
Typical power consumption pattern of a WSN is low average power (no active power
consumption except watch dog timer) but occasional occurrence of high concentrated burst of
power to accomplish a task such as activating external sensors or sending radio packets. If
3
these bursts occur with a low duty cycle such that the total energy needed for a burst can be
accumulated between bursts then the output can be maintained entirely by the energy
harvesters. An ideal energy harvesting scheme is required to maintain low leakage power of
harvested energy during WSN idle period yet able to supply high pulsed power on demand.
Multi-level supply voltage (VDD) is common for WSN systems implemented using
low power modern CMOS process. External I/O interface circuits typically works at 3 V (5 V
for legacy devices) and internal digital core circuits typically works at 1 V. Modules such as
sensors, analog-to-digital-converters (ADC) and amplifiers always prefer higher voltage
headroom to achieve better resolution, gain and linearity [11]. For battery-powered
applications, such multiple output voltage can be realized using Single-Inductor-MultipleOutput (SIMO) DC-DC converter [12]-[14] or multiple series regulator i.e. low dropout
regulator (LDO) [15]-[17]. These conventional approaches become unrealistic when the input
power approaches microwatts range as the overhead power is too high to jeopardize the entire
system operation.
Design requirements of energy harvesting system to power a wireless sensor node and
the associated challenges hitherto discussed are summarized in Table 1.1.
TABLE 1.1 SUMMARIES OF DESIGN REQUIREMENTS AND CHALLENGES
Input voltage
0 – 12 V
Input current
0 – 1 mA
Input power
0 – 1 mW
Dual output voltage
1 V (Digital), 3 V (Analog, RF and sensors)
CMOS 0.13-µm process
nominal threshold voltage
0.3 – 0.4 V
CMOS 0.13-µm process
nominal voltage
1.2 V (Thin oxide), 3.3V (Thick oxide)
-
Design features required
-
Smallest input voltage and power
possible
Smallest overhead and leakage power
possible
Highest voltage conversion ratio and
efficiency possible
Self-start-up during cold-start state
Over-voltage protection
4
1.3
Thesis Contribution
The contributions of this thesis are as follow:
The state-of-the-art of microwatts energy harvesting sources and storage capacitors
were reviewed. Catering to the device characteristics of different energy harvesting sources
and storage capacitors, an integral multi-source energy harvesting scheme is proposed to
power a multi-VDD wireless sensor node (WSN) at system level.
Circuit level innovations required in building the proposed system architecture, i.e.
linear regulator, switched-inductor and switched-capacitor converters were subsequently
pursued. New circuit topologies designed and new perspectives on existing circuit discovered
during the process include:
A circuit topology conventionally used for digital logic application i.e. SchmittTrigger cell is proposed as comparator block. Multi-threshold technique is employed to
minimize static leakage current. This comparator circuit consumes nano watts range of
quiescent power at off-state, which is instrumental in energy constraint applications. A
process insensitive shunt regulator and voltage supervisor is derived based on this cell.
In contrast to the common views that only high turns-ratio transformer can assist in
boosting very low input voltage, this thesis shows that in fact 1:1 ratio transformer can be
used for the same objective. It is demonstrated that boost converter topology based on 1:1
transformer yields similar start-up voltage and indeed has better power conversion efficiency.
Charge pump is proposed to supplement the shunt regulator, by intentionally adjusting
the built-in power loss of the topology. This circuit transfers unused energy to secondary
storage capacitor. Due to the bi-directionality of power flow, energy can be transferred back
to the main storage capacitor when the primary power source is absent or insufficient.
5
1.4
Thesis Organization
This thesis is organized into seven chapters. In the first chapter, the overview of
research motivation, challenges and goals are outlined.
Chapter 2 reviews four common energy harvesting sources i.e. thermoelectric
generator, microbial fuel cell, photovoltaic cell and piezoelectric harvester. Subsequently
these sources are classified in terms of power availability, using a voltage-current-time
matrix. Lastly a study of high density thin-film capacitor characteristics wraps up the chapter.
Chapter 3 presents the multi-level stacked capacitor system level architecture
proposed, which is designed after considering the characteristics of different energy sources
and storage capacitor. Basic DC-DC converters including linear regulator, switched-inductor
and switched-capacitor converters which can be used to build the proposed system are also
briefly discussed.
Chapter 4 explains the design and circuit operation of the six-transistor SchmittTrigger cell. Applications of this comparator circuit in voltage supervisor and shunt regulator
are elaborated. Simulations and measurements of the prototype chip are presented.
Chapter 5 first analyzes the conventional transformer used in boost converter for very
low input voltage energy source. New boost converter topologies using 1:1 transformer are
proposed, which comprise of unipolar and bipolar versions. Circuit performance of this new
class of circuit using different transformer parameters and transistor types are reported.
Chapter 6 studies the internal power loss mechanisms of cross-coupled charge pump,
and its application to transfer unused power to secondary storage capacitor, in parallel or in
lieu of shunt regulator. Further enhancement over the ordinary cross-coupled charge pump,
i.e. a bipolar clock driven version and the associated level shifter circuit are presented.
Simulations and measurements of systems configurations based on secondary power
extraction are reported.
Finally, Chapter 7 concludes and summarizes the entire thesis. This chapter also
suggests several future research directions possible.
6
CHAPTER 2
REVIEW OF ENERGY HARVESTING SOURCES AND STORAGE
Advancement in the thin-film fabrication has successfully produced new generation of
energy harvesters at reasonable cost, comes with compact size and able to generate
microwatts range of power via surrounding events. An overview of energy harvesters
commercially available are given in this chapter. Section 2.1 to Section 2.4 reviews four
different kinds of energy harvesting, using different energy transduction principle i.e.
thermoelectric, biological reaction, photoelectric and piezoelectric. Section 2.5 classifies these
sources into two table of summary according to their voltage-current-time matrix. Finally
Section 2.6 studies characteristics of modern thin-film high density capacitors as energy
storage element due to their enhanced life time over rechargeable batteries.
2.1
Thermoelectric generator (TEG)
Thermoelectric generator (TEG) is an interesting energy harvester for its continuous
operation against environmental condition change, due to omnipresence of thermal energy
gradient (which manifests as temperature difference). State-of-the-art TEGs are fabricated
using thin-film deposition technology of Bi2Te3 material. Such improvements are desirable
for further system miniaturization. The new generation TEG [18] has smaller device area with
increased power density (100 µW/mm2), compared to conventional bulk material based TEGs
[19] (13 µW/mm2) at temperature difference of 10°C. Simplified circuit model of TEG [18],
current-voltage characteristics are shown in Figure 2.1. Internal resistance (RTEG) of new
generation TEG is 400 Ω, which is 80 times larger whereas the absolute output power for
conventional TEG is 8 times higher. The output power and power density comparisons of the
two generation of TEGs are shown in Figure 2.2.
7
Figure 2.1
Figure 2.2
Simplified equivalent circuit model and output characteristics of TEG [18]
Power and Power density of conventional TEG (TEG-I) and new
generation TEG (TEG-II)
8
2.2
Microbial fuel cell (MFC)
Besides thermoelectric solution, another emerging power source is microbial fuel cells
(MFC). MFC harvests electricity from organic dispose such as waste water, which is
essentially byproduct of catalytic activities of microorganisms over various organic
substrates. The niche application of MFC is waste water treatment and water quality monitor.
Current state-of-the-art MFCs are fabricated using emerging material such as graphene [20]. It
is interesting to note that thin-film TEG operating at low temperature difference (4 to 5 °C)
and graphene-based MFC have similar electrical characteristics, as shown in Figure 2.3.
Electrically both energy sources can be modeled as an ideal voltage source (V GEN) in series
with internal resistance (RS) of a few hundred ohms.
Figure 2.3
2.3
I-V characteristics of TEG [18] at ΔT = 4 °C, ΔT = 5 °C and MFC
Photovoltaic cell (PVC)
PVC is capable of converting light directly into electric energy. Most PVCs consist of
silicon material. Light is often present for a prolonged period, during which the light energy
can be accumulated in storage mechanisms and then used when needed. [21], [22] Simplified
circuit model of PVC in [21] and typical output behavior is shown in Figure 2.4.
9
Figure 2.4
2.4
Simplified equivalent circuit model of PVC and its output characteristics
Piezoelectric harvester (PEH)
PEHs with size smaller than a US quarter coin and internal parasitic capacitance of a
few nano Farad are now manufactured via commercial CMOS process [23]. The generated
power is in alternating current (AC) mode and thus requires to be rectified before use.
Simplified circuit model of PEH with rectified output in [23] and its typical output behavior is
shown in Figure 2.5. However, as miniaturization continues, the mechanical vibration
bandwidth for smaller devices is also getting smaller (a few Hertz). Therefore PEH is
sensitive towards environment stimuli and the output power profile is often discontinuous in
time.
10
Figure 2.5
2.5
Simplified equivalent circuit model of PEH and its output characteristics
Summary of Energy Source Characteristics and Classification
Table 2.1 summarizes key device characteristics of four different energy harvesters
under low output power condition (less than 100 µW) i.e. TEG only has 2°C of temperature
difference between the Peltier junctions, MFC with 50 ml of biofuel, PVC is illuminated at
200 lux (indoor lighting condition) and PEH is vibrated at 0.1 g. Electrical behavior of TEG
and MFC generally changes slowly over time and therefore can be regarded to be continuous
time operation. PVC and PEH are responsive towards input stimuli change and will change its
electrical output abruptly. Hence PVC and PEH can be classified to be discontinuous time
operation. Table 2.2 classifies these four energy harvesters into according to voltage-currenttime matrix.
11
TABLE 2.1
Type
VOC (max)
ISC (max)
VMPP*
PMPP**
DEVICE CHARACTERISTICS OF DIFFERENT ENERGY SOURCES
TEG [18]
MFC [20]
PVC [21]
0.3 V
0.6 V
4V
750 µA
(@ΔT=2°C)
0.15 V
(@ΔT=2°C)
56 µW
(@ΔT=2°C)
2.7 mA
0.35 V
440 µW
7 µA
(@200 lux)
3V
(@200 lux)
14 µW
(@200 lux)
Dimension
4×3×1
37×37×37
35×13×1
(L×W×H mm3)
*
VMPP = Operating voltage of energy source at maximum power point
**
PMPP = Output power of energy source at maximum power point
TABLE 2.2
Type
PEH [23]
8V
(rectified)
14 µA
(@0.1g)
4V
(@0.1g)
56 µW
(@0.1g)
15×15×6
CLASSIFICATIONS OF ENERGY SOURCES
TEG [18]
MFC [20]
PVC [21]
PEH [23]
Voltage
Low
Low
High
High
Current
High
High
Low
Low
Time
DT
DT
CT
CT
*CT: Continuous time DT: Discontinuous time
2.6
High Density Capacitor as Energy Storage
A capacitor is analogous to storage reservoir for electrical charge carriers, as a water
bucket to water flow. The capacitor leakage current can be compared to the water seeping
through the water bucket. A capacitor will never become fully charged if the leakage current
is greater than or equal to the supply current. Designer needs to take extra caution especially
when these capacitors are to be charged by microwatts power source as the charging current
are comparable to leakage current. Recently, molecularly thin film capacitor of 28 nm
thickness (claimed to be better than graphene) and capacitance density of 27.5 μF/cm2 (2000
times higher than currently available commercial products) was fabricated using oxide
nanosheets [24]. Leakage current versus applied voltage characteristics of such emerging
capacitor type is shown in Figure 2.6, of which leakage current is exponentially dependent on
DC bias.
12
Figure 2.6
Leakage current versus voltage profiles of the ultrathin capacitor
One way to reduce leakage current is to bias a capacitor at much lower value than its
full rated voltage. By setting capacitor voltage to 1 V (50%) of full rated voltage (2 V) using
individual regulator designed for each stack capacitor, leakage current can be reduced to only
1% of full rated value of capacitor. Similar trend can also be observed on off-the-shelf generic
tantalum capacitors [25] or 40% of rated voltage for a commercially available super-capacitor
[26]. Nevertheless a favorable side-effect is that lowering capacitor operating voltage
simultaneously increases the work life of capacitor, which means less maintenance works. For
critical application such as military and aerospace where long lifespan is necessary, designer
typically uses at most 50% of rated voltage or even lower.
Connecting capacitors in series results in the voltage being split between the
capacitors and in turn this is influenced by the leakage current difference between the
individual capacitors in a series, as shown in Figure 2.6. The leakage current component can
be modeled as a parallel resistor to the capacitor. The leakage current differences become
apparent when the circuits are activated in the form of overvoltage on the component with the
13
lowest leakage current. Since considerable fluctuations can be found between individual
capacitors (even from the very same production run) in terms of their leakage currents and
capacitance, it is possible that large voltage differences may occur and one capacitor in the
stacks will sustain higher voltage despite all having the same nominal capacitance. It is
therefore important that both capacitance and leakage current differences are balanced in the
system since leakage current can vary up to two order of difference.
The simplest form of balancing circuit is a fixed value resistor parallel to each
capacitor. However, this method merely provides balanced voltage but not voltage regulation.
To obtain both balancing and regulated voltage, a low quiescent current shunt regulator (with
minimal leakage current in its internal voltage reference and parasitic junction diodes) is a
better candidate. Chapter 4 presents a possible circuit solution for this application, derived
from a standard digital cell.
14
CHAPTER 3
SYSTEM ARCHITECTURE AND CIRCUIT BLOCKS
In previous chapter, electrical characteristics of various energy harvesting source and
storage capacitors were reviewed. Based on these properties, this chapter first proposed
integral system schemes to accommodate multiple types of energy sources simultaneously
and minimize storage leakage loss. Each circuit block that can be utilized to implement the
proposed system i.e. linear regulator, switched-inductor and switched-capacitor DC-DC
converters are then stepped through briefly in sequential manner.
3.1
Proposed Multi-Source Stacked Capacitor System
Under extreme low input stimulus as shown in Table 2.1, the output power from
miniaturized PVC and PEH is of microwatts range, albeit output voltage at open circuit
condition of these sources can be as high as 8 V. Considering the burst mode nature of
incoming power, isolation diodes and interfacing power IC are especially vulnerable to
breakdown. In standard CMOS process, for instance in the selected UMC 0.13-µm process,
the nominal voltage is only 1.2 V for thin oxide transistor and 3.3 V for thick oxide transistor.
Obviously input protection circuit needs to be included to avoid overvoltage breakdown
caused by such high harvester output voltage. Conventionally series regulator such as low
dropout regulator (LDO) is preferred over shunt regulator for higher power efficiency but this
topology does not provide any input protection. When input voltage is as high as 8 V, the
differential voltage across the dropout transistor is 5 V, if the output voltage is set to 3 V; this
condition exceeds the drop out transistor breakdown limit.
The fundamental difference between battery power source and energy harvesting
source is that energy harvesters have significantly higher source resistance (>>1 Ω) compared
to battery (<1 Ω). However, in battery powered application, charge stored in non-rechargeable
battery is limited. Before the battery stored charge depletes, power sourcing capability of a
battery is much higher than energy harvesting source in general. Therefore if shunt regulator
is used, constant power will be drawn from battery despite the load power being low. This is
disaster especially for low duty long working hour WSN application because battery charge
depletes quickly. This scenario is exactly how the conventional wisdom i.e. series regulator is
15
more efficient is being derived.
For energy harvesting source, supply of electrical charge is in theory unlimited and
most of the time the energy harvester is charging up the storage capacitor. Before storage
capacitor voltage reaches the designed threshold, the regulator is turned off. Having a shunt
regulator in this scenario basically acts as charge release valve. The objective is to sense the
storage capacitor voltage, once the set threshold is reached, additional charge harvested will
be dissipated by shunt regulator. If a series regulator is used instead, the system is prone to
overvoltage failure as excess charge will continue to accumulate and build up storage
capacitor voltage. Overvoltage protection should be prioritized over power conversion
efficiency in this scenario. Hence the automatic protection against overvoltage function of a
shunt regulator is indeed attractive for energy harvesting application. High voltage headroom
generated by PVC and PEH output can be absorbed by a properly designed shunt regulator
such as [27], allowing storage capacitor to be directly charged by these sources.
Multi-level supply voltage (VDD) is common for WSN systems implemented using
low power modern CMOS process. External I/O interface circuits typically works at 3 V (5 V
for some legacy device) and internal digital core circuits typically works at 1 V. Modules such
as sensors, analog-to-digital-converters (ADC) and amplifiers always prefer higher voltage
headroom to achieve better resolution, gain and linearity [11]. For battery-powered
applications, such multiple output voltage can be realized using Single-Inductor-MultipleOutput (SIMO) DC-DC converter or multiple series regulator i.e. LDO. This approach
becomes unrealistic when the input power approaches microwatts range as the overhead
power is too high to jeopardize the entire system operation. In order to realize multi-level
supply voltage using minimal overhead power, one intuitive way is to stack up capacitors in
series, where capacitive divider will provide the output voltage on individual capacitor VCN
according to (1), where N is the number of capacitors in stack, VCC is the applied voltage:
VCn 
V CC
N
(3.1)
The first proposed scheme essentially emulates a water bucket fountain by envisioning
capacitor as individual water bucket; as illustrated in Figure 3.1. Incoming charge from high
voltage low current (HVLI) energy harvesting sources i.e. PVC and PEH will charge up stack
16
capacitors directly. Once capacitor voltage reaches the set value, excess charge will be pushed
to next capacitor below, and eventually to ground if all capacitors are fully charged to preset
ΔV value i.e. 1 V. This operation is similar to push pull shunt regulation discussed in [28].
Diodes can be used to isolate incoming power of PVC and PEH.
By combining the idea of divided series capacitor voltage to provide multiple voltage
level, by connecting multiple capacitors in series, multiple voltage levels can be generated.
Top capacitor (3V) can power high voltage circuits (I/O, sensors, ADC, analog and RF) and
bottom capacitor (1V) can power low voltage low power digital circuits. In this proposed
scheme, high incoming power can be driven directly by the primary power source when it is
available. However when ambient power is insufficient, capacitor stacks will act as “flyingbattery” configuration [29] to supply high power, short interval required by WSN since each
capacitor-shunt regulator pair forms a standalone “battery”. All capacitors in the stack share a
common DC current when WSN draws current.
An additional boost converter is required to extract power from a low voltage low
current (LVLI) energy harvesting source i.e. TEG. As extra power from TEG will be shunted
to ground by shunt regulator, a fast response charge pump is also proposed to extract C S3
power to CS1 (which provides 3 V output), whenever PVC and PEC do not generate sufficient
power. During operation, bottom capacitor CS3 will be first fully charged up to 1 V, followed
by CS2 (2 V) and then finally CS1 (3 V). This is because the leakage current from shunt
regulator at higher stack trickles down and charges up the bottom capacitor. Such voltage
charge up sequence is indeed desirable as this enables the core digital baseband to be first
started up prior to other peripheral modules.
In Chapter 5, a bipolar output version of boost converter is proposed. For such
converter, an alternative system configuration as shown in Figure 3.2 can be used. Instead of
regulator unipolar charge pump in Figure 3.1, a bipolar clock driven charge pump (which is
discussed in Chapter 6) is needed to extract and merge energy from CPOS and CNEG into CHV.
Both systems accept low input and high input voltage sources, and can simultaneously
harvests multiple energy sources (continuous-time or discontinuous-time, low output voltage).
Both systems can generate multiple output voltage levels to suit different supply voltage
requirements.
17
Figure 3.1
Proposed energy harvesting scheme I (Unipolar Outputs)
Figure 3.2
Proposed energy harvesting scheme II (Bipolar Outputs)
18
3.2
Brief Review of Linear Regulator
There are two possible implementations for linear regulators i.e. series and shunt
regulators. In principle these circuits can be designed based on the functional blocks shown in
Figure 3.3 and Figure 3.4 respectively. The internal resistance of energy harvesting source can
be treated as series resistance RS needed in any typical linear regulator realization. Series
voltage regulator is more power efficient but lacks the ability to prevent over-voltage. Shunt
voltage regulator is less power efficient but it can protect the circuit from over-voltage, which
is useful when interfacing with high voltage low input energy source. However, linear
regulator can only step down input voltage to generate a lower output voltage. The best
conversion power efficiency possible is VO / VS, which implies that this type of regulator is
considered efficient only when the ratio of conversion is close to unity.
Figure 3.3
Basic working principle of series voltage regulator
Figure 3.4
Basic working principle of shunt voltage regulator
Voltage Reference element forms the foundation of linear regulator since VDD must be
either equal or a multiple of reference voltage VREF. For good regulation, VREF must be stable
across VDD variations. Voltage Sample element monitors VDD and translates it into a level
equal to the VREF for a desired regulated voltage. Variations in VDD cause feedback which
changes VSAMPLE to some value greater than or less than the VREF. ΔVSAMPLE causes
19
comparator to drive series or shunt element which would respond appropriately to correct the
output voltage change.
Figure 3.5
3.3
Basic working principle of (a) buck, (b) boost, (c) buck-boost switchedinductor DC-DC converter
Brief Review of Switched-Inductor Converter
Switched-inductor converter involves three different electrical components i.e. switch
SWN, inductor LN, diode DN, with the objective of converting a given supply voltage VS, to
output voltage VO. There are three basic configurations possible, as illustrated in Figure 3.5.
Figure 3.5(a) is a buck converter [30] where VO < VS. Figure 3.5(b) is a boost converter [31]
where VO > VS. Figure 3.5(c) is a buck-boost converter [32] where VO can be larger than or
less than VS. All output-input voltage relationship of these converters can be adjusted by
changing the switching clock duty cycle. The advantage of switched-inductor converter is the
high conversion power efficiency, which can be up to 90%, achievable across different
conversion ratio. The disadvantage is the requirement of off-chip inductor, which is bulky and
expensive. Fully integrated on-chip switched-inductor converter is a popular on-going
research topic [33], [34].
20
Figure 3.6
3.4
Basic working principle of switched-capacitor DC-DC converter for (a)
step-down, (b) step-up, (c) invert
Brief Review of Switched-Capacitor Converter
An alternative to using inductor is by shifting to the other reactive circuit element, i.e.
capacitor. Switched-capacitor DC-DC converter is also known as charge pump. The main
advantage is that fully integrated on-chip implementation is possible and bi-directionality of
conversion. For applications where bulky off-chip components must be avoided, charge pump
is a good compromise between linear regulator and switched-inductor. Similar to the switchedinductor counterpart, as shown in Figure 3.6, there are three basic switched-capacitor
configurations, which allow designers to step down [35], step up [36] and invert [37] a given
voltage. Typically 50% duty 2-phase (Φ1, Φ2) clock is used.
21
3.5
Summary of different DC-DC converter
Table 3.1 summarizes the characteristics of different DC-DC converter circuits
according to conversion possible, peak power efficiency and output voltage control.
TABLE 3.1
SUMMARY OF DIFFERENT DC-DC CONVERTERS
Conversion
direction
(Up / Down)
Peak power
efficiency
Output voltage
Linear
Regulator
Down
Low
Adjustable by
reference voltage
Switchedinductor
Up / Down
High
Adjustable by
clock duty cycle
Switchedcapacitor
Up / Down
Medium
Adjustable by
clock duty cycle
Type
22
CHAPTER 4
SHUNT REGULATOR AND VOLTAGE SUPERVISOR BASED ON DIGITAL
SCHMITT-TRIGGER CELL
This chapter chiefly discusses the circuit implementation and operation of a sixtransistor Schmitt-Trigger, which has very low off-state quiescent power due to the digital
nature. Two applications i.e. shunt regulator and voltage supervisor based on this core circuit,
are demonstrated. In the last section, we wrapped up the chapter by presenting the simulation
results and experimental results obtained from the prototype chip.
4.1
Shunt Regulator
There are many possible implementations for shunt regulators, most are designed
based on the working principle shown in Chapter 3.2. The internal resistance of energy
harvesting source can be treated as series resistance RS needed in any typical shunt regulator
realization. Conventional implementation of comparator is a high gain op-amp with
differential input and fixed current source biasing. Op-amp operation continuously draws
current since system start-up; even there is no input transition yet. An alternative way to
reduce this fixed quiescent current consumption is to switch to digital static logic cell. Due to
the binary nature, quiescent current of digital static logic is essentially zero except the leakage
current component.
The proposed digital logic based shunt regulator is shown in Figure 4.1. Voltage
reference and voltage monitor blocks jointly form the equivalent of Voltage Sample element
shown in Figure 3.4. To reduce quiescent power, voltage reference reported in [38] is
designed in this thesis, which consumes less than 1 nW of static power. Voltage monitor
block is actually an active DC level shifter which is derived based on the flipped voltage
follower topology [39]. Instead of a differential input op-amp, a classic six transistors CMOS
Schmitt-Trigger [40] is used as the comparator element.
23
Figure 4.1
4.2
Digital logic based implementation of shunt voltage regulator
Six-transistor Schmitt-Trigger
The topology of implemented Schmitt-Trigger with the W/L ratios of all transistors is
shown in Figure 4.2. P0, P2, N0 and N2 are specifically sized to minimize leakage current. The
equivalent of Voltage Reference input terminal is indeed hidden in circuit property of
Schmitt-Trigger i.e. upper tripping threshold voltage (VH_TRIP). Hence this design eliminates
the need of negative input terminal of a conventional analog comparator. Due to the positive
feedback, Schmitt-Trigger offers excellent transition edge (high gain) and well defined
switching threshold point. The peak power (short circuit power) of a CMOS Schmitt-Trigger
can be shown to be:
PSC  VDD  N 0 (VH _ TRIP  VTN 0 ) 2
(4.1)
where βN0 = 0.5µNCOX(W/L)N0 and VTN0 is threshold voltage of N0. The built-in hysteresis of
a Schmitt-Trigger increases or decreases the switching threshold depending on the direction
of the input transition based on first order trip point’s formulas (VL_TRIP is the lower trip point)
as follows:
VH _ TRIP 
VL _ TRIP 
V TN 0VDD  N 2 /  N 0
1
N 2 / N 0
 P 0 /  P 2 VDD  VTP 0 
1   P0 /  P2
24
(4.2)
(4.3)
Given that βN2 = 0.5µNCOX(W/L)N2, βP0 = 0.5µPCOX(W/L)P0, βP2 = 0.5µPCOX(W/L)P2 and VTP0
is threshold voltage of P0.
The output characteristic of Voltage Monitor block is shown in upper left corner of
Figure 4.2. VBIAS is held at 0 V before VDD reaches the minimal value required for SchmittTrigger to have the desired switching threshold point. This helps VDD to increase
monotonically i.e. VSHUNT will track VDD, and turning off PSHUNT. The output characteristic of
VSHUNT is shown in lower left corner of Figure 8. When VBIAS reaches VH_TRIP, SchmittTrigger switches its VSHUNT output node abruptly, forcing PSHUNT to start drawing current
from VDD rail, and thus regulating VDD equal to VTARGET. VSHUNT node is considered the
critical node in the regulator. Leakage current of P2 and N0 will cause VSHUNT to deviate from
tracking VDD during initial start-up. Hence effective suppression of leakage currents from the
VSHUNT node is necessary.
Figure 4.2
Illustration of Schmitt-Trigger leakage suppression
During start-up, feedback transistor N2 is turned on whereas N0 and N1 are off.
Whenever VBIAS is low, N2 pulls the middle node A to a high potential. This forces the drainsource voltage of N1 (VDS1) close to zero and its gate-source voltage (VGS1) into the negative
value which reduces the leakage current through N0 exponentially. Hence the result is
25
effective leakage suppression from the output node VSHUNT, which minimizes the output level
degradation. Moreover multi-threshold transistor technique is employed such that 3.3 V thick
oxide type transistor with high threshold voltage and low leakage current are used as P 2, N0
and N2 transistors. Transistors P0, P1 and N1 are 1.2 V thin oxide type transistor to minimize
the total VDD headroom requirement. By adopting multiple types of transistors in the same
topology, leakage current, short circuit power and minimum VDD required can be optimized.
With the excellent ION / IOFF ratio, this Schmitt-Trigger topology scales excellently,
which functions well even with sub-threshold operations i.e. at VDD smaller than 160 mV as
proven by [41], [42]. However, hand calculations via (3) and (4) are no longer valid at such
low VDD and design becomes heavily dependent on SPICE simulation. Consuming only the
leakage current at idle state, the maximum current drawn by a Schmitt-Trigger is during the
trip point VH_TRIP; of which such characteristic is desired for a shunt regulator operation. The
operation of a Schmitt-Trigger can be viewed as adaptive bias amplifier for the equivalent
analog circuit. Biasing current is allowed to peak during critical transition (which needs the
highest gain) and zero biasing current during idle state and start-up.
Schmitt-Trigger can be deemed as the perfect comparator in term of power
consumption in this context. Conventional “problem” i.e. more gain for positive cycle and
less gain for negative cycle is paradoxically again becomes favorable for shunt regulator
application. Negative cycle of input voltage implies insufficient power from energy
harvesting source; subsequently lowering gain of Schmitt-Trigger and cause more current to
be diverted to the load instead of being shunted to ground via PSHUNT. During positive cycle of
input voltage (more harvested power), Schmitt-Trigger has higher gain which helps shunting
extra current to ground. In the default implementation, RCOMP represents the equivalent
resistance of transistor drain-body junction leakage component. To further adjust the targeted
output voltage after fabrication, the value of resistor RCOMP can be adjusted by having an
additional bond pad to access the VSHUNT node and connect an additional off-chip resistor.
This off-chip resistor is only able to compensate for the process variation whenever RCOMP is
higher than the simulated value. Note that this circuit is susceptible to CMOS process
variation and can only offer coarse voltage regulation with 100 mV margin of error,
depending on process corners as shown in Figure 4.12.
26
4.3
Voltage Reference and Voltage Monitor
Regular 1.2 V BJT-based voltage mode BGR [43]-[45] cannot be used to generate
VREF in the proposed shunt regulation due to high supply voltage requirement. Many papers
about sub-1V BGR have been reported since IC technology ventured into sub-micron age;
most of them applied the resistive division or current mode idea [46]-[48]. The classical
topology of this category is known as current mode BGR, which consumes large chip area
due to large resistance value. For energy harvesting applications, it is important that power
and area overhead in the control circuit to be minimized as much as possible. Hence, a 2transistor voltage reference [38] which only consumes tens of pico watts as shown in Figure
4.3(a) is used. The generated reference voltage VREF, about 161 mV, is used to bias other
control circuit.
Figure 4.3
Figure 4.4
(a) 2-T picowatt voltage reference (b) 3-T voltage monitor
Simulated temperature variation of 2-T picowatt voltage reference
27
Figure 4.5
Simulated line regulation of 2-T picowatt voltage reference
Simulated temperature variation of the designed voltage reference is shown in Figure
4.4. Depending on process corners (Fast, slow and typical), the temperature variation ranges
from 46 ppm/ºC to 306 ppm/ºC. As shown in Figure 4.5, simulated line regulation
performance of the designed voltage reference spans between 8.2 mV/V to 9.6 mV/V. The
circuit starts up at 0.2 V.
Besides, a voltage monitor circuit, such as one shown in Figure 4.3(b) requires this
biasing circuit to work. During start-up of voltage monitor, transistor PB0 is off while
transistors PB1 and PB2 are diode-connected. Voltage at VBIAS node is relatively stable with
value equal to 2nVTlnY, where n is the sub-threshold slope factor, VT is the thermal voltage
(26 mV at room temperature) and Y is the ratio of W/L of transistor PB0 over PB1.
4.4
Voltage Supervisor in Piezoelectric Energy Harvesting System
Typical output power profile available from a piezoelectric harvester is shown in
Figure 4.6. Despite low current available, in open circuit mode, rectified output from PEH can
easily reach 10 V or higher. Such high voltage will cause break down in sub-micron CMOS
transistors easily. Therefore trade-off must be made between maximum efficiency at higher
input vibration amplitude or minimum harvestable energy. Energy harvesting system
(example system diagram is shown in Figure 5.16, Chapter 5.4) using a voltage supervisor
circuit [49] will decide the minimum harvestable energy by setting arbitrary VThreshold level.
The choice of VThreshold is made based on the fact that typical transistors available in modern
sub-micron CMOS processes will work at 1 V of supply voltage. By holding VRECT at a
28
constant value, the harvesting circuit will present an effective constant load “seen” by the
piezoelectric harvester, regardless of changes of actual load or activation of one-shot boost
converter. As only limited charge is drawn per activation of boost converter, piezoelectric
harvester cantilever will not suffer excessive mechanical damping, allowing usable voltage to
be output at lower vibration amplitudes. In other words load isolation is implemented.
Figure 4.7 shows transistor-level schematic of the voltage supervisor designed. The
threshold voltage that triggers PSW is set to 1 V, which is the nominal voltage of 0.13-µm
CMOS process. As only limited charge is drawn per activation cycle of voltage supervisor,
this circuit can avoid over-loading the PEH. This characteristic is instrumental for
piezoelectric cantilever types that are prone to mechanical damping whenever too much
charge is being extracted. The core of the voltage supervisor is a 6T Schmitt-Trigger cell
aforementioned. Due to negative VGS1 at start-up, this comparator draws minimal quiescent
current. Whenever VBIAS reaches Schmitt-Trigger tripping point VH_TRIP, propagating falling
edge signal of VTD will turn on transistor PSW, allowing VRECT to charge up CIN.
Figure 4.6
Piezoelectric harvester output power profile
29
Figure 4.7
4.5
Voltage supervisor circuit detects presence of discontinuous-mode energy source
and its measured operation waveforms
Simulations and Measurements
4.5.1 Simulated Schmitt-Trigger hysteresis operation
The designed Schmitt-Trigger is simulated in Cadence using BSIM SPICE models of
UMC 0.13-µm process, provided by the foundry. The simulated hysteresis response at
unloaded condition is shown in Figure 4.9, showing small hysteresis of 6 mV, VH_TRIP = 1 V
and VTARGET = 1.07 V.
4.5.2 Accelerated cold start-up time with multiple sources
To evaluate start-up time of a system shown in Figure 3.1, all three energy harvesting
sources are simulated using the power parameters (VOC, ISC) shown in Table 2.1 and circuit
model parameters obtained from datasheets [18], [21], [23]. With all three sources
simultaneously charging up storage capacitors, the system cold start-up time (0 V → 3 V) can
be reduced to 59.4 ms; compared to 150.4 ms using single source (PEH) only; shown in
Figure 4.10. There is a significant improvement of 91 ms.
30
4.5.3 Simulated start-up sequence of VREF, VBIAS, VSHUNT and VDD
Start-up sequence of VREF, VBIAS, VSHUNT and VDD were simulated, where both cases
i.e. without RCOMP and with RCOMP are considered. With an RCOMP of approximately 20 MΩ,
ripple voltage of VDD is reduced by 23 mV, as shown in Figure 4.11.
4.5.4 Measurement results from prototype chip
During measurement test, three prototype chips fabricated using UMC 0.13-µm
process are wire bonded on PCB. Each chip is identical and contains one copy of shunt
regulator (SR) and one NBOOST transistor (3.3V thick oxide type transistor). Die photo
showing the active die area taken by independent shunt regulator and NBOOST transistor is
shown in Figure 4.8. Total active area required in fabricating three shunt regulators is
approximately 0.08 mm2, excluding bond pads.
The fabricated shunt regulator was tested based on Figure 4.1 set up; where a voltage
source VS was swept from 0.8 V to 2 V, RS was set to 1 kΩ and RL was set to 1 MΩ. The
shunt regulator begins regulation once VS exceeds 1.1 V. As shown in Figure 4.12, before
performing any trimming via off-chip RCOMP, mean output voltage VDD of designed shunt
regulator measured over six samples is 1.118 V (σ = 8 mV) at regulated state, which shows
minimal die-to-die variation and within simulated process corners. System operations based
on Figure 4.7, where voltage supervisor detects whether discontinuous time source is active or
not, are shown in Figure 4.13, showing that the voltage supervisor is triggered on whenever
input voltage exceeds 1 V.
Figure 4.8
Die photos of shunt regulators
31
Figure 4.9
4.6
Schmitt-Trigger DC hysteresis and threshold trip point simulations
Summary
This chapter showed the possibility of building microwatt quiescent power voltage
regulator and voltage supervisor using a Schmitt-Trigger circuit, which is originally a digital
cell. Actual measurement results show that the die-to-die variation is small. The benefit of
being digital is that this circuit will be a flexible topology that can be scaled with the
decreasing trend of the CMOS nominal supply voltage.
32
Figure 4.10
Simulated system cold start-up time required by single source (PEH only)
and three sources (PVC+PEH+TEG) system
33
Figure 4.11
Start-up transient pre-layout simulation without RCOMP (top)
post-layout simulation with RCOMP (bottom)
34
Figure 4.12
Figure 4.13
Die-to-die measured regulated voltage versus simulation
Measured operation waveforms when voltage supervisor is (a) dormant,
(b) activated due to high DT-source
35
CHAPTER 5
PULSE TRANSFORMER BOOST CONVERTER
This chapter first introduces the major problem faced by circuit designers, which is the
low voltage start-up problem of interfacing power converter, under sub-threshold input
voltage. A refined transformer-based boost converter is then proposed, together with several
variants examined, i.e. unipolar and bipolar versions, conventional and dynamic threshold
transistors. Maximum power point tracking algorithm and circuit designed for the proposed
boost converter is illustrated. Lastly we wrapped up this chapter by presenting the
corresponding measurement results obtained from the prototype chips fabricated.
5.1
Low voltage energy source start-up problem
Two major problems for low voltage energy harvesting systems to be reckoned with
are self-start-up ability and energy transfer efficiency of the interfacing voltage converter.
Works reported earlier to solve these two problems include additional external battery [50],
mechanical switch [51] and specially modified fabrication process [52], which are all
expensive solutions. For fully electrical and battery-less solution, the common principle is to
use two inductors configured in mutual feedback. Such feedback can be realized either by
cross coupled transistor pair [53] or by built-in mutual inductance of a transformer, due to
common magnetic core sharing between inductors. Industry adopted the latter and launched a
transformer-based solution [54] but its conversion efficiency decreases as input voltage
increases. This problem is addressed by a dual-mode solution [55], a circuit which runs
transformer oscillation mode (TOM) similar to [54] at low input voltage, and normal boost
converter mode when input voltage exceeds the programmed threshold value.
However, low power efficiency and self-start-up problems revisited when
conventional transformer-based boost converters are powered by new generation TEG or
MFC, which have higher power density and higher internal resistance operating at sub-mW
output power. Due to the high internal resistance, there is higher voltage drop across R S
resulting in a smaller output current, which affect the circuit operations of [54] and [55].
36
5.2
Comparisons with Other Transformer Topologies (Start-up and Efficiency)
Transformer has two basic properties, i.e. voltage transformation and impedance
transformation, which are related to transformer turns-ratio depending on applications.
Voltage up conversion via high turns-ratio transformer is a straight forward solution to
achieve self-start-up at low input voltage. Seemingly free ride over this transformer property
turns out to have hidden trade-offs, i.e. low conversion efficiency. This factor is discussed
along with fail start-up scenario in the next section. Efficiency graph comparison between the
two transformer-based boost converters [54] and [55] is shown in Figure 5.1. Based on
transformer oscillation mode (TOM) only, the best efficiency obtainable is only 40%. Albeit
[55] improved conversion efficiency of TOM significantly upon activating normal boost
converter mode, there is still significant power loss even after entering higher input power
region. This effect cannot be eliminated due to the parasitic transformer effect inherited from
TOM, which will be further elaborated.
Figure 5.1
Efficiency graph comparison between two state-of-the-art transformerbased boost converters (LTC3108 and JSSC2012 [55])
37
5.2.1 Start-up and efficiency loss of transformer oscillation mode
Simplified schematic of the transformer-based boost converter proposed by [54] is
shown in Figure 5.2. VGEN is the open circuit voltage of TEG, RS is internal resistance of
TEG, L0 and L1 are the primary and secondary winding inductance of a transformer with
N0:N1 turns ratio. Self-start-up functionality is realized through the LC resonant oscillation
caused by the positive feedback loop L1-C1-Gm-L0, where Gm is the transconductance of
MTOM. Thanks to transformer’s high turns ratio (N=N0:N1; typical values are 1:50 to 1:100), a
boosted voltage magnitude equivalent to (N×ΔV) is generated at the secondary winding L1.
This induced voltage is then rectified by diode D1, and delivered to load RL.
The maximum output voltage VO is limited by a Zener diode-like shunt regulator DZ
to avoid overvoltage. This mechanism works fine with TEG of low internal resistance (RS less
than 5 Ω). However, with the new high power density TEG, which has high internal resistance
around 400 Ω [18], the output current and Gm become limited. There is significant drop across
the internal resistance RS, which lowers the effective source voltage VS and reduces ΔV
across L0. Power transfer (ΔV×IL0) over transformer coupling is reduced and secondary
winding voltage (N×ΔV) is also reduced. Under this scenario, the transformer oscillation fails
to generate sufficiently high VX to turn on the rectifier, disabling self-start-up operation.
Figure 5.2
Simplified schematic of transformer oscillation mode boost converter
38
Assuming MTOM to be a perfect switch, end-to-end power transfer efficiency of the
transformer oscillation circuit is given by:

VO I O
VS I L 0
(5.1)
As the conservation of power holds, while transformer increases input voltage ΔV, it
needs to reduce secondary winding current IL1 by the same ratio N i.e. IL1=IL0/N concurrently.
IO is assumed to be IL1, therefore,

 VO
(5.2)
N VS
Since the output voltage VO is always regulated to a fixed value by DZ; as VS
increases, η will decrease inversely proportional to VS even under the assumption that all
components are lossless. Power not consumed by RL load is typically absorbed by shunt
regulator attached to the VO node.
Figure 5.3
Simplified equivalent circuit of dual-mode transformer-based solution at
boost converter mode
5.2.2 Efficiency loss after boost converter mode change
The simplified equivalent circuit of dual-mode transformer-based solution at boost
converter mode by [55] is shown in Figure 5.3. There are two power transistors, i.e. MTOM and
MBCM which are turned on exclusively during respective mode of operation. The circuit is
configured to enter normal boost converter mode with MTOM turned off; and MBCM driven by
39
another PWM voltage mode control scheme discussed in [55], whenever input power is
greater than 500 µW. Efficiency achieved in boost converter mode is greater than TOM,
reaching 57% at best as shown in Figure 5.1. However, other boost converter which is
implemented using similar basic topology and fabrication process [50] had reported efficiency
up to 75%, implying that at least 15% efficiency is lost due to the circuit architecture of [55].
It is believed that there are two factors contributing to this efficiency degradation. First factor
is the leakage current of MTOM during boost converter mode. Although the gate of MTOM is
connected to circuit ground during the boost converter mode, off-state leakage current is
significant considering the large power MOS size and the fact that MTOM is a native transistor
(zero threshold voltage). Leakage power becomes more severe when input voltage increases.
Second factor is the transformer inter-winding capacitance CIW, often ignored in basic
transformer model. By Miller theorem property, CIW can be decomposed into CP and CS as
shown in Figure 5.3. If CIW = 20 pF and N = 100, CS will be 20 pF and CP will be 2 nF,
approximately 100 times of CINTW. By applying transformer impedance transformation
property, parasitic capacitances such as CS that appear at secondary side can be mirrored back
to transformer primary side. The effective capacitance CP’ seen from primary side will be
approximately 200 nF, which is N2 times of CS. This can cause switching delay in MBCM,
slowing down transition of VX and increases switching loss in MBCM. Another power
efficiency loss factor worth considering is the unusually high DC coil resistance demonstrated
by the miniaturized high turns-ratio transformer. For example, a 1:100 turns ratio transformer
[78], which is a standard component recommended by datasheet of [54] has L1 coil resistance
up to 316 Ω, compared to 1:1 turn ratio transformers which generally have coil resistances of
less than 3 Ω as shown in Table 5.2.
Therefore to solve both self-start-up problems and low efficiency problems, high
turns-ratio transformer must be avoided. Despite boost converter based on high turns-ratio
transformer offers direct voltage multiplication effect at low input voltage, the disadvantages
i.e. high leakage current of idle TOM power transistor and multiplied effect of parasitic
capacitance need to be taken into consideration.
40
5.3
Unipolar and Bipolar Continuous Time Operations
The Meat Grinder [35] is an inductive energy transfer circuit which is used to supply
high-current pulsed power applications such as electromagnetic propulsion, using coupled
inductors of 1:1 turn ratio. The improved boost converter in this thesis is motivated and
derived from a single stage Meat Grinder. The proposed boost converter circuit [57] without
any output regulation or maximum power point tracking is shown in Figure 5.4. High turnsratio transformer is no longer required and instead N is reduced to 1, which is the lowest value
possible. By setting N to 1, transformer parasitic capacitance is kept at minimal value,
avoiding the multiplication effect of the transformer impedance transformation property.
Unity turn-ratio transformers are commonly used by the telecommunication industry; known
as pulse transformers [58]. They are typically used to transmit or receive high speed digital
pulses in wired Local Area Network (LAN) application. This boost converter utilizes the
mutual coupling feedback property of transformer, to autonomously generate square pulses
during start-up. However, high inductance (>500 µH) is required for the proposed boost
converter to accomplish low voltage start-up.
Figure 5.4
Proposed boost converter using 1:1 turn ratio pulse transformer
41
Figure 5.5
Conceptual blocks of proposed boost converter
The objective of a Meat Grinder circuit is to multiply the output current deliverable to
end load. System loop current is ramped up to reach the fundamental maximum, of which at
this instant switch connected to first inductor is opened; power is then delivered to end load
via the second inductor only. Energy stored in first inductor before cut-off is pushed to second
inductor via the linking mutual inductance. The proposed boost converter has a different
objective than Meat Grinder i.e. to multiply output voltage instead of output current to end
load. The similarity is that when system current (inductor current L1) reaches maximum, at
this instant switch M1 is opened, causing power to be delivered to end load via single inductor
(L1) only. Mutual inductance causes M1 to turn on and off based on MOS saturation
(maximum) current. The conceptual blocks of the proposed boost converter are redrawn in
Figure 5.5.
In conventional single inductor switching converter, a separate clock generation
circuit is necessary to drive the power stage. This boost converter is interesting because the
clock generation is inherently embedded as part of the circuit property, an integral part of the
power stage. Switching frequency is determined by the chosen inductor value and currentvoltage profile of the power transistor.
42
In Figure 5.5, M1 is replaced with its simplified equivalent model; gate capacitance CG
and on-resistance RON. The boost converter can be functionally divided into three branches
i.e. branch-pulse (L0-CC||RC-CG), branch-power (L1-RON) and branch-load (D1-CL). Branchpulse is essentially an over-damped RLC circuit, which generates free-running digital square
pulses across CG to control M1 current; branch-power is a LR circuit which acts as system
energy extraction and delivery path; branch-load is a single-diode rectifier which is turned on
only when VX is boosted to a value higher than VO.
All capacitors have zero charge at initial condition. Since CC >> CG, equivalent
capacitance of CC-CG in series is approximately CG. During start-up, magnitude of IL0 rises
and charges up CG rapidly, with maximum IL0 limited by RC. Once VG is fully charged up to
VS, IL0 stops increasing and remains constant. Since there is no more magnetic flux change in
branch-pulse, branch-power operation is independent of branch-pulse despite the mutual
inductance linking two branches. At this instant, M1 is turned on and drain current increases
according to (VS-VX)/L1 rate. The maximum drain current reachable is equal to the saturation
current equation given by:
I DSat  nCOX
W
(VG V TH) 2
2L
(5.3)
where µn = electron mobility, COX = oxide capacitance, W/L = transistor width over length,
VTH = MOS threshold voltage. Initial current component of IL1 comprises of M1 sub-threshold
leakage current and active current (drain current). Active current eventually dominates once
VG is fully charged up by IL0.
When IL1 reaches IDSat which is determined by the applied gate voltage, it is
impossible for IL1 to increase any further, thus changing the circuit status-quo. VX in high
magnitude will be induced, branch-load (rectifier) will be turned on and IL1 now flows into CL
in decreasing trend. Due to the mutual coupling between L1 and L0, induced VX will be
mirrored to branch-pulse, as induced voltage appears across L0 in inversed polarity; VG is now
(–VX+VS). Negative VG turns off M1 instantaneously. Owing to the negative gate bias, offstate leakage current of M1 is reduced significantly.
43
Energy stored on inductor L1 (0.5IDSat2L1) is delivered to CL and this builds up the
output voltage VO. Energy delivery continues until IL1 becomes zero ampere. At this instant,
the circuit status-quo is reverted back to the same initial condition, except that CG is now
charged to VS. At this point the circuit now completes one oscillation cycle. The oscillation
cycles repeat indefinitely trying to increase VO. The boost converter enters a steady-state
whenever the VO reaches an equilibrium state i.e. energy delivered = energy dissipated by
load. At steady-state, VG during ON cycle will be 2 times VS, and equals to (–VX+VS) during
OFF cycle. Detailed circuit dynamics of the boost converter is shown in Figure 5.6. From
Figure 5.6 we can observe that this circuit functions as an autonomous zero current switching
(ZCS) boost converter, without the need of additional sensing amplifier and comparator [51]
in conventional ZCS boost converter.
Using the relationship known from the conventional boost converter formula,
assuming VD = 0 V and complete transfer of inductor energy to load, by assuming complete
and ideal energy transfer from a fully charged inductor (0.5IPEAK2 L1) to the load in every
switching cycle, that the autonomous pulse switching frequency of this boost converter is:
f SW 
2VO2
2
I DSAT
L1 RL
(5.4)
where IPEAK = IDSat = f(VG), VG = 2VS. Using this timing information, switching loss on NBOOST
gate capacitance can be determined. Hence to minimize switching loss at a fixed output
voltage, one way is to use the highest inductance possible, subject to transformer physical size
and cost constraint. For designer to increase the IDSAT and reduce the fSW, first, pick transistor
type with higher saturation current at the same gate voltage (lower threshold voltage) and
second, increase the W/L sizing of the transistor.
Designer can also choose to increase the output voltage but this would make transistor
easier to breakdown as the maximum drain-gate transistor junction voltage is 2VO in this
topology, due to the transformer mirroring effect. To increase the output voltage with long
term reliability in mind, the necessary trade-off of this design is to use thick oxide transistor
which has higher breakdown voltage, but occupies larger chip area and parasitic capacitances.
Consequently both minimum self-start-up voltage and power loss are increased.
44
Figure 5.6
Proposed boost converter operation waveforms
Another dominant loss, i.e. transformer loss is primarily due to the secondary inductor
coil resistance RL1, which can be calculated using the inductor current, IL1:
PRL1  I L21,RMS  RL1 
1 VS
TON RL1
3 L1
(5.5)
During off-state cycle, the negative voltage is then reflected on NBOOST gate, which
will turn off NBOOST and effectively suppresses NBOOST off-state leakage current. Negative
voltage generated across L0 is also stored on CNEG, with VNEG tracking VPOS closely. If the full
negative voltage (–VX+VIN) is applied on transistor gate during TNEG period, large gateinduced-drain-leakage (GIDL) current would flow and reduce boost converter efficiency. It is
necessary to optimize the reverse bias applied during the negative cycle to achieve the
minimum leakage current, which is approximately –0.3 V for 0.13-µm CMOS process [59].
45
Off-state current due to sub-threshold leakage and GIDL effects with respect to reverse bias
voltage applied to the transistor for CMOS 0.13-µm technology is shown in Figure 5.7. Hence
a reverse bias diode is added to the transistor gate to set the peak negative gate voltage. This
diode also serves as antenna diode to cope with the antenna effect during chip fabrication,
which will cause transistor gate breakdown, and reduce process yield if not properly handled.
Figure 5.7
Off-state current due to sub-threshold leakage and GIDL effect
46
5.3.1 Output regulation and gate bias changer
The output voltage of the boost converter is given by:
VO 
VS I PEAK RL
2
(5.6)
Therefore the output voltage without regulation is essentially dependent on input
voltage VS and load resistance RL only since IPEAK is a function of VS as explained. For
energy harvesting systems, both input voltage and load resistance are unpredictable depending
on environmental circumstances and applications. Hence in order to provide a regulated
output voltage, a shunt regulator similar to the Zener diode (DZ) concept is proposed as shown
in Figure 5.8.
Figure 5.8
Impedance adjustment principles in boost converter
47
Due to the random nature of energy harvesting sources, input voltage could vary
significantly and transistor overvoltage protection is necessary. By using a shunt regulator,
output voltage VO can be clamped to the reverse breakdown voltage of DZ and thus protecting
M1 from breakdown. Due to the unavailability of on-chip Zener diode in standard CMOS
process, a custom designed shunt regulator (circuit detail is illustrated in Chapter 4) that has
similar I-V behavior to a Zener diode [60] is designed as replacement. In the prototype chip,
the voltage reference for the voltage supervisor (fundamentally a comparator) in the shunt
regulator is designed based on the 2-transistor topology [38] which consumes only picowatt
range of power. Turn-on voltage of DZ is set to 1 V, to allow safe margin for M1 before the
oxide breakdown occurs. Input voltage (VS) range from 21 mV to 1 V can be achieved. Extra
power harvested per cycle not dissipated by load resistor RL will be diverted to ground by
ISHUNT of DZ, keeping VO regulated at 1 V.
The fundamental nature of energy harvesting voltage converter is the need to deal with
imperfections found in power sources such as the internal resistance found in TEG or MFC.
Due to this non ideality, voltage converter needs to adapt its input impedance to match the
value of internal resistance. Maximum power obtainable from a voltage source V GEN with
series internal resistance RS, is given by:
PMAX 
2
VGEN
4 RS
(5.7)
RS is a fixed value known in advanced by designer, which can be extracted from the
slope of energy harvester’s I-V characteristics shown in Chapter 2. From Figure 5.8, system’s
maximum power point is reached, whenever VS is exactly half of VGEN and RIN matches the
same value of RS. RIN of the proposed boost converter can be calculated from the inductor
current IL1, given by:
RIN 
VS
I L1_ Average

2VS
I PEAK
From the inductor volt-second balance relationship, it can be rearranged to:
48
(5.8)
RIN 
2 L1
TON
(5.9)
Since L1 is a designer-control parameter, the input impedance of boost converter in
operation can be determined by measuring the pulse width TON of the VX pulse generated by
the boost converter itself, which can be computed conveniently by microcontroller (MCU)
program. For basic boost converter without additional control as shown in Figure 5.5, the
pulse width is always controlled by the IDSat of M1 at VG = 2VS, according to the MOS IV
(saturation) curve. To control RIN, the only design parameter is by controlling VG, which leads
to the concept of gate bias changer circuit as shown in Figure 5.9.
Figure 5.9 Gate bias changer concept to alter boost converter input impedance
49
Basic gate bias changer concept consists of DG-RG-MMPP i.e. a low turn-on voltage
diode DG (can be implemented with an on-chip PMOS diode), diode current limiter RG, and
MMPP which is a MOS switch to enable or disable gate bias changer controlled by VMPP
signal. When VMPP = 1, DG-RG-MMPP is connected in parallel to M1 gate, which changes VG to
become turn-on voltage (VDG) of DG, which is designed to be lower than 2VS. Lower VG
decreases IDsat and thus reducing TON of boost converter and increasing RIN. During start-up,
gate bias changer should be turned off as gate bias changer itself will consume extra power
(several µW at least). If it is turned on during cold-starting, minimum input power required to
start the system will increase. Gate bias changer will not work without the diode DG as DG’s
forward diode voltage provides the necessary voltage biasing to reduce IDSat of power MOS.
Uni-directional current flow of DG also ensures the necessary voltage polarity at VG. Without
DG, in negative cycle, high reverse current will flow across drain-body junctions of MMPP,
which causes potential latch-up risk.
5.3.2 Bipolar output version of pulse transformer boost converter
By adding an additional diode DNEG and storage capacitor CS4 at the primary inductor
path, negative voltage generated due to the symmetry of 1:1 transformer can be stored in
additional stacked capacitor, as shown in Figure 5.10. However, only one shunt regulator is
needed. Operation waveforms of this modified bipolar output boost converter are shown in
Figure 5.11. The negative voltage generated that would tracks VPOS (3 V in this
implementation) automatically. Hence the total voltage headroom available for WSN can be
doubled to 6 V with ±3 V bipolar output. Nevertheless the power deliverable is different
between the positive and negative rail. For real-time power delivery, majority of power will
be delivered via inductor L1.
5.3.3 Potential applications of bipolar supply
Considering the unstable nature of WSN power, one useful strategy is that the sensor
node can save the critical last known system state such as required radio power and network
information into its non-volatile memory (NVM). Once power is resumed, the information
stored could read the NVM and restore the sensor node back into the optimal state in
immediately, eliminating radio recalibration time and power. Bipolar supply is necessary for
read/write circuits of NVM cell. Bipolar supply provides an intuitive way to interface sensors
50
which generate bipolar voltage in nature mode, without unnecessary voltage conversion that
incurs power loss. Bipolar supply is also useful for switched mode Class-D RF amplifier [61],
[62] or complementary Class-E RF amplifier [63], typically used in a power efficient radio
communication scheme for On-Off-Keying (OOK) modulation [7].
Figure 5.10
Integration of bipolar output pulse transformer boost converter into the
proposed stack capacitors scheme [64]
51
Figure 5.11
Bipolar output pulse transformer boost converter operation waveforms
5.3.4 DTMOS version of pulse transformer boost converter
According to [65], Dynamic Threshold MOSFET (DTMOS) basically refers to
MOSFET in which the source-substrate junction which is kept reverse biased in conventional
usage being forward biased. Initial design of DTMOS is achieved using 0.25-um technology,
operated at 77 K [66] and used 0.6 V voltage supply with the body substrate tied to fixed
forward biasing potential. In later years, two types of DTMOS which is called gate controlled
lateral bipolar transistor (GC-LPNP) [67] and Silicon-on-insulator (SOI) MOSFET [68], [69]
with substrate tied to the gate terminal were demonstrated. H. Kotaki uses modified Advanced
Isolation (SITOS) and Gate-to-Shallow Well contact (SSS-C) to achieve bulk DTMOS [70].
SOI DTMOS was demonstrated to be good candidate for ultra-low power CMOS applications
and GC-LPNP was used for some compact low power analogue application.
52
CMOS technological advancements have led to successful fabrication DTMOS in bulk
process. [71] and [72] form their bulk DTMOS by tying gate and well together but their
design have limiting VDD to 0.6-0.8 V. Such design has the advantage of no severe chip area
penalty as extra biasing and control circuit is not necessary. By using modified bulk CMOS
process [70], parasitic well capacitance is minimized and higher operating frequency [73] is
achieved. In [74], DTMOS structure is first implemented using industry standard deep submicron CMOS process with deep N-well isolation structure. The realization of [74]’s
DTMOS is shown in Figure 5.12. As shown in Figure 5.13 and Figure 5.14, the current drive
capability of DTMOS is clearly superior over conventional MOS. Transconductance gm over
drain current ratio of DTMOS at low µA-current range is 30% higher than conventional
MOS.
Figure 5.12
Cross-section of Bulk DTMOS realized with deep N-well isolation and the
required CMOS process flow [74]
In conventional CMOS, technology scaling to smaller feature size and lower V TH will
increase the operating speed. However, when foundry process engineers lower the V TH, subthreshold behavior of MOSFET is degraded. This is because stand-by current increases in
static circuit and thus VTH is limited to 0.4 V for many processes. DTMOS was one of the
approaches proposed to overcome such constraints, especially operation at very low VDD.
53
Figure 5.13
gm-to-Ids ratio of DTMOS and conventional MOS
Figure 5.14
Ids versus Vds of DTMOS and conventional MOS
54
Figure 5.15 Bipolar pulse transformer boost converter, cross-section view of DTMOS
configuration, and self-start-up free-running boost converter operation waveforms
In DTMOS configuration, gate input voltage forward biases the substrate, hence
threshold voltage VTH will decrease due to the famous body effect equation [71]:
VTH  VTH 0  
 2  V  2  
F
BS
F
(5.10)
where VTH0 is threshold voltage when substrate voltage, VBS = 0V. Parameter γ (gamma) is
called the body-effect-co-efficient. ΦF is the Fermi Potential.
DTMOS behave in such way: lowered VTH in ON state to achieve extra speed gain but
in OFF state, the steep sub-threshold slop of those non-scaled conventional MOSFET is
maintained to minimize reverse leakage current. This is achieved by varying VBS component
in the body effect equation in ON and OFF state. Motivated by this property, this thesis
explores the usage of DTMOS transistor in the pulse transformer boost converter circuit, as
55
shown in Figure 5.15. The operation is similar to the previous bipolar case, except that the
NBOOST gate is clamped to one diode drop, on both positive and negative directions.
Due to the transistor body effect in DTMOS, during TPOS period, forward biasing
NBOOST body improves transistor’s transconductance (gm) and current drive at low voltage.
Under extraordinarily high input power, forward bias power of D WELL that increases sharply
also limit the maximum input voltage to below 0.3 V. During TNEG period, negative NBOOST
body voltage increases transistor’s threshold voltage, further suppressing off-state transistor
current which is already at negative gate voltage.
5.4
Discontinuous Time Operations
In piezoelectric energy harvesting system, the power is available in discontinuous time
fashion, as discussed in Chapter 2. If a pulse transformer boost converter is attached after the
voltage supervisor stage, as shown in Figure 5.16, the switching operation of boost converter
will also become discontinuous. Simulated waveform of such discontinuous operation is
shown in Figure 5.17.
Figure 5.16
Piezoelectric Energy Harvesting system architecture
56
Figure 5.17
5.5
Discontinuous time operation of pulse transformer boost converter
Continuous Time Maximum Power Point Tracking (MPPT) Techniques
Conventional maximum power point tracking (MPPT) algorithm for transformer boost
converter [55] requires sampling of TEG open circuit voltage (VGEN), and modifying PWM
duty cycle to change the input voltage to 0.5 VGEN. This approach needs to periodically switch
off boost converter so that open circuit voltage can be sampled and updated according to
environmental change. Since RS is a known constant value with all values of VGEN, we can
achieve MPP by setting the input impedance to match RS, without the need to sample VGEN.
The input impedance of this boost converter can be derived from timing of the self-generating
pulse.
The proposed MPPT algorithm is shown as flow chart in Figure 5.18(a). MPP tracking
process can be performed continuously without momentary loss of power due to open circuit
voltage sampling. A MCU can continuously calculate the TON pulse width by sampling VX via
one of the I/O port pins. MCU then compares the calculated RIN based on (5.9) to the known
RS of energy harvesters. Depending whether calculated RIN is smaller than or greater than
required RS, MCU will decrease or increase RG. The accuracy of measured pulse will depend
57
on the quality of measuring clock in terms of frequency (the higher the more accurate) and
timing drift. In real application, temperature changes slowly over time. Hence MPPT
algorithm can be executed at very low duty cycle i.e. once every few seconds or so to reduce
computation power overhead.
Besides, the temperature variation of RS of thin-film TEG [18] is less than 1% of its
nominal value, even when ∆T is up to 60 ⁰C. However, since ∆T in typical energy harvesting
application is small, such variance is acceptable and RS can be regarded constant. To ensure
absolute variability is less than 5%, simulations based on the assumption R S varies by 20%
(an excessive approximation), the tracked MPP voltage is only off by 5%. For very high
performance system, designers need to incorporate additional temperature sensor and look-up
table containing the temperature variation information RS to compensate for all process,
voltage and temperature (PVT) variation accurately.
There are two possible ways of implementing the proposed MPPT algorithm via
adaptive change of RG. First, as shown in Figure 5.18(b), is to replace RG with a digital
potentiometer; which is suitable for discrete component solution. Second implementation as
shown in Figure 5.18(c) is more suitable for fully on-chip solution, where MMPP is replaced
with an array of NMOS transistors, with their on-resistance designed in binary-weighted
fashion. This solution saves more chip area than previous solution as additional multiplexers
are needed inside a digital potentiometer besides similar chip area for resistance.
For example, assuming the total resistance needed is 40 kΩ. With CMOS standard
0.13-µm technology, if on-chip high resistance poly resistors are used, total chip area for
resistors alone is around 10 µm2; if custom sized transistor is used to implement the resistors,
less than 2 µm2 is necessary. Besides using MCU, dedicated digital logic using custom design
approach to implement the MPPT algorithm is possible with estimated chip area for such
block less than 400 µm x 400 µm in UMC 0.13-µm process. Since typical TON pulse is of the
100’s µs to ms range, digital clock can be run at MHz (100s of ns) clock range. The power
consumption of such on-chip MPPT circuit is estimated to be within the ballpark of 100 µW
when active. If MPPT algorithm is allowed to be run at low duty cycle (once for every few
second, since temperature change is typically slow), average power can be reduced to µW
range. Lastly, simulation waveforms showing the effect with and without MPPT via gate bias
changer is shown in Figure 5.19.
58
Figure 5.18
Maximum power point tracking algorithm and possible implementations
using timing of VX
59
Figure 5.19
Simulation waveforms showing maximum power point operations
60
Figure 5.19(a) shows the simulated MPPT operations on and off under low input
voltage condition i.e. 100 mV. Such low input voltage is obtained using low RS (30 Ω) TEG
with maximum available input power of 83 µW. Figure 5.19(b) shows the simulated MPPT
operations on and off under high input voltage (1.2 V) generated by a high R S (400 Ω) TEG
with maximum available input power of 900 µW. Without the gate bias changer, M 1 has
higher IDSat and draws more current from the source, hence lowering effective input voltage.
To extract more power from source, gate bias changer is turned on to reduce IDSat. As a result,
less current is drawn per switching cycle and MPP input voltage equals to 0.5 V GEN is
accomplished.
5.6
Measurement Results of Different Pulse Transformer Boost Converters
5.6.1 Measurement results of unipolar version
The prototype chip (1.5 mm × 1.5 mm) fabricated using UMC 0.13-µm technology is
shown in Figure 5.20. Power MOS using four different transistor types available in the
fabrication process were taped out and tested respectively, i.e. 1.2V native (LVZT), 1.2V
standard low threshold (LVLT), 3.3V native (HVZT), and 3.3V standard low threshold
(HVLT). Transistor characteristics for each type are shown in Table 5.1.
Figure 5.20
Proposed Boost Converter Die Photo
61
TABLE 5.1
TRANSISTOR TYPES USED IN EXPERIMENTS
Standard VDD = 1.2 V
(Thin gate)
LVZT
LVLT
Standard VDD = 3.3 V
(Thick gate)
HVZT
HVLT
W/L
(µm / µm)
384/1.2
512/0.12
100/1.8
4000/0.34
Threshold Voltage
(VTH)
0 mV
250 mV
80 mV
300 mV
Measured IOFF
(VD = 0.1 V, VG = 0 V)
30 µA
95 µA
28 µA
4 µA
Measured ION
(VD = VG = 0.1 V)
73 µA
476 µA
48 µA
31 µA
ION / IOFF ratio
2.43
5.01
1.71
7.75
Transistor types
The die area of the controller combined with LVZT, LVLT, HVZT and HVLT are
0.048 mm2, 0.043 mm2, 0.038 mm2 and 0.096 mm2, respectively. LVZT, LVLT, HVLT and
their controllers are connected via on-chip routing but HVZT and its controller are connected
via off-chip routing. Excluding the computing module i.e. MCU which is off-chip, the die
area of the standalone controller containing the rest of the MPPT control is 0.035 mm 2.
During measurement, four miniature pulse transformers with different characteristics are
used, with the detail specifications shown in Table 5.2.
Transformers A, B and D have identical physical size but different electrical
parameters. Transformer B and C has similar inductance but different inter-winding
capacitance (CIW). An off-chip generic Schottky diode with 50 mV turn-on voltage @ ID =
500 nA is used as D1 during measurement. The diode junction capacitance at 0 V bias is 28
pF, with the measured I-V characteristics at 25 ºC shown in Figure 5.21.
RS is set to 400 Ω to emulate real TEG source from [18]. Ceramic-type SMD
capacitors with 1 µF (rated voltage 25 V) are selected to implement the storage capacitors
(CS1 to CS4). Minimum self-start-up voltage and minimum input power required to start-up the
proposed topology for different transformer-transistor combination are summarized in Table
5.3. The minimum start-up voltage measured is 21 mV (at 5.8 µW input power) and minimum
start-up power of 1.3 µW (at 35 mV input voltage). It is found that transistor with the lowest
62
ION/IOFF ratio also has the highest start-up voltage. The start-up voltage becomes lower if
higher inductance is used.
Self-start-up ability persists under voltage source with high
internal resistance up to 400 Ω, which is accomplished via autonomous square pulse
oscillation instead of conventional sinusoidal LC resonant tank oscillation. Instead of
adopting dual-mode approach, this boost converter can work at normal boost converter mode
for the entire input voltage range.
TABLE 5.2
TRANSFORMERS PARAMETERS USED IN EXPERIMENTS
Transformer
A
B
C
D
Part number
Murata
78601/9C
Murata
78601/16C
Coilcraft
DA2099-AL [76]
Murata
78601/2C
Turn ratio
1:1
1:1
1:1
1:1
Inductance L1
10 mH
4 mH
4 mH
0.5 mH
Leakage
inductance
0.86 µH
0.47 µH
13 µH
0.25 µH
Coil DC
resistance
1.30 Ω
0.84 Ω
2.85 Ω
0.34 Ω
Inter-winding
capacitance
121 pF
78 pF
13 pF
22 pF
PCB footprint
9.5 mm ×
9 mm
9.5 mm ×
9 mm
13 mm ×
11.5 mm
9.5 mm ×
9 mm
63
Figure 5.21
Schottky diode I-V characteristics at 25 ºC
TABLE 5.3
INPUT POWER, SWITCHING FREQUENCY AT MINIMUM STARTUP VOLTAGE AND
PEAK POWER EFFICIENCY FOR ALL TRANSFORMER-TRANSISTOR COMBINATIONS
A (L1 = 10 mH,
CIW = 121 pF)
B (L1 = 4 mH,
CIW = 78 pF)
C (L1 = 4 mH,
CIW = 13 pF)
D (L1 = 0.5 mH,
CIW = 22 pF)
LVZT
35 mV
1.3 µW
15 kHz
74.5%
40 mV
2.0 µW
41 kHz
67.8%
52 mV
2.3 µW
50 kHz
68.2%
45 mV
3.9 µW
350 kHz
64.3%
LVLT
21 mV
5.8 µW
2 kHz
70.5%
28 mV
8.5 µW
15 kHz
68.9%
29 mV
7.3 µW
17 kHz
63.6%
36 mV
8.5 µW
100 kHz
66.7%
64
HVZT
125 mV
10.9 µW
22 kHz
60.1%
164 mV
18.9 µW
60 kHz
52.5%
141 mV
13.7 µW
94 kHz
51.3%
171 mV
15.1 µW
350 kHz
50.0%
HVLT
40 mV
11.0 µW
4 kHz
72.6%
58 mV
1.7 µW
55 kHz
68.4%
44 mV
1.8 µW
170 kHz
62.8%
85 mV
4.8 µW
520 kHz
63.8%
Measured operation waveforms of proposed boost converter at the lowest input
voltage (VS = 21 mV) using LVLT and inductor A (L1 = 10mH, CIW = 121pF) are shown in
Figure 5.22. Peak inductor current is around 550 µA. As shown in measurement transistor
gate voltage VG is negative during power delivery to RL, which assists to suppress transistor
off-state leakage current. Measured operation waveforms at non-MPP state (MPPT off) and
MPP state (MPPT on) are shown in Figure 5.23 respectively. For this measurement VGEN is
set to 1.2 V and the input voltage VS at MPP is 0.6 V, transistor LVLT and inductor A were
used. It is shown that VG is modified in MPP state which subsequently changes peak inductor
current IL1 from 5.2 mA to 3.0 mA. Input power therefore also increases from 390 µW at nonMPP state to 900 µW at MPP state.
Figure 5.22 Measured VS, VG, VX node voltage and inductor IL1 current waveforms
using LVLT transistor (with the lowest input voltage)
65
Figure 5.23
Measured VS, VG, VX node voltage and inductor current IL1 operation
waveforms at non-MPP and MPP state for VGEN = 1.2V
66
The choice of transformer coil inductance primarily determines the switching
frequency of this boost converter, instead of choice of power transistor which is shown in
Figure 5.24. With high inductance (10 mH), free running switching frequencies (without
MPPT) are around order of kHz regardless of transistor types but with low inductance (0.5
mH), the switching frequencies are increased to order of 100 kHz. To illustrate the effect of
inter-winding capacitance, two different transformers with same inductance but different
inter-winding capacitance CIW are tested. As shown in Figure 5.25, larger CIW reduces
switching frequency as higher CIW introduces extra switching delay time.
Higher inductance also improves the power efficiency as shown in Figure 5.26 due to
reduced switching frequency (losses). For transformers with similar inductance, Figure 5.27
shows that higher CIW increases power efficiency at higher input power (>1 mW) but at low
input power (<1 mW) lower CIW gives better efficiency.
Figure 5.24
Measured free running switching frequency (without MPPT) using L1 =
10mH transformer A and L1 = 0.5 mH transformer D
67
Figure 5.25
Measured free running switching frequency (without MPPT) using
L1 = 4 mH transformers (B, C)
Figure 5.26
Measured power efficiency versus different transistors using L1 =
10 mH and L1 = 0.5 mH transformers
68
Figure 5.27 Measured power efficiency versus different transistors using L = 4mH
transformers with 13 pF CIW and 78 pF CIW
Two combinations i.e. 10 mH-LVZT (best efficiency) and 0.5 mH-LVZT (lowest
efficiency) are selected and compared with the existing transformer-based boost converter, in
Figure 5.28. Designers can trade-off overall system size with efficiency by using transformer
with smaller inductance. At low input power region (less than 500 µW), TOM boost converter
has better power efficiency than the proposed design. However, as input power is increased to
above 500 µW, in term of efficiency, the proposed design is 5% better for the worst
combination (0.5 mH-LVZT) and 30% better for the best combination (10 mH-LVZT).
Finally, power efficiency of different transistors using transformer A (L = 10 mH) versus the
input voltage is shown in Figure 5.29. A table showing the performance comparisons of
related single output, unipolar boost converters (including non-transformer-based) designed
for low power energy harvesting applications is summarized in Table 5.4.
69
Figure 5.28 Measured power efficiency comparisons between 10 mH-LVZT (best)
and 0.5 mH-LVZT (worst) combinations with existing transformer boost
converter LTC3108 and JSSC2012 [55]
Figure 5.29
Measured power efficiency of different transistors using L = 10mH
transformer versus input voltage VS with RS = 400 Ω
70
TABLE 5.4
PERFORMANCE COMPARISONS WITH RELATED WORKS
References
JSSC 2010
[50]
JSSC 2013
[53]
LTC3108
[54]
JSSC 2012
[55]
Unipolar
version
CMOS Process
0.13 µm
N/A
0.13 µm
0.13 µm
Start-up mechanism
External
battery
65 nm
Cross
coupled
inductors
Minimum self-startup
voltage
650 mV
50 mV
20 mV
40 mV
21 mV
(LVLT)
Maximum input
voltage
100 mV
200 mV
500 mV
300 mV
1V
Regulated output
voltage
1V
1.2 V
2.35-5 V
2V
1V
Peak efficiency
(end-to-end)
75%
73%
40%
61%
74%
(LVZT)
Maximum output
power
175 µW
1.2 mW
600 µW
2.7 mW
2 mW
Maximum power
point tracking?
No
Yes
No
Yes
Yes
1:100
1:60
Transformer Transformer
1:1
Transformer
5.6.2 Measurement results of unipolar-DTMOS version
Measurements confirmed that using the DTMOS version of boost converter, power
conversion efficiency is improved compared to similar sized conventional transistor (without
deep N-well isolation). Measured power efficiency of different transistors using L = 10 mH
transformer versus input voltage is shown in Figure 5.30. Improvement is the highest at input
voltage of 200 mV; which is up to two times (18% to 36%)
5.6.3 Measurement results of bipolar version
Multiple bipolar output configurations based on Figure 5.10, i.e. ±1 V, ±2 V and ±3 V
are tested. One shunt regulator chip and 2-capacitor stack are needed to generate ±1 V output;
two shunt regulator chips and 3-capacitor stack are needed to generate ±2 V output; whereas
±3 V configuration requires three shunt regulator chips and 4-capacitor stack. Figure 5.31
shows the measured VX and VY pulse to transfer charge to top capacitor and bottom capacitor,
which works in inverted symmetry style. VG of NBOOST transistor goes into negative bias
71
during charge transfer period (after transistor current reaches peak current IDSAT). This
property assists in suppression of NBOOST leakage current during off-state, subsequently
forcing all inductor current IL1 to flow into storage capacitors CS1-CS3 only, instead of leaking
into circuit ground. HVLT type transistor is used for this version due to the higher (3.3V)
voltage rating.
Figure 5.32 shows the difference of driving strength between inductor L0 and L1 i.e.
there is higher inductor current in IL1 than IL0. Inductor L0 is loaded with the presence of
additional impedance (RC-CC-NBOOST gate) besides DNEG and storage capacitor CS4; whereas
L1 only need to drive DPOS and storage capacitors CS1-CS3. From the measurements, minimum
input voltage (VIN) required to generate ±3 V, ±2 V and ±1 V are 86 mV, 81 mV and 71 mV;
with free-running switching frequencies at 6.2 kHz, 7.3 kHz and 9.6 kHz, respectively, as
shown in Figure 5.33(a)-(c). Figure 5.33(d) shows the four output voltage levels by the
stacked capacitors. By using the mirroring property of pulse transformer-based boost
converter and one additional storage capacitor, the system is capable of generating bipolar ±3
V output voltage at minimum input voltage of 86 mV (boost conversion ratio up to 70) and
input power of 26 µW only.
The increased supply voltage headroom is desirable for sensitive and high power
blocks i.e. sensors, analog and RF circuits in terms of achieving better ADC resolution,
amplifier gain and linearity. The remaining branches of the stacked capacitors simultaneously
provide 2 V and 1 V outputs which can be used by ultra-low power digital blocks of less
supply voltage sensitive. The proposed multi-source energy harvesting scheme is compared
against another two state-of-the-art multi-source multi-output harvesting schemes i.e. [77]
from the industry and [8] from the academia, as summarized in Table 5.5.
5.7
Summary
The proposed pulse transformer boost converter has been silicon validated, using
different kinds of transistors and transformers. This proves the robustness, feasibility and
flexibility of this circuit under different circuit configurations. Depending on application
requirement, a bipolar output version is possible, the additional cost consists of an additional
diode and a capacitor.
72
TABLE 5.5
COMPARISON TABLE OF PROPOSED SCHEME OVER EXISTING MULTI-INPUT
SOURCE SCHEMES
LTC3330 [77]
JSSC 2012 [8]
Bipolar version
N/A
0.35-µm CMOS
0.13-µm CMOS
# of input sources
2 (PVC / PEH)
3 (PVC / PEH /
TEG)
3 (PVC / PEH / TEG)
DC-DC
architectures
Dual-Inductors
Buck-Boost +
LDO
Single-Inductor
Multiple-Output
Buck-Boost
Transformer-Boost +
Shunt Regulator
2/3
2
2/3/4
20 mV
71 mV
(Max VOUT = ±1 V)
81 mV
(Max VOUT = ±2 V)
86 mV
(Max VOUT = ±3 V)
Fabrication
technology
Storage capacitors
Minimum input
voltage
3V
Minimum input
power
7 µW
90 µW
11 µW
(@±1 V VOUT)
19 µW
(@±2 V VOUT)
26 µW
(@±3 V VOUT)
Regulated output
voltage levels
2 (Buck-Boost,
1.8~5 V;
LDO,1.2~3.6 V)
2 (SIMO: 1.8 V,
2.5 V)
2 (±1 V) /
3 (±2 V, 1 V) /
4 (±3 V, 2 V, 1 V)
Maximum output
power
250 mW
10 mW
6 mW
Peak power
conversion
efficiency
93%
87%
57%
Boost conversion
ratio (max)
2.8
60
70
Storage capacitors
balancing?
Yes
No
Yes
Maximum power
point tracking?
No
Yes
No
73
Figure 5.30
Measured DTMOS power efficiency of different transistors using L = 10
mH transformer versus input voltage VS with RS = 400 Ω
Figure 5.31
Measured VX, VY, VG and IL1 waveforms
74
Figure 5.32
Measured VIN, VCS1, IL1 and IL0 waveforms
75
Figure 5.33 Measurements showing (a) Minimum VIN at max VOUT = ±3 V configuration, (b) Minimum VIN at max VOUT = ±2V
configuration, (c) Minimum VIN at max VOUT = ±1 V configuration, (d) Four level outputs (±3 V, 2 V, 1 V) at max VOUT = ±3 V configuration
76
CHAPTER 6
CHARGE PUMP FOR SECONDARY POWER EXTRACTION
In previous chapters, the primary power stage responsible for extracting energy from
EH sources have been discussed. Shunt regulators such as the one discussed in Chapter 4 is
used to regulate the output from a free-running switched-inductor boost converter. In contrast
to such conventional wisdom, this chapter investigates the potential of charge pump as a
candidate to supplement or even substitute the shunt regulator. Cross-coupled charge pump,
both the original unipolar clock version and the revised bipolar clock version were employed
as the sample circuit for this study. Several system configurations adopting the concept of
using charge pump as secondary power extraction are proposed, and subsequently either presilicon simulated or post-silicon validated.
6.1
Concept of Secondary Power Extraction
The only design concern of conventional DC-DC converter is to convert input-output
voltage levels, where the input power is assumed to be perpetually available and high enough
to drive the control circuit. Circuit switching therefore stops when the load is not drawing any
power since the assumption is that input source always has sufficient power to supply. In the
context of energy harvesting, considering the random nature of the energy source availability,
the role of power converter in an energy harvesting system is beyond a conventional DC-DC
converter. For example, control overhead power needs to be minimized. Essentially there is
mismatch between power available and required loading power in time. To solve such
imbalance, adding extra energy buffer (battery or capacitor) to the system is one possible
solution. The idea is, excessive power that is harvested, but not consumed by load, will be
transferred to another secondary storage capacitor. Charge pump is proposed to be the
intermediary circuit that will extract the excess energy to the secondary capacitor, for two
reasons. First, charge pump can be designed fully on-chip, saving the requirement of another
bulky inductor off-chip. Second, the power extraction rate of charge pump can be easily
adjusted by changing frequency of the pumping clock.
77
This chapter investigates three possible configurations of using charge pump as the
auxiliary energy transfer circuit, which would supplement or replace shunt regulator in the
previous power stage. These configurations are:
i) Configuration 1: Boost Converter + Shunt Regulator + Unipolar Charge Pump
ii) Configuration 2: Boost Converter + Shunt Regulator + Bipolar Charge Pump
iii) Configuration 3: Boost Converter (DTMOS) + Bipolar Charge Pump only
6.1.1 Configuration 1: Boost Converter + Shunt Regulator + Unipolar Charge Pump
The proposed concept can be applied to conventional high turns-ratio transformer boost
converter system, besides the proposed 1:1 transformer system since similar shunt regulator is
used to regulate the boost converter output voltage. The proposed system is based on LTC3108
topology [54], which is a boost converter using a 1:100 turns ratio transformer [78] as shown
in Figure 6.1. The TEG model simulated is assumed to have output voltage capability 50 mV /
°C and internal resistance RTEG of 5 Ω. As the conservation of power holds, while transformer
increases input voltage ΔV, it needs to reduce secondary winding current IL1 by the same ratio
N i.e. IL1 = IL0/N concurrently. IO is assumed to be IL1. Since the output voltage VO is always
regulated to a fixed value by DZ; as VIN increases, η will decrease inversely proportional to VIN
even under the assumption that all components are lossless. Assuming MTOM to be a perfect
switch, end-to-end power transfer efficiency of the transformer oscillation circuit in Figure 6.1
is given by:

 VO
N VIN
(6.1)
The secondary stage charge pump turns on based on the input voltage level detected.
Conventional approach for voltage detection requires either voltage domain ADC or analog
comparator, which needs high voltage headroom or high biasing current to achieve high
linearity or gain. In order to minimize the power overhead required during computation of
input voltage level, the proposed system implements a time-based solution i.e. first detects the
transformer oscillation period at VX node, then calculate the period using digital counter and
on-chip clock. Sinusoidal to pulse conversion can be handled by a basic digital static logic
78
gate. Multi-threshold design techniques using multiple types of transistors are used to deal with
multiple voltage islands with varying supply voltage domains.
Figure 6.1
Figure 6.2
1:100 transformer boost converter and unipolar charge pump [79]
1:1 transformer boost converter and bipolar charge pump [80]
79
6.1.2 Configuration 2: Boost Converter + Shunt Regulator + Bipolar Charge Pump
Another possible system configuration is shown in Figure 6.2. Incoming power from
TEG will first power up the bipolar output pulse transformer boost converter (Chapter 5.3.2)
and generates ±1 V, which will be stored in CPOS and CNEG respectively. Once VDD reaches 1
V, the secondary charge pump will be activated. Both on-chip clock sources (CLK_FIX and
CLK_FLEX) are designed based on current-starved inverter-based ring oscillator. Using
inverter and negative level shifter switch driver, CLK_FLEX will be converted into two
complementary phase bipolar clock pulses (CLK1 and CLK2), which swing between +1 V
and –1 V. These clocks will drive a conventional cross-coupled pair charge pump (to be
discussed in Chapter 6.2). Due to the enhanced voltage swing, the charge pump circuit
becomes a voltage tripler instead of the usual voltage doubler. To sense the input voltage,
conventional approach requires voltage domain analog-to-digital-converter (ADC), which
consumes significant amount of power. Since the turn-on period of boost converter varies
based on input voltage, as discussed in Chapter 5.3.1, a pulse counter driven by a fixed
frequency clock (CLK_FIX) will measure this duration to determine the input voltage
indirectly. A 4-bit digital control word (FREQ_CONT) will represent the duration measured.
Whenever input voltage becomes higher, charge pump will be driven at a higher clock
rate, in order to accelerate charge extraction rate. The charge pump is only activated during
turn-on period of boost converter cycle (VX node of boost converter becomes high) to avoid
loading down storage capacitor CPOS at idle state. Based on the detected VX turn-on period,
clock frequency (CLK_FLEX) driving the charge pump will be hopping between 200 kHz
and 2 MHz, within 16 different clock rates, adjusted by the 4-bit FREQ_CONT digital code.
6.1.3 Configuration 3: Boost Converter (DTMOS) + Bipolar Charge Pump only
In the event that DTMOS (illustrated in Figure 5.15, Chapter 5.3.4) is used to
implement the NBOOST transistor for a pulse transformer boost converter, it is possible that
shunt regulator to be safely eliminated completely, while avoiding the oxide break-down
problem. This is because the body-source diode of DTMOS will self-limit the input voltage
range to below one diode drop, subsequently limiting the output voltage.
80
6.2
Unipolar and Bipolar Charge Pump
Conventional cross-coupled charge pump (Figure 6.3(a)) is first reported by [81],
which is used as a voltage doubler circuit. Recent works [82] implemented this conventional
topology using CMOS 0.18-µm process, which shows 77% efficiency when converting 0.9 V
to 1.7 V. The minimum operation voltage of a charge pump is subject to the binary switching
signal transfer limit, known as the Meindl limit [86]. The fundamental equation that governs
the theoretical minimum allowable supply voltage for a functional charge pump is:
VDD ,MIN  2
SS 
kT

 ln 1 

q
60mV 

(6.2)
where k is the Boltzmann’s constant and T is the absolute temperature and SS is the subthreshold swing (typically 60 mV / decade for standard CMOS transistor). Hence the minimum
supply voltage is 36 mV for UMC technology. Nevertheless for zero-threshold or near-zerothreshold transistors available in deep sub-micron CMOS, the minimum supply voltage
becomes 15 mV [83]. With dynamic body biasing technique using both forward and reverse
bias, negative level shifter and adaptive dead-time technique (Figure 6.3(b)) proposed by [84]
[85], this charge pump topology can be used with supply voltage down to 0.15 V.
This research explores cross-coupled charge pump topology due to several reasons, i.e.
high efficiency at nominal supply voltage, possibility of fully on-chip integration, minimal
electromagnetic interference (EMI) issue compared to the inductive DC-DC converter. The
bipolar clocked cross-coupled charge pump version is shown in Figure 6.4, which is a DC-DC
converter circuit that can convert two bipolar voltage levels into unipolar level. Doubled
voltage swing in this circuit compared to conventional cross-coupled charge pump improves
the transistors NA, NB, PA and PB on-resistances. Using negative voltage (-VDD) instead of
ground (0 V) to drive the bottom supply rail of charge pump, the output voltage level can be
further increased [87]. The unipolar clock generated on-chip needs to be converted to bipolar
voltage level. To perform the bipolar level shifting i.e. from (0 V ↔ 1 V) to (-1 V ↔ +1 V), a
bootstrapping negative switch driver highlighted in Figure 6.4 is necessary [88]. In contrast to
[84] which needs an additional negative level shifter and auxiliary negative voltage generator
to enhance the switch conductance, this bipolar charge pump utilizes the readily generated
81
bipolar output voltage from the bipolar output transformer boost converter in the previous
power stage to achieve similar objective.
There are several power loss mechanisms in charge pump which reduce power
efficiency. For example, as charge pump frequency is set to be proportional to the harvested
power, switching loss also increases linearly according to pumping frequency. Moreover, as
boost converter generates bipolar supply (essentially double the magnitude of unipolar) in the
first power stage, the gate switching loss in the clock buffer design is four times than the
unipolar counterpart. In cross-coupled charge pump without dedicated driver for each passing
transistor, reverse shoot through loss is inevitable and these events happen during each clock
transition. For conventional self-gate drive cross coupler, these reverse shoot through current
are generated every half-clock period and cannot be controlled. Power loss increases as
switching activities increase and get worse at higher input voltages. For sub-mW harvesting
power, capacitor leakage power is significant and increases exponentially according to
capacitor’s stored voltage [89], [90]. Nevertheless the aforementioned internal power loss
mechanisms and associated equation that can be manipulated to suppress the over-voltage
problem, as summarized in Table 6.1. Note that bipolar charge pump has significantly higher
power loss than its unipolar sibling.
TABLE 6.1
Loss mechanism
INTERNAL POWER LOSS MECHANISMS OF CHARGE PUMPS
Loss equation (Unipolar)
Loss equation (Bipolar)
Clock buffer gate switching
CLVDD2FCLK
4CLVDD2FCLK
Clock buffer shoot through
VDDISC1
2VDDISC1
Reverse shoot through
VDDISC2
2VDDISC2
2VDD.Aexp(2BVDD)
3VDD.Aexp(3BVDD)
Reservoir capacitor leakage
82
Figure 6.3
(a) Cross-coupled charge pump (b) non-overlapped clock generation
Figure 6.4
Bipolar cross-coupled charge pump and peripheral circuits
83
6.3
Charge Pump Control and Peripheral Circuits
In Figure 6.1, charge pump will be turned on after the input voltage level detected
exceeds programmed threshold. Conventional approach requires either voltage domain ADC
or analog comparator, which needs high voltage headroom or high biasing current if either
high linearity or gain is needed. To minimize the power overhead required during
computation of input voltage level, this system implements a time-based solution i.e. first
detects the transformer oscillation period at VX node, then calculate the period using digital
counter and on-chip clock. Hence for the timing measurement purpose, the frequency
accuracy of the clock generator becomes critical.
6.3.1 Frequency Adjustable Oscillator
A known, typical application of current-starved ring oscillator is to measure the effect
of supply voltage variation. In this system, the voltage dependency of ring oscillator
frequency can be employed to control the charge pump current delivery. Depending on supply
voltage, the on-chip oscillator generates clock signal CLK that runs between 20 kHz to 2
MHz. Signal CLK is passed to the unipolar-to-bipolar clock level shifters and buffers, which
are used to drive pumping capacitors CFLY_A and CFLY_B. Clock pumping frequencies is
designed to track the input voltage (power), which also determines the charge pump current
delivery rate.
6.3.2 Unipolar to Bipolar Level Shifter
As shown in Figure 6.4, P0, P1 and N1 form a CMOS inverter to switch the inverter
output node. CZ is the bootstrapping capacitor and N0 is the pre-charge transistor. N0 and N1
are triple-well NMOS transistors and are isolated from other NMOS transistors since their bulk
node (tied to VZ) is unstable during transient operation. Parasitic capacitance CPAR is formed
between the P-well and deep N-well. CLOAD is the load capacitance seen by the output node.
The proper CZ value (pF range of capacitor is needed) must be selected in order to achieve the
required voltage level. Cascode transistor P1 with gate shorted to ground will reduce the VGD
overstress of P0. The node voltage VZ is given by:
84
VZ  VPOS 
CZ
CZ  C LOAD  C PAR
(6.3)
The designed level shifter works fine with higher clock frequency but will fail
whenever input clock is smaller than 10 kHz, for CZ set to 10 pF. This is because the
switching transition relies on the CZ value; larger CZ capacitance and buffer size are needed in
order to run the level shifter at low clock frequency.
6.3.3 Bi-directionality of Power Flow
For system in Figure 6.4, the non-overlapped clock is optimized for bipolar supply
voltage with symmetrical magnitude. Under the condition when the main power source lack
sufficient power to charge up CPOS and CNEG via the core boost converter, significant shortcircuits power loss in the clock buffers occurs. Since charge pump topology has bidirectional
power flow property, charge pump can transfer back energy from reservoir capacitor back to
CPOS. Therefore it is also possible to add a third voltage-limited energy source such as a solar
cell to trickle charge reservoir capacitor directly, where the maximum PVC voltage is slightly
higher than reservoir capacitor voltage VHV, as shown in Figure 6.4.
6.4
Simulations and Measurements Results
6.4.1 Simulation results of configuration 1
The first proposed system shown in Figure 6.1 is simulated using UMC 0.13-µm
CMOS process. Figure 6.5 shows the simulated self-oscillation period of transformer loop and
maximum power harvestable by the charge pump. The operation waveforms of this system
are shown in Figure 6.6. On top of Figure 6.6 it shows the system turns off the charge pump
as digital control detects low input voltage (34 mV) via signals C:0 to C:3, hence generating 1
V output only. Bottom figure of Figure 6.6 shows the system can provide dual outputs 2 V
and 1 V when it detects input voltage is high (131 mV). Charge pump enabling threshold is
designed as 100 mV, which is equivalent to 20 µs of transformer self-oscillation period.
85
Figure 6.5
Maximum power harvestable by charge pump and transformer boost
converter self-oscillation period versus TEG voltage
6.4.2 Simulation results of configuration 2
The simulated operations for the second proposed system (Figure 6.2) under varying
input voltage are shown in Figure 6.7. With lower VIN, charge pump is running at lower
frequency. As VIN increases, the system senses the voltage change and will speed up the
charge pump clock frequency accordingly.
6.4.3 Measurement results of configuration 3
The bipolar charge pump prototype fabricated in UMC 0.13-µm process is shown in
Figure 6.8, occupying 0.9 mm2. As shown in Figure 6.9, with DTMOS as power transistor,
output voltage can be increased safely, up to bipolar ±2 V, compared to unipolar 1 V in [91],
which used the same transistor type as unipolar version. Bipolar charge pump then generates
5.03 V based on ±2 V, 200 kHz clock. The measured final output voltage versus input voltage
is plotted in Figure 6.10, which verified the proposed bipolar charge pump, is capable of
generating output voltage up to 6 V from 300 mV input. Besides, connecting deep N-well
substrate VDNW to either ground or VPOS did not show noticeable difference in term of
performance.
86
6.5
Summary
A cross-coupled charge pump has been designed to salvage the unused power to a
back up capacitor, instead of being shunted to ground. The bipolar version of charge pump
can merge the bipolar outputs from previous power stage (boost converter) back into single
polarity output. By adaptively adjusting the clock frequency driving the charge pump, charge
pump can supplement or even replace a shunt regulator entirely, if properly designed or
DTMOS primary power stage is used. Time-based control algorithm can be utilized to sense
the incoming power magnitude, and changes the charge pump frequency accordingly.
87
Figure 6.6
Simulated system operations for configuration 1 under varying input
voltage
88
Figure 6.7
Simulated system operations for configuration 2 under varying input
voltage
89
Figure 6.8
Chip micrograph of the fabricated DTMOS boost converter and bipolar
charge pump
Figure 6.9
Measured bipolar clock charge pump operations
90
Figure 6.10
Measured output voltage of configuration 3 (without shunt regulator)
91
CHAPTER 7
CONCLUSIONS
7.1
Conclusions
At system level, this thesis presented an energy harvesting scheme which
simultaneously harvest multiple energy sources with different voltage-current-time
characteristics, while eliminating the complicated time multiplexing algorithms and
associated circuitries of other multi-source schemes. The proposed scheme offers multiple
supply voltage levels, with bipolar option that allows flexible interfacing of external sensors,
which is instrumental in wireless sensor node applications. Increased voltage headroom
significantly improves the performance of sensors, ADC, analog and RF amplifiers. Having
multiple sources in the system has significantly shortened system start-up time.
At circuit level, 0.13µm technology is chosen for prototype implementation as it is
considered an optimum choice of CMOS technology for ultra-low voltage circuit design.
Advanced CMOS technologies with shorter channel length have diminishing returns in
advantages from the perspective of low voltage analog circuits [83]. The first circuit designed
is a Schmitt-Trigger, which is essentially a digital logic cell is proposed to build microwatt
quiescent power voltage regulator and voltage supervisor. Owing to the virtue of the circuit’s
digital nature, it is a flexible topology that can be scaled with the decreasing trend of the
CMOS nominal supply voltage. Leakage current paths are carefully optimized to ensure
smooth monotonic start-up. Output voltage of this regulator can be trimmed to deal with
process variation via single trimming resistor.
An improved fully electrical, self-start-up boost converter designed using miniature
pulse transformer is presented. By choosing transformer turn ratio to 1:1, parasitic capacitance
can be minimized, avoiding the multiplication effect of impedance transformation caused by
transformers high turns-ratio. Experimental results show that the proposed topology is flexible
on the choice of power transistor. The minimum self-start-up voltage and peak power
efficiency closely matches the state-of-the-art boost converters. Input protection diode of
92
dynamic threshold MOSFET techniques can extend the output voltage to exceed the nominal
CMOS process breakdown voltage. Using symmetrical mirroring of pulse transformer boost
converter, designers can generate an optional negative supply voltage, which tracks the
absolute value of the positive supply voltage.
Incoming power level from energy harvesting sources can be sensed from boost
converter cycle using time domain approach, which favorably avoids power hungry voltage
domain ADC. Leveraging on this property, adaptively clocked on-chip charge pump based on
sensed input voltage can effectively supplement a shunt regulator to extract excess power
harvested by the first stage converter to secondary storage capacitor, without EMI concerns.
In primary power stage where DTMOS boost converter is used, shunt regulator can be
eliminated entirely since the body-source diode clamps the incoming voltage magnitude.
7.2
Potential Future Works
Energy harvesting is an emerging, on-going research field, particularly in the
development of next generation energy harvesters and energy storage using fiber-based
composite materials [92]. Despite enjoying the convenience of being wearable and flexible,
these emerging devices also pose new design challenges for circuit designers, due to the
interchangeable roles of energy storage and generators in operation, and also the fluctuating
electrical characteristics. Therefore it is necessary to explore digital-based reprogrammable
power management integrated circuits which are capable of adapting to such unique device
characteristics during in-circuit operation.
For example, the 2-transistor voltage reference used in this thesis can be redesigned to
the 4-transistor version. By using binary weighted on-chip digital selector circuit, the output
voltage of the shunt regulator can be adjusted during in-circuit operation. The flexibility is
desirable in many applications, especially for calibration purpose.
In this thesis, multiple types of transistor available in the CMOS process have been
explored. However, there are rooms for further optimization which is by exploring the hybrid
type of transistors, connected in parallel. For example, thin oxide transistor can be used at low
93
input power range to achieve lower start-up voltage, but the system would switch to thick
oxide transistor at high input power range to achieve better power efficiency.
Since high density capacitors suffer severe leakage power loss which is proportional to
stored voltage, additional capacitor can be installed in parallel fashion if greater energy is
demanded. This design approach would require a multiple-output charge pump topology.
Hence further study in designing an advanced reconfigurable charge pump topologies [93][95] which have multiple output, self-driven clock and balances bi-directionality of power
flow would be instrumental.
Finally, further miniaturization of the system size is another research direction worth
pursuing. For instance, advanced three-dimension die stacking packaging technology [96] can
further reduce system board area. Novel wire bonding techniques [97] and new transformer
toroidal core material [98] to realize miniaturized transformer on PCB would also be
interesting research topics to explore.
94
REFERENCES
[1]
IEEE Internet of Things. [Online]. Available: http://iot.ieee.org/
[2]
D. Evans, “The Internet of Things – How the Next Evolution of the Internet is
Changing Everything,” Cisco Internet Business Solutions Group (IBSG) white paper,
April 2011.
[3]
S. E. Page, F. Siegert, J. O. Rieley, H. V. Boehm, A. Jaya and S. Limin, “The amount
of carbon released from peat and forest fires in Indonesia during 1997,” Nature, vol.
420, no. 6911, pp. 61-65, Nov. 2002.
[4]
W. Lutz, W. Sanderson and S. Scherbov, “The coming acceleration of global
population ageing,” Nature, vol. 451, no. 7179, pp. 716-719, Feb. 2008.
[5]
K. Michael and K.W. Miller, “Big Data:New Opportunities and New Challenges,”
IEEE Computer, vol. 46, no. 6, pp. 22-24, Jun. 2013.
[6]
D. Larcher and J-M. Tarascon, “Towards greener and more sustainable batteries for
electrical energy storage,” Nature Chemistry, vol. 7, no. 1, pp. 19-29, Jan. 2015.
[7]
M. Danesh and J. R. Long, “An Autonomous Wireless Sensor Node Incorporating a
Solar Cell Antenna for Energy Harvesting,” IEEE Transactions on Microwave Theory
and Techniques, vol. 59, no. 12, pp. 3546-3555, Dec. 2011.
[8]
S. Bandyopadhyay and A. P. Chandrakasan, “Platform Architecture for Solar, Thermal
and Vibration Energy Combining With MPPT and Single Inductor,” IEEE J. Solidstate Circuits, vol. 47, no. 9, pp. 2199-2215, Sep. 2012.
[9]
R. Andosca, T. G. McDonald, V. Genova, S. Rosenberg, J. Keating, C. Benedixen and
J. Wu, “Experimental and theoretical studies on MEMS piezoelectric vibrational
energy harvesters with mass loading,” Sensors and Actuators A:Physical, vol. 178, pp.
76-87, May 2012.
95
[10]
H. Bottner, J. Nurnus, A. Schubert and F. Volkert, “New high density micro structured
thermogenerators for stand alone sensor systems,” 26th International Conference on
Thermoelectrics (ICT 2007), Jun. 2007, pp. 306-309.
[11]
P. I. Mak and R. P. Martins, “High-/Mixed-Voltage RF and Analog CMOS Circuits
Come of Age,” IEEE Circuits and Systems Magazine, vol. 10, no. 4, pp. 27-39, Nov.
2010.
[12]
D. Ma, W. H. Ki, C. Y. Tsui and P. K. T. Mok, “Single-Inductor Multiple-Output
Switching Converters with Time-Multiplexing Control in Discontinuous Conduction
Mode,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 89-100, Jan. 2003.
[13]
D. Ma, W. H. Ki and C. Y. Tsui, “A pseudo-CCM/DCM SIMO switching converter
with freewheel switching, “ IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 10071014, Jun. 2003.
[14]
X. Jing and P. K. T. Mok, “Power Loss and Switching Noise Reduction Techniques
for Single-Inductor Multiple-Output Regulator,” IEEE Trans. Circuits Syst. I, vol. 60,
no. 10, pp. 2788-2798, Oct. 2013.
[15]
C. Zhan and W. H. Ki, “Analysis and Design of Output-Capacitor-Free Low-Dropout
Regulators With Low Quiescent Current and High Power Supply Rejection,” IEEE
Trans. Circuits Syst. I, vol. 61, no. 2, pp. 625-636, Feb. 2014.
[16]
C. Zhan and W. H. Ki, “An Output-Capacitor-Free Adaptively Biased Low-Dropout
Regulator With Subthreshold Undershoot-Reduction for SoC,” IEEE Trans. Circuits
Syst. I, vol. 59, no. 5, pp. 1119-1131, May 2012.
[17]
E. N. Y. Ho and P. K. T. Mok, “Wide-Loading-Range Fully Integrated LDR With a
Power-Supply Ripple Injection Filter,” IEEE Trans. Circuits Syst. II, vol. 59, no. 6, pp.
356-360, Jun. 2012.
[18]
Micropelt, MPG-D751 Datasheet. [Online]. Available:
http://www.micropelt.com/down/datasheet_mpg_d651_d751.pdf
96
[19]
Marlow Industries, TG12-2.5 Datasheet. [Online]. Available:
http://www.marlow.com/media/marlow/product/downloads/tg12-2-5-01l/TG122.5.pdf
[20]
H. Wang, G. Wang, Y. Ling, F. Qian, Y. Song, X. Lu, S. Chen, Y. Tong and Y. Li,
“High power density microbial fuel cell with flexible 3D graphene-nickle foam as
anode,” Nanoscale, vol. 5, no. 21, pp. 10283-10290, Aug. 2013.
[21]
“Solar Cells ECS300 and ECS310,” [Online]. Available:
http://www.enocean.com/en/enocean_modules/ecs-300-data-sheet-pdf
[22]
“Thin Film Solar Cell SP3-37,” [Online]. Available:
http://www.powerfilmsolar.com/products/?sp337&show=product&productID=271533
&productCategoryIDs=6573
[23]
“MEMS-based Vibrational Energy Harvesting,” [Online]. Available:
http://www.microgensystems.co
[24]
C. Wang, M. Osada, Y. Ebina, B. –W. Li, K. Akatsuka, K. Fukuda, W. Sugimoto, R.
Ma and T. Sasaki, “All-Nanosheet Ultrathin capacitors Assembled Layer-by-Layer via
Solution-Based Processes,” ACS Nano, 2014. [Online]. Available:
http://dx.doi.org/10.1021/nn406367p
[25]
“Kemet
Application
Notes
For
Tantalum
Capacitors”
[Online].
Available:
http://www.kemet.com/kemet/web/homepage/kechome.nsf/weben/08114D8D1402B2
D6CA2570A500160901/$file/F3100_TaLdPerChar.pdf
[26]
A. S. Weddell, G. V. Merrett, T. J. Kazmierski and B. M. Al-Hashimi, “Accurate
Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes,” IEEE Trans.
on Circuits and Systems II: Express Briefs, vol. 58, no. 12, pp. 911-915, Dec. 2011.
[27]
P. Sarkar and S. Chakrabartty, “Compressive Self-Powering of Piezo-Floating-Gate
Mechanical Impact Detectors,” IEEE Trans. on Circuits and Systems I: Regular
Papers, vol. 60, no. 9, pp. 2311-2320, Sep. 2013.
97
[28]
E. Alon and M. Horowitz, “Integrated Regulation for Energy-Efficient Digital
Circuits,” IEEE J. Solid-state Circuits, vol. 43, no. 8, pp. 1795-1807, Aug. 2008.
[29]
H. Ertl, J. W. Kolar and F. C. Zach, “Analysis of a multilevel multicell switch-mode
power amplifier employing the “flying-battery” concept,” IEEE Trans. on Industrial
Electronics, vol. 49, no. 4, pp. 816-823, Aug. 2002.
[30]
M. P. Chan and P. K. T. Mok, “Design and Implementation of Fully Integrated
Digitally Controlled Current-Mode Buck Converter,” IEEE Trans. Circuits Syst. I, vol.
58, no. 8, pp. 1980-1991, Aug. 2011.
[31]
T. Y. Man, P. K. T. Mok and M. Chan, “A 0.9-V Input Discontinuous-ConductionMode Boost Converter With CMOS-Control Rectifier,” IEEE J. Solid-State Circuits,
vol. 43, no. 9, pp. 2036-2046, Sep. 2008.
[32]
K. W. R. Chew, Z. Sun, H. Tang, and L. Siek, “A 400 nW single-inductor dual-inputtri-output DC-DC buck-boost converter with maximum power point tracking for
indoor photovoltaic energy harvesting,” IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers, 2013, pp. 68-69.
[33]
C. Huang and P. K. T. Mok, “A 100 MHz 82.4% Efficiency Package-Bondwire Based
Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area
Reduction,” IEEE J. Solid-State Circuits, Vol. 48, No. 12, pp. 2977-2988, December
2013.
[34]
C. Huang and P. K. T. Mok, “An 84.7% Efficiency 100-MHz Package BondwireBased Fully Integrated Buck Converter With Precise DCM Operation and Enhanced
Light-Load Efficiency,” IEEE J. Solid-State Circuits, Vol. 48, No. 11, pp. 2595-2607,
November 2013.
[35]
J. Jiang, Y. Lu and W. H. Ki, “Analysis of Two-Phase On-Chip Step-Down Switched
Capacitor Power Converters,” IEEE Asia Pacific Conference on Circuits and Systems
(APCCAS), Ishigaki Island, Okinawa, Japan, Nov. 2014, pp 575-578.
98
[36 ]
F. Su and W. H. Ki, “Design Strategy for Step-Up Charge Pumps with Variable
Integer Conversion Ratios,” IEEE Trans. Circuits Syst. II, vol. 54, no. 5, pp. 417-421,
May 2007.
[37]
C. C. Wang and J. C. Wu, “Efficiency improvement in charge pump circuits,” IEEE J.
Solid-State Circuits, vol. 32, no. 6, pp. 852-860, Jun. 1997.
[38]
M. Seok, G. Kim, D. Blaauw and D. Sylvester, “A Portable 2-Transistor Picowatt
Temperature-Compensated Voltage Reference Operating at 0.5 V,” IEEE J. SolidState Circuits, vol. 47, no. 10, pp. 2534-2545, Oct. 2012.
[39]
J. Ramirez-Angulo, R. G. Carvajal, A. Torralba, J. Galan, A. P. Vega-Leal and J.
Tombs, “The flipped voltage follower: a useful cell for low-voltage low-power circuit
design,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May. 2002, vol. 3, pp.
615-618.
[40]
I. M. Filanovsky and H. Baltes, “CMOS Schmitt trigger design,” IEEE Trans. On
Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 1, pp. 4649, Jan. 1994.
[41]
N. Lotze and Y. Manoli, “A 62 mV 0.13 µm CMOS Standard-Cell-Based Design
Technique Using Schmitt-Trigger Logic," IEEE J. Solid-State Circuits, vol. 47, no. 1,
pp. 47-60, Jan. 2012.
[42]
J. P. Kulkarni, K. Kim and K. Roy, “A 160 mV Robust Schmitt Trigger Based
Subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313,
Oct. 2007.
[43]
G. K. Balachandran and R. E. Barnett, “A 110nA voltage regulator system with
dynamic bandwidth boosting for RFID systems,” IEEE J.Solid-State Circuits, vol. 41,
no.9, pp. 2019-2028, Sep. 2006.
[44]
R.J. Widlar, “New Developments in IC Voltage Regulators,” IEEE J.Solid-State
Circuits, vol. 6, no. 1, pp. 2-7, Feb. 1971.
99
[45]
K.E. Kuijk, “A Precision Reference Voltage Source,” IEEE J.Solid-State Circuits, vol.
8, no. 3, pp. 222-226, Jun. 1973.
[46]
H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui,
“A CMOS bandgap reference circuit with sub-1V operation,” IEEE J.Solid-State
Circuits, vol. 34, no. 5, pp. 670-674, May 1999.
[47]
P. Malcovati, F. Maloberti, C. Fiocchi and M. Pruzzi, “Curvature-Compensated
BiCMOS Bandgap with 1-V Supply Voltage,” IEEE J.Solid-State Circuits, vol. 36,
no. 7, pp. 1076-1081, Jul. 2001.
[48]
K.N. Leung and P.K.T. Mok, “A Sub-1-V 15-ppm/ºC CMOS Bandgap Reference
without Requiring Low Threshold Voltage Device,” IEEE J.Solid-State Circuits, vol.
37, no. 4, pp. 526-530, Apr. 2002.
[49]
Y. K. Teh, P. K. T. Mok, “A Piezoelectric Energy Harvesting Interface Circuit Using
One-Shot Pulse Transformer Boost Converter based on Water Bucket Fountain
Strategy,” Proceedings of the 2014 IEEE International Symposium on Circuits and
System (ISCAS 2014), Melbourne, Australia, 1 - 5 Jun 2014.
[50]
E. J. Carlson, K. Strunz, and B. P. Otis, “A 20mV Input Boost Converter With
Efficient Digital Control for Thermoelectric Energy Harvesting,” IEEE J. Solid-State
Circuits, vol. 45, no. 4, pp. 741-750, Apr. 2010.
[51]
Y. K. Ramadass and A. P. Chandrakasan, “A Battery-Less Thermoelectric Energy
Harvesting Interface Circuit With 35mV Start-up Voltage,” IEEE J. Solid-State
Circuits, vol. 46, no. 1, pp. 333-341, Jan. 2011.
[52]
P. H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M.
Takamiya, and T. Sakurai, “Start-up techniques for 95 mV step-up converter by
capacitor pass-on scheme and VTH-tuned oscillator with fixed charge programming,”
IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1252-1260, May 2012.
100
[53]
P. S. Weng, H. Y. Tang, P. C. Ku, L. H. Lu, “50 mV-Input Batteryless Boost
Converter for Thermal Energy Harvesting,” IEEE J. Solid-State Circuits, vol. 48, no.
4, pp. 333-341, Apr. 2013.
[54]
Linear Technology, LTC3108 Datasheet. [Online]. Available:
http://cds.linear.com/docs/Datasheet/3108fb.pdf
[55]
J. P. Im, S. W. Wang, S. T. Ryu, and G. H. Cho, “A 40 mV Transformer-Reuse SelfStart-up Boost Converter With MPPT Control for Thermoelectric Energy Harvesting,”
IEEE J. Solid-state Circuits, vol. 47, no. 12, pp. 3055-3067, Dec. 2012.
[56]
O. Zucker, J. Wyatt, K. Lindner, “The Meat Grinder: Theoretical and practical
limitations,” IEEE Trans. on Magnetics, vol. 20, no. 2, pp. 391-394, Mar. 1984.
[57]
Y. K. Teh and P. K. T. Mok, “Design of Coupled Inductor-Based Boost Converter for
Ultra Low Power Thermoelectric Energy Harvesting using Pulse Transformer with
75mV Start-up Voltage,” in Proc. IEEE Int. Conf. Electron Devices and Solid-State
Circuits (EDSSC), Hong Kong, Jun. 2013.
[58]
Murata Power Solutions, 786-series General Purpose Pulse Transformer Datasheet.
[Online]. Available: http://www.murata-ps.com/data/magnetics/kmp_786.pdf
[59]
B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy and S. Borkar, "Effectiveness
and scaling trends of leakage control techniques for sub-130 nm CMOS technologies,"
Proc. Low Power Electronics and Design (ISLPED), pp. 122-127, Aug 2003.
[60]
J. Yi, W. H. Ki, P. K. T. Mok and C. Y. Tsui, “Dual-Power-Path RF-DC Multi-Output
Power Management Unit for RFID Tags,” Proc. IEEE Symp. on VLSI Circuits
(VLSIC), Kyoto, Japan, pp. 200-201, Jun. 2009.
[61]
W. J. Chudobiak and D. F. Page, “Frequency and power limitations of Class-D
transistor amplifiers,” IEEE J. Solid-State Circuits, vol. 4, no. 1, pp. 25-37, Feb. 1969.
101
[62]
T. Johnson and S. P. Stapleton, “RF Class-D Amplification With Bandpass Sigma–
Delta Modulator Drive Signals,” IEEE Trans. on Circuits and Systems I: Regular
Papers, vol. 53, no. 12, pp. 2507-2520, Dec. 2006.
[63]
S. H. -L. Tu and C. Toumazou, “Low-distortion CMOS complementary class E RF
tuned power amplifiers,” IEEE Trans. on Circuits and Systems I: Fundamental Theory
and Applications, vol. 47, no. 5, pp. 774-779, May 2000.
[64]
Y. K. Teh, P. K. T. Mok, “A Stacked Capacitor Multi-Microwatts Source Energy
Harvesting Scheme With 86 mV Minimum Input Voltage and ±3 V Bipolar Output
Voltage,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems
(JETCAS), Vol 4, Issue 3, pg 313 – 323, Sep 2014.
[65]
D. L. Hidalga, F. J. and M. J. Deen, “The dynamic threshold voltage MOSFET,”
Proceedings of the 2000 Third IEEE International Caracas Conference on Devices,
Circuits and Systems, Cancun, Mexico, pp. D63/1-D63/7, Mar 2000.
[66]
G. Baccarani, M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory and
its application to a ¼ micrometer MOSFET design,” IEEE Transactions on Electron
Devices, vol. 31, no.4, pp. 452 – 462, Apr 1984.
[67]
Z. Yan, M.J. Deen, D.S. Malhi, “Gate-controlled lateral PNP BJT: characteristics,
modeling and circuit applications,” IEEE Transactions on Electron Devices, vol. 44,
no. 1, pp. 118-128, Jan 1997.
[68]
F. Assaderaghi, D. Sinitsky, S.A. Parke, J. Bokor, P.K. Ko, C. Hu, “Dynamic
Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEEE
Transactions on Electron Devices, vol. 44, no. 3, pp. 414-422, Mar 1997.
[69]
F. Assaderaghi, “DTMOS: its derivatives and variations, and their potential
applications,” Proceedings of the 12th International Conference on Microelectronics,
(ICM 2000), Tehran, Iran, pp 9-10, 2000.
102
[70]
H. Kotaki, S. Kakimoto, M. Nakano, T. Matsuoka, K. Adachi, K. Sugimoto, T.
Fukushima and Y. Sato, “Novel bulk dynamic threshold voltage MOSFET (BDTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C)
processes for ultra low power dual gate CMOS,” International Electron Devices
Meeting, San Francisco, CA, USA, pp.459 – 462, Dec. 1996,.
[71]
Y. C. Hung and B. D. Liu, “0.75-V subthreshold CMOS logic using dynamic substrate
bias,” Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and
Systems, Tainan, Taiwan R.O.C., pp. 345 – 348, Dec. 2004.
[72]
L. S. Y. Wong and G. A. Rigby, “A 1 V CMOS digital circuits with double-gatedriven MOSFET,” IEEE ISSCC Dig. Tech. Papers, pp. 292-293, Feb 1997.
[73]
Y. K. Teh, F. Mohd-Yasin, F. Choong, M. B. I. Reaz, A. V. Kordesch, “Design and
Analysis of UHF Micro-Power CMOS DTMOST Rectifiers,” IEEE Transactions on
Circuits and Systems II, Vol 56, Issue 2, pg 122-126, Feb 2009.
[74]
Y.C Chang, J.G. Su, H.M. Hsu, S.C. Wong, T.Y. Huang, and Y.C. Sun,
“Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz normalmode ft and 220 GHz over-drive mode ft for RF applications,” Digest of Technical
Papers 2001 Symposium on VLSI Technology, Kyoto, Japan, pp.89-90, Jun 2001.
[75]
P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, “Analysis and Design of Analog
Integrated Circuits 5th Edition,” USA, John Wiley & Sons, Inc, January 2009.
[76]
Coilcraft, DA2099-AL Transformer Datasheet. [Online]. Available:
http://www.coilcraft.com/pdfs/da2099.pdf
[77]
Linear Technology, LTC3330 Datasheet. [Online]. Available:
http://cds.linear.com/docs/en/datasheet/3330f.pdf
[78]
Coilcraft Coupled Inductors-LPR6235 Datasheet. [Online]. Available:
http://www.coilcraft.com/pdf_viewer/showpdf.cfm?f=pdf_store:lpr6235.pdf
103
[79]
Y. K. Teh, P. K. T. Mok, “A Dual Mode Thermoelectric Energy Harvesting Circuit
Using Transformer-based Boost Converter, Charge Pump and Time-Domain Digital
Control,” Proceedings of the 2014 IEEE International Conference of Electron Devices
and Solid-State Circuits (EDSSC 2014), Chengdu, China, 18 - 20 Jun 2014.
[80]
Y. K. Teh, P. K. T. Mok, “A Bipolar Output Pulse Transformer Boost Converter with
Charge Pump Assisted Shunt Regulator for Thermoelectric Energy Harvesting,”
Proceedings of the 2014 IEEE 57th International Midwest Symposium on Circuits and
Systems (MWSCAS 2014), College Station, Texas, USA, 3 - 6 Aug 2014.
[81]
P. Favrat, P. Deval and M. J. Declercq, “A high-efficiency CMOS voltage doubler,”
IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410– 416, Mar. 1998.
[82]
S. Bandyopadhyay, P. P. Mercier, A. C. Lysaght, K. M. Stankovic and A. P.
Chandrakasan, “A 1.1 nW Energy Harvesting System with 544pW Quiescent Power
for Next-Generation Implants,” Proc. IEEE Int. Solid State-Circuits Conf. (ISSCC), pp.
396-397, Feb. 2014.
[83]
C. Galup-Montoro, M. C. Schneider, and M. B. Machado, “Ultra-low voltage operation
of CMOS analog circuits:Amplifiers, oscillators, and rectifiers,” IEEE Trans. on
Circuits and Systems II: Express Briefs, vol. 59, no. 12, pp. 932–936, Dec. 2012.
[84]
J. Kim, P. K. T. Mok and C. Kim, “A 0.15V-Input Energy-Harvesting Charge Pump
with Switching Body Biasing and Adaptive Dead-Time for Efficiency Improvement,”
Proc. IEEE Int. Solid State-Circuits Conf. (ISSCC), pp. 394-395, Feb. 2014.
[85]
J. Kim, C. Kim, P.K.T. Mok, Y.K. Teh, “A low-voltage high-efficiency voltage
doubler for thermoelectric energy harvesting,” Proceedings of the 2013 IEEE
International Conference of Electron Devices and Solid-State Circuits (EDSSC 2013),
Hong Kong, 3 – 5 Jun 2013.
[86]
J. D. Meindl and A. J. Davis, “The fundamental limit on binary switching energy for
terascale integration (TSI),” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1515–
1516, Oct. 2000.
104
[87]
W. Jung, S. Oh, S. Bang, Y. Lee, D. Sylvester and D. Blaauw, “A 3nW Fully
Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor DC-DC
Converter,” Proc. IEEE Int. Solid State-Circuits Conf. (ISSCC), pp. 398-399, Feb.
2014.
[88]
P. Liu, X. Wang, D. Wu, Z. Zhang and L. Pan, “A novel high-speed and low-power
negative voltage level shifter for low voltage applications,” Proc. IEEE Int. Symp.
Circuits and Systems (ISCAS), May 2010, pp. 601-604.
[89]
S. Kim and P.H. Chou, “Size and Topology Optimization for Supercapacitor-Based
Sub-Watt Energy Harvesters,” IEEE Trans. Power Electronics, vol. 28, no. 4, pp.
2068-2080, Apr 2013.
[90]
G. V. Merrett, A. S. Weddell, A. P. Lewis, N.R. Harris, B. M. Al-Hashimi and N. M.
White, "An Empirical Energy Model for Supercapacitor Powered Wireless Sensor
Nodes," Proc. Int. Conf. Computer Communication and Networks (ICCCN), pp. 1-6,
Aug 2008.
[91]
Y.K Teh and P.K.T. Mok, “Design of Transformer-Based Boost Converter for High
Internal Resistance Energy Harvesting Sources With 21 mV Self-Start-up Voltage and
74% Power Efficiency,” IEEE J. Solid-state Circuits, vol. 49, no. 11, pp. 2694-2704,
Nov 2014.
[92]
J. Zhong, Y. Zhang, Q. Zhong, Q. Hu, B. Hu, Z. L. Wang and J. Zhou, “Fiber-Based
Generator for Wearable Electronics and Mobile Medication,” ACS Nano, vol. 8, no. 6,
pp. 6273-6280, Apr. 2014. DOI: 10.1021/nn501732z
[93]
Z. Hua and H. Lee, “A Reconfigurable Dual-Output Switched-Capacitor DC-DC
Regulator With Sub-Harmonic Adaptive-On-Time Control for Low Power
Applications,” IEEE J. Solid-state Circuits, vol. 50, no. 3, pp. 1-13, Mar. 2015.
[94]
X. Zhang and H. Lee, “An Efficiency-enhanced auto-reconfigurable 2×/3× SC charge
pump for transcutaneous power transmission,” IEEE J. Solid-state Circuits, vol. 45, no.
9, pp. 1906-1922, Sep. 2010.
105
[95]
H. Lee, Z. Hua, and X. Zhang, “A reconfigurable 2×/2.5×/3×/4× SC DC-DC regulator
with fixed on-time control for transcutaneous power transmission,” IEEE Trans. Very
Large-Scale Integr. (VLSI) Syst.,vol.PP, no.99, pp.1-11, 2014.
[96]
A. Yu, J. H. Lau, S. W. Ho, A. Kumar, W. Y. Hnin, W. S. Lee, M. C. Jong, V. N.
Sekhar, V. Kripesh, D. Pinjala, S. Chen, C. -F. Chan, C. -C. Chao, C. -H. Chiu, C.- M.
Huang, and C. Chen, “Fabrication of high aspect ratio TSV and assembly with finepitch low-cost solder microbump for Si interposer technology with high-density
intercon-nects,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 1, no. 9, pp.
1336–1344, Sep. 2011.
[97]
M. Raimann, A. Peter, D. Mager, U. Wallrabe, J.G. Korvink, “Microtransformer-Based
Isolated Signal and Power Transmission,” IEEE Transactions on Power Electronics,
vol. 27, no. 9, pp. 3996-4004, Mar. 2012.
[98]
E. Macrelli, A. Romani, N. Wang, S. Roy, M. Hayes, R.P. Paganelli, C. Mathuna and
M. Tartagni, “Modeling, Design, and Fabrication of High Inductance Bond Wire
Micro-Transformers with Toroidal Ferrite Core,” IEEE Transactions on Power
Electronics, DOI:10.1109/TPEL.2014.2370814, 2014.
106
APPENDIX A
PROTOTYPE PHOTOS
Figure A.1
New Generation TEG by Micropelt
Figure A.2
Test chip wire-bonded on test PCB
107
Figure A.3
Prototype Test PCB with Transformers A and D
Figure A.4
Prototype Test PCB with Transformers B and C
108
APPENDIX B
BIOGRAPHY
Ying-Khai TEH (鄭穎凱) was born in Ipoh, Perak, Malaysia. He received the B.Eng.
and M.Eng.Sc. degrees in Electronics from the Multimedia University (formerly University
Telekom Malaysia), Cyberjaya, Malaysia, in 2005 and 2009, respectively. He is currently
pursuing the Ph.D. degree at the Hong Kong University of Science and Technology, with the
Integrated Power Electronics Laboratory (IPEL), Department of Electronic and Computer
Engineering. His research interest is energy harvesting circuit design.
He is a recipient of the Telekom Malaysia Scholarship (2000–2004), Canada
Commonwealth Graduate Exchange Scholarship (2008), and Hong Kong Ph.D. Fellowship
(2010–2014). He also received the Excellent Student Paper Award in the 2009 IEEE
International Conference on ASIC (ASICON), Changsha, China and the Best Student Paper
award in the 2014 IEEE International Midwest Symposium on Circuits and Systems
(MWSCAS), College Station, Texas, USA.
109
LIST OF PUBLICATIONS
During my PhD program, I have published my research findings in refereed journal
and conference articles listed below:
Journal Publications:
[J1]
Y.K. Teh, P.K.T. Mok, “DTMOS-based Pulse Transformer Boost Converter with
Complementary Charge Pump for Multi-Source Energy Harvesting,” IEEE
Transactions on Circuits and Systems II (TCAS2), to be submitted for review.
[J2]
Y.K. Teh, P.K.T. Mok, “Design of Transformer-based Boost Converter for High
Internal Resistance Energy Harvesting Sources With 21 mV Self-Start-up Voltage and
74% Power Efficiency,” IEEE Journal of Solid State Circuits (JSSC), Vol 49, Issue
11, pg 2694 – 2704, Nov 2014.
[J3]
Y.K. Teh, P.K.T. Mok, “A Stacked Capacitor Multi-Microwatts Source Energy
Harvesting Scheme With 86 mV Minimum Input Voltage and ±3 V Bipolar Output
Voltage,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems
(JETCAS), Vol 4, Issue 3, pg 313 – 323, Sep 2014.
[J4]
A.M.H. Kwan, S. Song, X. Lu, L. Lu, Y.K. Teh, Y.F. Teh, E.W.C. Chong, Y.G.W.
Hau, F. Zeng, M. Wong, C. Huang, T. Akira, M. Yoshihide, N. So, T. Toshiyuki, T.
Osamu, “Improved Designs for an Electro-Thermal In-Plane Micro-Actuator,” IEEE
Journal of Microelectromechanical Systems (JMEMS), Vol 21, Issue 3, pg 586 - 595,
Jun 2012.
Conference Publications:
[C1]
Y.K. Teh, P.K.T. Mok, “A Bipolar Output Pulse Transformer Boost Converter with
Charge Pump Assisted Shunt Regulator for Thermoelectric Energy Harvesting,”
Proceedings of the 2014 IEEE 57th International Midwest Symposium on Circuits and
Systems (MWSCAS 2014), College Station, Texas, USA, 3 - 6 Aug 2014.
(MWSCAS Best Student Paper)
110
[C2]
Y.K. Teh, P.K.T. Mok, “A Dual Mode Thermoelectric Energy Harvesting Circuit
Using Transformer-based Boost Converter, Charge Pump and Time-Domain Digital
Control,” Proceedings of the 2014 IEEE International Conference of Electron Devices
and Solid-State Circuits (EDSSC 2014), Chengdu, China, 18 - 20 Jun 2014.
[C3]
Y.K. Teh, P.K.T. Mok, “A Piezoelectric Energy Harvesting Interface Circuit Using
One-Shot Pulse Transformer Boost Converter based on Water Bucket Fountain
Strategy,” Proceedings of the 2014 IEEE International Symposium on Circuits and
System (ISCAS 2014), Melbourne, Australia, 1 - 5 Jun 2014.
(ISCAS Student Travel Grant Award)
[C4]
Y.K. Teh, P.K.T. Mok, “Design of coupled inductor-based boost converter for ultra
low power thermoelectric energy harvesting using pulse transformer with 75mV startup voltage,” Proceedings of the 2013 IEEE International Conference of Electron
Devices and Solid-State Circuits (EDSSC 2013), Hong Kong, 3-5 Jun 2013.
(Nominated for the circuit track Best Student Paper)
[C5]
J. Kim, C. Kim, P.K.T. Mok, Y.K. Teh, “A low-voltage high-efficiency voltage
doubler for thermoelectric energy harvesting,” Proceedings of the 2013 IEEE
International Conference of Electron Devices and Solid-State Circuits (EDSSC 2013),
Hong Kong, 3 – 5 Jun 2013.
[C6]
A.M.H. Kwan, S. Song, X. Lu, L. Lu, Y.K. Teh, Y.F. Teh, E.W.C. Chong, Y.G.W.
Hau, F. Zeng, M. Wong, C. Huang, T. Akira, M. Yoshihide, N. So, T. Toshiyuki, T.
Osamu, “Designs for improving the performance of an electro-thermal in-plane
actuator,” Proceedings of the 2011 IEEE/IFIP 19th International Conference on VLSI
and System-on-Chip (VLSI-SoC), Hong Kong, 3 - 5 Oct 2011.
111