ECEG-3201 Digital Logic Design
Addis Ababa Institute of Technology
(AAIT) Department of Electrical and
Computer Engineering
AAIT, Department of
Tsegamlak Terefe (PhD)
Learning Outcomes
◼ At the end of the lecture, students should recall;
Comparators.
❑ NAND gates.
❑ NOR gates.
❑ Full adders.
❑ Multiplexers.
❑ Priority encoders.
❑
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Comparators
An arithmetic circuit that compares the relative sizes
of two binary numbers is called a comparator.
◼ A comparator produces three outputs, called AeqB,
AgtB, and AltB.
◼ The AeqB output is set to 1 if A and B are equal. The
AgtB output is 1 if A is greater than B, and the AltB
output is 1 if A is less than B.
◼ The desired comparator can be designed by creating
a truth table that specifies the three outputs as
functions of A and B. However, even for moderate
values of n, the truth table is large.
◼
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Comparators
A better approach is to derive the comparator circuit
by considering the bits of A and B in pairs.
◼ Let A = a3a2a1a0 and B = b3b2b1b0. Define a set of
intermediate signals called i3, i2, i1, and i0. Each
signal, ik , is 1 if the bits of A and B with the same
index are equal.
◼
ik = Ak  Bk
◼
The comparator’s AeqB output is then given by
AeqB = i3 i2 i1i0
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Comparators
An expression for the AgtB output can be derived by
considering the bits of A and B in the order from the
most-significant bit to the least-significant bit.
◼ The first bit-position, k, at which ak and bk differ
determines whether A is less than or greater than B. If
ak = 0 and bk = 1, then A < B. But if ak = 1 and bk = 0,
then A > B.
◼
AgtB = a3 b3 + i3a2 b2 + i3 i2a1 b1 + i3 i2 i1a0 b0
◼
The AltB output can be derived by using the other two
outputs as.
AltB = AeqB + AgtB
AAIT, Department of
Electrical and Computer
Engineering
5
Tsegamlak Terefe (PhD)
Comparator Circuit Implementation
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NAND and NOR Logic Gates
NAND and NOR functions which are obtained by
complementing the output generated by AND and OR
operations, respectively.
◼ These two functions are attractive because they are
implemented with simpler electronic circuits than the
AND and OR functions.
◼ They are also universal gates.
◼
NAND
AAIT, Department of
Electrical and Computer
Engineering
NOR
7
Tsegamlak Terefe (PhD)
NAND Logic Gate
◼
In relation to DeMorgan’s theorem;
❑ It specifies that a NAND of variables x1 and x2 is
equivalent to first complementing each of the
variables and then ORing them.
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NOR Logic Gate
◼
In relation to DeMorgan’s theorem;
❑ It states that the NOR function is equivalent to first
inverting the input variables and then ANDing them.
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NAND and NOR Logic Gates
Any logic function can be implemented either in sumof-products or product-of-sums form, which leads to
logic networks that have either an AND-OR or an ORAND structures, respectively.
◼ And such networks can be implemented using only
NAND gates or only NOR gates.
◼ Use
double inversion to implement any logic
expression using only NAND gates.
◼
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NAND Implementation Example
x1 x2 + x3 x4 x5
x1 x2 + x3 x4 x5 = ( x1 x2 )( x3 x4 x5 )
Any SOP
expression can be
implemented using
only NAND gates
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NAND
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NOR Implementation Example
( x1 + x2 )( x3 + x4 + x5 )
( x1 + x2 )( x3 + x4 + x5 ) = ( x1 + x2 ) + ( x3 + x4 + x5 )
Any POS
expression can be
implemented using
only NOR gates
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
NOR
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Baugh Wooley Multiplier
Check (10*12=120)
1010*1100 =1111000
Check (9*6=54)
0110*1001 =110110
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Synthesis of Logic Functions Using
Multiplexers
◼
Multiplexers can be used in a more general way to
synthesize logic functions.
Example 1: Implement XOR function using 4 to 1 multiplexer. F = w1  w2
w1
w2
F
0
0
0
0
1
1
1
0
1
1
1
0
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Synthesis of Logic Functions Using
Multiplexers
Example 2: Implement XOR function using 2 to 1 multiplexer. F = w1  w2
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Synthesis of Logic Functions Using
Multiplexers
Example 3: Using 4 to 1 mux. implement a three-input majority vote system
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Exercise
Implement F = w1  w2  w3 using a single 4 to 1 Mux
AAIT, Department of
Electrical and Computer
Engineering
19
Tsegamlak Terefe (PhD)
Priority Encoder
In a priority encoder each input has a priority level
associated with it.
◼ The encoder outputs indicate the active input that has
the highest priority.
◼ When an input with a high priority is asserted, the
other inputs with lower priority are ignored.
◼ The outputs y1 and y0 represent the binary number
that identifies the highest priority input set to 1. Since
it is possible that none of the inputs is equal to 1, an
output, z, is provided to indicate this condition. It is set
to 1 when at least one of the inputs is equal to 1. It is
set to 0 when all inputs are equal to 0.
◼
AAIT, Department of
Electrical and Computer
Engineering
20
Tsegamlak Terefe (PhD)
Priority Encoder
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Exercise 1
1. Design a combinational logic circuit that takes an
unsigned 2-bit number, X=X1X0, and computes the
square of that number, Y=X2. You have to show all
the necessary steps you have followed to arrive at
your final combinational logic circuit design.
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
Exterciese 2
1. Determine the outputs
functions A and B as
sums of minterms. You
may use any process to
determine the result.
2. The circuit shown has
the functionality of a
usually used arithmetic
component. What does
the circuit do and what
are other names for A
and B?
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)
What to do this week?
◼ Reading assignment.
❑
Read about Flip-Flops, Registers, Counters, and a
Simple Processor, Chapter 7, Fundamentals of
digital logic with Verilog design, page 349 – 385.
AAIT, Department of
Electrical and Computer
Engineering
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Tsegamlak Terefe (PhD)