ARENBERG DOCTORAL SCHOOL
FACULTY OF SCIENCE
Department of Physics and Astronomy
Charge traps at interfaces of high-mobility
semiconductor channels with oxide
insulators
NGUYEN Hoang Thoan
Supervisory committee:
Prof. Dr. Michel Houssa (Chairman)
Prof. Dr. André Stesmans (Promoter)
Prof. Dr. Valery Afanas’ev (Co-promoter)
Prof. Dr. Paul Hurley
(Tyndall National Institute, Ireland)
Dr. Guy Brammertz (IMEC )
Prof. Dr. Michael Wübbenhorst
Prof. Dr. Joris Van de Vondel
March 2013
Local promoter:
Dr. Truong Thi Ngoc Lien
Dissertation presented in
partial fulfillment of the
requirements for the degree
of Doctor in Science
KU LEUVEN
Arenberg Doctoral School
Faculty of Science
Department of Physics and Astronomy
Semiconductor Physics Laboratory
Celestijnenlaan 200D, B-3001 Leuven, box 2417
Charge traps at interfaces of high-mobility
semiconductor channels with oxide
insulators
NGUYÊN
e
Hoàng
Thoan
Supervisory committee:
Prof. Dr. Michel Houssa (Chairman)
Prof. Dr. André Stesmans (Promoter)
Prof. Dr. Valery Afanas’ev (Co-promoter)
Prof. Dr. Paul Hurley
(Tyndall National Institute, Ireland)
Dr. Guy Brammertz (IMEC )
Prof. Dr. Michael Wübbenhorst
Prof. Dr. Joris Van de Vondel
March 2013
Local promoter:
Dr. Truong Thi Ngoc Lien
Dissertation presented in
partial fulfillment of the
requirements for the degree
of Doctor in Science
© 2013 KU Leuven – Faculty of Science
Celestijnenlaan 200D, B-3001 Leuven (Belgium)
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ISBN number ISBN 978-90-8649-600-6
Legal depot number D/2013/10.705/15
iii
To parents and my family
Acknowledgements
I would like to thank all the people who supported me throughout the course
of my PhD and contributed, directly or indirectly, to the completion of this
dissertation.
First and foremost, I want to thank my promoters, Prof. André Stesmans
and Prof. Valery Afanas’ev, for their guidance, inspiration, knowledge
and unfailing encouragement and support. Their support, guidance and
encouragement from the beginning to the final level, motivated and enabled
me to develop an understanding of the subject. Thank you very much for
spending a lot of time to review, critical reading and making suggestions
for improvements of this thesis and all my articles.
I would also like to thank my co-promoter in Vietnam, Dr. Lien Truong,
who first introduced me to Prof. André Stesmans, and also supported my
PhD studies.
I am also grateful to all jury members, Prof. Michel Houssa, Dr. Guy
Brammertz, Prof. Joris Van de Vondel, Prof. Michael Wübbenhorst and
Prof. Paul Hurley, for reading, evaluating and giving valuable comments to
improve this thesis.
I would like to thank the Belgian Government, The Belgian Technical
Cooperation (BTC) for the financial support; Thanks to Thu Huong, Thanh
Huong, Liesbet, Nicolas, Francoise... for their great organization.
Thanks to a number of friends and colleagues, in particular Mikhail and
Yanina for their discussion at the first stage of my PhD. I also want to thank
all my colleagues in the Semiconductor group: Mugwort, Hsing-Y, Mihaela,
Francesca, Emilio, Sang, Duc, Koen, Jacek, Adam, Rao, Mikhail, Oreste,
Florin, Bas, Serena, Gonda, Daniel... who made me feel like at home. I
v
vi
Acknowledgements
would like to thank Gonda also for her support and organization of my stay
at KU. Leuven.
During the time of my study in Belgium, I met a lot of Vietnamese students
and their families (Tuyet, Xa, Mai+Lu, Thuy+Jorg, Phuong+Phillipe,
Duc+Tam, Hai+Thoa, Hanh+Sang, Dinh, Hoai+Hans, Thuy+Phuong,
Tien+Thanh, Hieu, Cuong, Van, Hasa...), to whom I am grateful for their
supportive friendship.
My great thankfulness also goes to my colleagues at the School of Engineering
Physics, Hanoi University of Science and Technology.
From all of my heart, my biggest gratitude goes to my family, for their
unconditional love and hard work, for putting my education as their highest
priority even in a time of deep economical crisis. I am very grateful to my
husband, Dang Quang, who has been a constant support and encouragement
through the necessary ups and downs of the project. I would also like to
thank my little daughter, Hoang Lan, for her love.
Contents
Contents
vii
List of abbreviations
xiii
List of symbols
xv
List of Figures
xix
List of Tables
xxix
1 Introduction
1.1 Extending Moore’s Law . . . . . . . . . . . . . . . . . . . .
1.2
1
1
High mobility semiconductors . . . . . . . . . . . . . . . . .
3
1.2.1
SiGe alloy semiconductor . . . . . . . . . . . . . . .
3
1.2.2
1.2.3
Germanium . . . . . . . . . . . . . . . . . . . . . .
III-V compound semiconductors . . . . . . . . . . .
5
6
1.3
Common issues with interface traps
. . . . . . . . . . . . .
7
1.4
Objectives of the thesis
. . . . . . . . . . . . . . . . . . . .
9
2 Extraction of interface trap properties by using CV and GV
measurements
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 AC model of a MOS capacitor . . . . . . . . . . . . . . . .
13
13
15
2.3
Capacitance methods of trap characterization
2.3.1
. . . . . . .
16
Low frequency CV method . . . . . . . . . . . . . .
16
vii
viii
CONTENTS
2.3.2
Determining the energy distribution of interface traps
using a low frequency CV curve . . . . . . . . . . .
19
2.3.3
High frequency CV method . . . . . . . . . . . . . .
21
2.3.4
Determination of flatband voltage and substrate’s
doping concentration . . . . . . . . . . . . . . . . .
23
2.3.5
High-low frequency method . . . . . . . . . . . . . .
27
2.3.6
Gray-Brown temperature-induced shift technique . .
27
Conductance method of trap characterization . . . . . . . .
30
2.4.1
Correlation of Gp /ω and Dit . . . . . . . . . . . . .
30
2.4.2
Extraction of Gp /ω from CV and GV measurements
32
2.4.3
Oxide capacitance and series resistance . . . . . . .
32
2.4.4
Interface trap density Dit . . . . . . . . . . . . . . .
35
2.5
Carrier capture cross section and interface trap time
constants . . . . . . . . . . . . . . . . . . . . . . . .
Measurement setups . . . . . . . . . . . . . . . . . . . . . .
36
39
2.6
Conclusion
40
2.4
2.4.5
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Interface state energy distribution and Pb defects at (110)Si/SiO2
interfaces: Comparison to (111) and (100) Si orientations
41
3.1
3.2
3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Experimental details . . . . . . . . . . . . . . . . . . . . . .
42
44
3.2.1
Sample preparation
. . . . . . . . . . . . . . . . . .
44
3.2.2
3.2.3
Electrical measurements . . . . . . . . . . . . . . . .
ESR spectroscopy . . . . . . . . . . . . . . . . . . .
45
46
Results and discussion . . . . . . . . . . . . . . . . . . . . . 46
3.3.1 Dependence of interface properties on silicon orientation 46
3.3.2
Comparison with ESR results . . . . . . . . . . . . .
55
3.3.3
Hydrogen passivation of Si dangling bonds . . . . . .
56
3.3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . .
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
58
4 Correlation between interface traps and paramagnetic defects
in c-Si(100)/a-Si:H heterojunctions
59
3.4
CONTENTS
ix
4.1
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Experimental details . . . . . . . . . . . . . . . . . . . . . .
59
61
4.3
Experimental results and analysis
. . . . . . . . . . . . . .
62
4.4
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
5 Chemical kinetics of hydrogen passivation and dissociation
reactions of Ge dangling bonds at the Si0.25 Ge0.75 /SiO2
interface
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Experimental details . . . . . . . . . . . . . . . . . . . . . .
71
71
73
5.2.1
5.3
5.4
5.5
Sample preparation
. . . . . . . . . . . . . . . . . .
73
5.2.2 CV measurements . . . . . . . . . . . . . . . . . . .
5.2.3 ESR measurements . . . . . . . . . . . . . . . . . . .
Experimental results and interpretation . . . . . . . . . . .
75
76
76
5.3.1
CV vs ESR probing . . . . . . . . . . . . . . . . . .
76
5.3.2
5.3.3
5.3.4
5.3.5
Passivation and dissociation: isochronal . . . . . . .
GST model . . . . . . . . . . . . . . . . . . . . . . .
Passivation and dissociation: isothermal . . . . . . .
GST model interpretation . . . . . . . . . . . . . . .
80
81
84
87
5.3.6
Full interaction case: effect of spreads on passivation
efficiency . . . . . . . . . . . . . . . . . . . . . . . .
91
Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Enhanced spread in activation energy . . . . . . . .
95
95
5.4.2
5.4.3
95
98
Non reactive defects . . . . . . . . . . . . . . . . . .
H2 molecule cracking . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . .
99
6 Passivation of Ge interfaces: Silicon passivation of Ge/HfO2
interfaces and Ge3 N4 passivation of Ge/metal contacts
101
6.1
6.2
Conclusion
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Ge/HfO2 interface passivation by silicon . . . . . . . . . . 102
6.2.1
6.2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . 102
Samples and measurements . . . . . . . . . . . . . . 102
x
CONTENTS
6.3
6.4
6.2.3 Results and discussion . . . . . . . . . . . . . . . . . 103
6.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 110
Schottky barrier control on Ge using Ge3 N4 . . . . . . . . 111
6.3.1
6.3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . 111
Samples and measurements . . . . . . . . . . . . . . 112
6.3.3
6.3.4
Extraction of Schottky barrier height by CV measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Pinning effect at n-type Ge/metal interface . . . . . 113
6.3.5
Schottky barrier control . . . . . . . . . . . . . . . . 114
6.3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 118
Conclusion of the chapter . . . . . . . . . . . . . . . . . . . 118
7 Interface and oxide traps in III-V/high-κ oxide structures
7.1
7.2
119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ALD TaSiOx insulators on InP, In0.53 Ga0.47 As and Si . . . 120
7.2.1
7.2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . 120
Samples and measurements . . . . . . . . . . . . . . 120
7.2.3
Charge trapping in (100)Si/TaSiOx /Au MIS structures121
7.2.4
Charge traping in (100)In0.53 Ga0.47 As/TaSiOx /Au
MIS structures . . . . . . . . . . . . . . . . . . . . . 124
Charge trapping in (100)InP/TaSiOx /Au MIS structures126
7.2.5
7.2.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . 127
7.2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 128
7.3 Charge traps at the (100)In0.53 Ga0.47 As/HfO2 interface with
Al-doped HfO2 . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.3.1
7.3.2
7.4
Introduction . . . . . . . . . . . . . . . . . . . . . . 128
Samples and measurements . . . . . . . . . . . . . . 129
7.3.3 Results and discussion . . . . . . . . . . . . . . . . . 130
7.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 133
Conclusion of the chapter . . . . . . . . . . . . . . . . . . . 134
8 General conclusions and outlook
135
8.1 General conclusions . . . . . . . . . . . . . . . . . . . . . . . 135
CONTENTS
8.2
xi
Future outlook . . . . . . . . . . . . . . . . . . . . . . . . . 137
Bibliography
139
List of publications
153
List of abbreviations
aAC
ALD
cCB
CMOS
CV
DC
DB
epiEOT
ESR
FET
FinFET
GOI
GST
GV
HF
HRTEM
iIC
IV
IL
LF
MBE
MIS
ML
MOS
amorphous
alternating current
atomic layer deposition
crystalline
conduction band
complementary MOS
capacitance-voltage
dirrect current
dangling bond
epitaxial
equivalent oxide thickness
electron spin resonance
field-effect transistor
fin field-effect transistor
germanium-on-insulator
generalized simple thermal
conductance-voltage
high frequency
high-resolution transmission electron microscopy
intrinsic
integrated circuit
current-voltage
interlayer
low frequency
molecular beam epitaxy
metal insulator semiconductor
molecular layer
metal-oxide-semiconductor
xiii
xiv
MOSHEMT
MUFET
MS
nMOSFET
PECVD
pMOSFET
PV
SBH
SGOI
SOI
ST
TEM
UHV
VB
WF
List of abbreviations
MOS high electron mobility transistor
multigate field-effect transistor
metal-semiconductor junction
n-channel metal-oxide-semiconductor field-effect transitor
plasma-enhanced chemical vapor deposition
p-channel metal-oxide-semiconductor field-effect transitor
photovoltaic
Schottky barrier height
silicon germanium-on-insulator
silicon-on-insulator
simple thermal
transmission electron microscopy
ultra-high vacuum
valence band
work function
List of symbols
Symbol
Description
Unit
ε0
∆Bpp
∆Vhys
κ
λ
µ
µe
µh
σn σp
σs
σEf , σEd
permittivity of vacuum (8.85 × 10−14 F/cm)
peak-to-peak line width
voltage hysteresis observed on a CV curve
dielectric constant
Debye length
carrier mobility
electron mobility
hole mobility
electron/hole capture cross section
standard deviation of surface potential
spread on the activation energy for passivation
and dissociation, respectively
interface trap time constant
electron capture time constant
hole capture time constant
surface potential, in unit of kT/q
thermal velocity of electrons/holes
the difference between the Fermi level EF
and the midgap
magnet angle
electron barrier height
F/cm
G
V
τit
τn
τp
υs
ῡT
qφB
ϕB
Φe
Continued on Next Page. . .
xv
cm
cm2 /Vs
cm2 /Vs
cm2 /Vs
cm−2
eV
s
s
s
cm/s
eV
deg
eV
xvi
List of symbols
Symbol
Description
Unit
ΦB,n
Φm
Φms
Schottky barrier height
metal work function
work function difference between metal
and semiconductor
semiconductor work function
surface potential
angular frequency
area of gate
magnetic field
magnetic field modulation amplitude
accumulation capacitance
burried oxide capacitance
corrected capacitance
high frequency capacitance
interface trap capacitance
low frequency capacitance
measured capacitance
measured capacitance at accumulation
minimum capacitance of MOS structure
oxide layer capacitance
parallel capacitance
semiconductor space-charge layer capacitance
top oxide capacitance
thickness of high-κ dielectric layer
thickness of oxide layer
interface trap density
energy level of interface state
energy at the bottom of conduction band
reaction activation energies for passivation
of defects in H2 and defect-H dissociation,
respectively
Fermi level
metal Fermi level
semiconductor Fermi level
eV
eV
Φs
ψs
ω
A
B
Bm
CA
CBOX
CC
CHF
Cit
CLF
Cm
Cma
Cmin
Cox
Cp
Cs
CTOX
dhigh-κ
dox
Dit
E
EC
Ef , Ed
EF
EFm
EFs
Continued on Next Page. . .
eV
eV
V
rad/s
cm2
G
G
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
F/cm2
cm
cm
cm−2 eV−1
eV
eV
eV
eV
eV
eV
xvii
Symbol
Description
Unit
Eg
Ei
EV
fD
semiconductor bandgap
intrinsic Fermi level
energy at the top of valence band
a particular universal function of standard
deviation of surface potential σs
frequency (ω = 2πf)
peak frequency in a Gp /ω versus f plot
parallel and perpendicular components
of an axial g matrix
free electron g factor
corrected conductance
measured conductance
accumulation measured conductance
equivalent parallel conductance
drain current
Boltzmann constant (k=1.38065×10−23 J/K)
thermal voltage (0.0259 V at 300 K)
passivation rate constant
dissociation rate constant
the gate length of a transistor
intrinsic carrier concentration
acceptor concentration
effective density of states in CB and VB
donor concentration
number of interface traps
number of oxide trapped charge
pressure
power consumption of a device
interface point defects
elementary charge (1.6 × 1019 C)
oxide fixed charge
interface trapped charge
oxide trapped charge
interface trap resistance
eV
eV
eV
f
fp
gk , g⊥
g0
Gc
Gm
Gma
Gp
IDS
k
kT/q
kf
kd
L
ni
NA
NC , N V
ND
Nit
Not
p
P
Pb , Pb0 , Pb1
q
Qf
Qit
Qot
Rit
Continued on Next Page. . .
Hz
Hz
S/cm2
S/cm2
S/cm2
S/cm2
A
J/K
V
cm3 s−1
s−1
cm
cm−3
cm−3
cm−3
cm−3
cm−2
cm−2
bar
W
C
C/cm2
C/cm2
C/cm2
Ω/cm2
xviii
List of symbols
Symbol
Description
Unit
Rs
S
T
Tan
Tox
Vdc
VDS
VFB
Vbi
VG
VT
w
W
Yit
Ym (ω)
Z(ω)
series resistance
spin quantum number
temperature
annealing temperature
oxidation temperature
dirrect current voltage
applied source-drain voltage
flatband voltage
built-in potential
gate bias voltage
threshold voltage
width of depletion layer
width of the transistor channel
complex admittance of interface traps
complex admittance
complex impedance
Ω/cm2
K
K
K
V
V
V
V
V
V
cm
cm
Ω−1
Ω−1
Ω
List of Figures
1.1
2.1
2.2
(a) Picture of the first transistor, made of germanium, fabricated
by scientists from Bell Labs, USA in 1947, and (b) TEM image of
a 65-nm Ge-pMOSFET as available in 2008 [35]. . . . . . . . . .
5
Band diagrams of a p-type semiconductor surface region illustrating
the presence of interface traps, i.e., acceptor traps “A” and donor
traps “D”, inside the semiconduction bandgap at flatband (a), when
bending up (b), and when bending down (c). Electron-occupied
interface traps are indicated by the bold em dashes and unoccupied
traps by the light em dashes [Ref. 46, p.343]. . . . . . . . . . . . .
14
(a) Schematic cross section of a MOS capacitor illustrating a simple
equivalent circuit; (b) The equivalent measurement circuit including
an oxide capacitor Cox and a semiconductor capacitance Cs in
series; (c) Voltage signal applied to the gate of the MOS capacitor
to measure its differential capacitance or admittance as function of
the DC gate bias VG . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.3
Equivalent circuits of a MOS capacitor used for capacitance methods
at low frequency (a), and at high frequency (b) [Ref. 44, p.323,p.327]. 18
2.4
Room-temperature low (20 Hz) and high frequency (1 MHz) CV
curves as measured on an n-Si MOS capacitor with a 20-nm Al2 O3
insulator and a substrate doping concentration ND ∼1×1016 cm−3 .
18
Surface band diagrams of n-type (a), and p-type (b) semiconductors
showing how the position of the Fermi level at the silicon surface is
related to the band bending. The arrows pointing up denote negative
potential, whereas the arrows pointing down denote positive surface
potential ψs [Ref. 44, p.95]. . . . . . . . . . . . . . . . . . . . . . .
21
2.5
xix
xx
LIST OF FIGURES
2.6
2.7
2.8
2.9
Plots of ψs versus gate voltage VG behavior obtained from the
theoretical and experimental high frequency CV curves of a MOS
capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2
2
A plot of (1/CHF
− 1/Cox
) versus gate voltage VG of a MOS capacitor, used to extract the flatband voltage VF B and semiconductor
substrate’s doping concentration. . . . . . . . . . . . . . . . . . . .
26
The shift of the Fermi level in n- and p-type Si relative to the
interface trap energy distribution caused by cooling the sample from
300 K to 77 K. The Dit (E) schematically shows the interface trap
distribution associated with Pb -type defects at Si/SiO2 interfaces. .
28
Equivalent circuits used for extraction of Dit by using the
conductance method: (a) MOS capacitor with interface trap time
constant τit =Rit Cit , (b) simplified circuit of (a) with equivalent
parallel capacitance Cp and conductance Gp , and (c) the circuit
with the measured capacitance Cm and conductance Gm [Refs. 44, 49]. 31
2.10 (a) Equivalent circuit of a MOS capacitor in strong accumulation
including the series resistance Rs ; (b)simplified version of (a); (c)
simplified version of (b) used to extract values of Cox and Rs from
the admittance measured in strong accumulation; (d)Equivalent
circuit of the MOS capacitor with corrected capacitance Cc and
conductance Gc (Ref. [44], p.223). . . . . . . . . . . . . . . . . . .
33
2.11 A calculated Gp /ω versus frequency curve, for a fixed VG in
depletion, as typically obtained from measurement by correcting
for Cox using Eq. 2.55, where fp is the frequency corresponding
to the peak value of Gp /ω. The points at fp /5 and fp × 5 define
the width of the curve on the low and high frequency side of fp ,
respectively [44, Ref.]. . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.12 Plot of (Gp /ω)/(Gp /ω)fp versus the standard deviation of the
semiconductor surface potential σs . This curve is used to determine
σs from the width of a Gp /ω versus log(f) curve, which is shown
in Fig. 2.11, measured at a given gate bias. Determination of the
frequency fp corresponding to the peak of the measured curve and
either the low or high frequency side width will suffice in using this
curve. For the values of σs greater than 3.5, the peak of the Gp /ω
versus log(f) curve becomes so broad that a large error will be made
in determining fp [Ref. 44, p.216]. . . . . . . . . . . . . . . . . . .
37
2.13 Plot of the universal function fD (σs ) defined in Eq. 2.66 as a
function of σs ; fD is used in Eq. 2.65 to calculate the interface trap
density [Ref. 44, p.217]). . . . . . . . . . . . . . . . . . . . . . . .
37
LIST OF FIGURES
2.14 Plot of ξp = ωp τ as a function of σs calculated by solving Eq. 2.70;
ξp is used to calculate the interface trap response time from Eq. 2.71
[Ref. 44, p.217]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxi
38
3.1
Dependence of the effective mobility of electrons and holes in the
channel on the Si surface orientation and the channel direction [10]. 43
3.2
100-kHz CV curves measured at 300 K on (100)Si/SiO2 (a),
(110)Si/SiO2 (b) and (111)Si/SiO2 (c) n- and p-type samples. . .
47
3.3
Magnified plots of normalized 100 kHz CV curves measured at 300 K
on (100)Si/SiO2 (a), (110)Si/SiO2 (b), and (111)Si/SiO2 (c) nand p-type samples. Vertical arrows in the panels (b) and (c) mark
the capacitance peak associated with the interface trap response. .
48
(a) Multi-frequency CV curves and (b) conductance-to-angular
frequency ratio-voltage (G/ω-V), of as-oxidized p-Si(110)/SiO2
sample measured at 300 K. . . . . . . . . . . . . . . . . . . . . . .
49
The parallel conductance (Gp )-to-angular frequency ratio as a
function of frequency, with the metal bias (VG ) used as parameter,
of as-oxidized p- and n-Si(110)/SiO2 samples measured at 300 K,
(a) and (b), respectively. . . . . . . . . . . . . . . . . . . . . . . .
50
Dit (E) profiles of Si/SiO2 interfaces derived from high-low frequency
CV (solid symbols) and GV (open symbols) methods in Si/SiO2
samples fabricated on (100), (110), and (111) faces of Si. Results
for the as-oxidized samples (no H-passivation) and those subjected
to H2 passivation (30 min anneal in 1.1 atm H2 at 400 o C) are
shown for comparison. . . . . . . . . . . . . . . . . . . . . . . . .
51
Hole and electron trapping time constant (a), and the capture cross
section (b) in as-oxidized (110) (111) and (100)Si/SiO2 entities as
a function of energy in the Si band gap. . . . . . . . . . . . . . .
52
Normalized 100 kHz CV curves measured at 300 K (open symbols)
and 77 K (solid symbols) of n- and p-type (110), (111), and
(100)Si/SiO2 samples (a, b, c), where Cox is the oxide capacitance
per unit area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
The shift of the Fermi level in n- and p-type Si relative to the
interface trap energy distribution caused by sample cooling from
300 K to 77 K. The probed energy range is indicated by arrows. .
54
3.4
3.5
3.6
3.7
3.8
3.9
xxii
LIST OF FIGURES
3.10 K-band derivative-absorption ESR spectrum observed at T=4.2 K
with the applied magnetic field aligned along the normal to the
(110)Si/SiO2 interface, showing the signal with characteristic
signature of Pb0 defects. The spectrum was measured using an
incident microwave power ≈0.2 nW and field modulation amplitude
≈0.3 G. The label Si:P denotes a marker signal from a co-mounted
Si:P marker sample. . . . . . . . . . . . . . . . . . . . . . . . . . .
55
3.11 Electrically active defect density Nit of Si/SiO2 interfaces compared
to [Pb ] obtained from ESR. The data for the (110)Si/SiO2 interfaces
grown at Tox =698 o C and 1154 o C are also shown for comparison.
The solid line denotes the ratio Nit /[Pb(0) ] ≈2, expected from isolated
amphoteric centers. The bold arrow indicates the trend found in
(110)Si/SiO2 when the oxidation temperature is decreased. Vertical
arrows indicate the effect of hydrogen passivation treatment (1.1 atm;
400 o C; 30 min) on Nit for the same samples. . . . . . . . . . . .
57
4.1
Schematic diagram of a heterojunction solar cell . . . . . . . . . .
60
4.2
Multifrequency CV curves measured at 300 K (a) and 77 K (b) on a
Al/a-Si:H(p+ ; 20 nm)/i-a-Si:H(28 nm)/n-(100)Si sample. Arrows
indicate the direction of the voltage sweep. . . . . . . . . . . . . .
62
Multifrequency CV curves measured at 300 K (a) and 77 K (b) on a
Al/a-Si:H(p+ ; 20 nm)/i-a-Si:H(54 nm)/n-(100)Si sample. Arrows
indicate the direction of the voltage sweep. . . . . . . . . . . . . .
63
100 kHz CV curves measured at 77 K on n- and p-(100)Si/aSi:H(intrinsic, 54−56 nm)/a-Si:H(p+ , 20 nm)/Al structures.
Arrows indicate the direction of the voltage sweep. . . . . . . . . .
65
Plots of [(Cacc /C)2 − 1] as a function of gate bias for n- and p(100)Si/i-a-Si:H(54 nm)/a-Si:H(p+, 20 nm)/Al structures. VF B
is evaluated by extrapolation of the plots to zero ordinate value.
Arrows indicate the direction of the voltage sweep. . . . . . . . . .
65
4.3
4.4
4.5
LIST OF FIGURES
4.6
4.7
4.8
5.1
5.2
5.3
xxiii
K-band (≈20.5 GHz) ESR spectra measured at 6 K (Pµ =25 nW;
Bm =1.3 G) on a p-(100)Si/a-Si:H(intrinsic, 56 nm)/a-Si:H(p+ doped, 20 nm) sample with (a) the magnetic field B oriented along
the [100] normal n to the sample surface (magnet angle ϕB =0o ) and
(b) at angle ϕB =55o with n showing the splitting up of the Pb0 signal
in two parts with intensity ratio 1:3 for the latter field orientation.
The signal at g=1.99869 stems from a co-mounted calibrated Si:P
marker sample. The dotted curves represent optimized total spectra
simulations, obtained as sums of the individual simulated component
signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
100 kHz CV curves measured at 77 K on Al/a-Si:H(p+ ; 20 nm)/aSi:H(intrinsic)/n-(100)Si samples as a function of the physical
thickness of the intrinsic a-Si:H layer. Arrows indicate the direction
of the voltage sweep. . . . . . . . . . . . . . . . . . . . . . . . . . .
67
Flatband voltage deduced with the gate voltage swept from accumulation to inversion () and hysteresis data ( ) extracted
from 100 kHz CV curves, all measured at 77 K on Al/a-Si:H(p+ ;
20 nm)/i:a-Si:H/n-(100)Si samples as a function of the physical
thickness of the i:a-Si:H layer. The dashed curve illustrates the VF B
shift expected for the case of re-charging of ∼1.2×1017 traps/cm3
distributed uniformly across the i-a-Si:H film, while the solid line
represents a least square linear fit used to infer the interface fixed
charge density (slope). The inset shows the sample structure. . . .
68
(a) Fabrication process of a SGOI structure by the Ge condensation
technique and (b) Cross-section transmission electron micrograph
of a SGOI wafer with 93 % Ge fabricated by the Ge condensation
technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
Ge content dependence of the negative charge density Nit extracted
from CV curve shifts at 77 K, and the density of GePb1 defects
measured by ESR. The GePb1 data, except for x=75 %) were taken
from Refs. [103, 104]. . . . . . . . . . . . . . . . . . . . . . . . .
77
Multi-frequency CV curves observed at T=77 K on the as-prepared
(100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2 entity. Arrows indicate the
direction of the voltage sweep. The resistance of the SiGe layer as
function of frequency and gate voltage is shown in the inset. . . .
78
xxiv
LIST OF FIGURES
5.4
(a) 100 kHz capacitance-voltage curves observed at T=77 K on an asprepared (100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2 entity and after
passivation at Tan =96, 300 or 375 o C for 36 min. Arrows indicate
the direction of the voltage sweep. The shift of the CV curves to
the left indicates a reduction of interface defects after annealing
in hydrogen; (b) First derivative X-band ESR spectra observed on
an as-prepared (top trace) (100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2
entity and after treatment in H2 at 375 o C (B//[100] interface
normal). The signal at g=1.99868 stems from a co-mounted Si:P
marker. Also shown is a ball-and-stick picture of the proposed
atomic model of the interfacial GePb1 defect. . . . . . . . . . . . .
79
5.5
Relative shift of the threshold voltage ∆VT (Tan )/∆VT,in =Nit (Tan )/Nit,in
and relative GePb1 density [GePb1 (Tan )]/[GePb1,in ] (crosses) vs.
Tan of isochronal heating in 1.05 atm H2 (solid squares, crosses)
and vacuum (open symbols). . . . . . . . . . . . . . . . . . . . . . 81
5.6
Temperature dependence of the H2 concentration at the interface,
calculated using Eq. 5.9 [cf. Ref. 116] for pH2 (ambient)=1.05 atm.
84
5.7
Relative threshold voltage shift ∆VT (Tan )/∆VT,in =Nit (Tan )/Nit,in
under isochronal (a) and isothermal (b) (3 cycles) heating in H2
(1.05 atm). The error bars for each data point represent the spread
over five to ten measurements. The solid curves represent the
optimal fits of the GST model (using the kinetics parameters listed
in table 5.1) taking into account that an amount of ∼20 % of charge
traps does not take part in the passivation. The dotted curve in panel
(a) is a fit for the ST model using the same parameter values listed
in table 5.1, but with spread σEf =0 (single valued Ef ), exposing the
inadequacy of such description. The dashed curve, describing reality,
represents the fitting of the full interaction GST model taking into
account the simultaneous action of passivation and dissociation. .
85
Recovery of GePb1 defects under isochronal dissociation by vacuum
annealing for 34 min (a) and isothermal dissociation at four
temperatures (b). All experimental data were normalized to meet
the starting condition that [GePb1 ]=0. The error bars for each
data point represent the spread over five to ten measurements. The
solid curves present the optimized self consistent fittings of the GST
model, from which the inferred parameters listed in Table 5.1 are
obtained. The dotted curve in panel (a) corresponds to a fitting
for the ST model using the same parameter values as tabulated in
table 5.1, but with spread σEd =0 (single valued Ed ), exposing the
inadequacy of the ST description. . . . . . . . . . . . . . . . . . .
86
5.8
LIST OF FIGURES
5.9
xxv
Gaussian distributions of activation energies for SiPb defects
at the standard (111)Si/SiO2 , interface and for GePb1 at the
(100 )Si0 .75 Ge0 .25 /SiO2 interface. The (strongly enhanced) overlap
between the two distributions in the bottom part directly illustrates
the ineffectiveness in attainable level of passivation for the Ge DB
defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
5.10 Isochronal behavior of [GePb1 ]/[GePb1 ]in starting from the condition
[GePb1 ](t=0)=[GePb1 ]in for annealing in 1.05 atm H2 for 36 min
under simultaneous action of passivation and dissociation (full
interaction case [105]) as calculated using the GePb1 data listed
in Table 5.1. The dashed curve was calculated using the singlevalued activation energy case, i.e., with spreads σEf =σEd =0. The
dotted curve was calculated using the same parameters for GePb1
as tabulated in Table 5.1, except for the spreads where values of
σEf =0.06 eV and σEd =0.08 eV previously found for the SiPb defect
in (111)Si/SiO2 are used. The calculated isothermal dissociation
behavior (Eq. 5.7) in vacuum is also shown for comparison (the
dash-dotted curve). Notice that the calculated data here have not
been renormalized for a ∼20 % immune part of defects. . . . . . .
93
5.11 Relative level (number) of non-passivated GePb1 defects attained as
function of annealing temperature for annealing time approaching
infinity and using pH2 =1.05 atm. . . . . . . . . . . . . . . . . . .
94
6.1
High-resolution cross-sectional transmission electron microscopy
(TEM) image of a Ge/Si/SiOx /Hf O2 stack [Ref. 123]. . . . . . . 103
6.2
300-K multi-frequency CV characteristics of p-(100)Ge/Si/SiO2
/HfO2 /Au entities with 3–6 expitaxially grown Si-MLs, deposited
using silcore at 350 o C (left), and silane at 500 o C (right). . . . . 104
6.3
Density of interface traps Dit extracted by the high-low frequency
CV and GV methods, measured on Ge/Si/SiO2 /HfO2 samples at
300 K. The calculations were done at VG values that correspond to
CHF /Cox ≈ 0.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.4
200-K multi-frequency CV curves and Gp /ω-versus-frequency of
p-(100)Ge/Si/SiO2 /HfO2 /Au entity with 4 Si MLs, deposited from
silcore at 350 o C (a and b respectively), and deposited from silane
at 500 o C (c and d respectively). . . . . . . . . . . . . . . . . . . . 106
6.5
Normalized 1-MHz CV curves measured at 300 K (open symbols)
and 77 K (solid symbols) of p-(100)Ge/Si/SiO2 /HfO2 /Au entity
with 4 Si MLs deposited from Silcore at 350 o C. . . . . . . . . . . 107
xxvi
LIST OF FIGURES
6.6
Comparison of Dit values (cf. Fig. 6.3) with the number of traps
∆Nit between the two Fermi levels at 300 K and 77 K extracted by
the shift of the flatband voltage ∆VF B when cooling down to 77 K,
for the samples deposited from Silcore at 350 o C. . . . . . . . . . . 108
6.7
300-K and 77-K CV curves measured on both p-type (left) and
n-type (right) (100)Ge/GeO2 /10-nm HfO2 /Au capacitors. . . . . 109
6.8
K-band derivative-absorption ESR spectrum observed at T=4.2 K
on (100)Ge/Si/SiO2 /HfO2 structures with the applied magnetic
field aligned parallel to the [111] direction. The label Si:P denotes
a marker signal stemming from a co-mounted Si:P marker sample. 110
6.9
(1/C2 ) against gate voltage for metal contacts on (a) n-(111)Ge
and (b) n-(100)Ge substrates measured at 77 K. . . . . . . . . . . 115
6.10 Schottky barrier heights of metal contacts on n-(111)Ge and
n-(100)Ge substrates deduced from CV measurements at 77 K.
The Schottky barrier for metal contacts on n-type Ge is almost
independent on the metal WF. . . . . . . . . . . . . . . . . . . . . 115
6.11 (1/C2 ) against applied voltage for metal contacts on n-(111)Ge
with a few monolayers of (a) amorphous Ge3 N4 and (b) single
crystalline Ge3 N4 inserted between the Ge substrate and the metal
contact, measured at 77 K. The data were corrected for a series
capacitance of the Ge3 N4 layer (Eq. 6.6) to obtain a linear behavior.116
6.12 Schottky barrier heights of metal contacts on Ge3 N4 /n-type Ge with
a few monolayers of amorphous or crystalline Ge3 N4 , determined
by low temperature CV measurements. Metals with increasing WF
were used, including Al, Cr, Co, Au, and Pt. . . . . . . . . . . . . 116
7.1
(a) Multi-frequency CVs and (b) Gc /ω-V characteristics of a pSi(100)/TaSiOx /Au capacitor measured at 300 K. . . . . . . . . . 121
7.2
Distribution of interface trap density below Si midgap at the p(100)Si/20-nm TaSiOx interface extracted by the high-low frequency
CV and GV methods. . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.3
100-kHz CV curves of a p-(100)Si/20-nm TaSiOx /Au MOS
capacitor measured at 300 K (a) and 77 K (b) using a bi-directional
voltage sweep over the range from -3 to +3 V (solid lines) and
from -7 to +7 V (dashed lines). Arrows indicate the direction of
the voltage sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LIST OF FIGURES
xxvii
7.4
(a) 300 K multi-frequency bi-directional CV traces obtained on an
n-In0.53 Ga0.47 As/10-nm TaSiOx /Au capacitor, where the arrows
indicate directions in the sequence of the applied voltage and
frequency sweeps; (b) Dit (E) across the In0.53 Ga0.47 As bandgap
extracted by the high-low frequency CV method on samples with
either a 10-nm or 20-nm thick silicate layer. The energy positions
in the gap have been determined using the Berglund integral method
(see paragraph 2.3.2.) . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.5
100-kHz CV curves measured at 300 K (solid symbols) and 77 K
(open symbols) on n-(100)In0.53 Ga0.47 As/TaSiOx /Au capacitors
with 10-nm (a) and 20-nm (b) thick silicate layer for a voltage
sweep from -2 to +2 V and from -5 to +5 V, respectively. Arrows
indicate the direction of the voltage sweep. . . . . . . . . . . . . . 125
7.6
(a) 300 K multi-frequency bi-directional CV traces obtained on
n-(100)InP/10-nm TaSiOx /Au. Arrows indicate directions in
the sequence of the applied voltage and frequency sweeps. (b)
Energy distribution of interface trap, Dit (E), across the InP
bandgap extracted by the high-low frequency CV method on n(100)InP/TaSiOx interfaces with a 10-nm, 15-nm or 20-nm thick
silicate layer. The energy positions in the gap have been determined
using the Berglund integral method (see paragraph 2.3.2). . . . . . 126
7.7
100-kHz CV curves of n-(100)InP/20-nm TaSiOx /Au measured at
300 K (solid line) and 77 K (dashed line) measured over a voltage
sweep from -5 to +5 V and back. Arrows indicate the direction of
the voltage sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.8
Structures of studied In0.53 Ga0.47 As/Hf O2 MOS capacitors, where
the oxide layers were Al-doped with the aim to passivate the
semiconductor/oxide interfaces. . . . . . . . . . . . . . . . . . . . 130
7.9
Multi-frequency CV curves measured at 300 K on a p-(100)In0.53 Ga0.47 As
/Al:HfO2 /Ni capacitor. Arrows indicate the direction of the
voltage sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.10 Multi-frequency CV curves measured at 4 different temperatures
in the range 77–300 K on an n-(100)In0.53 Ga0.47 As/Al:HfO2 /Ni
capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.11 Energy distribution of the interface trap density Dit (E) across
the In0.53 Ga0.47 As bandgap at the n-(100)In0.53 Ga0.47 As/Hf O2
interface extracted by the CV and GV methods. . . . . . . . . . . 132
xxviii
LIST OF FIGURES
7.12 100-kHz CV curves measured at 300 K (solid line) and 77 K (dashed
line) on both p- and n-(100)In0.53 Ga0.47 As/Al:HfO2 /Ni capacitors
for voltage sweeps from -2.5 to +2.5 V and back. Arrows indicate
the direction of the voltage sweep. . . . . . . . . . . . . . . . . . . 133
List of Tables
1.1
Bulk properties at 300 K of several high-mobility semiconductors in
comparison with standard Si. . . . . . . . . . . . . . . . . . . . .
4
3.1
Density of Pb0 centers, Dit peak values, and (Nit )1/2 , the integral
of Dit obtained from GV measurements over the upper (n-type)
and lower (p-type) half of the Si bandgap at the Si/SiO2 interface
obtained from the present work. . . . . . . . . . . . . . . . . . . .
54
Inferred parameters within the GST model for the kinetics of thermal
passivation in H2 and dissociation activation in vacuum of GePb1
(GePb1 -H) defects at (100)SiGe/SiO2 interfaces, in comparison
with Si Pb defects at standard thermal (111)Si/SiO2 interfaces
(Tox ∼ 970 o C)) and Si Pb1 defects at (100)Si/SiO2 interfaces. . .
88
5.1
6.1
The barrier height of metal contacts on n-type (111)Ge without
and with 1.2 nm of amorphous and crystalline Ge3 N4 , measured
by the low temperature CV technique. The barrier height for Al
contacts with amorphous Ge3 N4 interlayers was measured by low
temperature IV experiments, giving 0.09±0.05 eV. The metal WFs
for different metals are taken from Ref. [143]. . . . . . . . . . . . 117
7.1
Comparison of the interface properties of 20-nm TaSiOx with
different semiconductor substrates, including Si, InP, and In0.53 Ga0.47 As.
The hysteresis was extracted from 100-kHz CV curves for a gate
voltage sweep from -5 to +5 V at Tm =300 K. The semiconductor
bandgaps are included for comparison. . . . . . . . . . . . . . . . . 128
xxix
Chapter 1
Introduction
1.1
Extending Moore’s Law
Over about the second half of the last century, the electronics industry
based on semiconductor devices has revolutionized the world. Thus far,
most of the conventional electronic devices have been fabricated on Si
substrates with the (100) surface crystalline orientation because of its high
electron mobility compared to other Si orientations, and the inherently
lowest interface trap (defect) density at the interface in the (100)Si/SiO2
entity –the most successful and basic ingredient in semiconductor devices.
This success story owns a great deal to the availability of Si’s natural
insulator, SiO2 , of great electrical quality and thermodynamic stability. The
thermally grown Si/SiO2 entity, in combination with hydrogen passivation,
represents a superb Si/insulator structure of high stability and excellent
interface properties. For the last four decades, the dimensions of MOSFET
devices, the majority of semiconductor devices, have been scaled down and,
accordingly, the complexity of the integrated circuits has increased according
to Moore’s law formulated in the 1960s [1, 2]. This states that the number
of devices on an integrated circuit increases exponentially, doubling over
every 2–3 year period. In the mean time, the minimum feature size in a
transistor has decreased exponentially with year.
However, as a result of the ever advancing MOSFET scaling, currently,
major hurdles (physical limits) are encountered including quantum tunneling
1
2
Chapter 1: Introduction
increasing gate leakage and oxide breakdown. These effects have to be
reduced in making faster and smaller integrated circuits. Also, to meet
the future technological requirements, much effort has been expended on
increasing the capabilities of MOSFETs. Both new materials (such as oxides
of higher dielectric constant κ, high mobility semiconductors) and new
designs have been introduced to maintain device scaling.
First of all, based on the highly successful Si technology, new Si-based
structures such as hybrid structures [3, 4], vertical MOSFET [5], multi-gate
MOSFET (i.e., MUGFET or FinFET) [6, 7], and quantum wells [8, 9]
have been introduced to keep on track with Moore’s law. This trend has
renewed the interest in the application of alternative surface orientations
such as (111) and (110)Si to optimize the performance of electrical devices.
More attention has been paid to (110)Si because this orientation shows a
much enhanced hole mobility, more than doubled, as compared to the (100)
orientation [10].
However, when introducing multi-gates to a Si MOSFET, one cannot get
homogenous thermal SiO2 of uniform thickness over the Si fin because the
thermal oxidation growth rate differs for differently oriented-Si surfaces.
To solve the problem, high-κ oxides such as Al2 O3 , HfO2 , and TaSiOx
have been introduced to replace the conventional thermal SiO2 , because
these oxides can be quite easily deposited by the atomic layer deposition
(ALD) technique. Compared to the SiO2 dielectric (κ=3.9), using high-κ
oxide dielectrics also allows for realizing the same areal capacitance with
a thicker dielectric layer, thus enabling reduction of leakage currents and
oxide breakdown of MOSFET devices when scaling down. It has been
reported that leakage current through HfO2 dielectric films are several
orders of magnitude lower than for SiO2 films with the same equivalent
oxide thickness, in the range of 0.9–2 nm. The equivalent oxide thickness
(EOT) is defined as
EOT = dhigh−κ
κSiO2
κhigh−κ
(1.1)
where dhigh−κ is the thickness of the high-κ layer, and κSiO2 and κhigh−κ the
dielectric constant of SiO2 and the high-κ layer, respectively. In 2007, Intel
introduced its novel 45-nm HfO2 -based transistor technology [11], herewith
establishing a success of high-κ research.
However, the presence of a high-κ material gate dielectric was found to reduce
HIGH MOBILITY SEMICONDUCTORS
3
the silicon mobility [12–14]. We then need high mobility semiconductors
to compensate for the loss of mobility caused by high-κ insulators.
High-mobility channel materials, such as Ge, Si1−x Gex , and compound
semiconductors such as InSb, InAs, GaAs, GaN, and Inx Ga1−x As are now
being intensively considered to maintain the performance requirements: (a)
maintain high drive currents to enable high speed, and (b) reduce power
consumption, which is directly related to the higher mobilities of these
materials than that of Si (cf. Table 1.1). The drive current, Id , of a
MOSFET in the saturation region is directly proportional to the carrier
mobility µ through the following equation [15, p120] [16, p306]
Id (saturation) =
µCox W
(Vgs − VT )2 ,
2 L
(1.2)
where W and L are the gate width and gate length of the transistor, Vgs
the gate voltage and VT the threshold voltage of the device. In turn, the
power consumption, P, behaves as
2
P ∼ VSD,sat
= (Vgs − VT )2 .
1.2
(1.3)
High mobility semiconductors
As mentioned in the previous section, high mobility semiconductors are
required to compensate for the loss of mobility caused by high-κ insulators.
In fact, enhancement of carrier mobility has already been realized by means
of introduction of strained Si channels [17–19] or change in Si channel
direction [20]. However, new high mobility semiconductors such as SiGe,
Ge, and III-V compounds offer even higher mobility over strained Si and
(110)Si. Bulk properties at 300 K of several semiconductors including Si,
SiGe, Ge and some III-V materials are compared in Table 1.1.
1.2.1
SiGe alloy semiconductor
Silicon-germanium (SiGe) materials and devices have been investigated for
more than 50 years [25–27]; Due to its large hole mobility and adjustable
band gap, SiGe is a good candidate for application as high mobility channel
material in novel complementary MOS devices [28, 29]. To this day, SiGe is
Chapter 1: Introduction
4
µh
(eV)
Eg
(cm−3 )
Nc
(cm−3 )
Nv
(cm−3 )
ni
11.9
κ
[21]
Ref.
Table 1.1: Bulk properties at 300 K of several high-mobility semiconductors in comparison with standard Si.
µe
(cm2 /V.s)
1.45×1010
Materials
(cm2 /V.s)
1.04×1019
[21]
2.8×1019
14.9
[21]
1.12
1.4 × 1013
16
[21]
430
∼ 8 × 1018
2.4×1013
13.1
[21]
1600
∼ 2.8 × 1019
6×1018
1.8×106
15.7
[21]
(100)Si
0.80
1.04×1019
7×1018
1.5×1012
17.7
[21, 23, 24]
[21, 22]
750
0.66
4.7×1017
18×1018
2×1016
13.9
[21]
11.9
1900
1.42
0.21×1018
7.3×1018
1.3×107
14.8
[21, 24]
1.45×1010
3900
400
0.73
4.2×1016
11×1018
1×1015
12.4
1.04×1019
Ge
9200
1400
0.17
5.7×1017
6.6×1018
6.3×1011
2.8×1019
GaAs
7700
850
1.35
8.7×1016
7.7×1018
1.12
GaSb
77000
200
0.36
2.1×1017
900
InSb
5000
500
0.75
∼1250
InP
40000
300
(110)Si
InAs
7800
Si0.25 Ge0.75
In0.53 Ga0.47 As
1.2 High mobility semiconductors
5
still a boiling topic, drawing the attention of many research groups all over
the world. Silicon Germanium-on-Insulator (SGOI) is a new technology
combining the benefits of two advanced technologies, Silicon-on-Insulator
(SOI) and SiGe, and provides the possibility of SiGe integration on Si, using
Si, SiGe and SOI technologies [30].
1.2.2
Germanium
N/IOFF performance for 65nm Ge pMOSFET and novel Si passivation
Since the invention of the transistor made of Ge (cf. Fig. 1.1(a)), in
scheme for1947
improved
EOT scalability
[31], germanium has been investigated for a long time for electronic
application. Ge was the key substrate material used during early days
1
1,2,5
1,2,5
1,2,6
, G. Hellings
, K.
Martens
Eneman
ard1,2, B. De Jaeger1, F.E.ofLeys
the semiconductor
devices.
However,
because, G.
of the
low quality,D.P.
of the
1
7
1oxide –unprotected GeO
1
1 thermally unstable
Ge
native
is
chemically
and
2
R. Loo , J.C. Lin , D. Shamiryan , T. Vandeweyer , G. Winderickx , E. Vrancken1, C.H.
1
1 passivation of
GeO2 provides
insufficient
the Ge Heyns
surface 1,4
[32, 33]– it
Yu7, K. De Meyer1,2, M.and
Caymax
, L. Pantisano
, M. Meuris1, M.M.
was later completely overruled by silicon [34]. However, because of its
2 hole and electron mobility germanium3has over recent times regained
75, B-3001 Leuven, Belgium,high
ESAT-INSYS, K.U. Leuven, Belgium, Intel assignee to IMEC, 4MTM,
5
7 future faster MOSFET devices.
technological
interest
for application
IWT, 6FWO,
Brussels,
Belgium, in
TSMC
K.U. Leuven, Belgium,
At
low
electric
field,
the
Ge
electron
mobility
µe =3900 cm2 V−1 s−1 and
Email: Jerome.Mitard@imec.be
2
−1
−1
hole mobility µh =1900 cm V s are respectively about three and four
times larger thanmethods
that of given
standard
(100)Si
[21,
34].
In addition,method
Ge hascoupled
a
in [3,4].
The
full
conductance
Abstract
relativelyofsmall bandgap,
Eg (Ge)=0.67
eV at 300
K (cf.
Eg (Si)=1.12
eV), the
with a broad
temperature
range
(80-300K)
enables
Ge pFET with a record performance
Ioff,s= 37nA/µm @Vdd= -1V. These
ntified and understood with respect to
s, minimizing series resistance and gate
etter control of Ge in-diffusion using a
-silicon passivation process allows
e-pFET with increased performance.
interface traps density extraction (DIT) all across the Ge
bandgap [5].
Hard
mask
Introduction
NiGe
NiGe
TiN/
devices have shown similar intrinsic
TaN
mobility compared to pMOS Si-(100)
Ge subtrate
velocity at low VDS suggest Ge devices
on Si
n for future high performance MOS
(a)
(b) Ge-pMOSFET
Fig. 1 TEM picture of 65nm
er, no results are available for Geow EOT and sub-70nm gate Figure
length.1.1:
In (a) Picture of the first transistor, made of germanium, fabricated
I -IOFF performance
strate high performance p-channel
Ge from Bell Labs, USARecord
by scientists
in 1947,ON
and (b) TEM image of a 65-nm
Good 65nm Ge pFET is shown in the TEM picture (fig. 1). IV
wo essential features.
Ge-pMOSFET as available in 2008 [35].
and CV plots of Fig. 2 and 3 demonstrate excellent
reproducibility, low gate leakage, small EOT (1.3nm) and a
abrication and Extraction
good interface passivation (weak frequency dispersion both in
re summarized in the table below:
accumulation and inversion regime). Hysteresis in electrical
mpatible process flow for Ge devices.
characteristics is also under control (ΔVTH, STATIC ~ 10mV).
Mobility for Germanium devices is more than 2 times Si and
roughly Lg-independent (fig. 4) suggesting: a) a good short
channel control and b) a weak scattering with defects close to
S/D [6]. Finally, a dramatic improvement is achieved for IONIOFF (fig. 5) leading to a record of performance for Ge-pFET:
ION = 478µA/µm and IOFF,SOURCE = 37nA/µm at VDD = -1V
dd
/3
Ge bulk [10]
-5
10
Vdd = -1V
6
Chapter 1: Introduction
that enables reducing power consumption of the devices by reducing the
power supply voltage. Up to now, using pure Ge has been a compromise as
the leakage current is much greater than in Si; however, by making use of
the germanium-on-insulator (GOI) structure, this leakage can be reduced
and greater control of the channel can be achieved [35].
High-κ dielectrics provide a way to avoid the problem with the unstable
Ge native oxide, GeO2 . The volatility of Ge surface oxides enables easy
surface cleaning in preparation for deposition of high-κ dielectrics. Hafnium
dioxide, HfO2 , is a leading candidate for high-κ dielectric devices, due to
its higher dielectric constant and better thermal stability relative to other
candidate materials. p-channel HfO2 /Ge MOSFETs with EOT down to
0.85 nm, exhibiting higher hole mobility than HfO2 /Si control samples,
have been reported [35, 36]. The density of interface traps (Dit ) is higher
for Si-passivated devices than for GeO2 -passivated devices, but improved
process control is achieved with the Si-passivated devices. The Dit (E) profile
is asymmetric in the Ge band gap with a higher trap density, in the order
of 1013 cm−2 eV−1 , near the Ge conduction band (CB) edge and a lower
trap density, in the order of 1012 cm−2 eV−1 , near the Ge valence band (VB)
edge [37].
Up to date, all Ge surface passivating methods which operate benificially
for p-channel MOSFETs (nMOSFETs) provide only minor improvement for
n-channel MOSFETs (nMOSFETs) so that channel mobility and ON-state
currents in these devices remain low.
1.2.3
III-V compound semiconductors
While Ge, with excellent hole mobility, offers great potential for pMOSFET
application, III-V channel materials are expected to replace Si for nMOSFET
components due to their very high electron mobility. For example, as can
be seen in Table 1.1, the electron mobility of GaAs is five times lager
than that of Si. It has already been demonstrated that ultra-high mobility
compound semiconductor-based MOSFETs and quantum well FETs (e.g.,
In0.7 Ga0.3 As and InSb) [38, 39] operate at low VSD with high performance.
Furthermore, In0.7 Ga0.3 As MOSHEMTs with an InP barrier stack have been
demonstrated with 3.5 times higher effective carrier velocity than strained-Si
n-MOSFETs [40]. In addition, another advantage of III-V semiconductors
COMMON ISSUES WITH INTERFACE TRAPS
7
is their direct bandgap raising much interest for optical and photonic device
application.
However, the most important issue in III-V technology still concerns the
semiconductor surface passivation. Surface passivation of III-V materials
has been extensively investigated in the past few decades and it is still a
very active topic especially regarding MOSFET structures.
1.3
Common issues with interface traps
The quality of semiconductor/insulator interfaces plays a key role in the
performance of electronic devices, including MOSFETs. Interface traps
are naturally incorporated at a semiconductor/insulator interface when the
interface is formed and these traps have a profound influence on the electronic
behavior of devices. Interface traps are well known to cause degradation of
various MOSFET performance parameters such as transconductance, carrier
mobility, and threshold voltage, and generally reduce the device reliability
and lifetime.
For these reasons, reduction of interface trap density represents a critical
issue in the fabrication of integrated circuits. The semiconductor industry
is permanently searching for techniques to minimize the density of interface
traps in devices. Therefore, a method for monitoring the interface trap
density is required to evaluate the efficiency of trap elimination. Among the
numerous experimental methods applied to infer interface trap properties,
the ac conductance (GV) method allows the determination of the most
complete set of parameters, including the trap density, energy distribution,
and capture cross-section.
In semiconductor device technology, silicon has so far played an all dominant
role as semiconductor material. This is due to a combination of both its
physical properties and its high natural abundance making it therefore
inexpensive. Another main factor in this Si success story is that the
natural oxide of silicon, SiO2 , forms an excellent insulator between the
gate electrode and the channel in a MOSFET. However, the basic Si/SiO2
entity, generally thermally grown, suffers from the presence of a substantial
amount of intrinsic interface defects, with a defect density in the order
of 1×1012 cm−2 . The defects are inherently incorporated to account for
8
Chapter 1: Introduction
interface mismatch, and in that “intrinsic” state, the Si/SiO2 would be
plainly useless for device application. Fortunately, the interface trap density
can be efficiently reduced to a level below 1×1010 cm−2 [41] by hydrogen
passivation, generally obtained through annealing in forming gas (N2 +H2 ).
In addition, the excellent insulating properties of SiO2 can also be exploited
as a mask during device fabrication [16, 42, 43]. Based on decades of Si/SiO2
interface studies, the intrinsic coordination defects, in particular Si dangling
bond (DB) point defects, have emerged as an archetypal source of interface
traps which have a devastating effect on the performance and reliability of
electronic devices. As a result, the DB model is widely employed nowadays
to explain the traps observed at interfaces of semiconductors other than Si,
such as Ge and III-V. However, still very little is known about the atomic
nature of interface traps at the latter “new” interfaces.
Using novel materials such as high-κ oxide in combination with highmobility semiconductors enables the fabrication of field effect transistors
with promising device performances. Yet, there are still shortcomings that
need to be improved. One of the challenges in fabricating high quality
devices is to improve the interfacial layer between the gate oxides and the
semiconductor substrate. Defects and imperfections at the interface of
high-κ films on silicon or other semiconductors, as well as charge trapping
within the oxide layer affect capacitance-voltage (CV) characteristics of
devices.
It follows that CV and GV methods using MOS structure is one of the
simplest ways to investigate the interfaces. The results obtained by these
methods on electrically active traps can be quantitatively compared to the
densities of defects observed at the interface by a physical technique, such
as electron spin resonance (ESR), sensitive to and with the ability to unveil
the atomic nature of point defects, the main source of interface traps. Such
combination of techniques provides potential for atomic identification of the
defects responsible for electron trapping at the interface, an ultimate goal
in interface characterization.
Finally, there is one more remark: In setting the background of the current
thesis, one may notice that the introduction so far presented is mainly
focused on the scaling issues involved with the Si CMOS based technology.
However, as will become clear later, part of the research carried out deals
with Si-based solar cell properties, more specifically, the analysis of the cSi/a-Si interface in solar cells. But, obviously, these ‘fields’ share overlapping
OBJECTIVES OF THE THESIS
9
issues: A common aspect of Si CMOS and Si solar cells is the requirement
of a very high level of Si interface passivation, which in the former case
enables one to realize a higher concentration of carriers with high mobility
in the transport channel, and in the later case, a low carrier recombination
rate. A fundamental difference, though, between the two cases is that with
respect to Si CMOS, passivation must be achieved by applying an insulator
layer onto the semiconductor channel whereas in the case of solar cells the
need to collect the irradiation-induced current mandates the application
of a semiconducting passivating layer. Nevertheless, the atomic origin
of the basic detrimental imperfections, being associated with Si (crystal)
dangling bonds, remains the same and, therefore, can be characterized using
the same metrology approaches, that is, combining ESR with electrical
characterization, as will be demonstrated in the present work.
1.4
Objectives of the thesis
From the brief reviews presented above, we may perceive that the proper
characterization of high-mobility semiconductor/oxide-based insulator
interfaces emerges as one of the hottest topics in semiconductor device
physics. The obtained results will provide useful information in support to
the replacement of the traditional silicon technology by a novel-generation
IC-technology. That will allow more transistors to be packed on a single
chip without affecting the chip manufacturing cost. In particular, realization
of high-mobility channels required for future generations of semiconductor
devices critically depends on our ability to eliminate and/or passivate the
interface traps. Obviously then, the understanding of the atomic nature
of interface traps, the mechanisms of their generation, factors influencing
their density as well as passivation/depassivation properties are of crucial
importance both from the fundamental point of view and from the device
application perspective.
In this study, the electron trap energy distribution at interfaces between
semiconductor crystals and amorphous, polycrystalline, or epitaxial oxide
insulators will be addressed to evaluate the influence of the lattice matching,
strain, and other factors on their occurring density. In one part, the
role of the mismatch-induced DB defects is investigated for substrates with
different crystallographic orientations. In another part, the behavior of traps
associated with epitaxial and amorphous interlayers will be compared for
10
Chapter 1: Introduction
different semiconductor crystals (Si, SiGe, InGaAs, InP) using a combination
of electrical methods and electron spin resonance.
There is one more remark that may be at place. As outlined, the current
thesis deals with the investigation of charges and (interface) traps in
semiconductor/insulator heterostructures almost exclusively carried out
by means of electrical probing methods such as CV, GV and current voltage
(IV). Generally, these represent the prime preferred and standard methods
for analysing charge traps, their recombination behavior, and associated
defect energy levels in semiconductor/insulator stacks; In fact, CV functions
as a basic, very sensitive standard and routinely applied tool for the study
of electrical properties of these structures. But these methods, sensing the
charge property of carriers, inherently lack atomic identification power of
the defects at the origin of traps, requiring other approaches.
Partly for this reason, in some specific cases, if enabling the approach,
the electrical probing has been complemented with conventional ESR
investigation, sensing the spin (magnetic moment) property of the defect
(or carrier). Sensing the spin provide access to the carrier (spin) wave
function (orbital), thus making conventional ESR the technique of choice
when it comes to identification of (point) defects on atomic scale. This puts
the ESR technique in a unique position on this matter, although it is in
absolute terms (much) less sensitive than the electrical techniques: The ESR
sensitivity for typical defect systems encountered in semiconductor/insulator
structures (e.g., Si DBs) is ∼(2–5)×1011 defects (of spin S=1/2) for
optimized low-temperature spectroscopy within acceptable signal averaging
time. Additional unique merits include that the conventional ESR technique
is highly selective in discriminating between different kinds of defects (spin
systems) individually, and furthermore, is an absolute method, in that it
may reliably determine absolute densities of occurring defects, thus enabling
the much wanted quantification of occurring defect systems individually.
This thesis presents the main results obtained by the CV and GV electrical
methods on interface trap properties at the interfaces of Si, Si1−x Gex , Ge
and III-V semiconductors with the most widely applied oxide insulators, such
as SiO2 , Al2 O3 , HfO2 , and TaSiOx . The study is carried out as a function
of substrate surface pre-treatment and crystallographic orientation. These
oxide insulators were extensively characterized in the past in combination
with the (100)Si surface, which allows a meaningful comparison when
combined with other surfaces and materials.
OBJECTIVES OF THE THESIS
11
The thesis is organized as comprised of 8 chapters:
After some introduction in Chapter 1, Chapter 2 continues with
overviewing the basics of MOS physics and the characterization of interface
traps at semiconductor/insulator interfaces by means of CV and GV
methods.
In chapter 3, traps at the (110)Si/SiO2 interface are investigated by
combining electrical methods with electron spin resonance measurements,
and the results are compared to those of the well studied (100) and
(111)Si/SiO2 interfaces. The results show that Pb(0) defects are responsible
for most of the interface traps observed in (110)Si/SiO2 . In addition, By
comparing CV curves measured at 300 K and 77 K for both n- and p-type
samples, the Pb(0) defects are confirmed to be amphoteric. This chapter
also suggests that reducing processing temperatures may result in a lower
density of electrically active interface traps.
Chapter 4 addresses the correlation between interface traps and paramagnetic defects in c-(100)Si/a-Si:H heterojunctions. In this chapter,
low-temperature (77 K) CV measurements are proposed as a technique
to quantify the densities of traps in c-Si/a-Si:H heterojunction solar cell
structures. By comparing the inferred trap densities to the results of ESR
spectroscopy we found that the DBs of silicon atoms at the surface of the
(100)Si substrate (Pb0 centers) and in a-Si:H layer (D-centers) provide the
most significant contributions to the density of traps.
Chapter 5 presents an extensive study on passivation and dissociation of
Ge DBs at Si1−x Gex /SiO2 interfaces. The goal of this chapter is to unveil
the kinetics of Ge DB passivation and to compare this behavior to that of
the well known behavior of Si DBs at the Si/SiO2 interface.
With the intent to help solving Ge-technology’s main issues, Chapter 6
presents some results on the passivation of the Ge/HfO2 interface by using
an Si/SiO2 interlayer, and eliminate Ge Fermi level pinning by using the
Ge3 N4 insulator.
In Chapter 7, we first present trap properties at interfaces of ALD-TaSiOx
with InP and In0.53 Ga0.47 As. Next, some results on HfO2 /In0.53 Ga0.47 As
interface passivation by using Al2 O3 is discussed.
The final chapter overviews the most important conclusions obtained in
the presented studies. It also discusses some suggestions for further research.
Chapter 2
Extraction of interface trap
properties by using CV and GV
measurements
2.1
Introduction
The electrical characteristics of an electronic device which employs a
semiconductor/oxide interface are very sensitive to the interface state density
and its distribution in the semiconductor bandgap [44]. Interface charge
traps, also called interface states are attributed to the presence of native
defects, impurities or damage-related imperfections, e.g., broken bonds,
at semiconductor/insulator interfaces. The interface charge traps can be
characterized by using several quatities such as Qit , Nit and Dit [45]. Qit is
the interface-trapped charge per unit area caused by trapping of electrons
or holes by defects at a semiconductor/insulator interface; Nit =(+/-)Qit /q
is the number of traps per unit area; and Dit is the energy distribution of
Nit inside the semiconductor bandgap
Dit (E) =
dNit (E)
,
dE
(2.1)
where E is energy position inside the semiconductor bandgap.
Interface traps are electrically active defects with an energy level distribution
13
14
Chapter 2: Extraction of interface trap properties by CV/GV measurements
“0”
Figure 2.1: Band diagrams of a p-type semiconductor surface region
illustrating the presence of interface traps, i.e., acceptor traps “A” and
donor traps “D”, inside the semiconduction bandgap at flatband (a), when
bending up (b), and when bending down (c). Electron-occupied interface
traps are indicated by the bold em dashes and unoccupied traps by the light
em dashes [Ref. 46, p.343].
throughout the semiconductor bandgap (Fig. 2.1). They may act as
generation-recombination centers, contribute to leakage current, lowfrequency noise, and reduce carrier mobility in semiconductor. The
occupancy of interface traps is determined by the position of their energy
levels with respect to the Fermi level at the semiconductor interface: All
interface traps below EF are ocuppied by an electron; however above EF ,
the traps are empty. Therefore, Qit depends on the semiconductor band
bending.
In the case of silicon, an intrinsic coordination dangling bond (DB) defect,
e.g. Pb(0) , can introduce a pair of energy levels in the gap, one can be
occupied by an electron (acceptor type), the other by a hole (donor type).
The traps related to trivalent Si atoms at the interface are acceptor-like
in the upper half, and donor-like in the lower half of the Si bandgap,
usually referred to as the amphoteric behavior of Si BDs. Figure 2.1 shows
band diagrams of a p-type semiconductor which illustrate the presence of
interface traps inside Si bandgap. At flatband condition electrons occupy
states below the Fermi energy (Fig. 2.1(a)) and the donor states below
EF remain neutral (labelled “0”), while those between EF and midgap are
positively charged (labelled “+”). The unoccupied acceptors above midgap
are neutral (labelled “0”) [46]. When the bands bend down, as shown in
Fig. 2.1(b), the same fraction of interface acceptors between midgap and the
AC MODEL OF A MOS CAPACITOR
15
Fermi level becomes occupied by electrons, leading to negatively charged
interface traps (labelled “–”).
There are several experimental methods used to investigate the properties
of charge traps at semiconductor/insulator interfaces in MOS structures,
such as CV and GV methods [47–50], the charge pumping method using
MOSFETs [51], electron spin resonance (ESR) [52, 53], and saturation
photovoltage (SPV) technique [54]. Among them, CV and GV methods
are the most common ones because of the simplicity of MOS capacitor
fabrication. In addition, GV method can provide detailed information on
capture cross section of the interface traps.
In this chapter, we overview the basics of the CV and GV methods which
are mainly used in this thesis to determine interface trap properties. After
the extraction of flatband voltage VFB and doping concentration in the
semiconductor using the high frequency CV method, the energy distribution
of traps can be evaluated using high or low-frequency CV methods. As a
complementary method of better sensitivity, the frequency dependent GV
measurements offer the possibility to verify results of a simple CV analysis.
2.2
AC model of a MOS capacitor
A MOS capacitor is comprised of an insulating oxide layer sandwiched
between a semiconductor substrate and a metal gate as schematically shown
in Fig. 2.2(a). It may also be related to as a Metal-Insulator-Semiconductor
(MIS) capacitor, if the composition of the insulating layer is different from
an oxide. The alternating current (AC) CV and GV measurements are
performed by applying a direct current (DC) voltage VG with ontop a small
AC signal δV = asin(ωt) between the top metal gate and the ohmic back
contact. The sweep of the DC bias is performed in a staircase fashion
as shown in Fig. 2.2(c). The admittance Y of a circuit is defined as the
inverse of the complex impedance Z=dV/dI, so Y=dI/dV. Because the AC
measurement bridge mode is set to parallel during the measurement, the
measured complex admittance is presented in the following form
Ym = Gm + iωCm ,
(2.2)
16
Chapter 2: Extraction of interface trap properties by CV/GV measurements
where Gm is the equivalent conductance, and Cm the equivalent capacitance,
as shown in Fig. 2.2(b).
For an ideal MOS capacitor, the equivalent circuit includes an oxide capacitor
Cox and a semiconductor depletion layer capacitor Cs in series:
Cox =
κox ε0
tox
and
Cs =
κs ε0
,
w
(2.3)
where κox and κs are the dielectric constants of the oxide and semiconductor
layers, respectively, ε0 = 8.85 × 10−14 F/cm is the permitivity of vacuum,
tox is the oxide thickness, and w is the width of the depletion layer.
2.3
Capacitance methods of trap characterization
2.3.1
Low frequency CV method
MOS structure
The low frequency (LF) CV method was developed by Berglund in 1966 [48],
and then modified by Kuhn [55]. The method provides information on the
surface potential in the semiconductor, ψs , and on the interface trap density,
VG
metal
Cox
oxide
Cm Gm
Cs
V = VG+aa sin(t)
semiconductor
t
ohmic contact
(a)
((b))
((c))
Figure 2.2: (a) Schematic cross section of a MOS capacitor illustrating a
simple equivalent circuit; (b) The equivalent measurement circuit including
an oxide capacitor Cox and a semiconductor capacitance Cs in series; (c)
Voltage signal applied to the gate of the MOS capacitor to measure its
differential capacitance or admittance as function of the DC gate bias VG .
2.3 Capacitance methods
17
Dit , but cannot evaluate their capture cross-sections or the trapping time
constants.
In a MOS structure with interface traps, a change in interface trap charge
density dQit occurs in accordance with any change in band bending in the
semiconductor, ψs . The charge balance condition is
dQG + dQs + dQit = 0,
(2.4)
where dQG and dQs are the differential variations of the gate charge and the
semiconductor space charge, respectively. These quantities may be related
to the corresponding capacitances as follows
Cox =
dQG
,
dVox
(2.5)
where dVox = dVG − dψs , and
dQit
,
dψs
(2.6)
dQs
.
dψs
(2.7)
Cit (ψs ) = −
Cs (ψs ) = −
Hence,
Cox d(VG − ψs ) = [Cs (ψs ) + Cit (ψs )]dψs .
(2.8)
We can see that a change in the gate bias causes a change in band bending
ψs described by the following equation
Cox dVG = [Cox + Cs (ψs ) + Cit (ψs )]dψs .
(2.9)
The differential LF capacitance of the MOS capacitor is defined by
CLF =
dQG
,
dVG
(2.10)
HF‐CV and LF‐CV
18
Chapter 2: Extraction of interface trap properties by CV/GV measurements
Cox
Cox
Cm Gm
Figure 2.3: Equivalent circuits
of a MOS capacitor used
for capacitance methods at
low frequency (a), and at
high frequency (b) [Ref. 44,
(a)
p.323,p.327].
CS
CS Cit
(a)
(b)
0 .5
A l2 O
3
/A l
C a p a c ita n c e ( F /c m
2
)
( 1 0 0 ) S i/ 2 0 n m
0 .4
0 .3
0 .2
2 0 H z
1 M H z
0 .1
0 .0
0
1
2
3
G a te v o lta g e ( V )
4
Figure 2.4: Room-temperature low (20 Hz) and high frequency (1 MHz) CV
curves as measured on an n-Si MOS capacitor with a 20-nm Al2 O3 insulator
and a substrate doping concentration ND ∼1×1016 cm−3 .
where the total charge per unit area is QG = −(Qs + Qit ). Combining
equations 2.9 and 2.10 leads to
CLF = −
dQG dψs
Cox
= (Cs + Cit )
.
dψs dVG
Cox + Cs + Cit
(2.11)
The equivalent circuit corresponding to Eq. 2.11 is shown in Fig. 2.3(a).
The relation between the capacitances of a MOS sample in the figure can
2.3 Capacitance methods
19
be rewritten as
1
1
1
=
+
.
CLF
Cox Cs + Cit
(2.12)
Correlation of Dit and Cit
When changing the gate bias in a MOS structure, the semiconductor surface
band bending ψs changes corresponding to a change in energy level of
interface traps: dE = qdψs , where q is the elementary charge (derived from
Eq. 2.19 in the next section). Using Eq. 2.1, Dit can be re-defined
Dit (E) =
dNit (E)
−dQit /q
Cit
dNit
=
= 2.
=
dE
qdψs
qdψs
q
(2.13)
Finally, Dit can be extracted as following
Dit =
1 Cox CLF
Cit
=
−
C
.
s
q2
q2 Cox − CLF
(2.14)
The LF-CV method is practical and easy to implement, especially for Si MOS
capacitor samples. However, the experimental and theoretical curves may
present some mismatch if the semiconductor, oxide and metal parameters
such as doping concentration, fixed charge, work function are not known
or if there are series resistance effects which have not been yet included in
theoretical curve simulations.
2.3.2
Determining the energy distribution of interface traps
using a low frequency CV curve
To determine the energy scale for the interface trap density distribution,
it is critical to know the semiconductor band bending ψs as a function
of the gate bias VG [56], which can be extracted from low frequency CV
curves. The surface band bending can be found from the low frequency
CV measurements through numerical integration (the Berglund integral)
[48], in combination with the flatband voltage point (VFB ) inferred from a
high-frequency CV curve (see section 2.3.3).
20
Chapter 2: Extraction of interface trap properties by CV/GV measurements
First of all, we have the following relation based on the gate charge
calculation:
dQG = Cox dVox = CLF dVG ,
(2.15)
so that
CLF = Cox
dVox
.
dVG
(2.16)
Since dVG = dVox + dψs ,
dVox
CLF = Cox 1 −
.
dVG
Cox
(2.17)
Finally, using the definition that surface band bending at flatband voltage is
equal to zero, ψs (VFB ) = 0, the following equation is obtained by integrating
Eq. 2.17:
ψs (VG ) =
Z VG h
VFB
1−
CLF i
dV.
Cox
(2.18)
As the next step, using semiconductor surface band diagrams as shown
in Fig. 2.5 and noticing that the trap changes their electron occupancy
when crossing the Fermi level, we can associate the energy position E of an
interface trap level with the Fermi level at a given ψs . The position E with
respect to the semiconductor VB edge is given as
E − EV =
Eg
+ qψs + qφB ,
2
(2.19)
where
φB =
kT ND
ln
q
ni
φB = −
kT NA
ln
q
ni
for an n-type semiconductor,
for a p-type semiconductor,
are obtained from the measured donor and acceptor concentrations, ND and
NA , respectively; ni is the intrinsic carrier concentration of the semiconductor
(ni = 1.45 × 1010 cm−3 for Si at 300 K), ψs is surface potential, and Eg is
energy bandgap of the semiconductor (Eg =1.12 eV for Si at 300 K). The
Band bending
2.3 Capacitance methods
21
qn
E
EC
EF
EC
Eg /2
qB
(E – EV)
Ei
Ei
qB
E
qs
Eg/2
EV
Interface
(a) n-type
(E – EV)
EF
EV
qs
Interface
(b) p-type
Figure 2.5: Surface band diagrams of n-type (a), and p-type (b)
semiconductors showing how the position of the Fermi level at the silicon
surface is related to the band bending. The arrows pointing up denote
negative potential, whereas the arrows pointing down denote positive surface
potential ψs [Ref. 44, p.95].
doping concentrations ND , NA can be extracted from a high-frequency CV
curve (see section 2.3.3).
2.3.3
High frequency CV method
The high-frequency CV method was developed by Terman [47] by comparing
the measured high frequency CV curve with the ideal one of a MOS capacitor
with the same doping level and oxide thickness. In this method, capacitance
is measured at a sufficiently high frequency so the interface traps do not
respond to the AC signal. Therefore, the traps give no contribution to the
measured capacitance (Cit (HF)=0). Although the interface traps do not
respond the AC probe frequency, they do respond to the slowly varying
DC gate voltage and, in this way, they cause a stretch-out in the CV curve
along the gate voltage axis.
Because in the ideal case, Cit (HF)=0, the equivalent circuit of a MOS
22
Chapter 2: Extraction of interface trap properties by CV/GV measurements
capacitor at high frequency includes only Cox and Cs in series, as shown in
Fig. 2.3(b). Thus, the capacitance at high frequency CHF is given by
CHF =
Cox Cs
.
Cox + Cs
(2.20)
Since Cox can be found from the accumulation capacitance, the depletion-
HFCV‐surface band bending
30
25
Dit=0
s (kT/q)
20
Dit=1012 cm-2eV-1
15
10
5
0
-5
-1
0
1
2
3
Gate voltage (V)
4
5
6
Figure 2.6: Plots of ψs versus gate voltage VG behavior obtained from the
theoretical and experimental high frequency CV curves of a MOS capacitor.
layer capacitance Cs can be extracted from the measured CHF . However, Cs
varies with the semiconductor surface potential, ψs . Therefore, the measured
CHF will be the same as for the ideal MOS capacitor only if the identical
ψs is attained. Knowing ψs that corresponds to a given CHF in the ideal
MOS capacitor, and measuring CHF (VG ) in the real MOS capacitor, one
can obtain a ψs versus VG curve for the real MOS capacitor that includes
the influence of the interface traps, as shown in Fig. 2.6. In fact, the amount
of stretch out, as reflected by dψs /dVG , determines the Dit quantity. Thus,
by graphical or numerical differentiation of the ψs versus VG curve, the
derivative dψs /dVG can be calculated. In addition, variable semiconductor
capacitance Cs is calculated for each value of the surface potential ψs by
using the procedure described in the previous sections. Finally, Cit can be
2.3 Capacitance methods
23
determined from Eq. 2.9 as following
Cit (ψs ) = Cox
h dψ −1
s
dVG
i
− 1 − Cs (ψs ).
(2.21)
Once Cit is found from Eq. 2.21, Dit ordinarily is inferred using Eq. 2.13
Dit (ψs ) =
2.3.4
i C (ψ )
Cit (ψs )
Cox h dψs −1
s s
−
1
−
=
.
2
2
q
q
dVG
q2
(2.22)
Determination of flatband voltage and substrate’s doping
concentration
This section will discuss the determination of VFB and semiconductor doping
concentration by using the high frequency CV method. The parameters
will be used to determine the energy position of interface traps within the
semiconductor bandgap (see section 2.3.1).
Determination of the substrate doping concentration
Considering an n-type substrate MOS capacitor biased in depletion region,
we suppose that when changing the gate bias dVG , the change in metal
charge dQG results in a variation of the depleletion layer depth by dw. Then,
the relation between donor doping concentration ND (w) at the depletion
edge is given as follows [Ref. 44, Eq. 9.1]
dQG = −qND (w)dw.
(2.23)
Since Cs = ε0 κs /w, the variation dw is also refected in the variation of Cs
dw = ε0 κs d(
1
).
Cs
(2.24)
Because Cox is independent on gate bias, and 1/Cm = 1/Cs + 1/Cox , the
above equation can be written as
dw = ε0 κs d(
1
).
Cm
(2.25)
24
Chapter 2: Extraction of interface trap properties by CV/GV measurements
Using the condition that dQG = Cm dVG together with Eq. 2.23, we obtain
−qND (w)dw = Cm dVG .
(2.26)
Then, using substitution of Eq. 2.25 in to Eq. 2.26 to eliminate dw, we
obtain
−qND (w)ε0 κs d(
1
) = Cm dVG .
Cm
(2.27)
Solving the above equation yields
h
ND (w) = − qε0 κs
1 d 1 i−1
.
Cm dVG Cm
(2.28)
d 1 i−1
.
dVG C2m
(2.29)
Then, finally, we obtain
h
ND (w) = −2 qε0 κs
Rewriting the above equation and replacing Cm by CHF yields [Ref. 44, Eq.
9.19, p.388]
h
ND (w) = −2 qε0 κs
d 1 i−1
.
dVG C2HF
(2.30)
This equation can be used in the depletion region with the assumption that
the influence of interface states on the measured capacitance is negligible [44].
Later on, Brews proposed a relation for active doping density determination
taking a correction for the CV curve stretch-out due to interface states into
consideration [57],[Ref. 44, p.388]
ND (w) = −2
1 − C
LF /Cox
1 − CHF /Cox
h
qε0 κs
d 1 i−1
.
dVG C2HF
(2.31)
If there is no stretchout due to interface traps, the correction term
(1 − CLF /Cox )/(1 − CHF /Cox ) = 1, and then the two equations above
become identical.
2.3 Capacitance methods
25
A similar result can be obtained for an acceptor-doped substrate to a
concentration NA
1 − C
NA (w) = 2
LF /Cox
1 − CHF /Cox
h
qε0 κs
d 1 i−1
.
dVG C2HF
(2.32)
Determination of flatband voltage
The flatband voltage, VFB , is defined as the value of the gate voltage, VG ,
at which the conduction and valence bands edges observed across the surface
of semiconductor are flat. That is, the surface potential (the band bending),
ψs , is equal to zero. There are several ways to infer the VFB experimentally
from CV curves.
A simple method to extract VFB is determination of the flatband capacitance
CFB value on the measured high frequency CV curve by comparing it to
the calculated value which immediately yields VFB :
CFB =
CFBS Cox
,
CFBS + Cox
(2.33)
where CFBS is the semiconductor surface capacitance at flatband condition
CFBS =
ε0 κ s
,
λn/p
(2.34)
and
s
λn/p =
ε0 κkT
2q2 ND/A
(2.35)
is the Debye length for an n- or p-type semiconductor, respectively.
This method is widely used because of its simplicity. However, it may lead
to an error when the influence of interface traps and charge non-uniformities
cannot be ignored or when the semiconductor doping is not uniform across
the space charge layer.
The second is extracting VFB from the intercept with the gate bias axis
of (1/C2HF − 1/C2ox ) versus VG curve. The basics for this method can be
derived from Eq. 2.27, that is valid in depletion of a MOS structure. By
26
Chapter 2: Extraction of interface trap properties by CV/GV measurements
replacing Cm by CHF , we have
d
1 C2HF
=−
2
dVG ,
qND (w)ε0 κs
(2.36)
Integrating from VFB to a gate voltage VG in depletion leads to
Z VG 1 VFB
d
C2HF
=−
2
dVG .
VFB qND (w)ε0 κs
Z VG
(2.37)
With assuming that the doping concentration is distributed uniform in the
semiconductor substrate, N(w)=const, we have
1
2
1
−
=−
(VG − VFB ).
qND (w)ε0 κs
C2HF C2FB
(2.38)
Then, a plot of (1/C2HF − 1/C2FB ) vs. VG will give a linear behavior in
depletion region with intercept on V-axis of VFB . Approximately, one can
use a (1/C2HF − 1/C2ox ) versus VG curve to extract VFB , as illustrated in
Fig. 2.7 with the inferred flatband voltage value VFB ≈1.55 V.
Cox 0.40 F/cm2
VFB  1.55 V
2
2 ) versus gate voltage V of a MOS
Figure 2.7: A plot of (1/CHF
− 1/Cox
G
capacitor, used to extract the flatband voltage VF B and semiconductor
substrate’s doping concentration.
2.3 Capacitance methods
27
Some other techniques to determinate VFB are discussed in Ref. 44, Chap. 10.
2.3.5
High-low frequency method
Both LF and HF capacitance methods require comparison of experimental
CV curves to theoretical simulations which limits their accuracy. A more
precise and simplified approach was proposed by Castagne and Vapaille
[50] for determination of Dit by combining the high and low frequency CV
curves to obtain Cs . In this way, they eliminated the uncertainty associated
with the calculation of Cs in Eq. 2.14 and replaced it with the measured Cs
obtained from the high frequency CV curve,
Cs =
Cox CHF
.
Cox − CHF
(2.39)
Substituting Eq. 2.39 into Eq. 2.14 gives Dit in terms of the measured low
and high frequency CV curves as
Dit =
2.3.6
CHF /Cox 1 CLF /Cox
−
.
q2 1 − CLF /Cox 1 − CHF /Cox
(2.40)
Gray-Brown temperature-induced shift technique
The technique based on the temperature-induced Fermi level shift has been
suggested by Gray and Brown [58, 59] for determination of the interface
trap density at Si/SiO2 interfaces. In this method, the HF capacitance is
measured as a function of temperature, usually from 300 K to 77 K. Lowering
the temperature causes the Fermi level to shift towards the majority carrier
band edge and the interface trap emission time constant τit increases. Hence,
interface traps near the band edges should not respond to typical AC probe
frequencies at low temperatures whereas at room temperature (RT) their
response may distort the HF CV measurements. When cooling a sample,
the change in gate bias needed to maintain the flatband condition is equal
to the Gray-Brown shift [Ref. 44, p.357]
q
VFB (T2 ) − VFB (T1 ) = −
Z EF (T2 )
EF (T1 )
Dit (E)dE
Cox
.
(2.41)
28
Chapter 2: Extraction of interface trap properties by CV/GV measurements
300 K
Ec
Ec
E
77 K
E
EF(n)
EF(n)
EF(p)
( )
Ev
Ev
EF(p)
Figure 2.8: The shift of the Fermi level in n- and p-type Si relative to the
interface trap energy distribution caused by cooling the sample from 300 K
to 77 K. The Dit (E) schematically shows the interface trap distribution
associated with Pb -type defects at Si/SiO2 interfaces.
If one knows the temperature dependence of the Fermi level EF and,
presumably, if Dit does not depend on temperature, Dit can be determined
as [Ref. 44, p.357]
Dit =
1 d[VFB (T1 ) − VFB (T2 )] h dEF (T2 ) i−1
.
q
dT2
dT2
(2.42)
In a non-degenerate semiconductor, when lowering the sample temperature
from 300 K to 77 K, the flatband voltage shifts corresponding to the interface
trapped charge between two positions of the Fermi level (Fig. 2.8).
VFB (77 K) − VFB (300 K) =
[EF (77 K) − EF (300 K)] ∆Qit
−
, (2.43)
q
Cox
and
∆Nit =
(∆VFB − ∆EF /q)Cox
,
q
(2.44)
where ∆Qit and ∆Nit represent the variation in interface trapped charge and
the number of interface traps when the Fermi level shifts from its position
at 300 K to that at 77 K, respectively; ∆VFB is the corresponding change
in flatband voltage, ∆EF is the difference of Fermi level energy at 300 K
and 77 K, and Cox is the capacitance of the oxide layer per unit area.
The Gray-Brown method normally detects only the interface traps between
2.3 Capacitance methods
29
the high- and low-temperature Fermi levels, which situate below midgap for
p-type semiconductor and above midgap for n-type one. In order to scan
both sides of the band gap, these experiments can be performed on both nand p-type samples with identical oxide layers. Because the Fermi levels at
77 K are very close to the band edges, the difference between VFB values
when measuring on both n- and p-type covers most of the semiconductor
bandgap, as illustrated in Fig. 2.8. In the case of a silicon substrate with
doping concentration in the 1014 –1017 cm−3 range, this shift covers ∼95 %
of the Si band gap width (1.16 eV) at 77 K, i.e., nearly the entire gap width
of 1.12 eV at 300 K [60]. Therefore, Nit can be determined by the shift in
the 77-K VFB between n- and p-type samples. Firstly, we have
VFB (n) − VFB (p) =
1
1
qNit
.
EF (n, 77 K) − EF (p, 77 K) +
q
q
Cox
(2.45)
Using the condition [EF (n, 77 K) − EF (p, 77 K)] ∼ Eg (300 K), Nit is
finally obtained as
Nit ≈
[VFB (n) − VFB (p)] − Eg (300 K)/q
Cox .
q
(2.46)
According to Stesmans and Afanas’ev [60], important advantages of this
modification of the Gray-Brown technique include the following:
• It allows detection of the interface traps close (<20 meV) to the
semiconduction band edges, unaccessible for room temperature (RT)
CV.
• Unlike HF CV and LF CV methods, it does not suffer from
the significant uncertainty of the semiconductor surface potential
determination near the band edges in case of high Nit . In addition,
the HF CV condition, necessary for a correct determination of VFB is
easier met at 77 K than at 300 K.
• It provides a reliable technique to deternime the total Nit across entire
gap because the energy range between the Fermi levels of n- and ptype semiconductors at low temperature covers most of semiconductor
bandgap.
30
2.4
Chapter 2: Extraction of interface trap properties by CV/GV measurements
Conductance method of trap characterization
The conductance method has been developed by Nicollian and Goetzberger
since 1967 [49], and is considered to be one of the most sensitive techniques
for determining Dit , down to levels of 109 cm−2 eV−1 . The conductance
method makes use of the linear relation between the interface trap density
and the peak Gp /ω dependence to determine Dit . This technique has
several advantages over other interface characterization techniques: (1)
High sensitivity, thanks to the fact that no conductance arises if interface
traps are absent;(2) Simplicity and easy implementation; (3) It gives clear
information on trap properties such as capture cross-section and energy
distributions of Dit ; (4) It does not require a MOSFET structure, a simple
MOS capacitor is sufficient.
There are two main steps to extract Dit by using the conductance method:
(1) Measuring AC capacitance and conductance as functions of VG and
frequency, followed by the determination of the Dit as a function of gate bias
from the equivalent parallel conductance Gp ; (2) From the low frequency
CV measurement, the semiconductor surface potential ψs is extracted as
a function of gate bias using Berglund integration, thus allowing one to
determine the position of trap levels in the semiconductor bandgap (cf.
section 2.3.1).
2.4.1
Correlation of Gp /ω and Dit
Figure 2.9 shows the equivalent curcuits of a MOS capacitor used to analyze
the GV data. For the case of single level of interface traps, admittances of
the circuits (a) and (b) are equal. Excluding Cox , we have:
iωCp + Gp = iωCs +
1
iωCit + ω2 τit Cit
= iωCs +
, (2.47)
Rit + 1/(iωCit )
1 + (ωτit )2
where τit = Rit Cit is the interface trap time constant. Taking the real part
of the above equation, in substituting Cit = qDit the dependence of Gp /ω
on Dit is obtained as
qωDit τit
Gp
=
.
ω
1 + (ωτit )2
(2.48)
Circuits ‐ GV method
2.4 Conductance method of trap characterization
Cox
Cox
Cm Gm
Cit
Cox
CS
Cp Gp
Rit
(a)
(b)
(c)
31
Figure 2.9:
Equivalent circuits used for extraction of
C
Dit byox using the conductance
method: (a) MOS capacitor
Cc Gctrap time conwith interface
stant τit =Rit Cit , (b) simplified
circuit of (a) with equivalent
parallel capacitance Cp and conRs Gp , andR(c)
ductance
the circuit
s
with the measured capacitance
Cm and conductance Gm [Refs.
(d)
(e)
44, 49].
However, the interface trap distribution may be continous in energy within
the semiconductor bandgap, and the capture and emission happen at traps
levels energetically positioned within a few kT/q of the Fermi level, leading
to a time constant dispersion and normalized conductance given by [49]
Gp
qDit
=
ln[1 + (ωτit )2 ].
ω
2ωτit
(2.49)
When surface potential fluctuations are taken into account, the Gp /ω versus
f curves get broader
Gp
=
ω
qDit
ln[1 + (ωτit )2 ]P(υs )dυs ,
2ωτ
−∞
it
Z ∞
(2.50)
ψs
where υs is surface potential in units of kT/q , i.e., υs = kT/q
, and P(υs ) is
the Gaussian distribution probility function for the surface potential
P(υs ) = √
h (υ − υ¯ )2 i
1
s
s
exp −
,
2
2σ
2πσs
s
(2.51)
with υ¯s being the mean surface potential, and σs the standard deviation of
the distribution.
32
Chapter 2: Extraction of interface trap properties by CV/GV measurements
2.4.2
Extraction of Gp /ω from CV and GV measurements
Figure 2.9(a) shows the equivalent circuit of a MOS capacitor used to
analyze the AC conductance data. In this equivalent circuit, Cox is the
oxide capacitance, Cs is the semiconductor capacitance, and Cit is the
interface trap capacitance. Resistance Rit represents the loss mechanism
related to capture and emission of carriers from the interface traps. The
circuit shown in Fig. 2.9(a) can be replaced by the circuit in Fig. 2.9(b),
where Cp and Gp are the parallel equivalent capacitance and conductance,
respectively.
Using the condition that circuit 2.9(b) is equivalent to 2.9(c), and with
exclusion of Cox (a constant value), one can obtain Gp /ω as a function of
frequency and gate voltage: Writing down that the complex resistances in
the two circuits are equal
1
1
1
+
=
,
iωCox Gp + iωCp
Gm + iωCm
(2.52)
we get
Gp + iωCp =
1
1/(Gm + iωCm ) − 1/(iωCox )
=
ωCox (Gm + iωCm )
,
iGm + ω(Cox − Cm )
(2.53)
and
Gp + iωCp =
ωCox (Gm + iωCm )[−iGm + ω(Cox − Cm )]
.
G2m + ω2 (Cox − Cm )2
(2.54)
By taking the real part of the above equation, we obtain
Gp
ωC2ox Gm
= 2
.
ω
Gm + ω2 (Cox − Cm )2
2.4.3
(2.55)
Oxide capacitance and series resistance
Equation (2.55) can be used to calculate Gp /ω for different gate voltages,
which will further be applied to extract properties of the interface traps.
2.4 Conductance method of trap characterization
33
Cox
Cox
Cox
Cc
Cit
CA
CA
Rit
Rs
(a)
Gc
Rs
(b)
Rs
(c)
Rs
(d)
Figure 2.10: (a) Equivalent circuit of a MOS capacitor in strong
accumulation including the series resistance Rs ; (b)simplified version of (a);
(c) simplified version of (b) used to extract values of Cox and Rs from the
admittance measured in strong accumulation; (d)Equivalent circuit of the
MOS capacitor with corrected capacitance Cc and conductance Gc (Ref. [44],
p.223).
However, the conductance of a MOS structure is very sensitive to series
resistance, necessitating the correction of both capacitance and conductance
in order to obtain a reliable estimate of Dit .
Figure 2.10(a) shows the equivalent circuit of a MOS capacitor in strong
accumulation, in which the accumulation layer capacitance CA is in parallel
with Yit . Because CA is large and shunts Yit , i.e., ωCA >> Yit , the
equivalent circuit can be modified into a more simple circuit presented
in Fig. 2.10(b). Moreover, because CA >> Cox , the circuit in Fig. 2.10(b)
can be simplified further to an equivalent circuit in Fig. 2.10(c).
To determine Rs , the MOS capacitor is biased into strong accumulation, in
which the equivalent circuit is reduced to the series-circuit of Cox and Rs
(Fig. 2.10(c)). The impedance of the circuit is equal to Za = Rs + 1/(iωCox ).
The following condition is obtained in strong accumulation
Rs +
1
i
Gm − iωCm
1
.
=
=> Rs −
= 2
iωCox
Gm + iωCm
ωCox
Gm + ω2 C2m
(2.56)
34
Chapter 2: Extraction of interface trap properties by CV/GV measurements
From the real part, Rs can be obtained:
Rs =
Gm
.
2
Gm + ω2 C2m
(2.57)
Taking the imaginary part, Cox can be extracted as
1
ωCm
= 2
,
ωCox
Gm + ω2 C2m
(2.58)
and
h
Cox = 1 + (
Gm 2 i
) Cm .
ω2 Cm
(2.59)
To correct for the influence of the series resistance, we use the condition
that the circuit shown in Fig. 2.10(d) is equivalent to the measured circuit
shown in Fig. 2.2(b)
Rs +
1
1
=
,
Gc + iωCc
Gm + iωCm
(2.60)
and
Gc + iωCc =
1
G2m + ω2 C2m
=
.
1/(Gm + iωCm ) − Rs
Gm − iωCm − (G2m + ω2 C2m )Rs
(2.61)
The above equation can be rewritten as
Gc + iωCc =
(G2m + ω2 C2m )(a + iωCm )
,
a2 + ω2 C2m
(2.62)
where a = Gm − (G2m + ω2 C2m )Rs . So, the corrected values of capacitance
and conductance are finally obtained as
Cc =
(G2m + ω2 C2m )Cm
,
a2 + ω2 C2m
(2.63)
35
fp/5
f p ×5
G
p
/ω( a r b . u n it)
2.4 Conductance method of trap characterization
fp
1 0
1
1 0
2
3
1 0
F re q u e n c y (H z )
1 0
4
Figure 2.11: A calculated
Gp /ω versus frequency
curve, for a fixed VG in
depletion,
as typically
obtained from measurement
by correcting for Cox using
Eq. 2.55, where fp is the
frequency corresponding to
the peak value of Gp /ω.
The points at fp /5 and
fp × 5 define the width of
the curve on the low and
high frequency side of fp ,
respectively [44, Ref.].
and
Gc =
(G2m + ω2 C2m )a
.
a2 + ω2 C2m
(2.64)
The above corrected Cc and Gc values are then used to extract Gp /ω by
means of Eq. 2.55 instead of Cm and Gm , respectively.
2.4.4
Interface trap density Dit
Figure 2.11 shows for a fixed VG value in depletion a calculated Gp /ω curve
as a function of log(f) (where ω = 2πf). The interface trap density Dit , and
the time constant τ can be determined from the magnitudes and positions
of the maxima of the Gp /ω vs. log(f) curves at different gate bias, given as
Dit =
G 1
p
,
f D (σs )q ω max
(2.65)
where (Gp /ω)max is the peak Gp /ω value at applied gate voltage, σs is
the standard deviation of the surface potential, and f D (σs ) is a particular
universal function of σs [Ref. 44, p.216]:
f D (σs ) =
(2πσ2s )−1/2
2ξp
Z ∞
−∞
exp −
η2 exp(−η)ln(1 + ξp2 exp2η)dη, (2.66)
2σ2s
36
Chapter 2: Extraction of interface trap properties by CV/GV measurements
where ξp = ωp τ and τ is the trapping time constant. Figure 2.13 shows a
plot of the universal function f D (σs ) defined in Eq. 2.66 as a function of σs .
f D is used in Eq. 2.65 to calculate Dit once σs is determined from Fig. 2.12,
[Ref. 44, p.217].
The procedure is based on the measurement of the width of this curve either
between the points fp and fp /n (n = 1, 2, 3...) or between fp and n × fp ,
where fp is the frequency corresponding to the peak value of Gp /ω. The
ratio between (Gp /ω)fp /n and (Gp /ω)fp is given by [Ref. 44, p.214]
η2 exp(−η)ln[1 + ξp2 exp(2η)/n2 ]dη
(Gp /ω)fp /n
2σ2s
−x
=n Z x
.
(Gp /ω)fp
η2 2
exp − 2 exp(−η)ln(1 + ξp exp2η)dη
2σs
−x
(2.67)
Z x
exp −
In addition, the ratio between (Gp /ω)nfp and (Gp /ω)fp is given by [Ref. 44,
p.215]
η2 exp(−η)ln[1 + n2 ξp2 exp(2η)]dη
(Gp /ω)fp /n
1 −x
2σ2s
.
=
Z x
(Gp /ω)fp
n
η2 2
exp − 2 exp(−η)ln(1 + ξp exp2η)dη
2σs
−x
(2.68)
Z x
exp −
Equations 2.67 and 2.68 are single-valued functions of σs , and are shown
graphically in Fig. 2.12 for the choice n=5. Using the experimentally inferred
ratios, the corresponding σs can be found graphically from Fig. 2.12. From
this value of σs , the applicable f D (σs ) value is found from Fig. 2.13, allowing
one to calculate Dit using Eq. 2.65.
2.4.5
Carrier capture cross section and interface trap time
constants
To determine the interface trap time constant, τ , we use the condition
d Gp = 0.
dξ ω fp
(2.69)
84
Chapter 4: Extraction of interface trap properties from …
Equations (4.24) and (4.25) are single-valued functions of σs, which
are plotted in Fig. 4.5. Choosing n=5 is reasonable because the values of
G p / ω at these frequencies generally will neither be too low nor too
close to the peak value so that accurate values of these ratios can be
found. Using the experimentally inferred ratios, the corresponding σs can
be found
graphically
from Fig. 4.5. Using this value of σs, the applicable
2.4 Conductance
method
of trap characterization
fD (σs) value is found from Fig. 4.6, allowing calculation of Dit using Eq.
(4.23).
37
Figure 2.12:
Plot
versus
the standard
of
Fig. 4.5.
Plot of
of [(G
the standard
deviationdeviation
of the
GPp//ω)/(G
ω ] /[ GP p//ω)
ω ] f fpversus
the semiconductor surface potential σs . This curve is used to determine
semiconductor surface potential σs. This curve is used to determine σs
σs from the width of a Gp /ω versus
log(f) curve, which is shown in
from the width of a <Gp>/ω versus log (f) curve, such as shown in Fig.
Fig. 2.11,4.4,
measured
gatebias.
bias.Determination
Determination
the frequency
fp
measuredat
at aa given
given gate
of theoffrequency
fp
corresponding
to the to
peak
theof measured
curve
thelow
low
corresponding
the of
peak
the measured
curveand
and either
either the
or or high
frequency
will suffice
in using
curve. For
For values
of σs of σs
frequencyhigh
side
width side
willwidth
suffice
in using
thisthis
curve.
the values
greater
than
3.5,
the
peak
of
the
<G
>/
ω
versus
log
(f)
curve
becomes
p
greater than 3.5, the peak of the Gp /ω versus log(f) curve becomessoso broad
broad that a large error will be made in determining fp [126].
that a large error will be made in determining fp [Ref. 44, p.216].
p
4.4. T h e a c c o n d u c t a n c e m e t h o d
85
.4
fD
s)
.3
.2
.1
0
0
1
2
s
3
4
5
4.6. Plot
Plot ofofthe
function
fD (σs)fas
a function of σ [127].
FigureFig.
2.13:
theuniversal
universal
function
D (σs ) defined sin Eq. 2.66 as a
function of σs ; fD is used in Eq. 2.65 to calculate the interface trap density
4.4.2.p.217]).
Evaluation of semiconductor parameters from measured
[Ref. 44,
capacitance and conductance
4.4.2.1. Surface potential, ψs(VG)
Referring to Fig. 4.1, an MOS structure can be represented by an
equivalent circuit including an oxide capacitance C ox in series connection
with a network which takes into account the contributions of the
semiconductor space-charge region and interface states. The small-signal
capacitance C of the device at an applied voltage VG is
dQ
.
dVG
(4.26)
dQ = C ox dVox ,
(4.27)
C (VG ) =
But,
so
Applying this condition to (5.76) yields"
m
exP
(- &)
-m
77)
( 125;+ 5;expexp277277 -In(] + 5; exp 277)I dq 0.
=
(5.84)
Solving (5.84) numerically yields 6, as a function of a,.Figure 5.20 is a plot
of 5, versus a, obtained this way. Then, from the relation 6, = w , ~ , , we
38
Chapter 2: Extraction of interface trap properties by CV/GV measurements
us(IN UNITS OF kT/q)
Fig. 5.20
Plot2.14:
of tp=
w,(c,NA)-'
exp(v,)
of us
by solving
(5.84); 5, is
Figure
Plot
of ξp =
ωp τ asafunction
as a function
ofcalculated
σs calculated
by solving
used to calculate interface trap response time from (5.85). After Goetzberger et aLzo
Eq. 2.70; ξp is used to calculate the interface trap response time from Eq. 2.71
Copyright (1976),
The Chemical Rubber Co., CRC Press. Reprinted with permission.
[Ref. 44, p.217].
Hence, we get [Ref. 44, p.217]
Z ∞
−∞
exp −
h 2ξ 2 exp2η
i
η2 p
2
exp(−η)
ln(1
+
ξ
exp2η)
dη = 0. (2.70)
p
2σ2s
1 + ξp2 exp2η
Figure 2.14 presents a plot of ξp on σs obtained by nummerically solving
Eq. 2.70. Then from the relation ξp = (ωp τ ), we obtain
τ=
ξp
.
ωp
(2.71)
The value ξp = ωp τ depends only on σs , in other words, it reflects only the
broadening of the Gp /ω(f) curves. Finally, trap capture cross sections can
be found,
σn =
1
exp(−υs )
τ ῡT ND
and
σp =
1
exp(υs ),
τ ῡT NA
(2.72)
for electrons and holes, respectively; where ῡT is the thermal velocity of
the carriers, typically 107 cm/s in silicon at room temperature [cf. Ref. 44,
p.212, p.221].
MEASUREMENT SETUPS
39
Summary of the GV method for interface trap characterization
In summary, there are several steps required to extract interface trap
properties using the GV technique:
1. From the measured CV and GV data, Gp /ω vs. f is extracted. For
a value of gate voltage in depletion, a curve such as that shown in
Fig. 2.11 is obtained.
2. The ratio of (Gp /ω)fp /5 /(Gp /ω)fp or (Gp /ω)5fp /(Gp /ω)fp is calculated.
3. Next, σs is found from Fig. 2.12.
4. Using this value of σs , f D (σs ) is found from Fig. 2.13 and Dit is
calculated from Eq. 2.65.
5. Finally, using the same value of σs , ξp is found from Fig. 2.14 and τ is
calculated from Eq. 2.71. In addition, the interface trap cross section
is calculated from Eq. 2.72.
The gate bias is then changed, and the process is repeated until a curve
of Dit is obtained as a function of gate bias, over a limited range of gate
bias in depletion [Ref. 44, p.213][61, 62]. To cover a wider range of energies
within the semiconductor bandgap, both n-type and p-type samples must
be measured.
2.5
Measurement setups
In this thesis, CV and GV data were measured as a function of DC gate
voltage and frequency by applying a small AC probing signal and DC bias
voltage over the MOS capacitor. The AC signal magnitudes were typically
chosen in the 10–50 mV range. The measurements were performed at
different temperatures (T=77–300 K) using HP4284A (f=20 Hz–1 MHz)
and HP4192A (f=5 Hz–13 MHz) precision LCR meters. The LCR meters
are connected to computers and then the measurements are controlled
through IEEE cards using the Labview program. To obtain low temperature
measurements, the samples together with their holder were immersed in
40
Chapter 2: Extraction of interface trap properties by CV/GV measurements
liquid nitrogen (T=77 K) or in dry ice (solid CO2 , T∼200 K) or in a
temperature-controlled cryostat.
2.6
Conclusion
In conclusion, CV and GV methods have been applied widely for
characterization of interface traps at semiconductor/insulator interfaces.
Each of them has its own advantages and disadvantages. While CV methods
are by far less time consuming than the GV method, the GV method is
still very important because it is considered as the most sensitive technique
for determining Dit , down to levels of ∼ 109 cm−2 eV−1 . The GV method is
also the most complete method because it gives additional information on
trap properties such as capture cross-sections and trapping time constants.
However, the GV technique only observes intermediate and fast states, but
not slow states. At the high-κ/semiconductor interface, a considerable
density of slow traps may escape detection by the GV method because
of the limitation of the frequency ranges of the equipments. By contrast,
the CV methods can detect both slow and fast traps. When lowering the
temperature to 77 K, using CV methods, one can observe traps very close
to semiconductor band edges and one can thus get reliable values of Nit
integrated over the entire gap width.
In this thesis, both CV and GV methods were used to investigate
semiconductor/insulator interface properties. The electrical results were
also compared with ESR studies.
Chapter 3
Interface state energy
distribution and Pb defects at
(110)Si/SiO2 interfaces:
Comparison to (111) and (100)
Si orientations
The purpose of this chapter is to present experimental results on electrically
active defects at (110)Si/SiO2 interfaces in comparison to the previously
studied (111) and (100) silicon orientations. The chapter begins with an
introduction to Si/SiO2 interfaces, followed by a description of the samples
studied and the measurement procedures. The study mainly focuses on
occurring interface traps, so the rest of chapter is devoted to a comparison of
the measured interface trap density distributions at the interfaces between
differently oriented Si crystals and thermal SiO2 . The content of this chapter
has been partially published in the Journal of Applied Physics [63].
The charge traps encountered at the (110)Si/SiO2 interface are investigated
by combining electrical methods (CV and GV methods, cf. chapter 2) with
ESR measurements, and the results are compared to the well studied (100)
and (111)Si/SiO2 interfaces. At all three Si crystal faces, the interface trap
density Dit as function of energy E in the Si band gap exhibits two peaks at
41
42
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
about 0.25 eV and 0.85 eV above the Si VB edge, with the trap density per
unit area Nit quantitatively correlated with the density of paramagnetic Pb(0)
centers (Si3 ≡Si• defects, where the dot symbolizes an unpaired electron).
By comparing CV curves measured at 300 K and 77 K of both n- and p-type
samples, the Pb(0) defects are confirmed to be amphoteric in their electrical
appearance. Effective passivation of interface traps by H2 annealing suggests
that Pb0 defects are responsible for most of the interface traps observed
in (110)Si/SiO2 . The amphoteric behavior, implying that one Pb0 defect
delivers two interface trap levels, was observed for the (100) and (111)Si
faces, i.e. Nit ≈ 2[Pb ]. However, this simple relationship is not holding
at (110)Si/SiO2 interfaces: The estimated interface trap density Nit at
the (110)Si/SiO2 interface oxidized at 930 o C is (6.7±0.5)×1012 , while the
Pb0 density as determined by ESR is about (6±1)×1012 cm−2 . Lowering
of the oxidation temperature leads to further reduction of the fraction of
electrically active Pb0 centers at the (110)Si/SiO2 interface, suggesting a
clustering of defects with Coulombic repulsion preventing transition of all
present Pb centers to a charged state.
3.1
Introduction
Compared to the workhorse (100)Si face, crystallographic orientation
of MOSFET channel along the (110)Si plane offers improvement in
hole mobility and more compact architecture of MOSFET (e.g., vertical
MOSFET, multigate FinFET devices [64, 65]) while remaining within
the framework of the highly successful Si MOS fabrication process. It is
known that the hole mobility is more than doubled at the (110) silicon face
compared with the conventional (100) one, while the electron mobility is
still the highest on (100) face as shown in Fig. 3.1 [10, 66]. The enhanced
hole mobility reflects the fact that the effective mass of holes is lower at
the (110) surface than at (100) [10, 66]. This also means that, by using
(110)Si/SiO2 technology, it is possible to increase the drive current without
changing the material and the device structure.
Both performance and reliability of a MOS device are significantly influenced
by the quality of the grown Si/SiO2 interface. Studies of Si/SiO2 interface
traps using MOS capacitors were first introduced by Terman [47], and then
extended in other works [58, 67–71]. In the 1960s, using the temperaturedependent CV technique, Gray and Brown evaluated the density of interface
3.1 Introduction
43
Figure 3.1: Dependence of the effective mobility of electrons and holes in
the channel on the Si surface orientation and the channel direction [10].
states Dit (E) as a function of E at SiO2 /Si interfaces for three silicon
interface orientations [58]. However, as the SiO2 layers were grown at
Tox =1000 o C by wet oxidation (O2 +80 ppm H2 O), it is difficult to evaluate
to what extent the hydrogen passivation factor, not realized at that time,
affected the results which precludes one from quantitative comparison. In
addition, the Dit (E) profiles reported by Gray and Brown disagree with later
experimental results: The Dit reported for the (100) face is far higher than
observed by other groups [72–74], while the two peaks on all Dit (E) profiles
44
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
are much closer to the Si band gap edges than in the Dit distributions
reported by other researchers for the (100) and (111)Si face orientations
[20, 44, 48, 72–79]. The goal of this chapter is to provide reliable quantitative
information regarding the electrical behavior of (110)Si/SiO2 interface traps
as analyzed by three electrical techniques. To achieve this, Dit (E) and Nit are
evaluated in a comparative way on thermal Si/SiO2 structures for the three
low-index Si faces and, in aiming to link with structural/physicochemical
insight, compared to the density of interfacial Si dangling bonds (DBs, Pb
type centers) determined by ESR on identical samples. This quantitative
comparison of the (110)Si/SiO2 , (111)Si/SiO2 , and (100)Si/SiO2 interfaces
in terms of Pb density and Dit is carried out under well controlled Hpassivation conditions, which is a prerequisite for meaningful comparative
assessment.
3.2
Experimental details
3.2.1
Sample preparation
Samples were prepared by making use of the oxidation facility present in
the Leuven Semiconductor Physics Laboratory. Three batches of samples
were independently prepared by oxidation at 930 o C in dry O2 (nominal
hydrogen content <0.1 ppm) for times t=180–209 min of commercial nand p-type Si wafers with (110), (100) and (111) crystallographic surface
orientations and with doping levels in the range of 1×1015 –2×1016 cm−3 .
Prior oxidation, the Si samples were subjected RCA-type cleaning: This
implied, first, treatment in a H2 SO4 -H2 O2 (4:1) mixture for 10 min at
∼90 o C, which after rinsing in H2 O was followed by a dip in aqueous HF
(1 HF (49 %):9H2 O) for ∼30 s followed by rinsing in H2 O again. Next,
the samples were treated in mixtures of H2 O : H2 O2 : NH4 OH (5:1:1) and
H2 O : H2 O2 : HCl (5:1:1) both for 10 min at ∼70 o C followed by rinsing in
H2 O. All rinsings in water were carried out in ultrapure H2 O of resistivity
ρ(300 o C)>10 MΩcm.
After oxidation, the samples were allowed to cool down in unaltered ambient
with semiexponential temperature decay (cooling time constant of ≈200 s).
To avoid passivation of interface defects by traces of moisture in the room
ambient, the samples were unloaded after cooling the furnance to room
3.2 Experimental details
45
temperature. Control depassivation of some samples by annealing in high
vacuum (10−6 Torr, 30 min at 630 o C) affirms the absence of any detectable
defect passivation. The oxide thickness determined using spectroscopic
ellipsometry was in the range of 25−30 nm for (100)Si/SiO2 , 35–42 nm for
(110)Si/SiO2 and 45–50 nm for (111)Si/SiO2 .
The oxidized Si samples were split in two sets: The first one was left in the
as-oxidized state to exclude passivation of interface defects by hydrogen,
i.e., to ensure their maximal manifestation. The second set of samples
was passivated by 30 min annealing in H2 (1.1 atm) at 400 o C. Finally,
MOS capacitors were prepared by evaporation of Au electrodes of (0.8–
1.5)×10−4 cm2 area [80]. The back side contact to the Si substrate was
fabricated by evaporation of a thick (≈0.3 µm) Al blanket after removing
the native oxide from the backside of the wafer in 1 % aqueous HF solution.
The treatments in H2 were carried out before the metal contact deposition as
we intended to analyse the passivation reactions in molecular hydrogen with
possible disturbing interference associated with the generation of atomic
hydrogen, known to occur in metallized systems [81, 82].
3.2.2
Electrical measurements
Electrical measurements were performed at 77 K (in liquid nitrogen) and at
room temperature in the frequency range f=20 Hz−1 MHz using a HP4284A
precision LCR meter. The energy distribution of interface traps Dit (E) was
extracted using either the GV method according to Nicollian and Brews [44],
or the low frequency CV technique described by Berglund [48] (cf. chapter 2).
The total density of interface traps per unit area (Nit ) was then calculated by
integrating Dit (E) over the silicon band gap. In addition, the total interface
trap density Nit (physically integrated across the entire Si band gap) was
determined from the absolute difference between the flatband voltages VFB
inferred from 100 kHz CV curves taken on p- and n-type Si MOS-capacitors
at 77 K [60]. The latter method offers much better accuracy by eliminating
uncertainties related to surface potential calculations.
46
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
3.2.3
ESR spectroscopy
Results of electrical measurements were compared to the density of Si DBs
(Pb -centers) measured using ESR spectroscopy [75]. The ESR experiments
were conducted on the same samples (p-Si) as those used for electrical
measurements. The ESR spectra were taken at 4.2 K using a K-band
(≈20.5 GHz) spectrometer operated in the adiabatic slow passage mode
Absolute densities of Pb -type centers were determined by double numerical
integration of the recorded absorption-derivative ESR spectra using the
signal of a calibrated co-mounted Si:P marker (g=1.99869) as reference.
The attained absolute accuracy is estimated at better than 20 %.
3.3
Results and discussion
3.3.1
Dependence of interface properties on silicon orientation
Initial characterization of the samples was done using 100 kHz CV
measurements at 300 K. Typical results obtained for (100), (110) and
(111) orientations of the Si crystal substrates are shown in Figs. 3.2 and
3.3 for both n- and p-type samples. As indicated by arrows in panels (b)
and (c) in Fig. 3.3, p-type (110)Si/SiO2 and (111)Si/SiO2 samples exhibit
a peak in the capacitance associated with the response of interface traps.
Remarkably, this response is observed even at the 100 kHz frequency thanks
to the fast supply of the minority carriers (electrons) from the unmetallized
periphery of the MOS capacitors inverted by the positive fixed charge present
at the interface [73]. From CV curves measured at different frequencies
(Fig. 3.4.a), it is obvious that the value of Dit at the p-(110)Si/SiO2 interface
is quite high. In going from low to high frequency, the conductance peak
(Fig. 3.4.b) moves toward a gate bias approaching the flatband point. In
this figure, we notice there appears a discontinuity in the behavior of Gp /ω
versus frequency, with a reversal in the trend and an increase in stepping to
100 Hz. This reversal in trend is likely due to an artifact associated with
the increasing influence (for lower f) of a low level of leakage current in
inversion.
More detailed information was obtained from the analysis of the parallel
conductance (Gp )-to-angular frequency (ω=2πf) ratio as a function of
3.3 Results and discussion
47
1 .0
( 1 0 0 ) S i/S iO
C /C
o x
0 .8
f= 1 0 0 k H z
T m = 3 0 0 K
0 .6
0 .4
0 .2
0 .0
2
p -ty p e
-1 0
-8
-6
(a )
n -ty p e
-4
-2
0
2
4
6
8
1 0
1 .0
o x
0 .6
C /C
0 .8
0 .4
( 1 1 0 ) S i/S iO
0 .2
0 .0
2
f= 1 0 0 k H z
T m = 3 0 0 K
p -ty p e
-2 0
-1 5
-1 0
n -ty p e
-5
0
5
(b )
1 0
1 5
1 .0
( 1 1 1 ) S i/S iO
0 .6
f= 1 0 0 k H z
T m = 3 0 0 K
2
C /C
o x
0 .8
0 .4
0 .2
0 .0
p -ty p e
-2 0
-1 5
-1 0
(c )
n -ty p e
-5
0
5
G a te v o lta g e ( V )
1 0
1 5
Figure 3.2: 100-kHz CV curves measured at 300 K on (100)Si/SiO2 (a),
(110)Si/SiO2 (b) and (111)Si/SiO2 (c) n- and p-type samples.
frequency with the applied metal bias (VG ) used as parameter, for asoxidized (no passivation) p- and n-Si(110)/SiO2 samples measured at 300 K
(Fig. 3.5). The interface trap density Dit , the hole and electron trapping
time constants τp and τn , and the capture cross sections (σp , σn ) can be
determined from the Gp /ω curves by fitting the experimental data with the
statistical model of Nicollian and Brews [44] (cf. section 2.4, p. 28) which
accounts for the surface potential fluctuations. Then, the Dit (E) profile
48
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
013710-2
Thoan et al.
C/COX
1.0
0.8
(100)Si/SiO2
n-type
p-type
0.6
-10
-5
0
(a)
5
10
C/COX
1.0
0.8
(110)Si/SiO2
n-type
p-type
0.6
-20
-10
0
(b)
10
20
C/COX
1.0
(111)Si/SiO2
0.8
n-type
p-type
0.6
-20
-10
0
VOLTAGE
(V) (V)
Gate
voltage
10
FIG. 2. The parallel conductance 共G
as a function of frequency with th
oxidized p- and n-Si共110兲 / SiO2 sam
(c)
20
Results of electrical meas
density of Si DBs 共Pb-ce
FIG.Magnified
1. Magnified plots
normalized
100 kHz100
CV curves
at 300 measured
Figure 3.3:
plotsof of
normalized
kHz measured
CV curves
spectroscopy.15 The ESR exp
K on 共100兲Si/ SiO2 共a兲, 共110兲Si/ SiO2 共b兲, and 共111兲Si/ SiO2 共c兲 n- and
at 300 K p-type
on (100)Si/SiO
andthe(111)Si/SiO
2 (a),
2 (b),
samen-samples 共p-Si兲 as thos
samples. Vertical
arrows(110)Si/SiO
in panels 共b兲 and
共c兲 mark
capacitance 2 (c)
and p-type
samples.
Vertical
arrows
in
the
panels
(b)
and
(c)
mark
the The ESR spectra were
peak associated with interface trap response.
ments.
capacitance peak associated with the interface trap response.
共⬇20.5 GHz兲 spectrometer
perature. Control depassivation of some samples by annealpassage mode. Absolute den
ing in vacuum 共30 min at 630 ° C兲 affirms the absence of any
determined by double numer
can be determined
of the
a function
of
detectable after
defectcalculation
passivation.
Thesurface
oxide potential
thickness as
deterabsorption-derivative ESR sp
gate voltage.
The
latter
was
achieved
using
the
low
frequency
(20
Hz)
CV
mined using spectroscopic ellipsometry was in the range of
brated comounted Si:P mar
measurements
integration
(the
Berglund
integral
[48])
,
35–42
nm
for
共110兲Si/
SiO
,
25–30through
nm for numerical
共100兲Si/ SiO
The in
attained absolute accurac
2
2
combination
a determination
VFB
from
the
high-frequency
(1
MHz)
samples.
The
oxidized
Si
and with
45–50
nm for 共111兲Si/ofSiO
%.
2
CV curvesamples
(cf. sections
2.3.2inand
were split
two2.3.4).
sets: The first one was left in the
as-oxidized state to exclude passivation of interface defects
III. RESULTS
AND DISCUS
The Dit (E) profiles obtained by both CV and GV methods are compared
in
by hydrogen, i.e., to ensure their maximal manifestation. The
Initial characterization o
second set of samples was passivated by 30 min annealing in
100
kHz CV measurements
H2 共1.1 atm兲 at 400 ° C. Finally, MOS capacitors were pretained for 共100兲, 共110兲, and 共
pared by evaporation of Au electrodes of 共0.8– 1.5兲
strate crystal are shown in
⫻ 10−4 cm2 area.
samples. As indicated by arro
Electrical measurements were performed at liquid nitro共110兲Si/ SiO2 and 共111兲Si/ S
gen and room temperatures in the frequency range
the capacitance associated w
f = 20 Hz– 1 MHz using a HP4284A precision LCR meter.
traps.16–19 Remarkably, this r
The energy distribution of interface traps Dit共E兲 was exkHz frequency thanks to fast
tracted using either the ac conductance 共GV兲 method accord共electrons兲 from the unmetal
ing to Nicollian and Brews,21 or the low frequency CV tech22
pacitors inverted by the posi
nique described by Berglund. The total density of interface
interface.17
traps per unit area 共Nit兲 was then calculated by integrating
More detailed informatio
Dit共E兲 over the silicon band gap. In addition, the total intersis of the parallel conducta
face trap density Nit 共integrated across the Si band gap兲 was
共␻ = 2␲f兲 ratio measured at 3
independently determined from the absolute difference be-
3.3 Results and discussion
49
1 0 0
(a )
8 0
2 0
p - ty p e ( 1 1 0 ) S i/S iO 2
6 0
C
c
(n F /c m
2
)
4 0
2 0 H z
1 0 0 H z
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
tox = 3 8 .7 n m
(b )
2 0
1 5
1 0
G
c
/ ω( n F / c m
2
)
1 0 0 H z
1 K H z
1 0 k H z
1 0 0 k H z
1 M H z
5
0
-2 5
-2 0
-1 5
-1 0
-5
G a te v o lta te ( V )
0
5
Figure 3.4: (a) Multi-frequency CV curves and (b) conductance-to-angular
frequency ratio-voltage (G/ω-V), of as-oxidized p-Si(110)/SiO2 sample
measured at 300 K.
Fig. 3.6 for all three studied silicon orientations. The Dit (E) distributions
of as-oxidized samples clearly show two peaks, located at about 0.25 eV,
and about 0.85 eV above the silicon VB top.
Figure 3.7 compares the inferred trapping time constants (τp , τn ) and
capture cross sections (σp , σn ) of holes and electrons at (110), (111), and
(100)Si/SiO2 interfaces as a function of energy in the Si band gap. While both
τ and σ are strong functions of energy [83], it appears that near band edges
they are of the same order of magnitude. This suggests that the same kind
of electron/hole traps is present at all three interfaces, which is corroborated
with nearly identical shapes of the Dit (E) profiles. Nevertheless, it is worth
of mentioning here is that we also found a slight difference (∼0.05 eV) in
50
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
0 .6
(a )
p - ty p e ( 1 1 0 ) S i/S iO
2
2
G G p / p ω/ w ( µ( µF F / c / c m m 2) )
0 .5
V G = -4 .6 V
0 .4
0 .3
V G = -1 .8 V
0 .2
0 .1
0 .0
(b )
0 .5
V G = 0 .8 V
2
0 .3
2
G
p
0 .4
/ ω ( µF / c m
)
n - ty p e ( 1 1 0 ) S i/S iO
0 .2
V G = -1 .0 V
0 .1
0 .0
2
3
4
lo g [f ( H z ) ]
5
6
Figure 3.5: The parallel conductance (Gp )-to-angular frequency ratio as
a function of frequency, with the metal bias (VG ) used as parameter, of
as-oxidized p- and n-Si(110)/SiO2 samples measured at 300 K, (a) and (b),
respectively.
the interface trap distribution peak position between (100)Si/SiO2 and two
other interface orientations of silicon, a finding also recently suggested on
the basics of transient spectroscopy results [74].
Figure 3.8(a) compares 100 kHz CV curves of both p- and n-type
(110)Si/SiO2 samples measured at 300 K and 77 K. Upon cooling to 77 K,
the CV curve of the p-type sample shifts to a larger negative gate voltage
indicating the presence of donor-type traps in the lower half of the band
gap, while the CV curve of n-type sample shifts to a more positive gate
3.3 Results and discussion
1 0
51
1 4
S i/S iO
2
th e r m a lly g r o w n
T ox = 9 3 0
1 3
1 0
1 2
C
D
it
(c m
-2
e V
-1
)
1 0
o
1 0
1 0
1 1
1 0
0 .0
A s - o x id iz e d
(1 1 1 ) C
(1 1 1 ) G
(1 1 0 ) C
(1 1 0 ) G
(1 0 0 ) C
(1 0 0 ) G
0 .2
V
V
A fte r H
V
2
p a s s iv a tio n
(1 1 1 )
(1 1 0 )
(1 0 0 )
V
V
V
0 .4
0 .6
0 .8
E - E v (e V )
1 .0
Figure 3.6: Dit (E) profiles of Si/SiO2 interfaces derived from high-low
frequency CV (solid symbols) and GV (open symbols) methods in Si/SiO2
samples fabricated on (100), (110), and (111) faces of Si. Results for the
as-oxidized samples (no H-passivation) and those subjected to H2 passivation
(30 min anneal in 1.1 atm H2 at 400 o C) are shown for comparison.
voltage indicating that acceptor-type traps are present above the Si midgap.
The same behavior is seen in (111) and (100) samples, as illustrated in
Fig. 3.8(b) and (c).
The difference in VFB values between n- and p-type MOS capacitors
with equal thickness of the insulating layer contains the contributions
corresponding to the difference in the Fermi level, EF , in the n- and p-type
semiconductors and a contribution of interface traps (cf. Eq. 2.45, Chap. 2).
Nit is the interface trap density integrated over the energy interval between
Fermi levels EF (n-type) and EF (p-type), Cox is the oxide capacitance per
unit area. At 77 K, the Fermi level is positioned at about 30 meV above
the VB in the p-type silicon and at about 30 meV below the CB edge in
the n-type silicon. For the doping levels of the used Si wafers (1×1015 –
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
1 0
-2
1 0
-3
1 0
-4
1 0
-5
1 0
-6
1 0
-1 5
1 0
-1 6
1 0
-1 7
1 0
-1 8
-2
C a p tu r e c r o s s s e c tio n ( c m
(a )
(1 1 0 )
(1 0 0 )
(1 1 1 )
τp
0 .0
τn
(b )
(1 1 0 )
(1 0 0 )
(1 1 1 )
)
T r a p p in g tim e c o n s ta n t ( s )
52
σp
σn
0 .2
0 .4
0 .6
E - E v (e V )
0 .8
1 .0
Figure 3.7: Hole and electron trapping time constant (a), and the capture
cross section (b) in as-oxidized (110) (111) and (100)Si/SiO2 entities as a
function of energy in the Si band gap.
2×1016 cm−3 ), the difference in VFB between 77 K CV curves of n- and
p-type samples corresponds to a shift in Fermi level over 1.1 eV in the Si
band gap at 77 K (1.16 eV), i.e., nearly over the entire Si band gap at 300 K
(1.12 eV) as illustrated in Fig. 3.9. Then, the total density of interface traps
Nit across Si band gap can be evaluated from the difference between the
VFB values inferred from 100 kHz CV curves taken on p- and n-type Si
MOS-capacitors at 77 K (Fig. 3.8) according to Eq. 2.46, Chap. 2.
The Nit evaluation using Eq. 2.46 does not require additional surface
potential calculations helping to attain better accuracy. Moreover, at
low temperature, the thermal emission of carriers from most of the traps is
negligible, making it easy to attain high-frequency CV curves thus improving
accuracy of the measurements. The Nit value inferred from Eq. 2.46 for
the (110)Si/SiO2 interface is (6.7±0.5)×1012 cm−2 . As outlined, Nit can
3.3 Results and discussion
53
1 .2
(1 1 0 )S i/S iO
1 .0
2
o x
0 .8
C
c
/C
0 .6
0 .4
1 0 0 k H z
s o lid s y m b o l: 7 7 K
o p e n s y m b o l: 3 0 0 K
0 .2
0 .0
-2 5
-2 0
-1 5
( 1 1 1 ) S i/S iO
1 .0
-1 0
(a )
-5
0
5
G a te v o lta g e ( V )
1 0
1 5
2 0
2
C /C ox
0 .8
0 .6
0 .4
1 0 0 k H z
s o lid s y m b o l: 7 7 K
o p e n s y m b o l: 3 0 0 K
0 .0
-3 0 -2 5 -2 0 -1 5 -1 0
-5
0
5
G a te v o lta g e ( V )
0 .2
1 .0
( 1 0 0 ) S i/S iO
(b )
1 0
1 5
2 0
2
0 .6
C
c
/C
o x
0 .8
0 .4
0 .2
0 .0
1 0 0 k H z
s o lid s y m b o l: 7 7 K
o p e n s y m b o l: 3 0 0 K
-1 2 -1 0
-8
-6
-4
-2
0
2
4
G a t e v o lt a g e ( V )
6
(c )
8
1 0
1 2
Figure 3.8: Normalized 100 kHz CV curves measured at 300 K (open symbols)
and 77 K (solid symbols) of n- and p-type (110), (111), and (100)Si/SiO2
samples (a, b, c), where Cox is the oxide capacitance per unit area.
54
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
Ec
300 K
Ec
E
77 K
E
EF(n)
EF(n)
EF
EF
EF(p)
( )
Ev
EF(p)
Ev
Figure 3.9: The shift of the Fermi level in n- and p-type Si relative to the
interface trap energy distribution caused by sample cooling from 300 K to
77 K. The probed energy range is indicated by arrows.
Table 3.1: Density of Pb0 centers, Dit peak values, and (Nit )1/2 , the integral
of Dit obtained from GV measurements over the upper (n-type) and lower
(p-type) half of the Si bandgap at the Si/SiO2 interface obtained from the
present work.
Si orientation
(100)
(100)
(110)
(110)
(111)
(111)
Type
p
n
p
n
p
n
[Pb0 ]
12
(10 cm−2 )
1.0±0.2
6±1
5±1
(Dit )peak
12
(10 cm−2 eV−1 )
3.1±0.3
2.5±0.3
10±2
11±2
48±10
20±5
(Nit )1/2
(1012 cm−2 )
0.7±0.2
0.8±0.2
1.8±0.5
2.2±0.8
4±1
3.0±0.8
also be estimated by integrating Dit (E) profiles extracted from CV and GV
methods over the Si band gap, yielding Nit values of (5±1)×1012 cm−2 and
(4±1)×1012 cm−2 (cf. Table 3.1), respectively. The latter values obtained
from CV and GV methods are distinctly lower than the result obtained
from difference between VFB values (n- and p-type) at 77 K, because of the
wider energy range covered by the latter method as illustrated in Fig. 3.9.
We also found that the density of the donor traps below Si midgap and
of acceptor traps above Si midgap are equal within the accuracy of our
measurements.
3.3 Results and discussion
3.3.2
55
Comparison with ESR results
d P µ/d B ( a r b . u n its )
Next, the electrical results are compared to the ESR data. The latter
reveal the occurence of only one type of paramagnetic defects at the
(110)Si/SiO2 interface as can be seen from the ESR spectrum taken at
4.2 K on (110)Si/SiO2 (Fig. 3.10), exhibiting a prominent Pb0 signal of
axial symmetry with g matrix principal values g// =2.0079 and g⊥ =2.0018,
corresponding to a density of unpaired spins (assuming S=1/2 centers)
[Pb0 ]=(6±1)×1012 cm−2 . Therefore, the two broad peaks observed in Dit (E)
are likely related the Pb0 centers revealed by ESR analysis, as was inferred
previously for (111) and (100)Si faces [76–78, 84]. In previous research, the
Pb0 defect was identified as trivalent interfacial Si, denoted Si3 ≡ Si• , where
the dot symbolizes an unpaired electron in a dangling sp3 < 111 >-like
orbital [53, 79].
Pb0
B // [110]
20.57 GHz
Si:P marker
g = 2.0038
Tox = 930 °C
7 3 0 0
7 3 1 0
Magnetic field (G)
7 3 2 0
7 3 3 0
7 3 4 0
7 3 5 0
7 3 6 0
Figure 3.10: K-band derivative-absorption ESR spectrum observed at
T=4.2 K with the applied magnetic field aligned along the normal to the
(110)Si/SiO2 interface, showing the signal with characteristic signature of
Pb0 defects. The spectrum was measured using an incident microwave power
≈0.2 nW and field modulation amplitude ≈0.3 G. The label Si:P denotes a
marker signal from a co-mounted Si:P marker sample.
56
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
3.3.3
Hydrogen passivation of Si dangling bonds
To assess the relative contribution of the Pb0 centers to the interface trap
density, we also investigated the electrical traps in the hydrogen-passivated
samples. It is known that nearly all Si DBs can be passivated by annealing in
H2 as revealed by their elimination from the ESR spectrum, a fact which has
also been affirmed here by ESR measurements of Pb0 centers at (110)Si/SiO2
interface. The mechanism of Pb defect passivation in molecular hydrogen
can be explained by the simple chemical reaction [85]:
Pb + H2 → Pb H + H,
(3.1)
or, indicating the Pb defect structure explicitly,
Si3 ≡Si• + H2 → Si3 ≡ Si − H + H.
(3.2)
The passivation of interfacial Si DBs (Pb -type centers) by hydrogen is a
well known and standard technological procedure, but for (110)Si/SiO2 it
has not been quantified before. Figure 3.4 compares Dit (E) of all three
Si/SiO2 interfaces grown at 930 o C, prior to and after H2 passivation. The
results clearly show that the density of Dit is reduced more than one order
in magnitude after passivation. Then it is evident that most of interface
traps at all three (110), (111) and (100) Si faces are removed after hydrogen
annealing. For (110) orientation, the value of Nit after passivation as
determined from Eq. 2.46 was (7±1)×1010 cm−2 . As the vast majority
of interface traps, like Pb0 centers, can be effectively passivated by H2
annealing, it is highly likely that the Pb defects are responsible for most of
the interface traps observed on (110)Si face, in line with the (100)Si/SiO2
and (111)Si/SiO2 cases.
3.3.4
Discussion
As the electrical results on the passivated samples show that most of the
interface traps in the as-oxidized samples are related to the amphoteric Si
DB type defects (Pb0 -centers), each of them should contribute two trap
levels to the Dit (E). Would all DBs contribute to Dit (E), the total density
of interface traps Nit integrated over Si band gap is then expected be double
of the Pb density, i.e. Nit ≈ 2[Pb ]. Vertical arrows indicate the effect of
3.3 Results and discussion
1 3
8 x 1 0
1 2
6 x 1 0
1 2
4 x 1 0
1 2
2 x 1 0
1 2
(1 1 1 )
A s - o x id iz e d
H 2 p a s s iv a tio n
o
T ox= 9 3 0
C
(1 1 0 )
T ox= 9 3 0
o
C
(1 1 0 )
T ox= 1 1 5 4
N
it
(c m
-2
)
1 x 1 0
57
o
C
(1 1 0 )
T ox= 6 9 8
(1 0 0 )
T ox= 9 3 0
o
C
o
C
0
0
2 x 1 0
1 2
4 x 1 0
1 2
1 2
6 x 1 0
[P b (0 )] (c m
-2
8 x 1 0
1 2
)
Figure 3.11: Electrically active defect density Nit of Si/SiO2 interfaces
compared to [Pb ] obtained from ESR. The data for the (110)Si/SiO2
interfaces grown at Tox =698 o C and 1154 o C are also shown for
comparison. The solid line denotes the ratio Nit /[Pb(0) ] ≈2, expected from
isolated amphoteric centers. The bold arrow indicates the trend found in
(110)Si/SiO2 when the oxidation temperature is decreased. Vertical arrows
indicate the effect of hydrogen passivation treatment (1.1 atm; 400 o C;
30 min) on Nit for the same samples.
hydrogen passivation treatment (1.1 atm H2 ; 400 o C; 300 min) on Nit for
the same samples.
To assess the validity of the above picture, Fig. 3.11 shows the total density
of interface traps Nit , determined from the difference in flatband voltages
of n- and p-type MOS capacitors at 77 K, as a function of DB density
[Pb ] measured by ESR on the samples in the as-oxidized state. In addition
also are shown the Nit and [Pb ] results for (110)Si/SiO2 samples grown
by silicon oxidation at Tox =698 o C and 1154 o C. The expected from the
amphoteric behavior, the ratio Nit : [Pb(0) ] ≈ 2 : 1 is observed for the (100)
and (111)Si faces but not for the (110) face. For (110)Si/SiO2 oxidized at
930 o C, the ratio is less, perhaps approaching 1:1, meaning that less (only
about one half) of Pb defects do act as charge trapping centers. Comparing
58
Chapter 3: Interface state energy distribution and Pb defects at (110)Si/SiO2 interfaces
(110)Si/SiO2 interfaces grown at different Tox , one may notice that with
lowering Tox , there is a trend that Nit decreases while [Pb0 ] is increasing
(cf. arrow in Fig. 3.11). Thus, at a lower oxidation temperature, a larger
fraction of Pb0 defects are not detected as rechargeable interface traps. In the
context of the exposed similarity of the three low-index Si/SiO2 interfaces in
terms of occurring Pb(0) -type interfacial defects, and the gathered detailed
understanding about their electrical behavior and atomic nature, this finding
regarding the (110)Si/SiO2 interface defects may come as a surprise, indeed.
Since this effect is found in both n- and p-type (100)Si/SiO2 samples, we
hypothesize that electrical inactivation of a significant density of Si DBs
as interface traps is caused by the Coulomb blockage when the electric
field of one charged defect precludes capture of a charge carrier of the
same sign by the neighboring traps. Such effect earlier observed for the
oxide hole traps near the (100)Si/SiO2 interface [86] would require areal
trap densities in excess of 1013 cm−2 , which is higher than the occurring
density of Pb0 centers in (110)Si/SiO2 . Therefore, we suggest that Pb0
centers at (110)Si/SiO2 interface are clustered, and this trend becomes more
pronounced with lowering of the oxidation temperature.
3.4
Conclusions
In summary, the interface trap density Dit (E) of (110), (111) and
(100)Si/SiO2 systems has been analyzed by conductance and capacitance
methods. It is found that Dit is highly sensitive to the Si face orientation,
highest for the (111) face, and lowest for the (100) face, with (110)Si/SiO2
closely resembling the (111)Si/SiO2 case. Two peaks in the Dit (E) profile
within Si band gap, at about 0.25 eV and 0.85 eV above the VB, are
observed for all three orientations and appear to be strongly correlated with
Pb interface defects, responsible for the majority of amphoteric interface
traps. While the atomic nature and the energy distribution of the traps at
the studied interfaces are much identical, comparison between the density
of the Si DB defects (Pb0 -centers) and the areal density of (110)Si/SiO2
interface traps reveals that not all Pb0 s are acting as charge traps. We
suggest clustering of the interfacial Si DB defects as the possible mechanism
of electrical inactivation of part of the Pb0 -centers in (110)Si/SiO2 .
Chapter 4
Correlation between interface
traps and paramagnetic
defects in c-Si(100)/a-Si:H
heterojunctions
In this chapter, low-temperature (77 K) CV measurements are proposed
as a technique to quantify the densities of charge traps in c-Si/a-Si:H
heterojunction solar cell structures. By comparing the inferred trap densities
to the results of ESR spectroscopy we found that the dangling bonds of
silicon atoms at the surface of the (100)Si substrate (Pb0 centers) and in the
a-Si:H layer (D-centers) provide the most significant contributions to the
density of traps. The content of this chapter has been partially published
in the Applied Physics Letters [80].
4.1
Introduction
Solar cells based on heterojunctions of crystalline Si with amorphous
hydrogenated silicon (c-Si/a-Si:H) attract considerable attention as they
allow one to reach high quantum efficiency (>20 %) while keeping a low
thermal budget that helps to reduce manufacturing costs [87, 88]. Figure 4.1
shows a typical hetorojunction solar cell structure using amorphous
59
60
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
Ag
80 nm
10 nm
5 nm
300 m
ITO
p+ a-Si:H
ii-a-Si:H
a Si:H
i-a-Si:H
 n-type (100)Si wafer 
5 nm
10 nm
50 nm
100 nm
i-a-Si:H
n+ a-Si:H
ITO
Agg
i-a-Si:H
Figure 4.1: Schematic diagram of a heterojunction solar cell
hydrogenated silicon, a-Si:H, as a passivation layer. A crucial contribution
8
to the success of these devices has to come from efficient passivation of
c-Si/a-Si:H interfaces aimed at sufficiently reducing the density of defects
acting as recombination centers (traps). Obviously, further fundamental
improvement of the c-Si/a-Si:H cells can be achieved if the inherent density of
recombination centers can be suppressed at the onset, a goal which requires
information regarding the atomic nature of the defects in the c-Si/a-Si:H
heterostructures as well as a reliable way to quantify their density. It has
recently been suggested [89] that the presence of interface traps in c-Si/aSi:H heterojunctions can be revealed by frequency-dependent capacitance
measurements. However, the problem of quantification remains unsolved
because one needs to make assumptions about the value of the electron (or
hole) capture cross section to estimate the trap density. Moreover, were
traps of more than one type be present in the heterostructure, this procedure
would become entirely unreliable.
In this chapter we will show that CV measurements at cryogenic
temperatures (77 K) enables determination of the trap densities both at the
c-Si/a-Si:H interface and inside the a-Si:H layer. Furthermore, by comparing
the electrical results to ESR spectroscopy data, we found that the dominant
contribution to the trap density in the (100)Si/a-Si:H entities is provided
by the Si DB defects at the (100)Si interface (Pb0 centers) and in the a-Si:H
layer (D-centers).
EXPERIMENTAL DETAILS
4.2
61
Experimental details
The studied samples were prepared on hydrogen-terminated n- and p-type
(100)Si (ND , NA ≈1015 cm−3 ) substrates by plasma-enhanced chemical
vapor deposition (PECVD) of intrinsic a-Si:H layers from a silane precursor.
The thicknesses of the latter layers range from 7 to 56 nm as determined
by spectroscopic ellipsometry. These were subsequently capped by PECVD
of a 20-nm thick p+ -doped a-Si:H layer using SiH4 and B2 H6 precursors.
To enable electrical characterization, aluminum electrodes were deposited
onto the p+ -a-Si:H layer by thermoresistive evaporation. A blanket layer
of evaporated Al was used as the backside contact to the silicon substrate.
Through the whole processing, the sample temperature did not exceed
180 o C. For ESR analysis, slices of 2×9 mm2 main area were cut from
p-(100)Si/i-a-Si:H (56 nm)/p+ -a-Si:H(20 nm) or p+ -a-Si:H(20 nm)/i-aSi:H(10 nm)/p-(100)Si/i-a-Si:H (10 nm)/p+ -a-Si:H(20 nm) structures (not
metallized), with their 9-mm edge along a <011> direction. Typically,
about ten were stacked in a sample bundle. Sample cutting damage was
removed by selective wet chemical etching (CP4). Immediately before each
ESR measurement, the native Si oxide was removed from back- and side
wall through dipping the sample in aqueous HF (1 %).
The CV measurements were conducted at 300 K and 77 K in the frequency
range of 1 to 103 kHz using an HP4284A LCR meter. Conventional first
absorption-derivative ESR spectra, dPµr /dB (where Pµr is the reflected
microwave power), were measured at 4.2 K using a K-band (≈20.5 GHz)
spectrometer driven in the adiabatic slow passage mode, for various
directions of the applied magnetic field B, at angle ϕB with the [100] sample
normal, in the (011)Si plane. The amplitude Bm of the applied sinusoidal
magnetic field modulation (∼100 kHz) and applied microwave power Pµ
were carefully limited so as to avoid any noticeable signal distortion. The
densities of ESR-active centers were determined by making use of a comounted calibrated Si:P marker sample [g(4.2 K)=1.99869±0.00002; spin
S=1/2] through double numerical integration of the, generally computersimulated, dPµr /dB spectra. The obtained absolute and relative accuracies
are estimated at ≈20 % and 10 %, respectively. Reliable assignment
(separation) of overlapping signals is obtained through making full use
of field angular dependent measurements, that is, exploiting the difference
between anisotropic (e.g., Pb0 center) and isotropic signals (e.g., D line)
(see below).
62
4.3
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
Experimental results and analysis
Figures 4.2 and 4.3 show multi-frequency curves measured at 300 K and
77 K on Al/p+ -a-Si:H/i-a-Si:H/n-Si(100) capacitors with i-a-Si:H thicknesses
of 28 nm and 54 nm, respectively. The CV curves measured at 300 K
(Figs. 4.2(a), and 4.3(a)) are significantly distorted by the leakage current
across the i-a-Si:H passivating layers. The high electrical conduction suggests
+
A l/p - a - S i/2 8 n m
T m = 3 0 0 K
0 .3
i- a - S i/c - S i
C ( µF / c m
2
)
0 .4
1 0 0 k H z
1 M H z
0 .2
0 .1
(a )
0 .0
+
A l/p - a - S i/2 8 n m
T m = 7 7 K
i- a - S i/c - S i
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
C ( µF / c m
2
)
0 .3
0 .2
0 .1
(b )
0 .0
-1 .0
-0 .5
0 .0
0 .5
1 .0
1 .5
2 .0
G a te v o lta g e (V )
Figure 4.2: Multifrequency CV curves measured at 300 K (a) and 77 K
(b) on a Al/a-Si:H(p+ ; 20 nm)/i-a-Si:H(28 nm)/n-(100)Si sample. Arrows
indicate the direction of the voltage sweep.
4.3 Experimental results and analysis
63
Al/p+-a-Si(20 nm)/i-a-Si(54 nm)/n-Si(100)
0.15
300 K
C (F/cm2)
1 kHz
10 kHz
0.10
100 kHz
1 MHz
0.05
(a)
0.00
0.15
C (F/cm2)
77 K
0.10
0.05
(b)
0.00
-1
0
1
2
VOLTAGE (V)
Figure 4.3: Multifrequency CV curves measured at 300 K (a) and 77 K
(b) on a Al/a-Si:H(p+ ; 20 nm)/i-a-Si:H(54 nm)/n-(100)Si sample. Arrows
indicate the direction of the voltage sweep.
that the interface barriers for electrons and holes at the c-Si/a-Si:H interface
are low and that the thermal generation rate in i-a-Si:H is high, which is
consistent with the 1.7-eV wide bandgap of the i-a-Si:H film found from
Figure 1.
spectroscopic ellipsometry data (not shown). In the voltage range between
0.5 and 1 V one observes a frequency dispersion similar to that reported
in Ref. [89]. However, the trap density determination in the presence of
leakage becomes unreliable because the equilibrium trap occupancy cannot
be guaranteed. Upon lowering the CV measurement temperature to 77 K
(Figs. 4.2(b) and 4.3(b)) the picture changes drastically: One observes well
64
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
behaving CV curves with little frequency dispersion in accumulation and
depletion, while in the inversion region the capacitance behavior reflects
the minority carrier supply from the inversion layer at the periphery of
the metal contact [76]. The observed hysteresis in the CV data is quite
remarkable and suggests trap recharging in the intrinsic a-Si:H layer, which
at 77 K acts as a classical insulator in the MOS capacitor structure [44].
The MOS-like behavior of the Si/a-Si:H/Al samples observed at 77 K makes
possible the extraction of the c-Si flatband voltage VFB that can further
be used to determine the trapped charge density. As mentioned previously
(chapters 2 and 3), the difference in VFB values between n- and p-type
MOS capacitors with equal thickness of the insulating layer contains the
contributions corresponding to the difference in the Fermi level, EF , in
the n- and p-type semiconductors and a contribution of the interface traps
(cf. Eqs. 2.45 and 2.46, where Cox is replaced by capacitor of the intrinsic
a-Si:H layer Ci-a-Si:H = ε0 κSi /di-a-Si:H ). Therefore, by comparing 77 K CV
traces in n- and p-type Si samples one can determine the total interface
trap density integrated over the entire Si bandgap Nit .
Application of this approach is exemplified in Fig. 4.4 which shows 77 K
100-kHz CV curves observed on n- and p-type Si/a-Si:H/Al structures with
a ≈54–56 nm thick i-a-Si:H insulator. Figure 4.5 shows the corresponding
plots of [(Cacc /C)2 − 1] as a function of gate bias, from which VFB can be
extracted (cf. section 2.3.4, Chap. 2). The observed difference in VFB of
≈2 V between the n- and p-type samples, as inferred from the CV traces
recorded with the voltage swept from accumulation to depletion, corresponds
to an interface trap charge density number of Nit ≈1×1012 cm−2 within the
c-Si bandgap. In addition, the 77 K CV curves exhibit a hysteresis of 0.33
and 0.43 V in the n- and p-type samples, respectively. As no CV curve
hysteresis is observed at 77 K in c-Si/SiO2 /metal capacitors (chapter 3), it
is probably caused by re-charging of defects in the i-a-Si:H layer.
ESR spectrum shown in Fig. 4.6(a) reveals a dominant Pb0 signal at
g=2.006 superimposed with weaker signals at g=2.0055 and at g=2.009.
As expected, upon rotation of the magnetic field (ϕB =55o ) with respect
to n, the Pb0 line splits in two as illustrated in Fig. 4.6(b): It appears to
exhibit anisotropy [75] characteristic for DBs of c-Si atoms at the interface
with a-Si:H. The two other lines show no anisotropy and, therefore, are
ascribed to defects in the a-Si:H layer. The line at g=2.0055 corresponds to
Si DBs in a-Si:H, known as the D center [90], while the origin of the defect
4.3 Experimental results and analysis
65
1 .0
p - S i( 1 0 0 )
n - S i( 1 0 0 )
C /C
a c c
0 .8
0 .6
0 .4
0 .2
0 .0
T = 7 7 K
f = 1 0 0 k H z
-2
-1
0
1
2
G a te v o lta g e ( V )
Figure 4.4: 100 kHz CV curves measured at 77 K on n- and p-(100)Si/aSi:H(intrinsic, 54−56 nm)/a-Si:H(p+ , 20 nm)/Al structures. Arrows
indicate the direction of the voltage sweep.
8 0
(C
a c c
2
/C ) -1
i- a - S i: H ( 5 4 n m )
n -ty p e
p -ty p e
T m = 7 7 K
1 2 0
4 0
0
-1 .5
-1 .0
-0 .5
0 .0
0 .5
G a t e v o lt a g e ( V )
1 .0
1 .5
Figure 4.5: Plots of [(Cacc /C)2 − 1] as a function of gate bias for n- and p(100)Si/i-a-Si:H(54 nm)/a-Si:H(p+, 20 nm)/Al structures. VF B is evaluated
by extrapolation of the plots to zero ordinate value. Arrows indicate the
direction of the voltage sweep.
66
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
dPμr/dB (arb. units)
B || [100] (ϕB = 0°)
(a)
Pb0
6 K; 20.4 GHz
g = 2.006
Si:P
g = 1.99869
g = 2.009
7240
ϕB = 55°
6 K; 20.4 GHz
7260
7280
7300
(b)
3/4 Pb0
dPμr/dB (arb. units)
g = 2.0074
g = 2.009
Si:P
g = 1.99869
1/4 Pb0
g = 2.0018
7240
7260
7280
7300
7320
Magnetic field (G)
Figure 4.6: K-band (≈20.5 GHz) ESR spectra measured at 6 K (Pµ =25 nW;
Bm =1.3 G) on a p-(100)Si/a-Si:H(intrinsic, 56 nm)/a-Si:H(p+ -doped,
20 nm) sample with (a) the magnetic field B oriented along the [100] normal
n to the sample surface (magnet angle ϕB =0o ) and (b) at angle ϕB =55o
with n showing the splitting up of the Pb0 signal in two parts with intensity
ratio 1:3 for the latter field orientation. The signal at g=1.99869 stems from
a co-mounted calibrated Si:P marker sample. The dotted curves represent
optimized total spectra simulations, obtained as sums of the individual
simulated component signals.
4.3 Experimental results and analysis
1 .2
67
A l/a - S i( p + ) /i- a - S i:H / c - S i
T m = 7 7 K , f = 1 0 0 k H z
1 .0
C /C
a c c
0 .8
0 .6
i- a - S i:H th ic k n e s s ( n m )
1 4
2 8
5 4
0 .4
0 .2
0 .0
0 .0
0 .5
1 .0
1 .5
2 .0
G a te v o lta g e ( V )
Figure 4.7: 100 kHz CV curves measured at 77 K on Al/a-Si:H(p+ ;
20 nm)/a-Si:H(intrinsic)/n-(100)Si samples as a function of the physical
thickness of the intrinsic a-Si:H layer. Arrows indicate the direction of the
voltage sweep.
at g=2.009 remains as yet unknown. For the corresponding defect densities,
we obtain: [Pb0 ]=(1.4±0.3)×1012 cm−2 , [D]=(4.6±0.3)×1011 cm−2 , and
[g=2.009]=(1.6±0.3)×1011 cm−2 .
It is instructive to compare the densities of traps inferred from the
77-K CV measurements to the densities of ESR active defects. Figure 4.7
shows 77-K CV curves measured at 100 kHz on n-Si(100)/i-a-Si:H/p+ -aSi:H/Al with different i-a-Si:H thickness (14, 28 and 54 nm). The 77-K CV
curve hysteresis voltage in the n-Si(100)/i-a-Si:H/p+ -a-Si:H/Al capacitors
depends on the physical thickness of the intrinsic a-Si:H layer parabolically
as illustrated in Fig. 4.8 by the open circles. This would suggest that most
of the observed traps are uniformly distributed across the a-Si:H layer [21].
Given this result, the density of trapped charges responsible for the 0.43-V
CV curve hysteresis in the p-type c-Si/a-Si:H sample can be estimated as
≈8×1011 cm−2 , corresponding to a volume trap density of 1.2×1017 cm−3 .
Taking into account that every DB represents an amphoteric center and
is expected to trap two electrons when the Fermi level is swept from the
valence to the conduction band of silicon, the resulting defect density of
≈4×1011 cm−2 coincides with the density of D-centers detected by ESR.
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
Al
1.4
di-a-Si
p+-a-Si:H
0.3
i-a-Si:H
Vhysteresis (V)
68
Vfb (V)
1.3
0.2
c-Si
1.2
0.1
1.1
Al/p+-a-Si:H/i-a-Si:H/n-Si(100)
1.0
0
10
20
30
40
50
0.0
di-a-Si:H (nm)
Figure 4.8: Flatband voltage deduced with the gate voltage swept from
accumulation to inversion () and hysteresis data ( ) extracted from
100 kHz CV curves, all measured at 77 K on Al/a-Si:H(p+ ; 20 nm)/i:aSi:H/n-(100)Si samples as a function of the physical thickness of the i:a-Si:H
layer. The dashed curve illustrates the VF B shift expected for the case of recharging of ∼1.2×1017 traps/cm3 distributed uniformly across the i-a-Si:H
film, while the solid line represents a least square linear fit used to infer the
interface fixed charge density (slope). The inset shows the sample structure.
With respect to this CV level sweeping, we may add one more remark:
Because both the Pb0 and D centers concern DBs of the same atom (Si),
one may expect that their electron occupancy will be identical since the
energy levels are expected to be close in c-Si and a-Si, so resulting in similar
sweeping and charging of defects.
Figure 4
The revealed correspondence of the 77-K CV curve hysteresis to the density
of Si DBs in the i-a-Si:H layer also allows us to evaluate the possible impact
of the Fermi level position in the c-Si substrate on the density of these
defects –as postulated in the so-called “defect-pool model” [91]. As already
mentioned above, the 77-K CV curve hysteresis in p-c-Si samples is larger
than in the n-type ones suggesting a somewhat (≈30 %) higher DB density
in the i-a-Si:H film on p-Si. However, this value corresponds to only about
4.3 Experimental results and analysis
69
10 % of the charge trapped at the a-Si:H/c-Si interface and, therefore, is
considered as insignificant given that one observes wafer-to-wafer variations
of comparable value. Nevertheless, the indicated 10 % value may be currently
accepted as the inaccuracy limit of the interface trapped charge density
determination from the VFB difference between n- and p-type c-Si samples.
The density of the observed paramagnetic Pb0 centers comes close to the
Nit found in the c-Si gap from the comparison of 77-K CV curves measured
on the n- and p-type samples. However, this result is unexpected since,
as mentioned above, one DB defect (Pb0 center) may trap two electrons
when the Fermi level is swept across the c-Si gap. Thus, Nit which is
routinely inferred from the net variation of the trapped charge density
[44, 45], is expected to be a factor of two higher than the Pb0 density. Yet,
as already reported for the (110)Si/SiO2 interface (Chapter 2), with lowering
of the interface formation temperature, one observes a transition from the
Nit ≈2[Pb0 ] trend to Nit ≈[Pb0 ], suggesting that the Si dangling bonds may
form close pairs. In this case, due to Coulomb repulsion, only one of the
centers in a pair can be charged positively or negatively, but both centers,
in the neutral state, will contribute to the ESR signal.
The available series of measurements for different thickness of the a-Si:H layer
(di−a−Si:H ) also offer the possibility to estimate the density of the effective
fixed charge often invoked in the analysis of a-Si:H/c-Si heterojunctions
[92, 93]. From Eq. (10.10) in Ref. [44], we have the dependence of VFB on
thickness of i-a-Si:H layer and the net interface charge
VFB − ∆Φms = −
Q0
Ci-a-Si:H
=−
Q0
di-a-Si:H
ε0 κi-a-Si:H
(4.1)
where the net interface charge Q0 = q.N0 is the sum of the “fixed oxide
charge” and the charge of interface traps, di-a-Si:H is the thickness of the
intrinsic Si layer, and Φms is the work function difference between the metal
and the semiconductor.
From the slope of the VFB dependence on di-a-Si:H observed on the n-type
c-Si samples (cf. symbol in Fig. 4.8) the net interface charge, i.e., the
sum of the fixed oxide charge and the charge of interface traps, is found
to be negative and equal to 0.42×1012 electrons/cm2 . This value is to be
compared to the density of the net negative charge on amphoteric DB traps
(Pb0 centers) of ∼0.5×1012 electrons/cm2 inferred from the VFB difference
between n- and p-type samples at 77 K. This suggests that the density of the
70
Chapter 4: interface traps and paramagnetic defects in c-Si(100)/a-Si:H heterojunctions
fixed charge does not exceed 1011 electrons/cm2 which would be consistent
with the results of simulations (see Fig. 2 in Ref. [93]).
One may also wonder about the finding that a considerable density of Si
DB defects is still observed despite growing the Si/a-Si:H samples in an
ambient abundant of H-containing precursors, i.e., SiH4 , B2 H6 , and H2 :
Why not reaching a higher level of DB passivation? This, we believe, is a
consequence of Si-H bond dissociation because the plasma discharge, applied
during a-Si:H deposition to enable reduction of the growth temperature,
emits a high intensity of vacuum ultraviolet photons with energies exceeding
the threshold value for photodissociation of Si-H bonds (∼7.9 eV) [94, 95].
Thus, considerable fraction of the Si DB defects will remain un-passivated
and are observed in the present study as the ESR-active Pb0 and D-centers.
To be noted here is that no annealing steps were performed after the a-Si
deposition −this to limit the number of processing steps to a minimum in
order to improve on sample reproducibility needed for reliable defect density
quantification. Post-deposition anneals have been shown to have a significant
effect such as observed in the increase of the minority carrier lifetime [96–
98], and by implication, in reducing the (electrically active) interface state
density. The elimination of un-passivated Si DB defects in c-Si/a-Si:H
structures would explain the reported lowering of the recombination rate,
indicating that the development of an efficient passivation strategy emerges
as a critical issue in improving the efficiency of c-Si/a-Si:H solar cells –an
obvious area where the currently proposed interface trap characterization
methodology may find application.
4.4
Conclusions
To conclude, we propose a simple and physically transparent method to
evaluate and quantify the interface trap density in Si/a-Si:H heterojunctions.
This provides a powerful analysis tool that can be used to optimize the solar
cell processing. As a first application, we found that the dominant traps
in (100)Si/a-Si:H stacks fabricated by low-temperature (<180 o C) PECVD
are associated with DBs of silicon atoms either positioned at the (100)Si
interface of the substrate crystal or in the a-Si:H layer.
Chapter 5
Chemical kinetics of hydrogen
passivation and dissociation
reactions of Ge dangling bonds
at the Si0.25Ge0.75/SiO2
interface
5.1
Introduction
Silicon-germanium (SiGe) materials and devices have been investigated for
more than 50 years [see, e.g., Refs. 25–27]. Due to its large hole mobility and
adjustable band gap, SiGe is a good candidate for a high mobility channel
material in novel CMOS devices [28, 29]. The use of Ge-rich SiGe alloys as
channel materials in future MOSFETs shows promise for improvement of
the electrical performances of these devices. Up to now, SiGe is still a hot
topic, attracting the attention of many research groups all over the world.
Silicon Germanium-on-Insulator (SGOI) is a new technology combining the
benefits of two advanced technologies: conventional Silicon-on-Insulator
(SOI) technology and SiGe technology. This approach has enabled the
integration of SiGe devices on Si wafers, using Si, SiGe and SOI technologies.
However, a major issue related to high-mobility semiconductors is the
71
72
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
presence of a large density of defects at their interface with gate insulators,
lying in 1012 –1013 cm−2 range [99–101]. These defects are detrimental to
electronic properties of heterostructure devices, and should be reduced to
the ∼1010 cm−2 level.
Recently, a large density (maximally about 1013 per cm2 of sample area) of Ge DB type defects has been observed by ESR on
(100)Si/SiO2 /(100)Si1−x Gex /SiO2 heterostructures grown by the condensation technique for x ranging from 0.55 to 0.75 [102, 103]. The defects can
be equally monitored quantitatively by ESR and the CV technique (see
Ref. [104]). Much helped by the acquired knowledge on Si Pb defects at
the (100)Si/SiO2 interface, the defect, termed GePb1 , has been tentatively
attributed to a Pb1 -like defect, i.e., a Ge DB at a strained Ge–Ge or
Ge–Si dimer at the interface. The maximum density of Ge DBs was found
at Si1−x Gex /SiO2 interfaces with Ge concentration in the range 70–75 %
[102, 103].
The Si DB-type interface defects in the Si/SiO2 entity, Pb -type centers
as identified by the ESR technique, form an archetypal dominant source
of detrimental interface traps [79]. For decades, it is known that Si Pb
DBs can be efficiently passivated by annealing in H2 to device grade
level (≤1010 cm−2 eV−1 ) [53, 79], the goal of the standard industrial
anneal in forming gas (∼10 % H2 in N2 ). The kinetics of hydrogen
passivation/depassivation of Si Pb defects at the Si/SiO2 interface are
well described by the generalized simple thermal (GST) model [105–107],
providing, among others, insight about the optimal passivation range.
Thinking in device terms, one may then wonder about the feasibility to
inactivate the interfacial Ge DBs through similar kinds of treatment. Would
it be reasonable to expect a close similarity in the passivation behavior of
topologically like DB defects, i.e., Si Pb and GePb1 , positioned at seemingly
isomorphic Si/SiO2 and Si1−x Gex /SiO2 interfaces. Here, doubts have been
raised [108, 109].
In this work, we have applied such study on the passivation in molecular H2
of interfacial Ge DBs. By combining electrical and ESR characterizations,
we have investigated the kinetics of the hydrogen passivation and defectH dissociation processes at (100)Si0.25 Ge0.75 /SiO2 interfaces. However, in
contrast to the case of Si Pb -type defects, hydrogenation is found not to be
an effective way of passivating GePb1 defects. Using the GST model, we
will show that, compared to the Si Pb case, the existence of larger spreads
EXPERIMENTAL DETAILS
73
in the activation energies for passivation and dissociation are at the origin
of a drastic reduction in the GePb1 passivation efficiency.
5.2
Experimental details
5.2.1
Sample preparation
Samples studied are condensation-grown (100)Si /SiO2 /(100)Si1−x Gex /SiO2
SGOIFabrication
entities obtained
from
IMEC, Leuven
SGOI
substrates
by (Courtesy of Dr. L. Souriau).
The condensation technique [29, 110] (cf. Fig. 5.1) starts from epitaxially
Ge condensation technique
q
Ge
SiGe
SOI
1
SiO2
SiO2
SiGe
SiO2
BOX
(Si)Ge
BOX
Si1-xGex
BOX
Si
Si
Si
Si
Epitaxial
deposition of
Si1-xGex (x≈0.27)
High Temperature dry oxidation
→Si selective oxidation
2
→Ge trapping between oxide
Si
BOX
3
Ge condensation
+ Thermal oxide removal
4 SGOI
(a)
 Epitaxial deposition of SiGe (20%Ge) layer on silicon on insulator (SOI)
wafer.
 Selective oxidation of Si and trapping of Ge between the two oxide that
leading to Ge enrichment of SGOI.
 Competition
C
titi
b t
between
G pile-up
Ge
il
att top
t
SiG /SiO2 interface
SiGe/SiO
i t f
andd Si-Ge
Si G
intermixing by diffusion. Ideally in a complete oxidation a pure crystalline GOI
27
layer should be obtained.
(b)
Figure 5.1: (a) Fabrication process of a SGOI structure by the
Ge condensation technique and (b) Cross-section transmission electron
micrograph of a SGOI wafer with 93 % Ge fabricated by the Ge condensation
technique.
74
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
growing a Si0.73 Ge0.27 layer (104 nm thick) on a Si(22 nm)/SiO2 /(100)Si SOI
wafer. This is followed by growing of a thin (6 nm) epi-Si layer intended to
prevent any Ge oxidation during the early stage of the thermal condensation
process. The latter consists of subjecting the structure to a three-step dry
oxidation (1150 o C, 1000 o C, 900 o C) process with intermediate annealing in
inert (Ar) ambient for selected times [110, 111]. Through selective oxidation
of Si and trapping of Ge between bordering Si oxide layers, this results in
the formation of a thinner Ge-enriched SiGe layer. In this process, there
is competition between Ge pile-up at the top SiGe/SiO2 interface, where
oxidation is carried through, and Si-Ge intermixing by diffusion. Etching to
partly remove the top SiO2 layer is the final step.
The parent sample obtained was cut into small pieces (∼10×15 mm2 for
CV measurements and 2×9 mm2 for ESR measurements) and subjected
to further treatment before each CV or ESR measurement. The variation
in the density of electrically active GePb1 defects under thermal treatment
has been assessed in two ways: (1) Through monitoring the induced shift in
threshold voltage ∆VT = −Qit /CTOX , where Qit is the inferred (negative)
charge at the interface; (2) in parallel, at some ‘checkpoints’, the density
of paramagnetic GePb1 centers was also measured by conventional X band
ESR (8.91 GHz) at 4.2 K. Yet, routinely, CV monitoring is used rather than
ESR because of sensitivity/versatility reasons.
Thermal cycles, both isochronally and isothermally, were carried out by
annealing samples in hydrogen or vacuum (pressure p≤2×10−6 mbar). An
isochronal passivation cycle consisted of subjecting a set of sample slices
(fresh slices for each step) for a fixed time (36 min) to passivation in
H2 (99.9999 %; 1.05 atm) at selected temperatures (Tan s) in the range
95–500 o C. An isothermal cycle consisted of submitting one sample (one
for each Tan ) at fixed temperature Tan to sequential passivation steps for
various times tan , each time followed by intermediate CV measurement.
Three (Tan =180 o C; 227 o C; 240 o C) and four (Tan =330 o C; 348 o C; 371 o C;
396 o C) isothermal cycles were performed in H2 and vacuum, respectively.
Before each subsequent annealing step of an isothermal cycle, the sample
was always cleaned, including removal of the metal contacts needed for
previous CV measurement. Each time, upon finishing a passivation cycle,
the sample was resubmitted to exhaustive dehydrogenation at 375 o C.
Upon the measurement, the retrieval of the initial [GePb1 ] value, i.e.,
Nit,in =(8±0.5)×1012 cm−2 (per sample area), thus assures that over the
5.2 Experimental details
75
various handlings, nothing irreversible had happened to the GePb1 system.
For the study of defect-H dissociation in vacuum (2×10−6 Torr), a set
of slices was initially (exhaustively) passivated in H2 at 409 o C (41 min)
resulting in an interface trap density Nit =(3±0.5)×1012 cm−2 , in agreement
with measured GePb1 densities.
Prior to the thermal passivation/dissociation cycling, as a test, as-received
slices were subjected to vacuum isochronal (34 min) treatments up to 425 o C
(cf. Fig. 5.5, open circles); no change was observed in Nit compared to the
initial value Nit =(8±1)×1012 cm−2 , providing a solid basis for the further
study. One reference isochronal cycle was also performed by annealing fresh
samples in vacuum for 34 min at different temperatures (up to 450 o C) to
verify whether additional interfacial Ge DBs are created by the annealing
steps. The concern here stems from such detrimental effect observed for the
Pb -type defect case at the Si/SiO2 interface [84, 112].
5.2.2
CV measurements
The density of electrically active defects at the Si1−x Gex /SiO2 interface
was extracted from CV measurements performed on MOS capacitors at
77 K (in liquid nitrogen) in the frequency range of 1 to 103 kHz using an
HP4284A LCR meter. It has been shown from CV measurements that
the SiGe layer obtained by the Ge condensation technique is naturally a
p-type semiconductor [104]. An ESR active GePb1 defect at SiGe/SiO2
behaves as an acceptor trap. It is neutral when empty, and negatively
charged when occupied by an electron. The energy level of this state is
close to the top of the VB in the semiconductor bandgap [113, 114]. To
enable electrical measurements, gold electrodes were deposited on the top
oxide layers by thermoresistive evaporation. The electrical behavior of the
structures was characterized by measuring the capacitance between a metal
electrode and the substrate Si crystal with the SiGe film connected to the
substrate by a metal (InGa alloy) ( coined “pseudo MOSFET” approach,
as shown in the inset in Fig. 5.3) [104]. Due to variations in the electrical
conduction of the thin SiGe layer, one can get frequency dispersion in the CV
curve when (RSiGe CBOX )−1 approaches ω=2πf (where f is the frequency of
the small alternating signal). When (RSiGe CBOX )−1 << 2πf, the measured
capacitance C = Cmin = (1/CTOX + 1/CBOX )−1 .
76
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
In the metal bias range corresponding to accumulation in the SiGe layer,
where (RSiGe CBOX )−1 >> 2πf, the measured capacitance corresponds to
that of the top oxide, defined as CTOX . However, when the thin Si1−x Gex
film is fully depleted, it contains no mobile carriers to respond to the ac
probing signal resulting in a decrease of the capacitance. This transition
from the conducting to the depleted state of the Si1−x Gex film is seen as a
drop on the CV curve at a “threshold” voltage ∆VT that can be used to
determine the negative interface charge Qit =−∆VT CTOX . The number of
interface trapped charge per unit area can be extracted as Nit =∆VT CTOX /q.
5.2.3
ESR measurements
Conventional first absorption-derivative ESR spectra, dPµ /dB (where Pµ is
the reflected microwave power), were measured at 4.2 K using a K-band
(≈20.5 GHz) spectrometer driven in the adiabatic slow passage mode, for
various directions of the applied magnetic field B, at angle ϕB with the [100]
sample normal n, in the (01̄1)Si plane. The amplitude Bm of the applied
sinusoidal magnetic field modulation (∼100 kHz) and applied microwave
power Pµ were carefully limited so as to avoid any noticeable signal distortion.
The densities of ESR-active centers were determined by making use of a
co-mounted calibrated Si:P marker sample [g(4.2 K)=1.99869±0.00002; spin
S=1/2] through double numerical integration of the, generally computersimulated, dPµ /dB spectra.
5.3
Experimental results and interpretation
5.3.1
CV vs ESR probing
Figure 5.2 compares, as a function of Ge concentration, the density of
negative charge (squares), Nit , calculated from ∆VT CV data taken at
77 K, and ESR-active GePb1 defects measured at 4.2 K on as-prepared
(100)Si/SiO2 /Si1−x Gex /SiO2 /SiO2 structures; the same samples were used
for both methods. As concluded before [104], this demonstrates the excellent
one-to-one correspondence, also quantitatively, of the interface trap (negative
charge) density, Nit , obtained from CV shift measurements and the density
of GePb1 defects determined by ESR, pointing to detection of one and the
5.3 Experimental results and interpretation
1 2
1 2
8
[G e P b1] (1 0
1 2
8
6
6
4
4
2
2
0
0
0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
G e c o n c e n tr a tio n ( % )
8 0
9 0
1 0 0
N u m b e r o f n e g a tiv e ly c h a r g e d tr a p s N
1 0
)
1 0
c m
-2
-2
)
1 4
E S R a t 4 .2 K
c m
[G e P b1] fro m
1 2
1 4
1 6
C V a t 7 7 K
(1 0
N it f r o m
it
1 6
77
Figure 5.2: Ge content dependence of the negative charge density Nit
extracted from CV curve shifts at 77 K, and the density of GePb1 defects
measured by ESR. The GePb1 data, except for x=75 %) were taken from
Refs. [103, 104].
same defect system by both methods. As mentioned, for the current all
round investigation of the hydrogen passivation/dissociation kinetics of the
Ge interface defect (trap), we have chosen a SGOI sample with x=75 % Ge.
Figure 5.3 shows multi-frequency CV curves observed on the as-received
(100)Si/SiO2 /(100)Si0.25 Ge0.75 /SiO2 entity. The resistance of the SiGe
layer, RSiGe , as function of gate voltage and frequency is also shown in
the inset. Because the threshold voltage is shifted to the right, we can
conclude that Qit is negative charge trapped at the SiO2 /SiGe interfaces.
Figure 5.4(a) shows 100 kHz CV curves measured at 77 K on an as-received
(100)Si/SiO2 /(100)Si0.25 Ge0.75 /SiO2 entity and after H2 passivation at
Tan =96, 300 or 375 o C for 36 min. The decrease of ∆VT after annealing in
H2 (Fig. 5.4(a)) indicates a reduction of negative charge at the interfaces.
The values of Nit estimated from the shift in threshold voltage ∆VT are
(8±1)×1012 and (3±0.5)×1012 cm−2 for the as-received sample and after
passivation at 375 o C, respectively. As discussed before, these values compare
very well with those inferred from ESR measurements.
78
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
Figure 5.3: Multi-frequency CV curves observed at T=77 K on the asprepared (100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2 entity. Arrows indicate
the direction of the voltage sweep. The resistance of the SiGe layer as
function of frequency and gate voltage is shown in the inset.
On the other hand, figure 5.4(b) presents some first-derivative X-band ESR
spectra of the GePb1 center measured at 4.2 K for B//n on as-prepared
(top trace) (100)Si/SiO2 /(100)Si0.25 Ge0.75 /SiO2 and after treatment in H2 at
375 o C. Remarkably, no Si Pb type defects are observed in this sample. For
this relative magnetic field direction (B//[100] interface normal), the Ge DB
signals are observed at g=2.0138±0.0003 and with ∆Bpp (X-band)≈10.5 G.
In previous work [103], the model suggested for the interfacial Ge DB
defects is GePb1 , i.e. Si–Ge• =Ge2 or Ge–Ge• =Si2 , where the symbol •
and the em dash represent a DB and a strained bond, respectively. The
figure illustrates the effect of the H2 treatment process on the Ge DB ESR
signal observed on the SGOI sample. Some relative densities of the defects,
[GePb1 (Tan )]/[GePb1,in ], are plotted (crosses ×) in Fig. 5.5, where [GePb1,in ]
and [GePb1 (Tan )] represent the observed densities on the sample in the
as-received state and after a passivation treatment in H2 at temperature
Tan , respectively.
5.3 Experimental results and interpretation
79
1 .0
N o r m a liz e d c a p a c it a n c e
0 .8
0 .6
a s - r e c e iv e d
o
T an= 9 6 C
0 .4
T an= 3 0 0
0 .2
0 .0
(a )
0
T an= 3 7 5
1 0
2 0
o
C
o
C
S i 0 .2 5 G e 0 .7 5 / S i O
3 0
4 0
5 0
G a te v o lta g e ( V )
8 .9 1 G H z ; 4 .2 K
g = 2 .0 1 3 8
B //[1 0 0 ]
d P µ/ d B ( a r b . u n i t s )
6 0
7 0
2
8 0
g = 1 .9 9 8 6 9
a s - r e c e iv e d
3 7 5
3 1 2 0
(b )
o
C p a s s iv a te d
S i
G e
G e
G e
3 1 4 0
3 1 6 0
3 1 8 0
M a g n e t ic f ie ld ( G )
3 2 0 0
Figure 5.4: (a) 100 kHz capacitance-voltage curves observed at T=77 K
on an as- prepared (100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2 entity and after
passivation at Tan =96, 300 or 375 o C for 36 min. Arrows indicate the
direction of the voltage sweep. The shift of the CV curves to the left
indicates a reduction of interface defects after annealing in hydrogen; (b)
First derivative X-band ESR spectra observed on an as-prepared (top trace)
(100 )Si/SiO2 /(100 )Si0 .25 Ge0 .75 /SiO2 entity and after treatment in H2 at
375 o C (B//[100] interface normal). The signal at g=1.99868 stems from
a co-mounted Si:P marker. Also shown is a ball-and-stick picture of the
proposed atomic model of the interfacial GePb1 defect.
80
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
The inferred areal density of GePb1 defects on the as-received sample is
(10±2)×1012 cm−3 (per sample area), in agreement with Nit data. A
separate ESR check after removing the top oxide layer showed that the
GePb1 density per sample area is reduced by factor of two, confirming that
the two interfaces are identical.
To be mentioned also is that, as modelled, ESR observes the defect in its
neutral charge state –the GePb1 center– while CV traces negative charge.
A GePb1 defect behaves as an acceptor trap in Ge-rich SiGe. It is neutral
when empty and negatively charged when it has trapped an (extra) electron
[113, 114]. As concluded before [104, 114], most of the interface traps at
the interface of Ge-rich SiGe/SiO2 have their energy level very close to the
VB, so even at 77 K, most of the traps are negatively charged. That is the
reason why we always observe negative charge by CV at 77 K. However,
because the energy level is still above the VB [104, 114], then, when cooling
down to 4.2 K, most of the GePb1 defects become neutral as the bandgap
widens (from 0.66 to 0.75 eV in Ge) and the Fermi level moves towards the
SiGe VB top edge.
5.3.2
Passivation and dissociation: isochronal
Figure 5.5 shows, as a main result, an overview of the results of isochronal
passivation in H2 (36 min, full squares) and dissociation in vacuum (34 min;
open squares) as a plot vs. Tan of VT (Tan )/VT,in = Nit (Tan )/Nit,in , that is,
the change in number of interface traps, Nit , relative to the initial value
Nit,in , for the range 25 < Tan ≤ 500 o C. As to the passivation process, the
results from cross checking ESR (crosses) and CV measurements are seen
to be in good agreement.
Noteworthy aspects in Fig. 5.5 include: (a) GePb1 defect passivation already
initiates from Tan ≈120 o C onward, a fairly low temperature; (b) With
increasing Tan of passivation, Nit (Tan ) decreases monotonically to reach a
minimum at Tan =375 o C, above which the passivation efficiency appears
to regress; (c) Even for the “optimum” Tan , the passivation efficiency is
disappointing, only reaching inactivation of ∼60 % of defects. A separate
check indicated that this situation does not alter for Tan =600 o C; (d)
Dissociation initiates from ∼325 o C onward, to monotonically increase up
to 425 o C, where Nit,in is reached again; (e) For annealing in vacuum at
temperatures higher than ∼425 o C, we notice an increase in defect density
5.3 Experimental results and interpretation
1 .6
81
R e fe r e n c e : V a c . a n n e a l ( 3 4 m in )
P a s s iv a tio n ( H 2, 3 6 m in )
1 .4
V a c . d e p a s s iv a tio n ( 3 4 m in )
1 .2
( T a n ) / ∆V T , i n
[ G e P b 1 ( T a n ) ] / [ G e P b 1 ,in ]
1 .0
0 .8
∆V
T
0 .6
0 .4
0 .2
0 .0
0
1 0 0
S G O I (7 5 % G e )
2 0 0
3 0 0
4 0 0
o
A n n e a lin g t e m p e r a t u r e T a n ( C )
5 0 0
Figure
5.5:
Relative
shift
of
the
threshold
voltage
∆VT (Tan )/∆VT,in =Nit (Tan )/Nit,in
and
relative
GePb1
density
[GePb1 (Tan )]/[GePb1,in ] (crosses) vs.
Tan of isochronal heating in
1.05 atm H2 (solid squares, crosses) and vacuum (open symbols).
above the initial as-received sample value, pointing to degradation of the
SiGe/SiO2 interface. A similar effect has been observed for the Si/SiO2
entity, isolated by ESR as creation of interfacial Pb -type defects [84, 112].
There, in the case of Pb defect creation at the (111)Si/SiO2 interface,
degradation was found to initiate from ∼640 o C onward [112], that is,
substantially higher than ∼425 o C. We thus find the Ge0.75 Si0.25 /SiO2
interface to be more sensitive to thermally induced degradation by annealing
in vacuum.
5.3.3
GST model
In the following, we will assume, in analogy to the case of the Pb center
at the Si/SiO2 interface, that the passivation and dissociation processes
of GePb1 centers correspond to the formation/cracking of GePb1 -H bonds
82
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
according to the chemical reactions
kf
GePb1 H + H,
GePb1 + H2 −→
(5.1)
k
d
GePb1 H −→
GePb1 + H,
(5.2)
for passivation of GePb1 in molecular H2 and GePb1 -H dissociation in
vacuum, respectively. Then, also in analogy with the Si Pb center case,
the reaction kinetics scheme of GePb1 passivation in H2 and GePb1 -H
dissociation can be consistently described by the generalized simple thermal
(GST) model [105–107, 115]; In this model the kinetics of the passivation
and dissociation reactions are described by the following rate equations
d[GePb1 ]/dt = −kf [H2 ][GePb1 ],
(5.3)
d[GePb1 ]/dt = kd (N0 − [GePb1 ]),
(5.4)
where t is the time, [H2 ] is the volume concentration of H2 molecules
at the interface SiGe/SiO2 , N0 the maximum number of GePb1 centers
present (maximum number of GePb1 centers observable by ESR after
exhaustive depassivation treatment), and kf and kd the rate constants of
the corresponding reactions. The temperature dependence of the first-order
rate constants are given by the Arrhenius expressions
kf = kf0 exp(−Ef /kT),
(5.5)
kd = kd0 exp(−Ed /kT),
(5.6)
where k is the Boltzmann constant, and kf0 , kd0 and Ef , Ed represent,
respectively, the pre-exponential factors and the characteristic activation
energies for the passivation and dissociation reactions.
With respect to defect passivation in H2 , basic ingredients of the model
include: (a) H2 is physically absorbed into the SiO2 layer and diffuses
molecularly among the accessible interstices in the a-SiO2 network, including
the reaction site at the interface defect center; (b) diffusion proceeds rapidly,
so the passivation is defect-H2 reaction limited; (c) on their way towards
the interface, no preliminary cracking of H2 molecules at internal sites in
the SiO2 occurs. The interface defect reacts directly with the H2 molecule.
For the kinetic analysis of these GePb1 passivation/depassivation processes,
we assume, as demonstrated before as being the physical reality for the
Si Pb defect case [105, 106], that the activation energies have Gaussian
distributions around the mean values Ef and Ed with standard deviations
σEf and σEd , respectively. Solving the rate equations (Eqs. 5.5 and 5.6)
5.3 Experimental results and interpretation
83
above, the kinetics for the reactions have been found accurately described by
the following generalized expressions [105, 106] for passivation by annealing
in H2
1
[GePb1 ]
=√
N0
2πσEf
Z ∞
0
(Efi − Ef )2
Efi
exp −
+ tkf0 [H2 ]exp(− )
2
kT
2σEf
dEfi ,
(5.7)
and for dissociation in vacuum starting from condition [GePb1 ](t=0) = 0
[GePb1 ]
1
=1− √
N0
2πσEd
Z ∞
0
exp −
(Edi − Ed )2
Edi
+ tkd0 .exp(−
)
kT
2σE2d
dEdi .
(5.8)
A Gaussian distribution of activation energies, reflecting back in a
distribution of rate constants centered around some average value at
each temperature, gives rise to a non-simple exponential rate process. In
order to obtain reliable kinetics parameters, all experimental data (both
isothermal, isochronal passivation/depassivation) have to be fitted as a
whole consistently.
An importance quantity needed in the description of defect passivation
by hydrogen is the concentration of hydrogen at the interface for a
particular pressure, pH2 , of supplied molecular hydrogen ambient. As
verified experimentally, hydrogen diffuses molecularly through a-SiO2 , and
the diffusion proceeds very rapidly, as shown by Shelby [116]. Accordingly,
the interfacial concentration of H2 during passivation is taken equal to the
physical solubility of H2 in bulk vitreous silica taken at the temperature of
passivation treatment. Thus, the concentration of H2 is calculated by the
approximate equation inferred from the work of Shelby [116]
[H2 ](cm−3 atm−1 ) = 2.639 × 1017 + 5.439 × 1021 exp(−(T/2.415)0.4299 ).
The supply of H2 is considered unlimited.
(5.9)
Figure 5.6 presents the temperature dependence of the H2 concentration at
the interface, calculated using the above equation for pH2 (ambient)=1.05 atm.
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
3 .0 x 1 0
1 8
2 .5 x 1 0
1 8
2 .0 x 1 0
1 8
1 .5 x 1 0
1 8
1 .0 x 1 0
1 8
5 .0 x 1 0
1 7
p H ( a m b ie n t ) = 1 .0 5 a tm
2
[H
2
] a t in te r fa c e ( c m
-3
)
84
0 .0
0
1 0 0
2 0 0
3 0 0
4 0 0
T e m p e ra tu re ( C )
o
5 0 0
6 0 0
Figure 5.6: Temperature dependence of the H2 concentration at the interface,
calculated using Eq. 5.9 [cf. Ref. 116] for pH2 (ambient)=1.05 atm.
5.3.4
Passivation and dissociation: isothermal
As noticed before with respect to the extensive ESR study on the hydrogen
interaction kinetics, passivation [115] and dissociation [85] of Pb centers
at the (111)Si/SiO2 interface, the isochronal study only is insufficient for
meaningful analysis of the kinetics. The complementation of this with
various isothermal cyclings for a set of well balanced temperatures, and then
with self consistent interpretation of all data en bloc is seen as essential
to enable inference of reliable (unique) kinetic parameters; For example,
within the GST description of dissociation (Eq. 5.8), three kinetic parameters
should be inferred independently. This cannot be undubiously achieved from
a single isochronal annealing cycle only because of the intertwined influence
Ed and kd0 have in Eq. 5.8, preventing unbiased parameter extraction.
Obviously, the same holds for the defect passivation study. The necessity of
such approach must not be overlooked.
Accordingly, various isochronal cyclings were performed. Figure 5.7(b)
shows the normalized relative threshold voltage shifts ∆VT (Tan )/∆VT,in
=Nit (Tan )/Nit,in observed for three isothermal heating cycles in H2
(1.05 atm) carried out at 180 o C, 227 o C, and 240 o C (accuracy ±2 o C)
for extended times. In turn, Fig. 5.8(b) shows four experimental defect-H
5.3 Experimental results and interpretation
N o r m a l i z e d ∆V T ( T a n ) / ∆V T , i n
1 .2
Is o c h r o n a l p a s s iv a tio n ; t = 3 6 m in
1 .0
E x p e r im e n ta l d a ta
G S T f ittin g
F u ll in te r a c tio n
S T m o d e l
0 .8
0 .6
0 .4
0 .2
0 .0
N o r m a l i z e d ∆V T ( t ) / ∆V T , i n
85
(a )
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
o
A n n e a lin g te m p e r a tu r e ( C )
Is o th e r m a l p a s s iv a tio n
1 .0
0 .8
6 0 0
T an = 1 8 0
o
C
T an = 2 2 7
o
C
T an = 2 4 0
o
C
0 .6
0 .4
0 .2
(b )
0 .0
0
1
2
3
4
5
6
4
A n n e a lin g tim e ( 1 0 s )
7
8
Figure
5.7:
Relative
threshold
voltage
shift
∆VT (Tan )/∆VT ,in =Nit (Tan )/Nit,in under isochronal (a) and isothermal
(b) (3 cycles) heating in H2 (1.05 atm). The error bars for each data
point represent the spread over five to ten measurements. The solid curves
represent the optimal fits of the GST model (using the kinetics parameters
listed in table 5.1) taking into account that an amount of ∼20 % of charge
traps does not take part in the passivation. The dotted curve in panel (a) is
a fit for the ST model using the same parameter values listed in table 5.1,
but with spread σEf =0 (single valued Ef ), exposing the inadequacy of such
description. The dashed curve, describing reality, represents the fitting of
the full interaction GST model taking into account the simultaneous action
of passivation and dissociation.
86
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
N o r m a l i z e d ∆V T ( T ) / ∆V T , i n
1 .2
0 .8
0 .6
0 .4
σEd=0
0 .2
0 .0
0
N o r m a l i z e d ∆V T ( t ) / ∆V T , i n
Isochronal dissociation, t = 34 min
(a)
1 .0
1 0 0
2 0 0
4 0 0
5 0 0
6 0 0
Annealing temperature ( C)
o
Isothermal dissociation
(b)
1 .0
3 0 0
0 .8
0 .6
0 .4
T = 396 °C
T = 371 °C
T = 348 °C
T = 330 °C
0 .2
0 .0
-0 .2
0
1
2
3
4
5
6
7
8
Vacuum annealing time (10 s)
4
9
1 0
Figure 5.8: Recovery of GePb1 defects under isochronal dissociation by
vacuum annealing for 34 min (a) and isothermal dissociation at four
temperatures (b). All experimental data were normalized to meet the starting
condition that [GePb1 ]=0. The error bars for each data point represent the
spread over five to ten measurements. The solid curves present the optimized
self consistent fittings of the GST model, from which the inferred parameters
listed in Table 5.1 are obtained. The dotted curve in panel (a) corresponds
to a fitting for the ST model using the same parameter values as tabulated in
table 5.1, but with spread σEd =0 (single valued Ed ), exposing the inadequacy
of the ST description.
5.3 Experimental results and interpretation
87
dissociation cycles (heating in vacuum) taken in the temperature range 330–
396 o C. In each case, the isochronal temperatures were chosen sufficiently
low to enable convenient tracking of the changing trap densities over an
appropriately extended time window. In each case also, the date were
normalized for the ∼20 % part of charge traps immune to hydrogen
interaction (vide infra).
5.3.5
GST model interpretation
Before proceeding to data interpretation, it needs to be remarked that, as
routinely done for, e.g., the case of Si Pb defect in Si/SiO2 , the analysis
of the GePb1 -hydrogen interaction kinetics is carried out on the basis that
in either dominant kinetic (temperature) regime, i.e., defect passivation or
dissociation, there is no significant perturbing influence of the unavoidable
simultaneously occurring reverse reaction (cf. Eq.5.1 vis-à-vis Eq. 5.2),
particularly so for the case of passivation: As both processes are thermally
activated, both will of course always happen simultaneously (occur in
parallel), although, as is the case here, with strongly different probabilities
depending on Tan and the difference in characteristic activation energies (Ef ,
Ed ). Thus, for example, for the independent analysis of passivation kinetics
in H2 over, say, the range ∼100–370 o C, the influence on the “passivation”
data by simultaneously occurring (reverse) dissociation should be negligibly
small over the whole Tan range considered.
If so, this then enables the prime approach where each part of the kinetics,
passivation or dissociation, is in first instance fully interpreted independently
on the basis of Eqs. 5.7 and 5.8, respectively, over a set of fully representative
data. Fortunately, this can be achieved reliably as well evidenced post hoc by
the obtained results (vide infra, cf. Table 5.1). Effectively, in this approach,
this means that one must restrict to the appropriate anneal temperature
range. As it emerges, this can be easily and reliably selected from the insight
obtained from the full interaction case analysis (cf. paragraph 5.3.6).
Also, in interpreting, it is assumed that in the study of dissociation in
vacuum any potential perturbing influence of repassivation of GePb1 defects
by atomic H released elsewhere in the sample (cf. Eq. 5.2) is considered
negligible. As discussed before [105], this premise appears of little concern
based on considerations about the behavior of H, H2 in SiO2 .
88
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
As to Pb defects in (111)Si/SiO2 the parameters inferred for the forward
passivation reaction are the activation energy Ef =1.51 eV, its spread
σEf =0.06 eV, and the rate constant pre-factor kf0 =9.8×10−8 cm3 s−1 ,
and, analogously, Ed =2.83 eV, σEd =0.08 eV, kd0 =1.6×1013 s−1 for the
dissociation reaction [105]. As mentioned above, we analyzed the current
results with the Si Pb GST defect model. And indeed, as a main
result, we found that the GePb1 data can be well described by the GST
model, provided that we assume there is an amount of ∼ 20 % of charge
traps –henceforth referred to as the immune part– not taking part in the
passivation/dissociation cycling. This conclusion follows consistently from
the fitting of all data, including passivation and dissociation. Compared
to the case of Si Pb at the (111)Si/SiO2 interface, this finding comes as
a surprise. Indeed, at the Si/SiO2 interface, for both (111) and (100)
orientations, the Pb defect system may adequately be passivated in H2
to levels far below the ESR detection limit. The origin for the partially
Table 5.1: Inferred parameters within the GST model for the kinetics of
thermal passivation in H2 and dissociation activation in vacuum of GePb1
(GePb1 -H) defects at (100)SiGe/SiO2 interfaces, in comparison with Si Pb
defects at standard thermal (111)Si/SiO2 interfaces (Tox ∼ 970 o C)) and Si
Pb1 defects at (100)Si/SiO2 interfaces.
GePb1
at (100)SiGe/SiO2
Si Pb (a)
at (111)Si/SiO2
Si Pb1 (b)
(c)
at (100)Si/SiO2
PASSIVATION
Ef (eV)
1.44±0.04
σEf (eV)
0.2±0.02
kf0 (cm3 s−1 )
11(+5/-8)×10−9
1.51±0.04
0.06±0.004
9.8(+8/-5)×10−8
1.57±0.04
0.15±0.03
(1.43±0.6)×10−6
DISSOCIATION
Ed (eV)
2.23±0.04
2.83±0.04
σEd (eV)
0.14±0.02
0.08±0.03
kd0 (s−1 )
(1.5±1)×1013
(1.6±0.5)×1013
(a) Ref. [85, 105, 115]
(b) Ref. [117]
(c) Thermally grown at Tox =176 o C
-
5.3 Experimental results and interpretation
89
non-addressability by H passivation in the case of the current Ge traps may
not be directly evident; it will be dealt with more in depth later.
Passivation of GePb1 defects
The fitting of the GST passivation model for the GePb1 system is illustrated
in Fig. 5.7, compiling all relevant results. Here, the data shown have been
normalized for the 20 % of immune charge traps. Self consistent fitting of
equation 5.7 to the isochronal passivation data together with those from
the three independently measured isothermal cycles (cf. Fig. 5.7), gives
the results Ef =1.44±0.04 eV, σEf =0.2±0.02 eV, for kf0 =1.1(+0.5/-0.8)
×10−8 cm3 s−1 . Figure 5.7(a) illustrates a successful fitting (solid curve) for
the isochronal passivation process. To be added here is that for the isochronal
passivation fitting, only data points for Tan ≤355 o C have been used, the
temperature region where the influence of simultaneous dissociation is still
negligible (vide infra). The figure also shows a calculated ST model fitting
using the same activation energy Ef =1.44 eV, but now single valued without
spread σEf , showing that the ST model is totally inadequate for a realistic
description of the current GePb1 passivation kinetics. The same conclusion
was obtained before for the case of Si Pb -type defects at Si/SiO2 interfaces
[115, 117].
In turn, the solid curves in Fig. 5.7(b), showing the relative threshold voltage
shifts ∆VT (Tan )/∆VT,in = Nit (Tan )/Nit,in for the isothermal passivation
cycles performed (heating in 1.05 atm H2 at three temperatures), represent
the successful consistent fittings of the GST model over all three isothermal
cycles. The estimated values of H2 volume density at the SiGe/SiO2
interface, used for the fitting, are 7.09×1017 cm−3 , 5.63×1017 cm−3 and
5.33×1017 cm−3 at 180, 227 and 240 o C respectively.
The inferred activation energy Ef =1.44 eV is found to be comparable to that
of the Si Pb defect at the (111)Si/SiO2 interface (cf. Table 5.1). However,
for the GePb1 case, the spread σEf on Ef is ∼2.5 times higher, and the
pre-exponential factor for the passivation rate constant is ∼10 times smaller.
90
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
Dissociation of GePb1 -H
One isochronal cycle with anneal time t=34 min (Fig. 5.5), and four
isothermal dissociation cycles (Tan =330, 348, 371 and 396 o C, respectively)
have been carried out in vacuum. For the interpretation, we assume that
the processes start at the condition [GePb1 ]=0, then a normalization step
has been done for all experimental data.
As outlined above, prior to starting dissociation studies, the as-received
samples were initially, as ‘zero’-setting step, “exhaustively” passivated
at ∼409 o C (∼41 min), the temperature value being chosen to establish
the maximal passivation level without creation (due to thermal interface
degradation) of additional GePb1 defects (cf. Fig. 5.5, passivation data).
Yet, we notice that, about 40 % of all traps remain unpassivated by H,
and in interpreting the dissociation data, this fact must be properly taken
into account. To this ‘non-zero’ value, there at least two contributions: (a)
as mentioned, to enable consistent interpretation of the data, we had to
incorporate that ∼20 % of the Ge DB interface trap system does not take
part in the passivation/dissociation cycling; (b) a second contribution to
the part of defects remaining unpassivated stems from the simultaneous
action of passivation and dissociation kinetics related with the existence of
excessive spreads on the respective activation energies, as will be outlined
below; As a result, a better defect passivation level can physically just not
been realized.
The value of ∼40 % of unpassivated traps was taken as zero level for the
dissociation experiments, and the data shown in Fig. 5.8 were accordingly
renormalized –this for clarity in data fitting based on Eq. 5.8, for which the
condition [GePb1 ](t=0)=0 is adopted.
Figure 5.8 compiles all experimental dissociation data, isochronal (panel a)
and isothermal (panel b), used for self consistent fitting of the GST model.
This means, with respect to the isochronal dissociation, exclusion of the
result for Tan >425 o C where, as mentioned, marring interface degradation is
seen to occur. Self consistent fitting of Eq. 5.8 for all dissociation data en bloc
gives the results Ed =2.23 eV, σEd =0.15±0.01 eV for kd0 =(1.5±1)×1013 s−1 .
The solid line in Fig. 5.8(a) shows an optimized fitting using these parameters.
Also shown in this figure (dotted curve) is the result of an ‘optimized’ fit by
the ST model (Eq. 5.8 with σEd =0) using the same dissociation parameters,
but with spread σEd =0 (single valued Ed ). Again, as observed for the
5.3 Experimental results and interpretation
[P b]
91
E f= 1 . 5 1
E d= 2 .8 3
2×(σE d = 0 . 0 9 )
2×(σE f = 0 . 0 6 )
s ta n d a rd s p re a d s
c o n v e n tio n a l S i/S iO
E f= 1 . 4 4
2×(σE f = 0 . 2 )
2
E d= 2 .2 3
2×(σE d = 0 . 1 5 )
e n h a n c e d s p re a d s
S i0 .2 5 G e 0 .7 5 / S iO 2
A c tiv a tio n e n e r g y ( e V )
Figure 5.9: Gaussian distributions of activation energies for SiPb
defects at the standard (111)Si/SiO2 , interface and for GePb1 at the
(100 )Si0 .75 Ge0 .25 /SiO2 interface. The (strongly enhanced) overlap between
the two distributions in the bottom part directly illustrates the ineffectiveness
in attainable level of passivation for the Ge DB defects.
passivation behavior, the inadequacy of the ST model is strikingly exposed,
also in this case. The ST dissociation prescription evolves for too abrupt
compared to the more gradual trend in the data. This observation adds one
more bonus in favor of the applicability of the GST interpretation.
The inferred kinetic parameters within the GST model for the GePb1 defect
are collected in Table 5.1, together with those previously obtained [85, 105,
115, 117] for the Pb defect at the thermal (111) and (100)Si/SiO2 interfaces.
As the dissociation energy correlates directly with the strength of the defectH bond, we thus find that the GePb1 -H bond is weaker than the Si Pb -H
bond.
5.3.6
Full interaction case: effect of spreads on passivation
efficiency
Figure 5.9 illustrates for different kinetic parameters the changing level of
overlap between the existing Gaussian distribution in the activation energies
for passivation in H2 and defect-H dissociation: The top part illustrates the
situation for the case of Pb in standard thermal (111)Si/SiO2 (Tox ∼900 o C),
92
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
while the bottom part sketches the findings for the currently studied GePb1
center. Obviously, in performing a thermal passivation treatment in H2 and
dealing with thermally activate processed, there is always a finite probability
for dissociation (reverse passivation) of formed passivated defect-H centers,
the larger so for higher annealing temperatures chosen given that Ed >Ef .
The veracity of this has been blatently expressed for the Si Pb case [105],
which has led to inclusion of both reactions (Eqs. 5.3 and 5.4) simultaneously
within the GST model (the so-called full interaction case by Stesmans
[105, 106]). Equation 7 in Ref. [105] represents the total rate equation,
which for the GePb1 defect is rewritten as
d[GePb1 ]
= −(kd + kf [H2 ])[GePb1 ] + kd N0 .
(5.10)
dt
For the case of defect passivation starting from the condition [GePb1 ](0)
= [GePb1 ]in = N0 , Eq. 5.10 gives
[GePb1 ]
1
=
{kd + kf [H2 ]exp[−(kd + kf [H2 ])t]}.
(5.11)
N0
kd + kf [H2 ]
When accounting for the Gaussian spreads in activation energies, we obtain
as final GST model full interaction case solution
[GePb1 ]
1
=
N0
2πσEf σEd
×
Z ∞Z ∞
0
0
(Efi − Ef )2 (Edi − Ed )2
exp −
−
2σE2f
2σE2d
kd + kf [H2 ]exp[−(kd + kf [H2 ])t]
dEfi dEdi ,
kd + kf [H2 ]
(5.12)
where the integration ranges span all occurring Efi and Edi values.
Expression 5.12 has been calculated numerically using the above inferred
GePb1 parameters listed in Table 5.1, and the result is shown in Fig. 5.10
(solid curve). For comparison, we also show data calculated using the same
GePb1 parameters except the spreads: The dotted curve corresponds to
the spreads comparable to those of Si Pb at the (111)Si/SiO2 interface
(σEf =0.06 eV, and σEd =0.08 eV), while the dashed curve is calculated
for the single-valued activation energy case (ST model), i.e., with spreads
σEf =σEd =0.
The calculation results shown in Fig. 5.10 clearly demonstrate the
devastating effect of the existence of excessive spreads, σEf and σEd ,
in activation energies on the attainable passivation efficiency. Even at
optimum temperature, only ∼80 % of the defects taking part in the
5.3 Experimental results and interpretation
93
passivation/dissociation cycling can be passivated, maximally occurring at
∼375 o C, as observed indeed (cf. Fig. 5.5 and solid curve in Fig. 5.10).
The increase in spreads, σEf and σEd , results in decreasing the passivation
efficiency and an increase of the optimum Tan value, at which, for a certain
anneal time t, the best passivation is reached. This is in agreement with
0
1 0
-1
[ G e P b 1 ] / [ G e P b 1 ] in
1 0
σE f = 0 . 2 e V , σE d = 0 . 1 5 e V
σE f = 0 . 0 6 e V , σE d = 0 . 0 8 e V
1 0
-2
1 0
-3
1 0
-4
1 0
-5
σE f = σE d = 0
σE f = 0 . 2 e V , σE d = 0 . 1 5 e V
D is s o c ia tio n
σE f = 0 . 0 6 e V , σE d = 0 . 0 8 e V
σE f = σE d = 0
0
1 0 0
2 0 0
3 0 0
D is s o c ia tio n
4 0 0
A n n e a l te m p e ra tu re ( C )
o
5 0 0
6 0 0
Figure 5.10: Isochronal behavior of [GePb1 ]/[GePb1 ]in starting from the
condition [GePb1 ](t=0)=[GePb1 ]in for annealing in 1.05 atm H2 for 36 min
under simultaneous action of passivation and dissociation (full interaction
case [105]) as calculated using the GePb1 data listed in Table 5.1. The
dashed curve was calculated using the single-valued activation energy case,
i.e., with spreads σEf =σEd =0. The dotted curve was calculated using the
same parameters for GePb1 as tabulated in Table 5.1, except for the spreads
where values of σEf =0.06 eV and σEd =0.08 eV previously found for the
SiPb defect in (111)Si/SiO2 are used. The calculated isothermal dissociation
behavior (Eq. 5.7) in vacuum is also shown for comparison (the dash-dotted
curve). Notice that the calculated data here have not been renormalized for
a ∼20 % immune part of defects.
94
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
1
σΕf = 0 . 2 e V , σΕd = 0 . 1 5 e V
0 .1
[ G e P b 1 ] / [ G e P b 1 , in ]
0 .0 1
1 E -3
1 E -4
σΕf = σΕd = 0
1 E -5
F u ll- in te r a c tio n
t →∞
1 E -6
G S T
S T
1 E -7
1 0 0
1 5 0
2 0 0
2 5 0
3 0 0
3 5 0
4 0 0
o
A n n e a lin g te m p e r a tu r e ( C )
Figure 5.11: Relative level (number) of non-passivated GePb1 defects attained
as function of annealing temperature for annealing time approaching infinity
and using pH2 =1.05 atm.
previous studies on passivation/activation of Si Pb defects [106]. Starting
from the condition [GePb1 ]/N0 = 1, we obtain from Eq. 5.12 for the time
approaching infinity, that the relative density of unpassivated dangling
defects approaches the limit
[GePb1 ]
N0
=
1
2πσEf σEd
×
Z ∞Z ∞
0
0
(Efi − Ef )2 (Edi − Ed )2
exp −
−
2σE2f
2σE2d
kd
dEfi dEfi .
kd + kf [H2 ]
(5.13)
For a H2 pressure pH2 =1.05 atm, this expression has been calculated
numerically as a function of annealing temperature, for the currently inferred
set of spreads σEf =0.2 eV and σEd =0.15 eV on the activation energies Ef ,
Ed of the GePb1 defect as well as for the ST model case σEf =σEd =0. The
results plotted semilogarithmically in Fig. 5.11 show that even after heating
for extended times, the level of passivation for the actual case (σEf =0.2 eV;
σEd =0.15 eV) cannot reach better than a few %.
DISCUSSION
5.4
Discussion
5.4.1
Enhanced spread in activation energy
95
As it emerges from the GST model interpretation, our data on the GePb1
hydrogen interaction kinetics reveal the presence of considerable spreads
σEf , σEd on the “forward”, Ef , and “backward”, Ed , activation energies,
2–3 times larger than for Pb in standard (111)Si/SiO2 (cf. Table 5.1). After
inserting the obtained parameters in the total equation [105] for simultaneous
action of passivation and dissociation, we found that only ∼80 % of the
defects taking part in the passivation/dissociation cycling can be passivated,
maximally occurring at ∼375 o C, as observed indeed (Fig. 5.10). After an
optimized passivation at ∼375 o C (for a 36 min treatment), about 20 %
of the GePb1 system still remains unpassivated, while for Si Pb defects,
the residual part still left active is only in the order of ppm [105]. With
average activation energies comparable to those of the Si Pb , the poor
degree of passivation is a direct result of the enhanced spreads σEf , σEd
in the activation energies as encountered before [106]. The latter results
from site-to-site variations in defect configuration related to non uniform
interfacial strain; The (100)Si1−x Gex /SiO2 interface would thus exhibit
enhanced randomness compared to that of standard (111)Si/SiO2 .
Here, however there is one more remark to be added. Pertinently, in previous
work [117] on the passivation in H2 of the Pb0 and Pb1 interface defects in
(100)Si/SiO2 (albeit in structures grown at low Tox ≈176 o C, thus with an
interface of lower quality), for both types of defects, substantial spreads
(σEf =0.14; 0.15, respectively) have been reported, well comparable to the
one found here for GePb1 . Taken together, compared to the (111) face,
this would point to enhanced randomness as being a more general epidemic
aspect of the (100) face –as noticed before [108].
5.4.2
Non reactive defects
The current work reports on the study of the full cycle (molecular) hydrogen
interaction kinetics of the GePb1 interface trap, enabling to establish an
overall picture. As it concerns the first study on an interfacial Ge DB defect,
it may be adequate to discuss some of the results in the light of those of
the prototype Si DB interface defects (Pb -type centers) in Si/SiO2 entities,
96
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
for which the hydrogen interaction kinetics appear rather well understood.
There are various aspects.
A first comment concerns the finding that within the self-consistent fitting
of the GST model over all data en bloc, about 20 % of the total GePb1 defect
system appears immune for the interaction with H2 . In fact, successful self
consistent fitting can only be obtained by incorporating this. This is not
the case for Si Pb defects, at least not to any detectable amount, raising
curiosity.
As modelled, effective passivation in H2 of interfacial Si or Ge DB defects
requires two essential parts: (a) diffusion of H2 to and (b) chemical reaction
at the defect site. With respect to (a), one may point to the fact that
currently one is dealing with two identical, simultaneously addressed,
interfaces –a top and an inner (buried) GeSi/SiO2 interface. So, within
the conventional picture, passivation of defects at the inner interface will
require lateral diffusion of H2 , entering the sample from the side, through
the buried SiO2 layer over distances of the order of millimeters. One might
then suggest diffusion limitation influences on attained passivation efficiency.
At first sight, it is deemed unlikely: (a) Diffusion limitations, depending
exponentially on temperature, would vary drastically over the current Tan
covered, getting weaker with increasing Tan ; (b) Diffusion of H2 in a-SiO2 is
a fast process. But, clearly, verification of the validity of this would require
accurate data on the diffusion properties of H2 in a-SiO2 . However, the
applicable value of the diffusivity (permeability) of H2 in SiO2 may be hard
to access, different values being reported for different types of a-SiO2 (see,
e.g., comment in Ref. [105]). Yet, based on one set of diffusion parameters
for H2 in a-SiO2 [118], diffusion restraints for the applied heating time
(∼35 min) may be quite feasible.
Thus, the uncertainty left would urge direct experimental verification.
Therefore, two pieces of sample –a small and a larger one– with a difference
of ∼ 6× in smallest lateral dimension were subjected in one treatment to an
equal stage of passivation in H2 (1 atm, ∼35 min) at 375 o C –the temperature
for maximal defect passivation (cf. Fig. 5.5). Subsequent CV measurements
at the center parts of the sample slices showed equal passivation level
(∼60 %) within experimental accuracy, which would directly counter the
diffusion restriction argument. This conclusion is independently affirmed by
ESR measurements on a Ge0.75 Si0.25 /SiO2 sample subjected to passivation
treatment in H2 at 250 o C, leaving a fraction y(≈70 %) of the GePb1 system
5.4 Discussion
97
ESR active. After removal of the top SiO2 layer, and hence the top Si/SiO2 ,
(48±5) % of y was retained, indicating, within experimental error, that
after passivation, equally intense GePb1 systems are left at both interfaces.
This is in conflict with the hypothesis of a diffusion limitation effect, which
would situate the total of the immune part of the GePb1 defects at the inner
SiGe/SiO2 interface. Indeed, in such case, after complete removal of the top
GePb1 system, a larger fraction of ESR active centers would have been left.
So, all in all, experimental evidence points to equally proceeding passivation
for both SiGe/SiO2 interfaces.
In switching gear, one may then look at the chemical reaction side of the
passivation step. Here, perhaps farfetched in consideration, a hint may come
from theoretical study [108] on the Ge/GeO2 system. There, it has been
concluded for the interfacial Ge Pb center (Ge3 ≡ Ge• ) at the Ge/GeO2
interface that molecular H2 is not effective in passivation, with a similar
conclusion reached for Ge DB defects in a-GeO2 [109]: In approaching, the
H2 molecule is cracked at the defect site (to form a GePb -H bond), but once
formed the GePb -H bond spontaneously dissociates (exothermic +0.3 eV
reaction) with a barrier of 1.2 eV, the released H atom snapping to a lone
pair 2p orbital of a neighbouring O atom in the GeO2 network –so it could
account for less effective passivation. (In passing, one may wonder about
what would be the outcome for a continued, unlimited supply of H2 ?)
To be remarked, however, is that the calculations have been performed for
the Ge/GeO2 interface, not the current GeSi/SiO2 one. But then, as a way
out, if projecting that about ∼20 % of the total of the SiGe/SiO2 interface
were of SiGe/GeO2 nature rather than SiGe/SiO2 , one might account for
the 20 % passivation immune GePb1 system. In this view, one thus has
to suppose considerable lateral compositional interface inhomogeneity, for
which, however, there seems so far no experimental evidence [111].
As a final remark, in putting things in correct perspective, to be added
also here is that the theoretical calculations were carried out for the GePb
(Ge3 ≡ Ge• ) DB center, rather than the currently studied GePb1 defect,
which are not the same. As both defects concern a DB at a defected
interfacial Ge atom, one might expect close, similar behavior, yet this still
remains to be verified.
98
5.4.3
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
H2 molecule cracking
As noticed before, a notable ‘sum rule’ aspect of the basic chemical
interaction scheme represented by Eqs. 5.1 and 5.2 for the interface defect
hydrogen interaction kinetics is that the net effect constitutes a reaction
mechanism for dissociation of the H2 molecule in SiO2 –better stated, at
Si/SiO2 interfacial sites– with apparent net activation energy obtained as
Et = Ef + Ed . Effectively, the interface trap does operate as a catalyst for
cracking of the H2 molecule. For the Pb defect at the (111)Si/SiO2 interface,
it is found that Et =4.34±0.06 eV, remarkably close to the value Evac
H2 =4.48 eV
2
for dissociation of H2 in vacuo. If Et may be taken as ESiO
,
the
activation
H2
2
energy for dissociation of a H2 molecule in SiO2 , it is thus found that ESiO
H2 is
only little smaller than Evac
H2 . As discussed before [85, 119], a small difference
may be expected, indeed. This close match is seen as adding confidence
for the appropriateness if the GST model description as underlayed by the
simple basic chemical reactions Eqs. 5.1 and 5.2. From this result, it is
also hinted that the reactions 5.1 and 5.2 proceed without presence of any
substantial intermediate energy barrier (no multi-step process) for either
reaction [119].
Taking this consideration to the current GePb1 case, we obtain Et =3.67±
0.06 eV, well below Evac
H2 =4.48 eV. There appears an energy ‘deficit’ of
2
∼0.7 eV, meriting attention. If the matching of the inferred Et = ESiO
H2
vac
to EH2 is to be put forward as a flagship criterion for the applicability
and validity of the GST model, then one could conclude negative as to
the ‘correct’ description for the current GePb1 case. Yet, the remarkable
degree of self consistency attained in description of the data make us believe
differently. Rather, there may be some factors overlooked in the overall
picture. For one, there is the matter of the defect’s charge state: focusing
on the passivation step, this proceeds starting from the Ge DB trap site
being in the negative charge state (cf. paragraph 5.3.1) vis-à-vis the case
for Pb in (111)Si/SiO2 where the defect was shown to be in the neutral
state during high T passivation. The charge state does affect the activation
energy for passivation and dissociation. The role of the charge state for
the Si Pb defect has been addressed into more detail, where on theoretical
grounds [120] it was concluded for the defect taken to the negative charge
state (positive bias), this to result in a significant reduction in passivation
rate (increase of Ef ). The influence for the current Ge DB is still unknown.
CONCLUSION
99
The charge state may cause an effect in various ways. For one, the charge
present may directly affect electrostatically the H–H bond strength of the
nearing H2 molecule. Another aspect concerns the possible influence, in
interacting with defects, of e-h pairs, generated at high rate at enhanced
temperatures in the GeSi semiconductor of rather small gap (Eg ≈ 0.9 eV).
2
In this respect, we notice that the inferred energy ‘deficit’ ESiO
H2 − Et is of
the order of Eg . The e-h pairs may ensure an effect through configurational
defect excitation and relaxation. Obviously, no definite account can yet be
provided for the failing ‘sum rule’; Further insight may come from deeper
theoretical analysis.
Finally, in a more drastic view, one may project the possibility that in the
defect-hydrogen processes, higher order kinetics is involved rather than the
first order kinetics the GST model is built on. Should a more complex
model be needed, this route is kept open for further consideration.
5.5
Conclusion
An extensive experimental study has been carried out on the hydrogen
interaction kinetics of the GePb1 defect at the SiGe/SiO2 interfaces of
the condensation grown (100)Si/a-SiO2 /Gex Si1−x /a-SiO2 structure. This
includes both defect passivation (pictured as GePb1 -H formation) and
reactivation (GePb1 -H dissociation), thus embodying a full cycle study which
would enable to establish an overall picture of the hydrogen interaction
kinetics. In previous ESR work, the defect has been identified as an
interfacial Ge DB point defect and the current work would thus represent a
first study of hydrogen interaction kinetics of an interfacial Ge DB defect
(trap). The defect occurs in maximum densities of ≈1×1013 per cm2 sample
area for x in the 0.70–0.75 range; the study here is carried out on x=0.75
samples.
From electrical measurements, the defect was concluded to behave as a
negative charge (electron) trap, and from ESR experiments in conjunction
with CV measurements, a close one-to-one correlation, also quantitatively,
has been demonstrated between the ESR-active GePb1 center and the
negative charge trap, allowing equal monitoring of the defect by ESR and
the CV technique. Here, for the major part, CV monitoring has been used
for reasons of sensitivity and versatility.
100
Chapter 5: Chemical kinetics of H passivation and dissociation reactions of Ge DBs
Interpretation of the data has much benefitted from the archival knowledge
on the hydrogen interaction kinetics of the Si Pb -type centers in thermal
Si/SiO2 structures, the behavior being well described by the GST model.
This model has also served as basis for the interpretation of the GePb1 data.
Major conclusions include:
a) It is found that all data on the passivation of the GePb1 centers and
dissociation of GePb1 -H centers may be consistently described by the
GST model, revealing, as required condition, that ≈20 % of all defects
do not take part in the hydrogen interaction kinetics –a 20 % immune
part. As one possibility, it has been suggested this to originate from
lateral non-uniformity in chemical interface composition.
b) The (100)Si0.25 Ge0.75 /SiO2 interface cannot be passivated in molecular
H2 to device-grade level for thermal budgets up to 500 o C (only 60 %
inactivation). This is a direct consequence of the presence of excessive
spreads σEf and σEd in activation energies for passivation, Ef , and
dissociation, Ed , respectively, the current case coming as a textbook
demonstration of their “devastating action”.
c) For annealing time ∼36 min, maximal passivation in 1.05 atm H2 is
obtained for Tan ≈375 o C, still leaving ≈40 % of the electron traps
unpassivated.
d) Regarding the dissociation treatment (anneal in vacuum), for Tan
increasing above 425 o C, the SiGe/SiO2 interface is seen to degrade,
as exposed by the additional creation of interface charge traps. If
including the studied structures in devices, this means that required
thermal treatments during device manufacturing should be kept below
425 o C.
e) For the dissociation activation energy of the GePb1 defect, the value
Ed =2.23±0.04 eV is inferred, which may be compared with the value
Ed =2.83±0.04 eV for the Si Pb defect in (111)Si/SiO2 . As the
dissociation energy correlates directly with the defect-H bond strength,
it is thus found the GePb1 -H bond to be weaker than the Si Pb -H one.
Chapter 6
Passivation of Ge interfaces:
Silicon passivation of Ge/HfO2
interfaces and Ge3N4
passivation of Ge/metal
contacts
6.1
Introduction
The first transistor invented in 1948 by Shockley et al. [31], and later, the
integrated circuit in 1958 by Kilby [121] were made of germanium. The
main advantage of Ge over Si is its high electron and hole mobilities (cf.
Table 1.1), allowing one to boost the transistor drive current, thus making
Ge an attractive replacement for silicon [34]. However, in contrast to Si,
Ge lacks a stable native oxide that can passivate its surface, at least, if not
protected by an appropriate capping layer (see, e.g., Ref. [122]): GeO2 is
water soluble and also thermodynamically unstable above 400 o C due to
the formation of volatile GeO [33]. Moreover, the relatively low permitivity
(κ ≈7–8) makes GeO2 unsuitable for use as a gate dielectric in downscaled
Ge MOS devices. Non-native oxides, such as SiO2 , Al2 O3 , HfO2 , and TaSiOx
have been being investigated to replace GeO2 . However, the high chemical
101
102
Chapter 6: Passivation of Ge interfaces
reactivity of Ge causes formation of a native oxide interlayer between the
alternative oxide and the Ge substrate, making it difficult to obtain a good
Ge/oxide interface. Hence, interface passivation represents a key challenge
for realizing Ge MOS transistors. In addition, the Fermi level pinning effect
is also a big challenge for the Ge technology by making it difficult to obtain
ohmic contacts to n-type Ge and Schottky contacts to p-type Ge.
For the reasons indicated above, two key problems emerge that have to be
solved to enable successful use of Ge in MOS-applications: the Ge surface
passivation and the alleviation of the Fermi level pinning effect in source and
drain regions. In this chapter, we will discuss some results on passivation
on Ge by a silicon interlayer and Schottky barrier height (SBH) control
by introducing a layer of germanium nitride between Ge and metals with
different work function (WF), that allows for un-pinning of the Fermi level.
6.2
Ge/HfO2 interface passivation by silicon
6.2.1
Introduction
For Ge technology, it appears essential to have an oxide-free Ge surface
before starting high-κ insulating film deposition. In this section, we
discuss the interface traps in Ge/HfO2 structures with a thin Si/SiO2
interlayer as passivation layer. The purpose of the Si-passivation is to
insert a Si/SiO2 interface into Ge/HfO2 gate stack to avoid oxidation of
Ge occurring when growing/depositing high-κ dielectric directly on Ge. As
to the Ge/Si/SiO2 /HfO2 gate stack, low processing temperatures may also
help avoid diffusion of Ge through the Si/SiO2 interlayer. Indeed, we will
show that the interface trap density can be reduced by approximately a
factor of three on samples with silicon passivation deposited at 350 o C,
compared to those using silicon passivation deposited at 500 o C.
6.2.2
Samples and measurements
The studied samples were prepared on germanium-on-silicon (GOS) wafers
with a p-type Ge doping level of ∼3×1016 cm−3 . After cleaning, 2−6
monolayers (MLs) of Si were epitaxially grown using either silane (SiH4 )
at 500 o C or silcore (Si2 H6 ) at 350 o C. In the next step, the Si layer was
a
6.2 Ge/HfO2 interface
passivation by Si
HRTEM
HfO2
SiO2
Si
Ge
350–400 cm
times the
devices).
The th
passivated
number o
gesting a much-improved Ge surface
passivation. Consistently, the average density of interface states, estimated from
charge-pumping current measurements, is
about 2 × 1011 cm−2 near midgap.29 The
much-improved passivation of the Ge
b
103
C (x 10–6 F / cm2)
shown in Figure 1b, the C-V characteristics
of a HfO2/SiO2/Si/Ge gate stack are much
improved compared to the HfO2/Ge gate
stacks with no Si passivation layers, which
were almost flat. Both the high-frequency
gate-to-channel capacitance (Cgc) and gate-
2.0
C gc
1.0
100 kHz
2 nm
0.0
–2.0
–1.0
0.0
Vg
Figure 6.1: High-resolution cross-sectional transmission electron microscopy
(TEM) image of a Ge/Si/SiOx /Hf O2 stack [Ref. 123].
c
d
dq |e |
DVth (V)
DFs (eV)
partially oxidized in ozonated water (1 ppm) for 1 min to form a ∼0.40.20
nmthick SiO2 interlayer. Finally,
a
8-nm
layer
of
HfO
was
deposited
by
the
2
Model
0.2
0.2
0.15
o
atomic layer depositionSiH
(ALD)
technique at 300 C, using HfCl4 and H2 O
4 @ 500°C
as precursors. High-resolution cross sectional TEM pictures of a typical 0.10
gate
Si H8 @ 350°C
stack, such0as shown in 3Fig.
6.1, indicate that aprupt0 interfaces without
0.05
visible defects were achieved.
–0.2
–0.2
To enable
electrical measurements, gold contacts were
deposited on0.00
top
of the HfO2 layers by thermoresistive evaporation in vacuum. Electrical 0
–0.4 were performed at 77 K (liquid N2 ), 200–0.4
measurements
K (solid CO2–0.05
) and
2
6
300 K in the frequency range f=10 –10 Hz using HP4284A and HP4192A
–0.10
precision–0.6
LCR meters. The energy distribution of interface
traps
D
it (E)
–0.6
–0.15
was extracted using the low temperature (200 K) conductance method to
ensure that factors
generation
and
0
1such as
2 thermal
3
4
5
6 weak
7 inversion response,
that interfere with DNumber
at 300 K, do not hamper the interface
it extraction
of Si Monolayers
trap density determination [37]. The number of interface traps ∆Nit located
between the Fermi levels at 300 and 77 K was determined from the flatband
voltage shift (∆VFB ) on 1-MHz CV curves observed when cooling the sample
down from 300 to 77 K.
5
10
Ge
6.2.3
Results and discussion
Figure 1. (a) High-resolution cross-sectional transmission electron diffraction (TEM) picture of a gate stack form
ultrathin
epi-Si
layer, partly
into SiOx, and
deposited at
by atomic
2 layer
Figure 6.2
shows
examples
of oxidized
multi-frequency
CVa HfO
curves
measured
300 Klayer deposition. (b) Gate
and gate-to-bulk capacitance (Cgb) versus gate voltage of a Si-passivated
Gep-type metal oxide semiconducto
o C (left panels)
on samples
with at3–6
MLs
obtained
from
silcore
350function
10 (c)
measured
100SikHz.
Calculated
change
in theatwork
of the Ge/Si and
slab (ΔΦs) as a function of the
o C Open
andWe
open
squares
correspond
to the
threshold
voltage shifts
silane at(MLs).
500 31,32
(righttriangles
panels).
first
notice
that there
appears
evidence
of measured on transistors
10
deposition, respectively. (d) Computed partial atomic charges δq along the Ge/Si slab (3 ML of Si)32; Z is the dis
slab. Black, green, and white spheres correspond to Ge, Si, and H atoms, respectively; p, dipole moment.
MRS BULLETIN • VOLUME 34 • JULY 2009 • www.mrs.org/bulletin
104
Chapter 6: Passivation of Ge interfaces
1 .0
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .8
0 .6
0 .4
3 S i-M L s
S ilc o r e , T
0 .2
p
o
= 3 5 0
T m = 3 0 0 K
2
o
C
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
1 .0
0 .8
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .6
0 .4
4 S i- M L s
S ilc o r e , T p= 3 5 0
0 .2
o
4 S i-M L s
S ila n e , 5 0 0
T m = 3 0 0 K
C
T m = 3 0 0 K
o
C
C a p a c i t a n c e ( µF / c m
2
)
C a p a c i t a n c e ( µF / c m
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
3 S i-M L s
S ila n e , 5 0 0
T m = 3 0 0 K
C
)
C a p a c i t a n c e ( µF / c m
2
)
1 .2
1 .0
0 .6
0 .4
5 S i-M L s
S ilc o r e , T p = 3 5 0
0 .2
o
5 S i-M L s
S ila n e , 5 0 0
T m = 3 0 0 K
C
2
)
T m = 3 0 0 K
C a p a c i t a n c e ( µF / c m
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .8
o
C
1 .0
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .8
0 .6
0 .4
6 S i-M L s
S ilc o r e , T p = 3 5 0
0 .2
o
6 S i-M L s
S ila n e , 5 0 0
T m = 3 0 0 K
C
T m = 3 0 0 K
0 .0
-1
0
1
2
G a te v o lta g e ( V )
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
3
0
o
C
1
2
G a te v o lta g e ( V )
3
Figure 6.2: 300-K multi-frequency CV characteristics of p-(100)Ge/Si/SiO2
/HfO2 /Au entities with 3–6 expitaxially grown Si-MLs, deposited using
silcore at 350 o C (left), and silane at 500 o C (right).
6.2 Ge/HfO2 interface passivation by Si
105
1 0
o
C V , s ila n e 5 0 0 C
o
G V , s ilc o r e 3 5 0 C
o
C V , s ilc o r e 3 5 0 C
T = 3 0 0 K
e V
-1
)
8
1 2
c m
-2
6
D
it
(1 0
4
2
0
2
3
4
5
N u m b e r o f S i- M L s
6
Figure 6.3: Density of interface traps Dit extracted by the high-low frequency
CV and GV methods, measured on Ge/Si/SiO2 /HfO2 samples at 300 K.
The calculations were done at VG values that correspond to CHF /Cox ≈ 0.5.
series resistance effects in accumulation. Series resistance influence appears
hardly avoidable since the semiconductor substrate represents a 1-µm thick
Ge layer, expitaxially grown on a high-resistive strain relief buffer on a
200-mm Si wafer. As can be seen from the figures, the hump visible in all
CVs is minimised for the sample with 4 monolayers of Si using the silcore
source at 350 o C, marking the lowest density of electrically active interface
defects attained over the samples studied. At first sight, the humps on
300-K CV curves might suggest a huge density of interface traps. However,
these humps are observed quite close to the weak inversion region of Ge at
RT (because of the small bandgap of Ge), so they may also be affected by
minority carrier generation, making it difficult to extract Dit accurately [37].
Figure 6.3 compares densities of interface traps at VG corresponding to
CHF /Cox ≈0.5, extracted by the high-low frequency CV (cf. Eq. 2.40) and
GV (cf. Eq. 2.65) methods. As suggested previously [37], the 1-MHz
frequency is not high enough as some interface traps still can follow the
AC signal and contribute to capacitance. Hence, using 1-MHz CV as a high
frequency characteristic may lead to errors. To improve on this, we used
6-MHz and 1-kHz CVs to extract Dit by the high-low frequency CV method.
The results obtained by the CV and GV methods are in good agreement.
Figure 6.3 reveals that using silcore to grow the Si-IL at low temperature,
350 o C, results in a better interface than using silane at 500 o C. It has been
106
Chapter 6: Passivation of Ge interfaces
1 .2
0 .6
4 -S i M L s ,
S ilc o r e T p = 3 5 0
0 .4
)
0 .8
0 .6
0 .4
4 S i- M L s
S ila n e , 5 0 0
T m ≈2 0 0 K
0 .2
0
1
2
G a te v o lta g e ( V )
0 .0
3
o
0
1
2
G a te v o lta g e ( V )
3
4 -S i M L s
S ila n e T p = 5 0 0
2 .4 5 V
C
T m ≈2 0 0 K
0 .3
o
C
T m ≈2 0 0 K
2
/ ω ( µF / c m
)
0 .1 0
C
0 .4
4 -S i M L s ,
S ilc o r e T p = 3 5 0
2 .3 5 V
o
(c )
(a )
0 .0
)
C
T m ≈2 0 0 K
0 .2
2
o
2
)
2
C a p a c i t a n c e ( µF / c m
0 .8
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
1 .0
C a p a c i t a n c e ( µF / c m
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
1 .0
/ ω ( µF / c m
V
V
V
V
0 .0 0
3
4
5
lo g [f( H z ) ]
0 .1
2 .2 5 V
(b )
2 .2 3 V
2 .4 5
2 .4 0
2 .3 5
2 .3 0
2 .2 5
0 .2
p
0 .0 5
V
G
G
p
2 .3 5
2 .3 2
2 .2 9
2 .2 6
2 .2 3
6
0 .0
3
V
V
V
V
V
4
(d )
5
l ol o g g ( [ f f _ ( H z ) ]
6
Figure 6.4: 200-K multi-frequency CV curves and Gp /ω-versus-frequency of
p-(100)Ge/Si/SiO2 /HfO2 /Au entity with 4 Si MLs, deposited from silcore
at 350 o C (a and b respectively), and deposited from silane at 500 o C (c and
d respectively).
suggested that for the Si-passivated Ge/HfO2 interface, traps are associated
by the presence of surface segregated Ge at the Si/SiO2 interface [124–126].
As reported by Heyns et al. [127], decreasing the Si deposition temperature
from 500 to 350 o C leads to a dramatic reduction of Ge incorporation in the
Si capping layer and Ge segregation, resulting in better passivated interfaces.
For the silcore sample set, the trap density decreases with increasing Si
thickness, and reaches a minimum on the sample with 4 Si-MLs, then
increases again.
Lowering the measurement temperature has been suggested as a solution to
reduce the effects of minority carrier response in depletion [37]. The CV
and GV measurements were performed at ∼200 K, and the obtained data
E c
3 0 0 K
∆
E c
7 7 K
E F(n )
E F(n )
N it
E F(p )
E v
E F(p )
E v
6.2 Ge/HfO2 interface passivation by Si
107
5
7 7 K
3 0 0 K
0 .8
4
3
-2
0 .6
1 2
0 .4
-1
0
( ×1 0
4 S i-M L s
S ilc o re
f = 1 M H z
1
∆N
it
it
o
∆N
0 .2
0 .0
2
c m
C /C
o x
) (7 7 K _ 3 0 0 K )
1 .0
1
G a te v o lta g e ( V )
2
3
0
S ilc o r e , 3 5 0 C
2
3
4
5
N u m b e r o f S i- M L s
Figure 6.5: Normalized 1-MHz CV curves measured at 300 K (open symbols)
and 77 K (solid symbols) of p-(100)Ge/Si/SiO2 /HfO2 /Au entity with 4 Si
MLs deposited from Silcore at 350 o C.
were used to extract Dit . Figure 6.4 shows multi-frequency CV curves and
Gp /ω versus frequency for samples with 4 Si MLs, measured at Tm ≈200 K.
At such low temperature, the weak inversion responses, which give rise
to the humps in 1-kHz CV curves at 300 K, are suppressed. Comparing
Gp /ω-f curves shown in Fig. 6.4, we can see that the conductance peak
of the silane sample is about three time larger than that of the silcore
sample. The estimated values of Dit from 200-K GV data are in ranges
of (1–2)×1012 cm−2 eV−1 and (3–5)×1012 cm−2 eV−1 on those 4 Si-MLs
samples deposited from silcore and silane, respectively.
Figure 6.5 shows an example of 1-MHz CVs measured at 300 K and 77 K on
the sample with 4 Si-MLs using the silcore source. When cooling down from
300 K to 77 K, the CV curves shift to the right. The same phenomenon was
observed at all p-type Si-passivated samples. This phemomenon is opposite
to the one observed on conventional p-type Si/SiO2 interfaces: CV curves of
a silicon p-MOS move to the left when cooling down (cf. Fig. 3.8, Chap. 3),
indicating positive donor trapped charge in the lower half of the Si bandgap,
as the Fermi level of a p-type subtrate goes down when cooling (cf. Fig. 2.8
in Chapter 2).
To explain the unexpected direction of VFB shifts observed on Si-passivated
Ge/HfO2 samples, we assume that there is a presence of a n-type region at
D it
6
5
4
4
3
3
2
2
1
it
(1 0
1 2
(1 0
c m
-2
c m
-2
e V
-1
)
) (7 7 K - 3 0 0 K )
5
1 2
Chapter 6: Passivation of Ge interfaces
D
108
1
∆N
it
∆N
S ilc o r e , 3 5 0
0
2
o
D
C
3
4
5
it
it
6
0
N u m b e r o f S i- M L s
Figure 6.6: Comparison of Dit values (cf. Fig. 6.3) with the number of traps
∆Nit between the two Fermi levels at 300 K and 77 K extracted by the shift
of the flatband voltage ∆VF B when cooling down to 77 K, for the samples
deposited from Silcore at 350 o C.
the p-Ge substrate surfaces. The formation of a n-type region on top of a
p-type substrate represents a reasonable hypothesis because the growth of
epitaxial-Si at elevated temperatures may generate thermal donors inverting
the doping type within a few nm-thin layer near the interface. Then, as a
result, the Fermi level at these interfaces shifts up when cooling the sample
(cf. Fig. 2.8, Chap. 2), leading to CV curves shifted to the right. This effect
represents the major reason for refraining from Dit (E) extraction because
the position of the Fermi level at the Ge/oxide interface cannot be evaluated
using the bulk doping level of the Ge substrate.
However, we still tried to estimate the number of interface traps ∆Nit
between the Fermi levels at 300 K and 77 K from ∆VFB . The results are
shown in Fig. 6.6 for the samples derived from Silcore, in comparison to
the Dit values previously shown in Fig. 6.3. The trend of ∆Nit versus the
Si-ML number is similar to that of Dit . This once again confirms that an
optimized interface was obtained on the sample with 4 Si-MLs deposited at
350 o C.
Next, we compare our results with CV measurements on GeO2 -passivated
Ge/HfO2 samples. Figure 6.7 shows multi-frequency CV curves measured
6.2 Ge/HfO2 interface passivation by Si
109
100 Hz
pGeRT2.spw
nGeRT2.spw
1 kHz
p-Ge(100)/GeO2(2 nm)/HfO2(10 nm)/Au
100 Hz
CC(F)
(nF)
2
2e-9
10 kHz
1 kHz
10 kHz
1
1e-9
1 MHz
100 kHz
T=300KK
T=300
1 MHz
100 kHz
TT=300
= 300 KK
n-Ge(100)/GeO2 (2 nm)/HfO2 (10 nm)/Au
0
0e+0
nGeLT1.spw
pGeLT1.spw
2e-9
2
T=77 K
T=77 K
100 Hz
100 Hz
C(F)
C (nF)
100 kHz
100 kHz
1
1e-9
1 MHz
1 MHz
0
0e+0
-3
-3
-2
-2
-1
-1
00
11
Gate voltage (V)
22
33 -3
-2-2
-1
-1
0
0
11
2
2
33
Gate voltage (V)
Figure 6.7: 300-K and 77-K CV curves measured on both p-type (left) and
n-type (right) (100)Ge/GeO2 /10-nm HfO2 /Au capacitors.
on both p- and n-type Ge/2-nm GeO2 /10-nm HfO2 /Au samples. The HfO2
thicknesses of the Ge-passivated samples and the Si-passivated ones are
comparable, 10 nm and 8 nm, respectively. When cooling down to 77 K, for
the p-type sample, very small VFB shifts to the left were observed. However,
for the n-type sample, much larger flatband voltage shift, ∆VFB ∼1 V, to
the right was observed. This value is comparable with ∆VFB observed on
the Si-passivated samples, 0.6–0.8 V, and the shift directions are the same,
to the right. These observation support our suggestion of a n-type region
Chapter 6: Passivation of Ge interfaces
d P µ/ d B ( a r b . u n i t s )
110
( 1 0 0 ) G e /e p i- S i/S iO 2 /H fO 2
2 0 .6 G H z
T = 4 .3 K ; B // [1 1 1 ]
S i:P
g = 1 .9 9 8 6 9
P b0
D
P b0
6 -S i M L s
th in n e r S i- c a p
7 3 0 0
7 3 2 0
7 3 4 0
7 3 6 0
M a g n e tic fie ld ( G )
7 3 8 0
Figure 6.8: K-band derivative-absorption ESR spectrum observed at T=4.2 K
on (100)Ge/Si/SiO2 /HfO2 structures with the applied magnetic field aligned
parallel to the [111] direction. The label Si:P denotes a marker signal
stemming from a co-mounted Si:P marker sample.
formation at the surface of the Si-passivated samples.
In the case of the Si/SiO2 interface, the DB defects are responsible for the
majority of electrically detected interface trap density (cf. Chap. 3). The
same kinds of defects were expected to be present at Ge/oxide interfaces.
While the electrical measurements reveal a high density of interface traps,
the conventional ESR spectroscopy still failed to detect Ge DB signal in any
Ge/insulator structure [113, 128, 129]. In fact, many investigations in Ge
DB defects in our samples have been conducted, however, no Ge DB defect
signal has been found so far. Otherwise, Si-related defects (both Pb0 and
D-centers) were observed on sample with 6-Si MLs ([Pb0 ]∼1×1012 cm−2 as
shown in Fig. 6.8.
6.2.4
Conclusion
In summary, we have demonstrated that Si passivation layer using silcore at
lower temperature shows better quality for Si-passivated Ge interface than
the one using silane at higher temperature. The optimum interface was
found on the sample with 4 Si-MLs growth from silcore source. The shift
to more positive voltage of VFB when cooling the sample down suggests
SCHOTTKY BARRIER CONTROL ON GE USING GE3 N4
111
formation of a n-type Ge region during the Si-epitaxial growth. No Ge DB
defects can be detected by ESR in Si-passivated samples, suggesting that
the observed high density of interface traps is not related to the DB type
defects.
6.3
Schottky barrier control on Ge using Ge3 N4
6.3.1
Introduction
Due to the strong Fermi-level pinning close to the Ge VB edge, most of
the p-type Ge/metal contacts show Ohmic characteristics, while n-type
Ge/metal contacts exhibit rectifying behaviors. On n-type Ge, the Schottky
contact is formed independently of the metal WF, as illustrated later in this
section (cf. 6.3.4). It is suggested that intrinsic Ge interface states cause the
Fermi level pinning, thus making the metal/Ge barrier height insensitive
to the metal WF [130]. Lowering the Schottky barrier height (SBH) and
the formation of Ohmic contacts on n-type Ge represent an important step
towards realization of n-channel Ge MOSFET.
It has been shown for Si/metal contacts that imposing a thin insulator
between low-WF metals and silicon can substantially reduce the Schottky
barrier of the junction and decrease the junction resistance [131, 132]. With
this approach, a SBH for Mg on n-type Si was reduced from 0.45 to 0.2 eV,
a reduction of the effective barrier height by approximately 0.25 eV was
achieved [132]. Recently, similar approaches have been introduced for n-type
Ge [133]: A thin layer of insulator is capped between Ge/metal contact,
that make significantly reduced the Fermi level pinning effect, allowing one
to control the barrier height by varying the WF of the metal.
In this section, we report a simple method to alleviate this Fermi-level
pinning effect by inserting a thin layer of germanium nitride (Ge3 N4 ) between
a metal and the Ge substrate. Upon introduction of this thin layer of Ge3 N4
(amorphous or crystalline), the effective SBHs of n-type (111)Ge with Pt, Au,
Co, Cr, and Al were found to be dependent on the WF of the corresponding
metal. It becomes a promising method to realize a low resistance metal
contact to n-type Ge, which is essential for n-channel Ge MOSFET devices.
112
6.3.2
Chapter 6: Passivation of Ge interfaces
Samples and measurements
Standard commercial single-crystal n-type (111) or (100)Ge substrates
(ND ∼1×1016 cm−3 , and ρ ∼ 0.15 Ωcm) were used in this work. These
substrates were chemically cleaned to remove metallic contamination,
particles, and native oxide from the surface, just before loading into an
ultrahigh vacuum (UHV) system. Subsequently, annealing in vacuum
(∼1×10−9 Torr) at 500 o C was performed to degas the samples. On this
clean Ge surface, either crystalline (epitaxial) or amorphous Ge3 N4 was
formed by exposure to nitrogen plasma at 700 and 200 o C, respectively.
X-ray photoelectron spectroscopy measurements revealed a Ge3 N4 thickness
of 1.2 nm for both the crystalline and amorphous Ge3 N4 ; More details on
this can be found in Ref. [133]. After growing, the samples were taken out
of the UHV system and immediately loaded into a metal deposition system
to minimize Ge oxidation. Metal (Al, Cr, Co, Au or Pt) contacts of 500 µm
diameter were deposited using metal evaporation through a shadow mask.
In order to prevent the metal from reacting with ambient air, an Au capping
layer was deposited on top of the Al, Cr, and Co contacts. A blanket cover
of the sample by Au or Al metal was used as the backside contact. Because
of the large surface area, a low resistance can be attained for this contact.
CV measurements were performed between the front and backside contacts
at 77 K to extract the SBH [134]. For comparison, metal contacts were also
prepared on n-(111)Ge and n-(100)Ge substrates without Ge3 N4 interlayer
growth. For reasons of completeness, it may be useful to add that the energy
bandgap of Ge3 N4 layers grown by plasma nitridation has been determined
as 4.4±0.1 eV and 3.68 eV by means of X-ray absorption spectroscopy [135]
and photoemission spectroscopy [136], respectively.
6.3.3
Extraction of Schottky barrier height by CV measurements
For a Schottky MS contact, the dependence of the capacitance on the applied
voltage provides information on the built-in potential and thus on the SBH.
The CV behavior of a Schottky diode on a n-type semiconductor is given
by the following equation [Ref. 16, Eq. 10, chap. 3]
C
ε0
=
=
A
WD
s
qκs ε0 ND
2(Vbi − VG − kT/q)
(6.1)
6.3 Schottky barrier control on Ge using Ge3 N4
113
or,
2(Vbi − VG − kT/q)
1
=
,
C2
A2 qκs ε0 ND
(6.2)
where A, VG , ND , Vbi , and κs , ε0 are the metal contact area, the applied
voltage, the donor concentration, the built in potential, the dielectric
constant of the semiconductor, and the electric constant, respectively. A plot
of (1/C2 ) versus VG gives a linear dependence with slope [2/(A2 qκs ε0 ND )],
and intercepts on the V-axis of Vi = (Vbi − kT/q). The SBH ΦB is then
calculated for a n-type semiconductor by the following equation
ΦB = qVbi + qΦn ,
(6.3)
where Φn is the difference between the conduction band edge and the Fermi
level of the corresponding semiconductor (cf. Fig. 2.5), and is given by
Φn = (EC − EF )/q = (kT/q)ln(NC /ND ),
(6.4)
where NC is the effective density of states in the conduction band
(NC =1.04×1019 cm−3 for Ge at 300 K).
In case we have a thin layer of insulator between the Ge semiconductor
and the metal, the total measured capacitance Cm is equivalent to the
capacitance of Ge, CGe , and the capacitance of the insulator, CGe3 N4 , in
series
1
1
1
=
+
Cm
CGe CGe3 N4
(6.5)
or, if rearranged,
1 2
CGe
6.3.4
=
1
Cm
−
1
CGe3 N4
2
.
(6.6)
Pinning effect at n-type Ge/metal interface
Figure 6.9 shows (1/C2 ) versus VG plots for metal contacts on n-type Ge
surfaces for both the (111) and (100) orientations. Here, we should remark
that some slight variations in the slopes of the plots may be associated with
differences in dopant concentrations of the Ge substrates (a different Ge
114
Chapter 6: Passivation of Ge interfaces
wafer was used for each metal). A linear behavior is observed on all plots.
From the intercepts of the linear fits with the VG axis, SBHs were extracted
following Eq. 6.3. The SBHs are shown in Fig. 6.10 as a function of the
metal WF, revealing that the SBH for direct metal contacts on n-type Ge
is almost independent on the metal WF. The surface orientation of the Ge
also does not have any measurable effect on the SBH values. The observed
SBH values are close to the bandgap of Ge at 77 K (Eg ≈0.73 eV) indicating
Fermi level pinning close to the top of the Ge valance band. The differences
in the SBH of Al, Cr, Co, Au, and Pt contacts for (111) and (100) surface
are -0.02, 0.05, 0.06, -0.02 and -0.01 eV, respectively, which are close to
the accuracy limit of the measurement. A difference of 0.06 eV has been
previously reported for Ni contacts on (111)Ge and (100)Ge substrates [137].
The Fermi level pinning can be explained by the metal-induced gap state
(MIGS) model suggested by Heine [138]. This model suggests that electron
states in the CB of the metal layer tail into the semiconductor gap, resulting
in metal-induced gap states that can be charged and thus reduce the
dependence of the SBH on the metal WF [139]. In addition, the Fermi
level pinning at n-Ge/metal interfaces may also be caused by the presence
of interface traps, which would shield the semiconductor from externally
applied electric fields. Therefore, if the MIGSs can be suppressed and the
interface traps can be passivated, the Fermi level pinning may be reduced.
Ge3 N4 is a potential candidate to passivate the Ge surface, that may alleviate
the Fermi level pinning [140–142].
6.3.5
Schottky barrier control
Figure 6.11 shows (1/C2 ) versus VG plots for metal contacts on n-(111)Ge
surface with a Ge3 N4 interlayer, with the data corrected by subtracting
a series capacitance (Eq. 6.6) to attain the theoretically predicted linear
behavior. The SBHs, obtained from the CV measurements, are plotted as
functions of the metal WF in Fig. 6.12, and summarized in Table 6.1. In the
case of amorphous Ge3 N4 , the Al contacts show a very low barrier height
and a correspondingly high leakage current. Therefore, CV measurements
were not possible for these contacts and the barrier height was deduced from
the current density at 77 K (1.5 A/cm2 ) as 0.09±0.05 eV. The dependence
of the SBH on the metal WF clearly indicates that the introduction of a thin
amorphous or crystalline Ge3 N4 layer eliminates the Fermi level pinning
6.3 Schottky barrier control on Ge using Ge3 N4
115
1/C2 (1020 F-22)
5
4
3
2
1
(aa)
n
n-type
(111
1)Ge
0
(b)
n-tyype (100)G
Ge
Gatete voltage
voltage (V
)
Gate
(VV)
Gate vooltage (V)
Figure 6.9: (1/C2 ) against gate voltage for metal contacts on (a) n-(111)Ge
and (b) n-(100)Ge substrates measured at 77 K.
0.8
Barrie
er heightt (eV)
07
0.7
0.6
Au
Al
Cr
0.5
Pt
Co
0.4
0.3
0.2
With t Ge
Without
G 3N4
0.1
0.0
4.0
(100)Ge
(
(111)Ge
)
linear fitting
linear fitting
g
4.4
4.8
5.2
Work function ((eV))
5.6
Figure 6.10:
Schottky barrier heights of metal contacts
on n-(111)Ge and n-(100)Ge
substrates deduced from CV
measurements at 77 K. The
Schottky barrier for metal contacts on n-type Ge is almost
independent on the metal WF.
and, therefore, allows one to control the barrier by choosing a metal with
appropriate WF. The S factor, given by the slope of the dependence of the
SBH on the metal WF [144]
S=
δΦB,n
,
δΦm
(6.7)
is a measure of the Fermi level pinning of metal contacts.
In the case of strong pinning S=0, while if there is no pinning S=1, and the
band offset is given by the electron affinity rule [144, 145]. SBHs of metal
116
Chapter 6: Passivation of Ge interfaces
6
a m o rp h o u s G e 3N
5
f = 1 0 0 k H z
T m = 7 7 K
c r y s ta llin e G e 3N
4
4
-2
)
f = 1 0 0 k H z
T m = 7 7 K
2 0
F
4
2
(1 0
3
P t
P t
A u
A u
C o
C r
e x tr a p o la tio n
C o
C r
A l
e x tr a p o la tio n
(a )
(b )
1 /C
2
1
0
-1 .5
-1 .0
-0 .5
0 .0
G a te v o lta g e ( V )
-1 .0
0 .5
-0 .5
0 .0
G a te v o lta g e ( V )
0 .5
1 .0
Figure 6.12: Schottky barrier
heights of metal contacts on
Ge3 N4 /n-type Ge with a few
monolayers of amorphous or
crystalline Ge3 N4 , determined
by low temperature CV measurements. Metals with increasing WF were used, including Al,
Cr, Co, Au, and Pt.
B a r r ie r h e ig h t ( e V )
Figure 6.11: (1/C2 ) against applied voltage for metal contacts on n-(111)Ge
with a few monolayers of (a) amorphous Ge3 N4 and (b) single crystalline
Ge3 N4 inserted between the Ge substrate and the metal contact, measured at
77 K. The data were corrected for a series capacitance of the Ge3 N4 layer
(Eq. 6.6) to obtain a linear behavior.
0 .8
(1 1 1 )G e /a -G e 3N
0 .7
(1 1 1 )G e /c -G e 3N
0 .6
lin e a r fittin g
4
lin e a r fittin g
4
C o
0 .5
C r
0 .4
A u
0 .3
P t
A l
0 .2
0 .1
0 .0
4 .0
4 .4
4 .8
5 .2
W o r k fu n c tio n ( e V )
5 .6
contacts on bare Ge are weakly dependent on the metal WF and, therefore,
are characterized by a low value of the S parameter. In the determination
of the S parameter for Ge, one should take into account that the maximum
achievable barrier height is limited by the bandgap. Therefore, a linear
dependence of the barrier height on the metal WF is expected only for the
limited range of the metal WF values. In the case of a Ge3 N4 interlayer,
we observe no saturation of the barrier height, except for the Pt contacts.
We, therefore, calculate the parameter S without taking into account the
6.3 Schottky barrier control on Ge using Ge3 N4
117
Table 6.1:
The barrier height of metal contacts on n-type (111)Ge
without and with 1.2 nm of amorphous and crystalline Ge3 N4 , measured
by the low temperature CV technique. The barrier height for Al contacts
with amorphous Ge3 N4 interlayers was measured by low temperature IV
experiments, giving 0.09±0.05 eV. The metal WFs for different metals are
taken from Ref. [143].
Metal
Al
Cr
Co
Au
Pt
WF (eV)
4.17
4.5
5.0
5.38
5.64
(100)Ge
no Ge3 N4
0.70±0.03
0.65±0.03
0.70±0.03
0.71±0.03
0.72±0.03
Barrier height (eV)
(111)Ge
no Ge3 N4
a-Ge3 N4
0.72±0.03 0.09±0.05
0.59±0.03 0.41±0.03
0.63±0.03 0.50±0.03
0.73±0.03 0.67±0.03
0.72±0.03 0.68±0.03
S-factor
0.02±0.05
0.02±0.05
0.37±0.07
c-Ge3 N4
0.0±0.1
0.1±0.1
0.2±0.1
0.5±0.1
0.55±0.1
0.43±0.15
values for Pt. The values of the S parameter increase from 0.02±0.05 for
bare Ge to 0.37±0.07 for amorphous and 0.43±0.15 for a crystalline Ge3 N4
interlayer. Aluminum contacts on amorphous and epitaxial Ge3 N4 show
barrier heights of 0.09±0.05 and 0.0±0.1 eV at 77 K, respectively. These
are the lowest barrier heights reported so far for metal contacts on n-type
Ge. The difference between the metal WF of Al [(4.17 eV (Ref. [143])] and
the Ge electron affinity [4.1 eV (Ref. [146])] is 0.07 eV. Hence, a barrier
height of 0.07 eV would be expected for an n-Ge/Al contact in the absence
of surface states and interface dipoles. Metals with a WF lower than that
of aluminum, e.g., Mg, could be used to reduce the SBH further.
As mentioned before, a thin Ge3 N4 layer unpins the Fermi level by (a)
reducing MIGSs (penetrating of metal electron wave functions into the Ge
bandgap), and/or (b) passivating the interface states. The Ge3 N4 separates
the metal from the semiconductor and, therefore, suppresses the penetration
of metal electron wave functions into the Ge. However, recently, the interface
states related to native defects at Ge surfaces have been shown to play a
more important role in the Fermi level pinning than the penetration of the
metal electron wave functions [147–149]. The growth of Ge3 N4 removes the
118
Chapter 6: Passivation of Ge interfaces
defects by consuming the top defective layer, thus forming a high quality
interface between Ge and Ge3 N4 [150]. Amorphous Ge3 N4 has been shown
to be a good passivation layer for (100)Ge [151]. It has also been shown
by theoretical calculations that crystalline Ge3 N4 is a passivation layer for
(111)Ge surfaces [140, 141]. We suggest that a thin Ge3 N4 layer, regardless
whether it is amorphous or crystalline, will reduce the interface state density
and, therefore, eliminate the Fermi level pinning.
6.3.6
Conclusion
In conclusion, we have investigated the influence of a few mono-layers of
amorphous and crystalline Ge3 N4 on metal contacts on Ge. Low temperature
CV measurements are used to accurately determine the barrier height. Both
amorphous and epitaxial Ge3 N4 effectively unpin the Fermi level, resulting
in a linear dependence of the barrier height on the metal WF with pinning
factor S of 0.37±0.07 and 0.43±0.15 for a-Ge3 N4 and c-Ge3 N4 , respectively.
Aluminum contacts on 1.2-nm amorphous and epitaxial Ge3 N4 show barrier
heights of 0.09±0.05 and 0.02±0.1 eV, respectively.
6.4
Conclusion of the chapter
This chapter demonstrates that passivation by using an interlayer such as
Si/SiO2 or Ge3 N4 is a fundamental way to improve the performance of Ge
interfaces. In the case of passivation by an Si/SiO2 interlayer, a much lower
Dit was obtained on samples with 4 Si-MLs using silcore as Si source. On
the other hand, Ge3 N4 allows for solving the problem of Fermi level pinning
on n-type Ge.
Compared to Si, Ge has a significantly high hole mobility (cf. Table 1.1 in
Chap. 1), making it a potential candidate for p-MOSFETs. However, the
electron mobility may be enhanced by using III-V compound semiconductors,
that will be discussed in the next chapter.
Chapter 7
Interface and oxide traps in
III-V/high-κ oxide structures
7.1
Introduction
Because of their high carrier mobility, III-V compound semiconductors have
been widely studied to replace Si in MOSFET devices. However, similarly
to Ge, III-V semiconductors lack wide bandgap insulating native oxides to
passivate their interfaces. Therefore, non-native high-κ oxides represent the
natural choice of dielectric materials for application in III-V MOS devices.
Fabrication of a high-quality, thermodynamically stable gate dielectric that
can passivate the III-V semiconductor interfaces efficiently remains the key
challenge for III-V MOSFET technology.
The purpose of this chapter is to investigate and compare interface
properties at different III-V/high-κ oxide interfaces. In the first part
of this chapter, the charge instability of ALD TaSiOx insulators on InP
and In0.53 Ga0.47 As is investigated. On the basis of our observations, we
suggest that a thin IL of Al2 O3 may be needed to appropriately passivate
high-κ/III-V interfaces. In the second part, preliminary results on the
passivation of the In0.53 Ga0.47 As/HfO2 interface by Al doping of the HfO2
layer during deposition will be discussed.
119
120
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
7.2
ALD TaSiOx insulators on InP, In0.53 Ga0.47 As
and Si
7.2.1
Introduction
ALD-tantalum silicate (TaSiOx ) has been proposed as a gate dielectric for
III-V semiconductors because of its high dielectric constant: κ ∼11 for
Ta/Si=1 and κ ∼15 for Ta-rich silicates [152, 153], as compared to Al2 O3
with κ ∼8 [13, 144, 154] conventionally used to passivate III-V interfaces.
The Ta silicate has also been reported to passivate interfaces of III-V
semiconductors, such as InP and In0.53 Ga0.47 As, delivering an acceptably
low density of interface traps and good transistor performance [40]. These
properties allow for a significant improvement on the scalability of the
gate stack towards the equivalent oxide thickness values required for the
22 nm node and beyond. This section presents electrical properties of MOS
structures with ALD TaSiOx as insulator, and either InP or In0.53 Ga0.47 As as
semiconductor, in comparison with the (100)Si/TaSiOx reference structure.
7.2.2
Samples and measurements
The studied samples were prepared in IMEC on standardly doped
p-(100)Si (NA ∼1015 cm-3 ), n-(100)InP and n-(100)In0.53 Ga0.47 As/InP
(ND ∼1017 cm-3 ) wafers by ALD of TaSiOx layers (Ta/Si≈1) from TaCl5 ,
SiCl4 , and H2 O precursors using a hot-wall cross-flow ASM Pulsar 3000
reactor connected to a PolygonTM 8300 platform. The substrate temperature
during the ALD process was fixed at 250 o C. The TaSiOx ALD process was
performed by n:m supercycles, consisting of n TaCl5 /H2 O cycles followed
by m SiCl4 /H2 O cycles. An individual TaCl5 /H2 O cycle consisted of a
TaCl5 pulse, a N2 purge, an H2 O pulse, and finally again a N2 purge. The
SiCl4 /H2 O cycle was defined correspondingly. By altering the number of
the cycles, m and n, three target thicknesses of the TaSiOx layer, 10–20 nm,
were achieved. The fabrication process was described in more detail by
Adelmann et al. in Ref. [152].
To enable electrical measurements, MIS capacitors were fabricated by
thermoresistive evaporation of Au electrodes on top of the TaSiOx film. CV
and GV measurements were performed at 300 K and 77 K in the frequency
7.2 ALD TaSiOx /InP, and In0.53 Ga0.47 As
121
range of f=20–106 Hz using an HP4284A precision LCR meter. The interface
trap density Dit was estimated by using high-low frequency CV and GV
techniques.
Charge trapping in (100)Si/TaSiOx /Au MIS structures
p -(1 0 0 )S i/2 0 -n m
2
)
7.2.3
C a p a c i t a n c e ( µF / c m
0 .4
x
/A u
T m = 3 0 0 K
0 .3
2 0 H z
1 0 0 H z
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .2
0 .1
2 0 H z
1 M H z
2 0 H z
1 0 0 H z
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
0 .0 5
0 .0 4
G c / ω ( µF / c m
2
T a S iO
0 .0 3
0 .0 2
0 .0 1
0 .0 0
-3
-2
G a t e v o lt a g e ( V )
-1
0
1
2
3
Figure 7.1: (a) Multi-frequency CVs and (b) Gc /ω-V characteristics of a
p-Si(100)/TaSiOx /Au capacitor measured at 300 K.
First of all, we evaluated the quality of ALD TaSiOx layers on an (100)Si
as the well studied reference substrate. Figure 7.1 shows typical multifrequency CV and GV characteristics of a p-(100)Si/TaSiOx /Au capacitor
measured at 300 K, showing a similar behavior as the standard (100)Si/SiO2
interface (cf. Chap. 3). The observed frequency dispersion of the CV curves
and the conductance peaks in depletion region indicate the presence of
traps at the Si/TaSiOx interface. The distribution of the interface traps Dit
in the lower half of Si bandgap was extracted by the high-low frequency
CV (Eq. 2.40) and GV (Eq. 2.65) methods and is shown in Fig. 7.2. The
122
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
2 .0
T a S iO
x
/A u
)
p -(1 0 0 )S i/2 0 -n m
C V
G V
c m
-2
e V
-1
1 .5
D
it
(1 0
1 2
1 .0
0 .5
0 .0
0 .0
0 .2
0 .4
0 .6
0 .8
E - E V (e V )
1 .0
Figure 7.2: Distribution of interface trap density below Si midgap at the
p-(100)Si/20-nm TaSiOx interface extracted by the high-low frequency CV
and GV methods.
distribution shows a peak value of Dit =(1.5±0.3)×1012 cm−2 eV−1 at ∼0.3 eV
above the Si VB edge. These values are comparable to Dit at the standard
(100)Si/SiO2 interface fabricated by thermal oxidation of silicon (cf. Chap.
3), suggesting that a good interface between Si and TaSiOx was obtained by
the ALD technique. Worth of mentioning here is that, when using TaSiOx
as an insulator, these low Dit values are obtained without applying any
post-deposition or passivation annealing to improve the interface quality.
Regarding the case of Si/SiO2 interfaces, where the interface traps can be
passivated effectively by annealing in hydrogen, we here expect the Dit
at Si/TaSiOx interface to be further reduced by annealing in forming gas
(N2 +10 % H2 ).
However, besides interface traps, it is also important to investigate charge
trapping in the tantalum silicate layer itself. The hysteresis ∆Vhys observed
in the CV curves was used to estimate the trapped charge density by using
the following equation
Qot = qNot = Cox ∆Vhys .
(7.1)
A CV curve hysteresis in the MOS structure has usually been attributed to
the presence of slow traps, that can communicate with the semiconductor
7.2 ALD TaSiOx /InP, and In0.53 Ga0.47 As
0 .4
C a p a c it a n c e
( µF
/c m
2
)
p -(1 0 0 )S i/2 0 -n m
123
T a S iO
x
/A u
p -(1 0 0 )S i/2 0 -n m
T a S iO
x
/A u
T m = 3 0 0 K
T m = 7 7 K
f = 1 0 0 k H z
f = 1 0 0 k H z
0 .3
0 .2
(a )
0 .1
(b )
V s w e e p -3 −+ 3 V
V s w e e p - 7 −+ 7 V
0 .0
-4
-3
-2
V s w e e p -3 −+ 3 V
V s w e e p - 7 −+ 7 V
G a t e v o lt a g e ( V )
-1
0
1
2
3
-3
-2
G a t e v o lt a g e ( V )
-1
0
1
2
3
4
Figure 7.3: 100-kHz CV curves of a p-(100)Si/20-nm TaSiOx /Au MOS
capacitor measured at 300 K (a) and 77 K (b) using a bi-directional voltage
sweep over the range from -3 to +3 V (solid lines) and from -7 to +7 V
(dashed lines). Arrows indicate the direction of the voltage sweep.
substrate by a tunneling process, as extensively discussed by Fleetwood
et al. [155]. As shown in Fig. 7.3(a), in our case, the trapped charge
density increases manifold upon electrical stressing, by applying a wider
voltage sweep when recording a CV curve. The 0.1 and 0.9-V hysteresises
recorded in the CV curves measured over the voltage ranges of -3 to +3 V
and -7 to +7 V indicate trapped charge densities of (0.2±0.1)×1012 cm−2
and (2.2±0.2)×1012 cm−2 in the TaSiOx layer, respectively. The observed
hysteresis suggests predominant trapping of electrons in the TaSiOx layer.
Comparison of the CV curves measured at 300 K and 77 K as shown in
Fig. 7.3 reveals that increasing the symmetric voltage sweep width causes a
predominant shift of the CV curves towards the positive gate voltages after
applying a larger (+7 V) positive bias to the metal electrode. This effect was
observed both at 300 K (a) and 77 K (b). To be noted here is that at 77 K, the
hysteresis in the CV curves is found only if a sufficient amount of electrons
is supplied to the surface of the p-type silicon by shortly illuminating the
sample with white light at maximal positive bias to compensate for the low
thermal generation rate. This is a clear indication that the charge instability
is caused by electron injection from the Si substrate and subsequent electron
124
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
trapping in the silicate film.
Charge traping in (100)In0.53 Ga0.47 As/TaSiOx /Au MIS
structures
0 .8
T a S iO
5
/ I n 0 .5 3 G a 0 .4 7 A s
1 2 0 H z
T a S iO
/ I n 0 .5 3 G a 0 .4 7 A s
-2
e V
0 .6
x
4
-1
x
3
c m
1 M H z
1 2
0 .4
it
(1 0
2
0 .2
L F C V m e th o d
tox= 1 0 n m
D
C a p a c i t a n c e ( µF / c m
2
)
1 0 -n m
)
7.2.4
1
tox= 2 0 n m
(a )
0 .0
0
-2
-1
0
1
G a te v o lta g e (V )
2
0 .1
0 .2
0 .3
(b )
0 .4
0 .5
0 .6
0 .7
E - E V (e V )
Figure 7.4: (a) 300 K multi-frequency bi-directional CV traces obtained on
an n-In0.53 Ga0.47 As/10-nm TaSiOx /Au capacitor, where the arrows indicate
directions in the sequence of the applied voltage and frequency sweeps; (b)
Dit (E) across the In0.53 Ga0.47 As bandgap extracted by the high-low frequency
CV method on samples with either a 10-nm or 20-nm thick silicate layer.
The energy positions in the gap have been determined using the Berglund
integral method (see paragraph 2.3.2.)
Next, we evaluated the quality of In0.53 Ga0.47 As/ALD-TaSiOx interfaces
using CV and GV data measured at 300 K. Figure 7.4(a) shows the 300-K
multifrequency C-V characteristics of an n-type (100)In0.53 Ga0.47 As/10nm TaSiOx /Au capacitor. The small dispersion observed in accumulation
may be associated with interface traps with energy levels close to the
In0.53 Ga0.47 As CB. However, no remarkable dispersion was observed in
depletion indicating a low density of interface traps in the energy range
close to the In0.53 Ga0.47 As midgap.
Figure 7.4(b) compares Dit (E) of In0.53 Ga0.47 As/TaSiOx interfaces with 10
or 20-nm thickness of the insulating layer. As can be seen from the figure,
the trap densities are in the range of (1–3)×1012 cm−2 eV−1 for both samples
in the energy window 0.2–0.4 eV below the semiconductor CB edge with
7.2 ALD TaSiOx /InP, and In0.53 Ga0.47 As
1 .2
(1 0 0 )In G a A s /1 0 -n m
1 .0
125
(1 0 0 )In G a A s /2 0 -n m
T a S iO x/A u
T m = 3 0 0 K
3 0 0 K
7 7 K
f = 1 0 0 k H z
T m = 7 7 K
f = 1 0 0 k H z
C /C
o x
0 .8
T a S iO x/A u
0 .6
0 .4
0 .2
0 .0
-2
-1
0
1
G a t e v o lt a g e ( V )
2
-3
-2
-1 0
1
2
3
G a t e v o lt a g e ( V )
4
5
Figure 7.5: 100-kHz CV curves measured at 300 K (solid symbols) and
77 K (open symbols) on n-(100)In0.53 Ga0.47 As/TaSiOx /Au capacitors with
10-nm (a) and 20-nm (b) thick silicate layer for a voltage sweep from -2 to
+2 V and from -5 to +5 V, respectively. Arrows indicate the direction of
the voltage sweep.
no significant dependence on the insulator thickness –a result comparable
to the values recently published in the literature for the interfaces with
Al2 O3 and HfO2 [156–158], and to the case of TaSiOx deposited on a (100)Si
substrate.
However, while enabling a low density of interface traps in the upper half
of the bandgap, TaSiOx insulators appear to suffer from significant charge
instability. This effect is illustrated in Fig. 7.5 which shows bi-directional
100-kHz CV curves measured on n-(100)In0.53 Ga0.47 As/TaSiOx /Au MIS
capacitors with 10-nm and 20-nm thick insulating films (panels (a) and
(b), respectively). There is no considerable Gray-Brown shift on the CV
traces when cooling the sample down from 300 K to 77 K, affirming a
low interface trap density in the upper part of the semiconductor bandgap.
A ∼0.2-V CV hysteresis observed at both temperatures on the 10-nm TaSiOx
sample corresponds to (1±0.5)×1012 cm−2 of trapped electrons uniformly
distributed across the silicate, whereas a 0.75-V hysteresis observed on the 20nm sample corresponds to a trapped charge density of (1.8±0.5)×1012 cm−2 .
Since the trapped electron density doubles in accordance with the silicate
thickness increase, we suggest the traps to be distributed across the whole
silicate layer.
126
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
7.2.5
( 1 0 0 ) In P /T a S iO
x
6
/A u
( 1 0 0 ) In P /T a S iO
d ox= 1 0 n m
5
tox= 1 0 n m
-1
)
T m = 3 0 0 K
x
tox= 1 5 n m
e V
1 .0
4
-2
tox= 2 0 n m
3
c m
1 2 0 H z
(1 0
1 2
C V m e th o d
0 .5
2
it
C a p a c ita n c e ( n F )
1 .5
Charge trapping in (100)InP/TaSiOx /Au MIS structures
D
1 M H z
1
(b )
(a )
0 .0
-1 .5
-1 .0
-0 .5
0 .0
0 .5
1 .0
G a te v o lta g e ( V )
1 .5
0
0 .0
0 .2
0 .4
0 .6 0 .8 1 .0
E - E V (e V )
1 .2
Figure 7.6: (a) 300 K multi-frequency bi-directional CV traces obtained on
n-(100)InP/10-nm TaSiOx /Au. Arrows indicate directions in the sequence
of the applied voltage and frequency sweeps. (b) Energy distribution of
interface trap, Dit (E), across the InP bandgap extracted by the high-low
frequency CV method on n-(100)InP/TaSiOx interfaces with a 10-nm, 15nm or 20-nm thick silicate layer. The energy positions in the gap have been
determined using the Berglund integral method (see paragraph 2.3.2).
Figure 7.6(a) shows 300 K multi-frequency CV curves of an n-(100)InP/TaSiOx /Au
capacitor with a silicate thickness tox =10 nm, while Fig. 7.6(b) compares
Dit (E) profiles obtained by using the high-low frequency CV method of n(100)InP/TaSiOx interfaces with different insulator thicknesses. Similarly to
the case of the In0.53 Ga0.47 As/TaSiOx interface, ALD-TaSiOx /InP samples
exhibit a Dit in the range of (1–3)×1012 cm−2 eV−1 in the energy interval
from the InP midgap to the level ∼0.2 eV below the InP CB edge with no
significant dependence on the insulator thickness.
When applying a bi-directional voltage sweep from -5 to +5 V to an
n-(100)InP/20-nmTaSiOx /Au capacitor, the CV curves at both 300 K
and 77 K show a hysteresis of ∼0.8 V (cf. Fig. 7.7). Comparing to the
In0.53 Ga0.47 As/TaSiOx case, the hystersis is barely sensitive to the bandgap
width of the semiconductor substrate (1.35 eV for InP and 0.75 eV for
In0.53 Ga0.47 As at 300 K), suggesting a relationship of the electron traps to
the insulating layer. At the same time, the hysteresis is not reduced at low
7.2 ALD TaSiOx /InP, and In0.53 Ga0.47 As
(1 0 0 )In P /2 0 -n m
1 .0
T a S iO
x
/A u
T m = 3 0 0 K
T m = 7 7 K
0 .8
f = 1 0 0 k H z
o x
C /C
127
0 .6
0 .4
0 .2
0 .0
-4
-3
-2
-1
0
1
2
3
4
5
G a te v o lta g e ( V )
Figure 7.7: 100-kHz CV curves of n-(100)InP/20-nm TaSiOx /Au measured
at 300 K (solid line) and 77 K (dashed line) measured over a voltage sweep
from -5 to +5 V and back. Arrows indicate the direction of the voltage
sweep.
temperature indicating that electron injection probably occurs through a
tunneling mechanism, which implies a low interface barrier for electrons [159].
7.2.6
Discussion
Using the internal photoemission method, Afanas’ev et al. have shown that
ALD TaSiOx on InP, In0.53 Ga0.47 As, and Si wafers exhibits a bandgap
of 4.5±0.1 eV, independent of the semiconductor substrate materials
[159], which is close to the gap value in amorphous Ta2 O5 [160, 161].
Furthermore, it has been found that direct ALD of TaSiOx on (100)InP and
(100)In0.53 Ga0.47 As substrates results in unexpectedly low electron barriers,
i.e., 2.0 eV on In0.53 Ga0.47 As and 2.4 eV on InP as tabulated in Table 7.1,
that cannot prevent electron injection into the silicate layer [159]. This
leads to electron trapping in the TaSiOx layer, which causes a considerable
charge instability of these interfaces [159]. Taking into account that the
In2 O3 bandgap is very narrow, in the range of 2.6–2.9 eV [159], the low
electron barriers at the InP/TaSiOx and In0.53 Ga0.47 As/TaSiOx interfaces
were explained by the formation of an In-rich interlayer. To avoid this
effect, one may consider passivation of the semiconductor by ALD of a few
128
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
monolayers of Al2 O3 , which enables the formation of an IL with low In
concentration and a wider bandgap [162].
Table 7.1: Comparison of the interface properties of 20-nm TaSiOx with
different semiconductor substrates, including Si, InP, and In0.53 Ga0.47 As.
The hysteresis was extracted from 100-kHz CV curves for a gate voltage
sweep from -5 to +5 V at Tm =300 K. The semiconductor bandgaps are
included for comparison.
Bandgap
(eV)
Φe (a)
(eV)
∆Vhys
(V)
Dit near midgap
(1012 cm−2 eV−1 )
1.12
1.35
0.75
3.1±0.1
2.4±0.1
2.0±0.1
0.20± 0.05
0.80± 0.05
0.75± 0.05
0.5±0.2
1±0.5
2±1
Si
InP
In0.53 Ga0.47 As
(a) Electron barrier between the top of the semiconductor VB and the bottom
of the TaSiOx CB, Ref. [159, 163]
7.2.7
Conclusion
In summary, we found that the trap density at ALD TaSiOx /In0.53 Ga0.47 As
and ALD-TaSiOx /InP interfaces is reasonably low, being in the order of
∼1012 cm−2 eV−1 . However, electron injection and trapping in the silicate
layer cause charge instability, challenging the application of TaSiOx in
MOSFET devices. Additional passivation may be needed to improve the
interfaces.
7.3
Charge traps at the (100)In0.53 Ga0.47 As/HfO2
interface with Al-doped HfO2
7.3.1
Introduction
In addition to TaSiOx , ALD HfO2 is also considered as a potential gate
oxide for III-V MOSFET devices. The HfO2 dielectric with κ ∼ 20 has been
successfully applied to 45-nm silicon MOSFET devices [11, 164]. However,
7.3 Charge traps at the In0.53 Ga0.47 As/Al : HfO2 interface
129
deposition of pure HfO2 directly on In0.53 Ga0.47 As leads to a poor interface
with Dit in the order of 1013 cm−2 eV−1 near the In0.53 Ga0.47 As midgap [157,
165, 166]. Recently, reduction of Dit was achieved by sulfur pretreatment
of the In0.53 Ga0.47 As surface prior to ALD of HfO2 [167]. However, native
oxides (Ga2 O3 , In2 O3 and As2 O3 ) rapidly regrew upon exposure of the
devices to the air resulting in interface degradation. It has been shown that
ALD of Al2 O3 from the trimethylaluminum (TMA) Al(CH3 )3 precursor
has a shelf-cleaning effect which is reported to reduce or even remove III-V
native oxides [168–170]. However, by itself Al2 O3 has a low κ-value (κ ∼8)
that limits the EOT scaling potential. One may consider to use a higher-κ
dielectric on III-V in combination with ALD Al2 O3 passivation. In this
section, we will evaluate the effect of Al doping of the HfO2 dielectric on
the quality of the In0.53 Ga0.47 As/HfO2 interfaces.
7.3.2
Samples and measurements
The studied samples, manufactured at the University of California at Santa
Barbara, USA, were Ni/Al:HfO2 /In0.53 Ga0.47 As/InP/Cr-Au entities with
structure schematically illustrated in Fig. 7.8. The substrates were 300-nm
or 200-nm thick As-capped In0.53 Ga0.47 As films grown by molecular beam
epitaxial (MBE) technique on (001)InP wafers. The In0.53 Ga0.47 As layers
were n-type (Si-doped 1×1017 cm−3 ) or p-type (Be-doped: 1×1017 cm−3 )
on n+ - or p+ -InP, respectively. Al-doped HfO2 layers were deposited by
chemical beam co-deposition technique from TMA and hafnium tertbutoxide
at 400 o C, as detailed in Ref. [171], resulting in a thickness of ∼5 nm. After
oxide deposition, the samples were annealed at 400 o C in nitrogen. MOS
structures were completed with 80-nm thick Ni metal gates, with an area
of (1–4)×10−4 cm2 , by electron beam evaporation through a shadow mask,
and with back ohmic contacts of Cr(10 nm)/Au(100 nm).
To extract Dit (E) across the In0.53 Ga0.47 As bandgap, CV and GV
measurements were performed at different temperatures from 300 K to
77 K, in the frequency range 102 –106 Hz by using a HP4284A impedance
analyzer. For the n-type In0.53 Ga0.47 As subtrate, it has been estimated that
this temperature range is sufficient to cover most trap energy levels in the
upper half bandgap of In0.53 Ga0.47 As [124].
InGaAS sample
130
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
Ni ((80 nm))
Al:HfO2 (~5 nm)
Ni ((80 nm))
Al:HfO2 (~5 nm)
n-InGaAs (300 nm)
~1017 cm-3
p-InGaAs (200 nm)
~1017 cm-3
n+-InP
> 11018 cm-3
p+-InP
> 11018 cm-3
Cr/Au (10/100 nm)
Cr/Au (10/100 nm)
Figure 7.8: Structures of studied In0.53 Ga0.47 As/Hf O2 MOS capacitors,
where the oxide layers were Al-doped with the aim to passivate the
semiconductor/oxide interfaces.
7.3.3
Results and discussion
Figure 7.9 shows multi-frequency CV curves measured at 300 K on a
p-In0.53 Ga0.47 As/Al:HfO2 /Ni capacitor. We observed a huge frequency
dispersion in maximum of capacitance, suggesting an interface trap
response. However, in the absence of well behaving CV or GV curves,
it is difficult to extract Dit values for this p-type sample. A 0.6-V hysteresis
observed on this sample indicates a high density of oxide trapped charge,
Not ∼(6±1)×1012 cm−2 .
Figure 7.10 shows multi-frequency CV curves measured on a n-In0.53 Ga0.47 As/
Al:HfO2 /Ni capacitor at different temperatures in the range from 77 to
300 K. At 300 K, a strong frequency dispersion is observed in the inversion
region due to the minority carrier response. In this figure (top left panel),
we notice presence of a peak in the inversion range. This peak us unlikely
to be associated with interface trap response since it is seem to disappear
entirely upon cooling the sample to 180 K (Fig. 7.10, top right panel); At
this temperature, one would not expect the response of interface states to
be completely eliminated.
Figure 7.11 shows the Dit (E) distribution extracted by the high-low frequency
CV, low frequency CV, and GV methods. The parameters of In0.53 Ga0.47 As
7.3 Charge traps at the In0.53 Ga0.47 As/Al : HfO2 interface
2 .0
p - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
2
T m = 3 0 0 K
)
1 .5
C a p a c i t a n c e ( µF / c m
2
131
/N i
1 .0
0 .5
0 .0
-2
1 k H z
1 0 k H z
1 0 0 k H z
1 M H z
-1
0
G a te v o lta g e (V )
1
Figure 7.9: Multi-frequency CV curves measured at 300 K on a p(100)In0.53 Ga0.47 As /Al:HfO2 /Ni capacitor. Arrows indicate the direction
of the voltage sweep.
1 .5
2
C a p a c i t a n c e ( µF / c m
n - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
T m = 3 0 0 K
1 0 0 H z
/N i
2
n - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
T m = 1 8 0 K
1 .0
n - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
T m = 1 2 0 K
1 .5
1 .0
2
/N i
2
1 0 0 H z
1 M H z
1 M H z
0 .5
)
C a p a c i t a n c e ( µF / c m
2
)
2 .0
/N i
1 0 0 H z
n - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
T m = 7 7 K
2
/N i
1 0 0 H z
1 M H z
1 M H z
0 .5
0 .0
- 1 .0
- 0 .5
0 .0
0 .5
1 .0
1 .5
G a te V o lta g e ( V )
2 .0
- 0 .5
0 .0
0 .5
1 .0
1 .5
G a te V o lta g e ( V )
2 .0
2 .5
Figure 7.10: Multi-frequency CV curves measured at 4 different temperatures
in the range 77–300 K on an n-(100)In0.53 Ga0.47 As/Al:HfO2 /Ni capacitor.
132
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
1 2
n - ( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l: H f O
1 0
/N i
)
H ig h -lo w fre q u e n c y C V
L o w fre q u e n c y C V
G V
8
-2
e V
-1
2
(1 0
1 2
c m
6
it
4
D
2
0
0 .0
0 .1
0 .2
0 .3
0 .4
E - E V (e V )
0 .5
0 .6
0 .7
Figure 7.11: Energy distribution of the interface trap density Dit (E) across
the In0.53 Ga0.47 As bandgap at the n-(100)In0.53 Ga0.47 As/Hf O2 interface
extracted by the CV and GV methods.
used for the high-low frequency CV include: the doping concentration
ND =1×1017 cm−3 , intrinsic concentration ni =6.3×1011 cm−3 , dielectric
constant κs =12.4 and Debye length λD =0.004 cm. The Cox value was
chosen at VG =2.5 V on the 100-Hz CV curve measured at 300 K. The results
obtained from the three Dit evaluation techniques are in good agreement
in the midgap range, all close to the value 2×1012 cm−2 eV−1 . Based on
comparison to the In0.53 Ga0.47 As/HfO2 interface without Al2 O3 interface
passivation where the value Dit ∼1013 cm−2 eV−1 is encountered near the
midgap [156], we can conclude that the presence of Al2 O3 passivation
noticeably improves the interface quality. A noteworthy observation also in
Fig. 7.11 is that Dit values near the CB edge derived by the CV methods
are much higher than the values obtained by the GV method, suggesting a
contribution of slow traps to the capacitance response.
A 0.2-V hysteresis is observed on the n-type sample which indicates an oxide
trapped charge density of Not ∼(2±1)×1012 cm−2 , smaller than the value
observed for the p-type sample, Not ∼(6±1)×1012 cm−2 . A portion of the
oxide traps near the interface may contribute to the slow traps near the
In0.53 Ga0.47 As CB edge as revealed by the CV method, Fig. 7.11.
7.3 Charge traps at the In0.53 Ga0.47 As/Al : HfO2 interface
1 .2
( 1 0 0 ) I n 0 .5 3 G a 0 .4 7 A s / A l : H f O
o x
0 .8
C /C
/N i
f = 1 0 0 k H z
3 0 0 K
7 7 K
1 .0
0 .6
2
133
n -ty p e
p -ty p e
0 .4
0 .2
0 .0
-2
-1
0
1
2
G a te v o lta g e ( V )
Figure 7.12: 100-kHz CV curves measured at 300 K (solid line) and 77 K
(dashed line) on both p- and n-(100)In0.53 Ga0.47 As/Al:HfO2 /Ni capacitors
for voltage sweeps from -2.5 to +2.5 V and back. Arrows indicate the
direction of the voltage sweep.
Figure 7.12 compares CV curves measured on both p- and n-type
In0.53 Ga0.47 AsAl:HfO2 samples at 300 and 77 K. For the n-type sample,
no considerable Gray-Brown shift of VFB was observed when cooling the
sample down to 77 K, indicating a low density of interface traps in the energy
range close to the In0.53 Ga0.47 As CB edge. From the difference of between
VFB values found from 77-K CV curves of n- and p-type samples, the total
number of traps was estimated to be in order of ∼1×1013 cm−2 . This
density is much larger than the value of Nit ≈2.8×1012 cm−2 inferred from
integration of CV-Dit (E) distribution across the In0.53 Ga0.47 As bandgap
(not shown), indicating the presence of slow traps in large density, which is
consistent with the observed CV curve hysteresis.
7.3.4
Conclusion
An improved n-In0.53 Ga0.47 As/HfO2 interface was achieved by Al doping
of the HfO2 layer during deposition, resulting in a Dit near midgap close
to 2×1012 cm−2 eV−1 . From this observation, we can conclude that the
presence of Al at the In0.53 Ga0.47 As/HfO2 interface improves the electrical
134
Chapter 7:Interface and oxide traps in III-V/high-κ oxide
quality of the interface; It may possibly be related with the formation of a
(very) thin Al2 O3 interlayer.
7.4
Conclusion of the chapter
In summary, ALD TaSiOx represents a good insulator on a (100)Si substrate.
However, on In-containing substrates such as In0.53 Ga0.47 As and InP,
formation of an In-rich interlayer reduces the interface barriers for electrons,
leading their injection and trapping in the silicate. The n-MOS capacitors
on In0.53 Ga0.47 As and InP with TaSiOx insulator exhibit a low level of
interface traps (in the low 1012 cm−2 eV−1 range) at energies close to the
CB edge. Electron injection and traping in the silicate layer cause charge
unstability, challenging the application of TaSiOx in MOSFET devices.
By doping of Al into the HfO2 layer, the quality of the n-In0.53 Ga0.47 As/HfO2
interface was improved, reaching a Dit near midgap of ∼2×1012 cm−2 eV−1 .
Chapter 8
General conclusions and
outlook
8.1
General conclusions
In this work, CV and GV methods of electrical characterization have been
combined with ESR analysis to study charge properties and distribution
of traps at interfaces of both traditional silicon and high-mobility
semiconductors such as SiGe Ge, and AIII BV . The studied insulators
were ranging from thermal SiO2 to its high-κ counterparts such as HfO2 and
TaSiOx . Extension of the electrical characterization to low temperatures
enabled us to provide more reliable results by suppressing the minority
carrier response and thermal emission of charge carriers from interface
traps.
The major conclusions of the thesis can be summarized as follows:
1. It is found that the interface trap Dit is highly sensitive to the Si
face orientation, the highest density encountered at the (111) face,
and lowest at the (100) face, with the (110)Si/SiO2 interface closely
resembling the (111)Si/SiO2 case. Two peaks in the Dit (E) profile
within Si band gap, at about 0.25 eV and 0.85 eV above the VB,
are observed for all three orientations and appear to be strongly
correlated with the presence of paramagnetic interfacial Pb defects and
135
136
General conclusions and outlook
responsible for the majority of interface charge traps. By comparing
CV curves at 300 K and 77 K measured both on p- and n-type samples,
we affirmed the amphoteric properties of traps at all three Si/SiO2
interfaces.
While the atomic nature and the energy distribution of the traps at
the studied interfaces are very similar, comparison between the density
of the Si Pb(0) -centers and the areal density of (110)Si/SiO2 interface
traps reveals that not all Pb(0) s are acting as charge traps. We suggest
clustering of the interfacial Si-dangling bond defects as the possible
mechanism of electrical inactivation of part of the Pb0 -centers at the
(110)Si/SiO2 interface.
2. This work indicates that low temperature (77 K) CV measurements
can be used to extract charge trap properties in c-Si/a-Si:H structures.
Combined with ESR analysis, these experiments reveal the presence
electrically active Pb0 defects at the (100)Si/intrinsic a-Si:H interface
and D-centers distributed throughout the a-Si layer are detected
both by electrically and ESR techniques in similar densities. The
significance of this work lies in the atomic identification of defects in
this stack, coupled with their electrical activity.
3. The investigated kinetics of hydrogen passivation and depassivation of
Ge DBs at Si0.25 Ge0.75 /SiO2 interfaces suggests that the passivation
of the Ge DB defects (GePb1 centers) occurs similarly to the case of
SiPb defects, with the mechanism of defect-hydrogen interaction well
described by the GST model. For passivation in molecular hydrogen,
the kinetic parameters are Ef =1.44±0.04 eV, σEf =0.2±0.02 eV, for
kf0 =1.1(+0.5/-0.8)×10−8 cm3 s−1 . The kinetic parameters of the GeH dissociation reaction are Ed =2.23±0.04 eV, σEd =0.14±0.02 eV
for kd0 =(1.5±1)×1013 s−1 . These activation energies are somewhat
smaller than those in the case of interfacial Si DBs (Pb -type centers at
Si/SiO2 interfaces). However, the values of spreads are much higher
than those obtained for SiPb , which explains the reduced passivation
efficiency of GePb1 centers.
The GePb1 centers cannot be passivated effectively in molecular H2 to
device-grade level for thermal budgets up to 400 o C with only ∼60 %
inactivation obtained. This is a direct consequence of the excessive
spreads in activation energies of the passivation and dissociation
processes.
FUTURE OUTLOOK
137
4. We demonstrated that the passivation method by using an interlayer
such as Si/SiO2 or Ge3 N4 is a prospective way to improve electrical
properties of Ge interfaces.
In the case of passivation by a Si/SiO2 interlayer, we have
demonstrated that a Si passivation layer grown using silcore at 350 o C
shows lower interface trap density in Ge/HfO2 structures than the
passivation using Si grown from silane at a higher temperature (500 o C).
The best interface was found in the sample with 4 Si-MLs growth
from silcore source at 350 o C.
In n-Ge/metal contacts, passivation by a plasma-grown Ge3 N4 IL
allows for solving the problem of Fermi level pinning on n-type Ge.
Both amorphous and epitaxial Ge3 N4 effectively unpin the Fermi level,
resulting in a linear dependence of the metal/semiconductor barrier
height on the metal work function with pinning factors S of 0.37
and 0.43 for amorphous-Ge3 N4 and crystalline-Ge3 N4 , respectively.
Aluminum contacts on 1.2-nm amorphous and epitaxial Ge3 N4 show
SBHs of 0.09 ± 0.05 and 0.02 ± 0.1 eV, respectively, i.e., nearly Ohmic
behavior.
5. Results of the interface trap analysis on III-V samples including ALDTaSiOx /InP, ALD-TaSiOx /In0.53 Ga0.47 As and HfO2 /In0.53 Ga0.47 As,
indicate that trap densities at ALD-TaSiOx /In0.53 Ga0.47 As and ALDTaSiOx /InP interfaces are reasonably low close to the conduction band
edge energies, in the order of ∼1012 cm−2 eV−1 . However, electron
injection from the semiconductor causes charge trapping in the silicate
layer, challenging the usefulness of such structures in MOSFET devices.
The presence of Al at the n-type In0.53 Ga0.47 As/HfO2 interface
improves the electrical quality of the interface. Dit near the
semiconductor midgap is estimated close to 2×1012 cm−2 eV−1 .
8.2
Future outlook
Experience gained in the course of the present work indicates that electrical
characterization needs refinement if applied to narrow-gap materials. Several
ways to improve on this can be proposed:
138
General conclusions and outlook
• Low-T CV/GV measurements become imperative to obtain reliable
trap information; For a narrow-gap semiconductor, further lowering
of the measurement temperature below 77 K may be of interest.
• The difficulty in attaining high-frequency response suggests transition
to radio-frequency (RF) measurements as the next step, which would
exclude the interface trap and minority carrier generation effects on
HF CV curves.
• A major issue when applying CV and GV methods to MOS samples
with ultrathin insulators is related to difficulties with ψs determination
since it becomes impossible to find it from quasi-static CV curve
because of leakages. A possible alternative technique using saturation
photovoltage measurements is suggested to determine ψs .
One more element that may draw future attention regards the charge state
of the studied Ge DB defect at the SiGe/SiO2 interfaces of the condensation
grown (100)Si/SiO2 /Gex Si1−x /SiO2 entities. CV measurements in the
temperature range T≥77 K in conjunction with ESR probing have
established close one-to-one correlation of the ESR active GePb1 center
with a negative charge (acceptor) trap. However, from ESR standpoint and
insight, the GePb1 center, which by ESR could so far only be observed at
liquid-He temperatures, is in the neutral charge state when ESR active: if
turning to the negative state, it would disappear from ESR screen. So, one
may aim for some deeper understanding of this charge “switching” aspect.
More insight here may come from attempting to expand ESR observations
up to ∼77 K. This however will be much demanding because of basic
spectroscopic/physical sensitivity limitations encountered with conventional
ESR spectrometers.
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List of publications
1. N. H. Thoan, K. Keunen, V. V. Afanas’ev, and A. Stesmans,
Interface state energy distribution and Pb defects at (110)Si/SiO2
interfaces: Comparison to (111) and (100) silicon orientations.
J. Appl. Phys. 109, 013710, (2011).
2. R. R. Lieten, V. V. Afanas’ev, N. H. Thoan, S. Degroote, W.
Walukiewicz, and G. Borghs,
Mechanisms of Schottky Barrier Control on n-Type Germanium Using
Ge3 N4 Interlayers.
J. Electrochem. Soc. 158, H358 (2011).
3. N. H. Thoan, M. Jivanescu, B. J. O’Sullivan, L. Pantisano, I. Gordon,
V. V. Afanas’ev, and A. Stesmans,
Correlation between interface traps and paramagnetic defects in c-Si/aSi:H heterojunctions.
Appl. Phys. Lett. 100, 142101 (2012).
4. V. V. Afanas’ev, H.-Y. Chou, N. H. Thoan, C. Adelmann, H. C.
Lin, M. Houssa, and A. Stesmans,
Charge instability of atomic-layer deposited TaSiOx insulators on Si,
InP, and In0.53 Ga0.47 As.
Appl. Phys. Lett. 100, 202104 (2012).
5. B.J. O’Sullivan, N.H. Thoan, M. Jivanescu, L. Pantisano, T. Bearda,
F. Dross, I. Gordon, V. Afanas’ev, A. Stesmans, and J. Poortmans,
Atomic and electrical characterisation of amorphous silicon passivation
layers.
Energy Procedia, 27, 185 (2012).
153
154
List of publications
6. H. Y. Chou, V. V. Afanas’ev, N. H. Thoan, C. Adelmann, H. C.
Lin, M. Houssa, and A. Stesmans,
Internal Photoemission at Interfaces of ALD TaSiOx Insulating Layers
Deposited on Si, InP and In0.53 Ga0.47 As.
IOP Conference Series-Materials Science and Engineering, Vol. 41,
2012, p. 012019.
7. N. H. Thoan, A. P. D. Nguyen, A. Stesmans, K. Keunen, and V. V.
Afanas’ev,
Chemical kinetics of the hydrogen-GePb1 defect interaction at the
(100)Gex Si1−x /SiO2 interface.
J. Vac. Sci. Technol. B 31, 010603 (2013).
8. N. H. Thoan, A. Stesmans, and V. V. Afanas’ev,
Hydrogen interaction kinetics of Ge dangling bond defects at
(100)Gex Si1−x /SiO2 interfaces .
J. Appl. Phys. (To be summitted).
Arenberg Doctoral School of Science, Engineering & Technology
Faculty of Science
Department of Physics and Astronomy
Semiconductor Physics Laboratory
Celestijnenlaan 200D, B-3001, Leuven, Belgium