clk byte_length[31:0] write_addr[31:0] read_addr[31:0] dma_en reset_0 Multiplier P[63:0] dma_done mul_result[63:0] B[31:0] A[31:0] Core_v1_0 addr_valid byte_length[31:0] write_addr[31:0] read_addr[31:0] dma_en operand2_mul[31:0] operand1_mul[31:0] write_data_valid write_data[31:0] mem_done dcache_data[31:0] addr[31:0] fetch_instr_pc[63:0] CLK mult_gen_0 write_mem read_mem j_addr[31:0] j_accept ecall stop_fetch stop rst_n clk Core_0 interface_aximm fetch_instr_pc[63:0] S_AXI_LITE axi_cdma_0 M_AXI cdma_introut AXI Central Direct Memory Access s_axi_lite_aresetn byte_length[31:0] CDMA_Control_v1_0 peripheral_reset[0:0] peripheral_aresetn[0:0] interconnect_aresetn[0:0] Processor System Reset m_axi_aclk mb_reset bus_struct_reset[0:0] proc_sys_reset_0 s_axi_lite_aclk dma_done interface_aximm dcm_locked mb_debug_sys_rst aux_reset_in Initializing System Cache ARESETN M0_AXI DCache S0_AXI ACLK Initializing M0_AXI ICache System Cache ARESETN slowest_sync_clk ext_reset_in S0_AXI ACLK write_addr[31:0] read_addr[31:0] dma_en rst_n clk CDMA_Control_0 result[31:0] mem_done interface_aximm DCache_Controller_v1_0 cache_rst_done write_data_valid write_data[31:0] addr_valid addr[31:0] write_mem read_mem rst_n clk DCache_Controller_0 ICache_Controller_v1_0 cache_rst_done j_addr[31:0] j_accept ecall ICache_Controller_0 stop_fetch stop rst_n clk axi_interconnect_0 M01_AXI M00_AXI AXI Interconnect (Discontinued) M01_ARESETN M01_ACLK M00_ARESETN M00_ACLK S02_ARESETN S02_ACLK S01_ARESETN S01_ACLK S00_ARESETN S00_ACLK ARESETN ACLK S02_AXI S01_AXI S00_AXI S_AXI APB_M AXI APB Bridge s_axi_aresetn s_axi_aclk AXI4_LITE axi_apb_bridge_0 AXI BRAM Controller BRAM_PORTA axi_bram_ctrl_0 s_axi_aresetn s_axi_aclk Block Memory Generator rsta_busy axi_bram_ctrl_0_bram BRAM_PORTA APB_M_0