IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 71, NO. 1, JANUARY 2024
301
Memristor-Inspired Digital Logic Circuits and
Comparison With 90-/180-nm
CMOS Technologies
Megha Nawaria, Sanjay Kumar , Member, IEEE, Mohit Kumar Gautam ,
Narendra Singh Dhakad , Rohit Singh , Member, IEEE, Sonal Singhal, Member, IEEE,
Pawan Kumar , Graduate Student Member, IEEE, Santosh Kumar Vishvakarma , Senior Member, IEEE,
and Shaibal Mukherjee , Senior Member, IEEE
Abstract— Compact low-power devices with ultrafast
processing speed are the fundamental building blocks
for the development of the state-of-the-art logic systems
and memristor prominently fulfills these demands and
plays a major role in digital circuit design. In this work,
design, implementation, and performance evaluation of
memristor-based logic gates, such as NOT, AND, NAND, OR,
NOR, XOR, and XNOR, and combinational logic circuits, such
as adder, subtractor, and 2 × 1 mux, are presented via
SPECTRE in Cadence Virtuoso. Herein, we propose an
optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis
with the conventional 180-nm complementary metal–oxide–
semiconductor (CMOS) technology. The utilized memristor
model is thoroughly validated with the experimental results
of a high-density Y2 O3 -based memristive crossbar array
(MCA), which shows a significantly low values of coefficient
of variabilities in device-to-device (D2D) and cycle-to-cycle
(C2C) operation. The area, power, and delay calculated from
these combinational circuits are found to be reduced by
more than 71.4%, 40%, and 54%, respectively, as compared
to the conventional 180-nm CMOS technology. The impact
of multiple CMOS technology nodes (90 and 180 nm) on the
power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristorbased design significantly improves the performance of
various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.
Index Terms— Combinational logic circuits, complementary metal–oxide–semiconductor (CMOS), logic gates,
memristor, power efficient.
I. I NTRODUCTION
Manuscript received 8 April 2023; revised 18 May 2023; accepted
18 May 2023. Date of publication 5 June 2023; date of current version 2 January 2024. This work was supported in part by the Council of Scientific and Industrial Research (CSIR) Project under Grant
22(0841)/20/EMR-II and in part by JSPS Invitational Fellowship under
Grant S23062. The review of this article was arranged by Editor
R. A. Sporea. (Corresponding author: Shaibal Mukherjee.)
Megha Nawaria is with the Hybrid Nanodevice Research Group
(HNRG), Department of Electrical Engineering, Indian Institute of Technology Indore, Indore, Madhya Pradesh 453552, India.
Sanjay Kumar is with the School of Engineering, University of Edinburgh, EH8 9YL Scotland, U.K.
Mohit Kumar Gautam is with Qualcomm India Private Ltd., Bengaluru
560037, India.
Narendra Singh Dhakad and Santosh Kumar Vishvakarma are with
Nanoscale Devices, VLSI Circuit and System Design (NSDCS), Department of Electrical Engineering, Indian Institute of Technology Indore,
Indore, Madhya Pradesh 453552, India.
Rohit Singh and Sonal Singhal are with the Electrical Engineering
Department, Shiv Nadar Institution of Eminence (Deemed to be University), Dadri 201314, India.
Pawan Kumar is with the Department of Electrical Engineering, Indian
Institute of Technology Delhi, New Delhi 110016, India.
Shaibal Mukherjee is with the Hybrid Nanodevice Research Group
(HNRG), Department of Electrical Engineering and the Centre for
Advanced Electronics (CAE), Indian Institute of Technology Indore,
Indore, Madhya Pradesh 453552, India, and also with the School of
Engineering, RMIT University, Melbourne, VIC 3001, Australia (e-mail:
shaibal@iiti.ac.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2023.3278625.
Digital Object Identifier 10.1109/TED.2023.3278625
N THE past several decades, complementary metal–oxide–
semiconductor (CMOS) technology has led to digital
electronics design and implement various digital circuits to
perform logic operations [1].
However, over the period of time, the CMOS technology
has suffered from diverse challenges in terms of usage of
large chip area, high power consumption, and low data processing speed leading to the saturation of scaling and device
performance [2]. Also, CMOS-based logic circuits suffer from
high-leakage power consumption, which further reduces the
device reliability [2]. The nanoscale memristors have the
remarkable potential to overcome these limitations with their
high scalability [3], high operating speed [4], high density
in crossbar array architecture [4], and nonvolatile nature [5].
Therefore, the capability of memristive devices can pave a
new path for future computer technology, wherein it may
instantaneously flip ON and OFF without loss of data and also
reduces the boot time of the system. On the other hand,
the physical limitations of the current CMOS transistor push
back the chip size and density due to scaling effects while
memristive technology is already on the edge to hit those
barriers effectively [6]. The memristor technology offers computing via vector-matrix multiplication in resource-intensive
applications with low power consumption [7], high storage
I
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TABLE I
C OMPARISON B ETWEEN O UR M ODEL W ITH OTHER
R EPORTED M ODELS
capability due to remarkable scaling ability [4], [8], [9], [10],
fast processing speed [4], and ability to compute new logic
patterns for computers.
In this article, several logic gates, such as NOT, AND, NAND,
OR , NOR , XOR, and XNOR , and combinational logic circuits,
such as 2 × 1 mux, full adder, and full subtractor, have been
designed and implemented using industry-standard Verilog-A
coding in the Cadence Virtuoso platform. Herein, a nonlinear analytical memristor model [11] is used to implement
logic circuits as mentioned above. The utilized memristor
model is thoroughly validated by the experimental results of
Y2 O3 -based single memristor and memristive crossbar arrays
(MCAs) that display stable switching response with ultralow
values of device-to-device (D2D) and cycle-to-cycle (C2C)
variability parameters [12].
This article is organized as follows. Section II introduces
the adopted experimentally validated memristor model, its
comparison with other reported models, and the physical
interpretation of the utilized parameters in analytical modeling.
Section III describes the process of logic circuits implementation with memristor and their circuit layouts. Section IV
describes the results and discussion by considering the performance evaluation parameters, such as area, power, and
delay comparison with the existing 180-nm CMOS technology
of the implemented logic circuits. Also, this section has
outlined the effect of CMOS technology nodes on circuit
power consumption. Section V summarizes the conclusion and
future scope of the research work.
II. M EMRISTOR M ODEL
In the past one decade, several mathematical models [13],
[14], [15], [16], [17] for memristor have been reported,
as discussed in Table I. These reported models show their
compatibility on various simulation platforms to perform the
resistive switching response. Table I shows the comparative
study between the proposed nonlinear analytical memristor
model [11] with other reported models [11], [12], [13], [14].
TABLE II
P HYSICAL I NTERPRETATION AND N UMERICAL VALUES OF
PARAMETERS U SED IN M ODELING
Here, (1) defines the current–voltage (I –V ) relationship of the
proposed analytical model, wherein several constants are used.
Table II shows the numerical values and physical significance
of the various parameters utilized in the following equation:
b1 wa1 eα1 Vi (t) − 1 + χ eγ Vi (t) − 1, Vi (t) ⩾ 0
I (t) =
.
b2 wa2 eα2 Vi (t) − 1 + χ eγ Vi (t) − 1 , Vi (t) < 0
(1)
Here, first component on the right-hand side of (1) represents flux-controlled memristive behavior with interfacial
switching mechanism, while the second term denotes the ideal
diode behavior in I –V characteristics and Vi (t) is the applied
input voltage.
Equation (2) describes a piecewise window function, f (w),
that assures the state variable (w) is between 0 and 1. The
range of parameter psets the limit of f (w) between 0 and 1,
and if p > 10, the upper value of f (w) is more than 1, which
clearly violates the essential conditions for window function,
as reported by Prodromakis et al. [18]


 (1 + w) p , 0 ≤ w ≤ 0.1 
0.1 < w ≤ 0.9 .
(1.1) p ,
f (w) = log
(2)


(2 − w) p , 0.9 < w ≤ 1
The time derivative of the state variable w(t) is represented
by the following equation, which is also dependent on the
nature of input voltage and window function:
dω
= A × vim (t) × f (w).
(3)
dt
It is evident from (3), constants A and m are the two
independent variables, which affect the time derivative of the
state variable. To ensure that the opposite polarity of the
applied voltage results in the opposite change in the rate of
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NAWARIA: MEMRISTOR-INSPIRED DIGITAL LOGIC CIRCUITS AND COMPARISON
303
Fig. 1. Implemented circuits for (a) NOT gate, (b) AND gate, (c) NAND gate, (d) NOR gate, (e) OR gate, (f) XOR gate, and (g) XNOR gate.
change of the state variable wherein parameter m must always
be an odd number. Most importantly, the previously described
models [14], [16] are dominated for bipolar memristive system, while the proposed memristor model is well suited for
both unipolar and bipolar memristive systems.
III. L OGIC C IRCUIT W ITH M EMRISTOR
Fig. 1 shows the implemented logic gates, such as NOT [see
Fig. 1(a)], AND [see Fig. 1(b)], NAND [see Fig. 1(c)], NOR
[see Fig. 1(d)], OR [see Fig. 1(e)], XOR [see Fig. 1(f)], and
XNOR [see Fig. 1(g)]. As seen from Fig. 1, one terminal of the
memristor is connected to a dc voltage source, i.e., Vdd and VIN
and VOUT are referred to as the input and output voltage signals, respectively. Here, it should be noted that when VIN = 1
(high input voltage), the transistor turns “on,” and the memristor is in “SET” condition with R M = Ron . At the same time, ntype metal–oxide–semiconductor (nMOS) is in the saturation
mode wherein the “ON” resistance RT is near equal to 0.
On the other hand, when VIN = 0 (low input voltage), the
transistor is in the “cutoff” region, but the memristor holds
the previous resistance value, and hence, VOUT is near equal
to “1” followed by some voltage drop across the memristor [7].
For the NAND logic operation, the output is “0” whenever both
serially connected transistors are in “ON” condition, and while
in the case of NOR gate operation, the output becomes “1”
whenever both transistors are in the “OFF” state. The similar
logic operations are also followed in the case of AND, OR,
XOR ,and XNOR logic gates. In this proposed work, the memristor acts as a variable resistor that has the ability to program,
store, and retain the previous input pattern and provide an output that is the function of current and past stored values. Here,
an nMOS transistor acts as a switch. The nMOS transistors
can control the memristor’s resistance, which further extends
the use of memristor in programmable logic circuits to implement the power-efficient circuitries for signal processing [19],
pattern recognition [20], and neural network applications [6].
Wang et al. [21] have implemented one-transistor one-resistor
(1T1R) configuration and performed 16 arbitrary Boolean
logic functions (AND, NAND, XNOR, and NOR), which can
be implemented with two sequential steps. The outcomes of
these logic computation are stored in the nonvolatile resistive
state of the memory and can be read out by an additional step.
Shen et al. [22] have reported the experimental demonstration
of the 1T1R configuration, wherein NAND and XOR operations
have been performed. Herein, the transistor is used in the dualgate voltage operation scheme, which effectively enhanced
the robustness of 1T1R configuration as compared with the
conventional scheme in 1R array.
By considering the aforementioned logic circuits, various
combinational logic circuits, such as full adder, full subtractor,
and a multiplexer, can also be implemented, which consume
less space, power, and time to perform the desired logic operations as compared to the conventional CMOS technology [23].
Here, Fig. 2 shows the combinational logic circuits, such
as full adder [see Fig. 2(a)], full subtractor [see Fig. 2(b)],
and 2 × 1 multiplexer (mux) [see Fig. 2(c)].
IV. R ESULTS AND D ISCUSSION
To design, implement, and evaluate the memristor-based and
traditional CMOS-based logic circuits, the industry-standard
Cadence Virtuoso platform (gpdk 180 nm) is utilized with an
identical set of input voltages, wherein two different pulses
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 71, NO. 1, JANUARY 2024
Fig. 2. Implemented circuits for (a) full adder, (b) full subtractor, and (c) 2 × 1 multiplexer (mux).
Fig. 3.
Transient responses for (a) AND, OR, NAND, NOR, XOR,and
XNORgates, (b) NOT gate, and (c) full adder and full subtractor.
Fig. 4. Transient response of a 2 × 1 multiplexer.
with the same time period but different duty cycles. The
identical set of input voltages ensures the correct functionality
of all logic circuits with the same level of supply voltage,
i.e., 1 V. Here, Fig. 3 shows the transient output responses
of the memristor-based various logic circuits, such as AND,
OR , NAND , NOR , XOR , and XNOR gates [see Fig. 3(a)], NOT
gate [see Fig. 3(b)], and full adder and full subtractor [see
Fig. 3(c)]. In addition, the proposed memristor model is fully
capable to perform the 2 × 1 mux logic operation, and output
transient response is depicted in Fig. 4.
As observed from Table III, the total number of devices
in the memristor-based logic is less than that in the CMOSbased logic circuits because a thousand memristors can be
fabricated on the same chip-level area as consumed by a single
CMOS. Here, the area utilized by a memristor is 9 nm2 ,
while the CMOS transistor consumes an area of 784 nm2
[25]. Therefore, a memristor captures 98.85% less space than
a CMOS transistor for chip-level implementation.
A. Area Comparison
B. Power Comparison
The design area of any logic circuit is the important physical
parameter and its optimization is the critical task to design the
area efficient layout. It should be noted that if the number of
devices in the circuit is increased, then the circuit consumes
more area and power as compared to the circuit, which has
a relatively lesser number of devices. Here, Table III shows a
comparative analysis between a number of devices used in the
memristor-based and CMOS-based logic circuits [24].
The primary goal of the represented work is to design
and implement various logic circuits, which perform the
logic operations with better power efficiency as compared to
conventional CMOS technology. Here, the calculated power
is dependent on the output voltage and thus varies according
to the type of logic gate. The output waveform for different
circuits will be distinct for the same sets of input, and hence,
the power dissipation for all logic gates and different models
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NAWARIA: MEMRISTOR-INSPIRED DIGITAL LOGIC CIRCUITS AND COMPARISON
305
TABLE III
A REA C ALCULATION FOR CMOS- AND M EMRISTOR -B ASED
L OGIC C IRCUITS
can be differentiated [24]. Here, (4) is utilized to calculate the
power of the implemented logic circuits
Z
1 T
Voutput × Iinput1 + Iinput2 dt .
(4)
Power =
T 0
For the two-input logic gate, four permutations are possible, such as {00}, {01}, {10}, and {11}, and the power
of each permutation has been calculated and considered for
the evaluation. After the calculation, the logic permutation is
considered which utilizes the highest power among them, and
this is assumed to represent the worst case scenario of utilized
power in a particular logic gate.
To evaluate the power consumption during logic operation,
an input pulse is applied in such a way that all four combinations are changed in a single time period, and the value of
“T ” (T is the time required for each logic operation) varies
according to the logic combination under operation. Next, the
power is calculated utilizing the aforementioned method by
integrating the total of all input currents and multiplying it by
the output voltage at a certain time instant. Fig. 5 shows the
power consumption comparative analysis between memristorbased and CMOS-based logic circuits.
As observed from Fig. 5, the massive advantage of
memristor-based logic circuits is that these consume significantly less power as compared to that by the existing
CMOS technology, which further extends the capabilities of
the memristors to implement power-efficient logic circuits
for a wide range of applications. As seen from Fig. 5(a),
the CMOS-based XNOR gate consumes the highest power
among all the logic gates, while after the introduction of the
memristor-based XNOR logic gate, the power consumption is
reduced by 56.04%. Similarly, the memristor-based NAND,
NOT, NOR , AND , OR , and XOR logic gates reduce power
Fig. 5. Comparison of power consumption between memristor-based
and CMOS-based (a) logic gate circuits and (b) combinational logic
circuits.
Fig. 6. Impact of CMOS technology node on power consumption for
(a) CMOS-based and (b) memristor-based logic circuits.
consumption by 77.29%, 53.55%, 58.95%, 51.30%, 16.38%,
and 38.83%, respectively, as compared to the corresponding
CMOS technology. In case of combinational logic circuits,
a 2 × 1 mux, full adder, and full subtractor result in a
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delay [24]. Here, Fig. 7 depicts the input and output waveform
patterns and their timing parameters
Tphl + Tplh
.
(5)
2
Fig. 8 depicts the comparative analysis of delay between
memristor-based and CMOS-based logic circuits. For the delay
calculation, the time difference between the input and output
waveform is considered wherein both input and output reach
50% of the value and then subtract their times. As observed
from Fig. 8(a), the XNOR and XOR gates have most complex
circuitry, which provides the enormous decrement in the delay
as compared to the existing CMOS technology.
In the case of memristor-based logic gates, such as NOT,
AND , NAND , OR , NOR, XOR , and XNOR show 58.34%,
52.82%, 42.93%, 55.69%, 61.83%, 65.78%, and 85.42% delay
improvement, respectively, as compared to CMOS technology [see Fig. 8(a)], while the combinational logic circuits,
such as 2 × 1 mux, full adder, and full subtractor, display
54.31%, 83.35% (sum), 46.48% (carry), 69.54% (difference),
and 54.31% (borrow) delay improvement, respectively, in comparison to the existing CMOS technology [see Fig. 8(b)].
Average delay =
Fig. 7.
delay.
Input and output waveforms for the NOT gate to calculate the
Fig. 8. Comparison of delay between memristor-based and CMOSbased. (a) Logic gates. (b) Combinational logic circuits.
reduction of power consumption by 64.51%, 42.08%, and
40.49%, respectively, in comparison to the corresponding
existing CMOS technology.
However, power consumption is also dependent on the
CMOS technology node and it can be further reduced if
a lower technology node is adopted, as shown in Fig. 6.
As seen from Fig. 6(a), the CMOS technology with 90-nm
node consumes comparatively less power than its 180-nm
technology counterparts, while the power consumption by the
memristor-based logic circuits is much lower than the preexisting CMOS technology nodes, as shown in Fig. 6(b).
C. Delay Measurement
The delay is referred to the time required to obtain the
output after applying the inputs. Here, the average delay is
considered, which is dependent on the rise time and fall
time delay. Equation (5) is utilized to evaluate the average
V. C ONCLUSION AND F UTURE O UTLOOK
Here, we propose a nonlinear memristor analytical model to
design and implement various logic gates and combinational
logic circuits via industry-standard Cadence Virtuoso. The
model is experimentally validated and demonstrated utilizing low-variance in-house fabricated MCAs. Moreover, the
memristor-based logic circuits show significantly better performance in terms of the usage of number of components,
total circuit chip area, and utilized power as compared to
those for the existing CMOS-based combinational logic circuits, wherein 180-nm CMOS technology has been utilized.
Furthermore, the presented study reveals that the variation in
the CMOS technology nodes (from 180 to 90 nm) significantly affects the power consumption in the logic circuitry.
Therefore, the designed circuits are highly reliable for their
use in future complex circuits and integrated circuits (ICs).
Furthermore, this work can be further extended by designing
and implementing power, area and delay efficient circuits for
the amplifier, oscillator, and neural networks.
ACKNOWLEDGMENT
Megha Nawaria would like to thank the Shiv Nadar Institution of Eminence (Deemed to be University), Dadri, India, for
providing access of the Cadence Virtuoso platform to perform
the circuits simulation work.
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