Project Report: MOSFET Sizing for Delay
Optimization in Logic Gates
1. Introduction
In Very Large Scale Integration (VLSI) design, precise timing is critical for high-performance
digital circuits. Logic gates, such as NOR and NAND gates, are fundamental building blocks,
and their propagation delay directly impacts system performance. This study focuses on
optimizing MOSFET sizing to minimize propagation delays in 2-input NOR and NAND gates,
ensuring balanced rise and fall times. Conducted at the Indian Institute of Technology
Kanpur using Electric and LT-Spice tools, this project investigates the relationship between
transistor sizing, delay, and power consumption under varying load conditions, with
applications in high-speed digital systems.
2. Experimental Methodology
The experiment involved designing schematics and layouts for 2-input NOR and NAND
gates using the Electric tool, followed by transient simulations in LT-Spice. MOSFET sizes
(n-MOS and p-MOS widths) were adjusted to achieve equal rise and fall times, optimizing
propagation delay. Performance metrics, including propagation delay (t_phl, t_plh, t_p) and
power consumption, were evaluated for load capacitances of 5 fF and 50 fF. Design Rule
Check (DRC) and Layout vs. Schematic (LVS) verifications ensured design accuracy.
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Key observations included:
• Delay Reduction with Sizing: Larger transistor widths reduced delay by increasing
drive current.
• Parasitic Effects: Layout parasitics slightly increased delays compared to schematics.
• Balanced Sizing: Optimal n-MOS to p-MOS ratios ensured symmetric rise and fall
times.
3. LT-Spice Simulation Flow
The simulation flow involved:
- Schematic Design: Creating NOR and NAND gate schematics in Electric.
- Input Signals: Applying pulse inputs to measure rise and fall times.
- Parametric Analysis: Varying MOSFET widths to equalize rise and fall times.
- Transient Simulation: Measuring propagation delays (t_phl, t_plh, t_p) and power
consumption.
- Layout Verification: Performing DRC and LVS checks, followed by layout-based
simulations.
4. Circuit Schematic Setup
NOR Gate:
- Transistors: Two n-MOS and two p-MOS transistors.
- Sizing: n-MOS = 5 µm, p-MOS = 12 µm (optimized for equal rise/fall times).
- Input Signals:
VIN1 A 0 PULSE 0 'SUPPLY' 100PS 20PS 20PS 500PS 1000PS
VIN2 B 0 PULSE 0 'SUPPLY' 200PS 20PS 20PS 500PS 1000PS
- Load: 5 fF and 50 fF capacitors.
NAND Gate:
- Transistors: Two n-MOS and two p-MOS transistors.
- Sizing: n-MOS = 6 µm, p-MOS = 10 µm.
- Input Signals:
VIN1 A 0 PULSE 0 'SUPPLY' 100PS 20PS 20PS 300PS 500PS
VIN2 B 0 PULSE 0 'SUPPLY' 640PS 20PS 20PS 200PS 500PS
5. Transient Waveform Results
Figure 1: NOR Gate Propagation Delay vs Load
Figure 2: NAND Gate Propagation Delay vs Load
6. Results and Analysis
Refer to the attached Excel file for detailed results and delay/power values under different
load conditions.
7. Conclusion
This study demonstrated that MOSFET sizing significantly impacts propagation delay in
NOR and NAND gates. Optimal sizing (n-MOS = 5, p-MOS = 12 for NOR; n-MOS = 6, p-MOS =
10 for NAND) achieved balanced rise/fall times and minimized delays. Corrected power
values (positive magnitudes) confirmed expected dynamic power trends, with layouts
consuming slightly more due to parasitics. The NAND gate’s high layout delay at 50 fF
highlights the need for parasitic optimization. The LT-Spice simulation flow provided a
robust methodology for performance optimization, applicable to advanced VLSI systems.
8. Remarks by Industry Mentor
The systematic approach to sizing and verification is commendable. The corrected power
values align with expected CMOS behavior. The NOR gate results are robust, but the NAND
gate’s high layout delay at 50 fF requires further parasitic analysis. Consider mobility-based
sizing for future work.
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