Circuit Optimization Virtuoso ADE Assembler Product Version: IC6.1.8, ICADVM18.1 August 2019 Copyright Statement © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2 Circuit Optimization Contents Introduction .............................................................................................................. 4 Intended Audience................................................................................................ 4 Overview .............................................................................................................. 4 Circuit Optimization Overview .................................................................................. 5 Circuit Optimization Definitions ............................................................................. 5 Pros and Cons of Circuit Optimization .................................................................. 8 Circuit Optimization Flow ......................................................................................... 9 Data Preparation .................................................................................................... 11 Setup Common to Global and Local Optimization.................................................. 12 Running Circuit Optimization with Global Optimization .......................................... 21 Running Circuit Optimization with Local Optimization ............................................ 26 Running Circuit Optimization Considering Process Variation ................................. 33 Overall Flow........................................................................................................ 33 Steps to Run Optimization Considering Process Variation ................................. 34 Circuit Optimization Results ................................................................................... 41 Results ............................................................................................................... 41 Comparison between Manual Design and Circuit Optimization Design .............. 42 Support .................................................................................................................. 42 Feedback ............................................................................................................... 42 Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 3 Circuit Optimization Introduction This document describes the application of circuit optimization using Virtuoso ADE. Intended Audience The audience includes circuit designers who are interested in reducing the time and effort spent in sizing the circuit device parameters to meet the specifications over corners. Overview This document focuses on the steps to apply circuit optimization. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 4 Circuit Optimization Circuit Optimization Overview This chapter describes circuit optimization and algorithm types. Circuit Optimization Definitions Circuit optimization is an iterative mathematical process to search the circuit design space to find the most optimal solution without simulating all possible combinations as in a brute force sweep. The optimization algorithm does not have circuit knowledge itself. The algorithm attempts to solve a mathematical optimization problem. • • Device parameters with sweep ranges Output measurements including specification targets Circuit Optimization Optimal Solution Figure 1 Optimization Flow Overview Inputs to optimization include the circuit device parameters, output measurements, and target specifications. The device parameter ranges define the design space. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 5 Circuit Optimization The optimizer varies device parameter values (within the allowed ranges defined by the user), simulates the circuit, and determines the cost of each simulated design point. The goal is to minimize the cost. A design point (candidate circuit for simulation) that meets all specifications has lower cost than a design point which fails to meet one or more specifications. Circuit Performance Cost Starting Point Local Optimum Global Optimum Input Parameter Figure 2 One-Dimension Example of Global and Local Optimum Global Optimization Global optimization searches multiple areas of the circuit design space to find the global minimum cost and optimal design point. The Virtuoso ADE global optimizer is based on the proven NeoCircuit technology, now in use for more than 15 years (Neolinear developed NeoCircuit and was acquired by Cadence). The global optimizer applies machine learning techniques to circuit optimization. Local Optimization Local optimization begins with a starting point and searches locally for the optimal solution. Given the one-dimensional example of Figure 2, local optimization searches the curve around the starting point and applies sensitivity analysis to determine the search direction. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 6 Circuit Optimization The Virtuoso ADE local optimization algorithms are based on publicly documented methods. BFGS is the default and recommended local optimization algorithm in Virtuoso ADE. Algorithm Description BFGS Broyden-Fletcher-Goldfarb-Shanno algorithm. This is the default and recommended algorithm for local optimization. BFGS is a gradient-based method. Gradient methods do well when the performance gradient can be calculated (output measurements return more than two or three states and do not result in evaluation errors) and design variables are naturally continuous. Conjugate Gradient A gradient-based algorithm. Not typically as efficient as BFGS. Brent-Powell Does not require a gradient. The algorithm searches in a fine grid around the starting point. Use Brent-Powell if your starting point is already close (for example, only a few specifications not met). The optimization should find the local minimum around the selected point, but it may also quit once that local minimum is found and then miss a more optimal solution in the local design space. Brent-Powell is not parallelized and runs only one point at a time, although it runs the least number of points on average compared to the other methods. Hooke-Jeeves Does not require a gradient. This method is also known as a pattern search algorithm. The algorithm searches in larger steps, but it can miss a local minimum. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 7 Circuit Optimization Pros and Cons of Circuit Optimization Circuit optimization does not replace the designer. It does not replace the need for understanding of the circuit operation. Circuit optimization saves time and effort by eliminating repetitive manual tweaks of the design. Optimization handles multiple design variables and output specifications, and automates the process of balancing the trade-offs to meet the specifications over all corners. The existing ADE setup is reused for optimization including ADE tests, variables, parameters, measurements, and specifications. It is important to define a set of circuit performance measurements (for example, ADE calculator expressions). If the designer views output waveforms to determine circuit performance, more effort must be spent in defining additional measurement expressions in order to use optimization. Additional setup is required to parameterize the design for optimization. Parameterization includes defining the matching relationships between circuit devices and defining the parameter ranges. Depending on the circuit under test, optimization may require hundreds or thousands of simulations. Optimization cannot be applied to large blocks that require very long simulation time. It is best applied to each sub-block individually to manage simulation time. For best performance, additional machine resources must be made available for optimization to search the design space more quickly. For example, you will experience reduced run time when you submit the optimization job to say 20 machines rather than running on 1 local machine. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 8 Circuit Optimization Circuit Optimization Flow This chapter describes the steps to follow to run circuit optimization in Virtuoso ADE. • Begin with the test and analysis setup in ADE Assembler. • Define output measurement expressions and set specification targets to measure the performance of the circuit. • Define a set of worst-case corners to enable for optimization. • Define the matching relationships between circuit devices (diff pairs, current mirrors, etc.). • Define parameter ranges for all devices that are part of the optimization. • Run global or local optimization. • If all specifications are not met, review the device parameter setup and design constraints, make changes as necessary, and rerun the optimization. When optimization is complete and all specifications are met, the next step is final verification over corners or Monte Carlo analysis. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 9 Circuit Optimization Circuit Testbench Device Parameterization • ADE Tests and Analyses • Output Measurements • Worst-Case VT Corners • Statistical Corners • Matching Relationships • Parameter Ranges • Global Optimization • Local Optimization Run Optimization • Size Over Corners Final Verification • Corners • Monte Carlo Figure 3 Optimization Flow Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 10 Circuit Optimization Data Preparation In this example, a sub-block of a larger PLL is optimized. The op amp of the PLL lowpass filter is optimized. It is important to break up a larger system into more manageable sub-blocks for optimization in order to reduce the simulation time. Prepare the following data prior to running optimization.: • Schematic of the sub-block to be optimized • Create the testbench and the ADE view • Model setup (statistical models required for Monte Carlo analysis) • Circuit analyses • Define output measurement expressions and specification targets • Define a set of worst-case corners • Device parameterization including matching relationships and optimization ranges Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 11 Circuit Optimization Setup Common to Global and Local Optimization This chapter describes the steps to prepare the circuit for optimization. 1. Open the design in Virtuoso ADE Assembler. Figure 4 Virtuoso ADE Assembler Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 12 Circuit Optimization 2. Create one or more ADE tests and define the analyses for each test. Figure 5 Define the ADE Tests and Analyses 3. Save only the selected signals that are required for measuring circuit performance. Do not save any other data that is not required for optimization. Saving only the necessary simulation data will reduce disk space requirements and improve run time. Figure 6 Save the Minimum Amount of Data Required for Optimization Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 13 Circuit Optimization 4. Define the output measurement expressions and specification target values. Specification types include minimize, maximize, less than (<), greater than (>), range, and tolerance. The “minimize” and “maximize” specifications are 'open-ended'. An open-ended specification is when you choose either minimize (min) or maximize (max), and then specify an ideal value. For an open-ended specification, ADE tries to continually improve upon the ideal value. So, if the ideal value for the UGF specification is “maximize to 1e+8”, 3e+8 is better than 2e+8. “Less than” or “greater than” specifications are 'close-ended'. A close-ended specification is when you specify a target value, and then specify that the resulting specification must be greater than (>) or less than (<) that target value. For a close-ended specification, ADE attempts to meet the target value, and exceeding the target is no better than meeting the target. So, if the target value for UGF is “>1e+8”, 3e+8 is no better than 2e+8. 5. Specify the 'info' type when you want to see the value of a measurement in the Optimization view, but do not want that specification to affect sizing. Figure 7 Output Expressions and Specification Targets Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 14 Circuit Optimization 6. Define a set of worst-case corners. Figure 8 Corners Setup Device parameterization constrains the circuit in terms of the allowed device parameter values (size of w, l, m, etc.). The matching relationships between instances are defined. If M0 and M1 are part of a current mirror, these two instances must be matched (or matched in ratio) rather than be sized independently. 7. Select 'Click to add' under Parameters in the Data View pane to dock the Variables and Parameters assistant on the schematic. Figure 9 Add Parameters Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 15 Circuit Optimization The schematic opens with the Variables and Parameters assistant docked on the right side. Figure 10 Variables and Parameters Assistant Docked to the Schematic Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 16 Circuit Optimization 8. Select two or more instances to match. In the Variables and Parameters assistant, select the parameters to match. Here, the two instances PM4 and PM5 of a diff pair are selected. The parameter width (total), length, and multiplier will be matched and parameterized. Figure 11 Matching the Parameters of a Differential Pair 9. Select the Match Parameters button in the Variables and Parameters assistant to create the parameters. Figure 12 Create the matched parameters Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 17 Circuit Optimization The newly created parameters are displayed in the lower half of the Variables and Parameters assistant. You did not create matched parameters for fingers and finger width parameters because they are already matched on the schematic and will not be modified during optimization. By default, the PM5 parameters appear as collapsed under PM4. PM4 defines the independent parameters, and PM5 is matched to PM4. The syntax of a matched parameter is <instance name>/<parameter name>@<lib name>/<cell name>/<view name>. If the instances are located at the same level of hierarchy, the lib/cell/view part of the parameter syntax can be omitted. Figure 13 PM5 Is Matched to PM4 Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 18 Circuit Optimization 10. Define ranges for the independent parameters. Enter the allowed range using the min:step:max syntax or specify a list of comma- or space-separated values. Figure 14 Edit the Value Column to Define the Allowed Range 11. If you do not see the parameters of interest for the selected instances, modify the Whitelist filter or change the list to view to 'Editable' or 'All'. Figure 15 Modify the Whitelist Filter Setup if Needed Figure 16 Change the View to Editable or All to Show Additional Parameters Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 19 Circuit Optimization 12. Create parameters for all other devices that will be optimized. Figure 17 Completed Set of Parameters The Run Summary form displays the total design space size. Figure 18 Size of Design Space Defined by the Parameters Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 20 Circuit Optimization Running Circuit Optimization with Global Optimization In this section, global optimization is performed without a starting point. First, you will run optimization over Nominal conditions, and then include corners. Finally, you will run optimization with the goal of minimizing power consumption of the op amp. 1. Select Global Optimization from the list of run modes. Figure 19 Select Global Optimization 2. Open the run mode options form by selecting the Options button. Figure 20 Select the Run Mode Options Button 3. Specify the global optimization options. Figure 21 Global Optimization Options Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 21 Circuit Optimization In this example, you are not providing a starting point for the optimization. The optimization will stop after all specifications are met (or the optimizer cannot find a solution). Conditional evaluation avoids unnecessary simulation by skipping points which are not an improvement on the current best point. 4. Select the Run Simulation button to start the optimization. Figure 22 Run Optimization It is typically recommended to perform a quick optimization over Nominal (with Corners disabled) to confirm that the specifications can be met. The best point of the optimization is displayed at the top of the table. Figure 23 All specs met at Nominal Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 22 Circuit Optimization Specifications are easily met at Nominal; so, corners are enabled for the next optimization run. Figure 24 All Specs Met over Corners 5. Open the Variable Display assistant to view the optimized values. Select the gray Parameters row in the Results tab for any point to view the variable values. The bar graph display is especially useful to identify if any variable is limited by its upper or lower bound. Figure 25 Variable Display Assistant Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 23 Circuit Optimization Optimizing with open-ended specifications Next, you will run an optimization to reduce power consumption. 6. Change the specification type from less than (<) to the open-ended 'minimize' type. Figure 26 Minimize the Power Spec 7. Next, change the optimization-stopping criteria. Choose to stop when there has been no improvement after 400 further points. Figure 27 Stop When No Improvement after 400 Points Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 24 Circuit Optimization 8. Run a global optimization to minimize power. Figure 28 Best-Point Result and Run Log The power was reduced from 317.7uW to 285.6uW at the worst corner AVDD_1.26_T_1. 9. Save the variable and parameter values of the best-point optimization result to a setup state. The result may also be back-annotated to the schematic. By saving the values to a setup state, you can recall the point later for simulation or you can use this result as a starting point for local optimization. Figure 29 Save the Best Point Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 25 Circuit Optimization Running Circuit Optimization with Local Optimization In this section, a local optimization is performed. Choose local optimization when you have a starting point to improve upon. You have already defined optimization ranges as follows. Before defining the starting point, save these parameter ranges to recall them later. 1. Specify a name in the Variables and Parameters assistant and then select Save to save the set of vars and parameters to the named Setup State. Figure 30 Save (Back-Up) the Optimization Parameter Ranges Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 26 Circuit Optimization 2. Next, define the starting point for the optimization. In ADE, the starting point is defined as a Setup State and defines a scalar value for each optimization variable or parameter. To create a starting point based on the current schematic design, select each parameter and then select 'Set to Design Value' from the context menu. Figure 31 Create a Starting Point Based on the Current Schematic Design The parameter values are set to the schematic values. Figure 32 Parameters Set to the Schematic Values Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 27 Circuit Optimization 3. Save this set of parameter values to a Setup State. Specify a name for the state and select Save. Figure 33 Save Schematic Design to Setup State to Use as Starting Point 4. Open the Local Optimization run options form. Select a Setup State to use as the starting point for optimization. You can choose to use the schematic starting point or the best point that was saved from the previous Global Optimization run. The result of GlobalOpt.2 is selected as the starting point. Figure 34 Set the Local Optimization Options 5. Define the parameter ranges for the local optimization. Reload the parameter ranges that were previously defined. Figure 35 Load the Parameter Ranges for Optimization Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 28 Circuit Optimization Comparing the starting point with the parameter ranges, you can see that several parameters are at their limits. For example, the Variable Display assistant shows that PM1.l = 3u, which is the upper limit of the range. Figure 36 Starting Point Compared to Ranges (Best Point GlobalOpt.2) Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 29 Circuit Optimization Another comparison of the starting point and the parameter ranges is available through the Variables and Parameters assistant. Figure 37 Select the Starting Point and Open the Compare Window Figure 38 Compare the Starting Point and Current Parameters Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 30 Circuit Optimization 6. Modify the parameter ranges to give more freedom to the local optimization. The new set of parameters were saved as 'ranges2'. Figure 39 Updated Parameter Ranges to Use for Local Optimization 7. Run local optimization. Figure 40 Run Local Optimization Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 31 Circuit Optimization When local optimization completes, the best point is displayed at the top of the Results table. All specifications are met, and power was reduced from 285.6uW (best point from the previous run) to 269.3uW at the worst corner AVDD_1.26_T_1. Figure 41 Local Optimization Results 8. Open the Variable Display assistant to view the parameter values. Select the gray-colored Parameters row in the Results table to view the values of the selected point. Figure 42 Local Optimization Result Parameter Values The result values may be back-annotated to the schematic or saved to a Setup State for further verification simulation. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 32 Circuit Optimization Running Circuit Optimization Considering Process Variation After optimization over supply voltage and temperature corners, a Monte Carlo analysis is performed for final verification. The number of Monte Carlo samples to run depends on the target yield requirement and probability (or confidence level). Given a 3-sigma target yield requirement (99.87% yield), ~2000 samples must be simulated to verify the estimate. Simulating 2000 or more samples may be very time consuming depending on the circuit. Virtuoso Variation Option provides efficient Monte Carlo methods to reduce the number of simulations for yield verification and statistical corner creation. In this section, since your op amp can be simulated quickly, you apply brute force standard Monte Carlo. Overall Flow Begin with Monte Carlo analysis and then create a statistical corner for each specification. After creating the corners, optimize the design over the statistical corners. When specifications are met over the statistical corners, you expect the yield to improve. Run a Monte Carlo analysis on the optimization result to verify that the yield has improved. Monte Carlo Create Statistical Corners Optimize Over Statistical Corners Final Monte Carlo Figure 43 Improve Yield by Optimizing over Statistical Corners Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 33 Circuit Optimization Steps to Run Optimization Considering Process Variation 1. Select the Monte Carlo Sampling run mode and specify the number of Monte Carlo sample points to simulate. Figure 44 Monte Carlo Options 2. Run Monte Carlo. Figure 45 Run Monte Carlo Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 34 Circuit Optimization The yield estimate is 37%. Figure 46 Monte Carlo Results Since the yield target is not met, statistical corners will be created. Then, the design must be modified either manually or by using optimization to meet the specifications over the statistical corners. Once the specifications are met over the statistical corners, another iteration of Monte Carlo is performed to verify the yield estimate. 3. Sort the transposed Results table to view the worst result for each specification. For each specification, sort the specification column and then select 'Create Statistical Corner' from the context menu to create the corners. Figure 47 Create Statistical Corner from Selected Result Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 35 Circuit Optimization Another method to create the corners is to select the specification from the Yield view and then select 'Create Statistical Corner from Worst Sample'. Figure 48 Create Statistical Corner from Worst Sample Notice that the statistical corners also include the supply voltage and temperature variation. You can decide if any of the original supply voltage and temperature corners are extraneous and disable them to reduce simulation time. Figure 49 Voltage, Temperature, and Statistical Corners Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 36 Circuit Optimization 4. Define the parameter ranges to prepare for optimization. Here, you load the ranges from the Setup State. Figure 50 Load the Parameter Ranges for Optimization 5. Specify the global or local optimization options. Here, local optimization is selected. The starting point is the result of the previous optimization. No stopping criteria is specified. After meeting all specifications, the optimizer will continue to run with the goal of improving on the open-ended specifications. Figure 51 Specify Local Optimization Options Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 37 Circuit Optimization 6. Run the optimization over statistical corners. The local optimization completes after a few hundred simulations. All specifications are met including those over the statistical corners. The best result point is displayed at the top of the table. Figure 52 Optimization over Statistical Corners 7. Save the best point to a Setup State. Figure 53 Save the Best Point Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 38 Circuit Optimization 8. The next step is to run Monte Carlo analysis to verify that the yield estimate has improved. In preparation for Monte Carlo, load the parameter values of the optimization result. Figure 54 Load the Result of the Optimization 9. In preparation for Monte Carlo, disable the statistical corners. Figure 55 Disable Statistical Corners Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 39 Circuit Optimization 10. Select the Monte Carlo Sampling run mode and again specify the number of Monte Carlo sample points to simulate. Figure 56 Monte Carlo Options 11. Run Monte Carlo. Figure 57 Final Monte Carlo Results All 2000 Monte Carlo samples now pass the specifications. The yield was improved by optimizing the design over statistical corners. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 40 Circuit Optimization Circuit Optimization Results Results The optimization result was verified over 2000 Monte Carlo samples. Figure 58 Final Monte Carlo Verification Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 41 Circuit Optimization Comparison between Manual Design and Circuit Optimization Design With manual design, the op amp block was verified to meet specifications over Nominal conditions. To save time and effort, optimization was applied to size the design over corners and to verify that the Monte Carlo yield target was met. Support Cadence Support Portal provides access to support resources, including an extensive knowledge base, access to software updates for Cadence products, and the ability to interact with Cadence Customer Support. Visit https://support.cadence.com. Feedback Email comments, questions, and suggestions to content_feedback@cadence.com. Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Page 42