Proceedings of the 8th International Conference on Communication and Electronics Systems (ICCES 2023)
IEEE Xplore Part Number: CFP23AWO-ART; ISBN: 979-8-3503-9663-8
2023 8th International Conference on Communication and Electronics Systems (ICCES) | 979-8-3503-9663-8/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICCES57224.2023.10192668
Performance Analysis of Different SRAM Cells
and Proposed 9T SRAM Cell
J.Ashwani
K.Deepa
B.Tech(ECE)
Madanapalle Institute of Technology & Science
Andhra Pradesh, INDIA
19699A0404@mits.ac.in
B.Tech(ECE)
Madanapalle Institute of Technology & Science
Andhra Pradesh, INDIA
19699A0417@mits.ac.in
K.Charan Kumar
Mr.B.Karthick
B.Tech(ECE)
Madanapalle Institute of Technology & Science
Andhra Pradesh, INDIA
19699A0413@mits.ac.in
Assistant Professor(ECE)
Madanapalle Institute of Technology & Science
Andhra Pradesh, INDIA
bkarthick39@gmail.com
Dr.Nehru Kandasamy
Professor(ECE)
Madanapalle Institute of Technology & Science
Andhra Pradesh, INDIA
nnehruk@gmail.com
Abstract—This article presents Designing of SRAM CELL
for low power implementations(PROP9T). The presented 9T
SRAM cell’s important layout parameters are evaluated using LTSPICE simulations. Comparable findings utilizing conventional
6T (CONV6T), conventional 7T (CONV8T), conventional 8T
(CONV8T), conventional 9T (CONV9T), and conventional 10T
(CONV10T) SRAM cells are shown with the estimated results.
The PROP9T has shown more read delay than CONV6T and
CONV8T. Two significant problems with power consumption
have been associated with CMOS technology scalability. The
problems with 6T, 7T, 8T, 9T, and 10T SRAM cells have been
reviewed in this study, and a comparison analysis based on many
factors, including read delay, power consumption and write delay
has been conducted. The SRAM array structure, which comprises
of sensing amplifiers and address decoders, is also included in
this study.
Index Terms—Write Power, Write Delay, Hold Power, Read
Delay
I. I NTRODUCTION
With the aid of recently developed technology, everyday
life has undergone a significant change and is now expanding
exponentially. A SRAM cell is made up of a latch, thus as
much as the energy is on, the cell information is maintained
and no refresh action is needed [1]. Four transistors that
make up two cross- coupled inverters store each bit in an
SRAM. The speed and energy usage of SRAM are significant
issues that have prompted several designs aimed at decreasing
energy use during both write and read operations. The memory
hierarchy of current computer systems must include highperformance on-chip caches [2].
The Stack Method refers to the procedure by which each
NMOS and PMOS transistor in the logic gates isdivided into
two transistors [3]. Because of the top NMOS transistor’s
increased supply to substrate voltages and bottom NMOS
transistor’s increased drain to source voltage, the leaky current
passing thru the NMOS transistor stack is reduced.
As a result, logic circuit power dissipation is decreased. As
comparison to a 6T traditional circuit, the suggested SRAM
memory cell uses less power during write and read operations.
For the threshold voltage area, the cell’s capacity to write
correctly and have enough read noise buffer is crucial. We
look at a few of these requirements for efficient functioning.
The study also suggests a new 9T SRAM that combines the
benefits of all these circuits. This research suggests a nine
transistor (9T) SRAM cell layout that can accommodate the
tiny characteristic sizes found in the CMOS ranges. The 9T
design offers significant advantages in terms of power usage
over the CONV8T and CONV10T cells [4].
When used with a low power supply and very reduced
feature sizes, the traditional six transistor (6T) SRAM cell
exhibits poor stability. The read stability is extremely low
because of voltage division between the access and driver
transistors during the read operation [5]. And therefore, a
9T SRAM cell is suggested in this article for excellent read
stability and low power consumption. The suggested cell
decreases dynamic power consumption by using a single bit.
The read static noise margin is enhanced by the total
isolation of the data storage nodes from the bit lines while
read operations. Hence, a 9T SRAM cell is suggested in this
work for excellent read stability and minimal power usage [6].
The suggested cell reduces the use of dynamic power by using
a single bit-line (BL) for write operations. The read static noise
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Proceedings of the 8th International Conference on Communication and Electronics Systems (ICCES 2023)
IEEE Xplore Part Number: CFP23AWO-ART; ISBN: 979-8-3503-9663-8
Fig. 1. Conventional 6T SRAM CELL.
margin is increased because the data is totally separated first
from bit line while read operation [7].
II. PROPOSED DESIGN
A. Maintaining the Integrity of the Specifications
The proposed 9T SRAM cell was created to overcome the
drawbacks of traditional 6T, traditional 7T, traditional 8T,
traditional 9T, and traditional 10T SRAM cells. Examples
include read/write delay, write power and high-power
consumption [8]. Nine transistors and six control lines make
up the planned 9T SRAM cell, also known as PROP9T. There
are Bit Line (BL), Write Word Line (WL), Read Word Line
(RWL), Zero Word Line (ZWL), Bit Line Bar (BLB), and
Read Bit Line Bar (RBLB), as shown in the diagram (Fig.2).
All control lines (RWL, RBLB) are active during a read
operation, but only the WWL, BL, and BLB control lines are
active during a write process. The ZWL will be always Zero.
Fig. 3. Proposed 9T SRAM cell.
are also referred to as storage nodes. Because they transport
data to storage nodes L and H, the transistors MN3 and MN4
are referred to as access transistors. With these two transistors,
the bit cell can only read or write data [9].
This paper compares our suggested design to five different
ideas. They include the conventional 6T SRAM (abbreviated
as CONV6T in Figure 1), as well as the CONV7T, CONV8T,
CONV9T, and CONV10T. The LTSPICE Simulator has been
used to simulate, validate, and compare the performance of
our suggested design (PROP9T).
III. C ONVENTIONAL 9T SRAM C ELL
Using this circuit, data stability is improved and leakage
power is minimized. The contents are totally separated from
the bit - line while such a read operation by the conventional
9T SRAM cell [10] and [11]. The fast cut off sleep mode
of the stationary 9T SRAM cells lowers the leakage power
consumption when equated to traditional 6T SRAM cells [12]
and [13].
Fig. 2. Schematic Proposed 9T SRAM Cell.
The occurrence of VDD is avoided by connecting the
transistors MP3 and MP4 to the ZWL control line, which is
never zero and keeps them constantly ON. The MP1 and MP2
are once more connected to the MP3 and MP4 in turn. The
letters L and H are used to identify these output nodes, which
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Fig. 4. CONV9T SRAM cell.
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Proceedings of the 8th International Conference on Communication and Electronics Systems (ICCES 2023)
IEEE Xplore Part Number: CFP23AWO-ART; ISBN: 979-8-3503-9663-8
IV. O PERATIONS
V. P ERFORMANCE E VALUATION
A. Read Operation
The read operation’s goal is to effectively gather the information from the inverter pair without inadvertently switching it
[14]. Assuming node Q is where logic ”1” is kept. Precharged
to a value that is as near to VDD as feasible is the bit line (BL).
By asserting the control signal RD and turning on transistor
logic M6, the read operation is initiated. The data recorded at
Q must be linked to the gate terminal of transistor M6 fora
proper read operation [15] and [16]. The read action is then
accomplished by discharging the RBL through transistors M5M7-M6.
The simulation results for the CONV6T, CONV7T,
CONV8T, CONV9T, CONV10T, and planned 9T SRAM
bit cells are shown in this section. Estimates of read/write
delay, hold power, and write power are provided, along with
a comparison of the results. Two CMOS inverters’ pull-up
transistors (MP1 and MP2) are 180nm in size.
The pull-down transistors for two CMOS inverters (MN1
and MN2) are 180 nm in size.
• The MN3, MN4, MN5, MN6, MN7 access path transistors are 180 nm in size.
•
A. Comparison of Read Delay
According to the read operation discussion. All control
lines (RBLB, RBL, and RWL) are raised HIGH during read
operation. Either BL or RWL begins to discharge from its
original values depending on the values stored [6].The sensing
amplifier detects this variation with regard to source voltage.
TABLE I
R EAD D ELAY C OMPARISON AT D IFFERENT S UPPLY VOLTAGES
Vdd
0.2
0.5
0.8
1.0
1.5
1.8
Fig. 5. Schematic 9T SRAM Cell.
B. Write Operation
Flipping the data recorded on the inverter pair is the purpose
of the write operation. The write circuitry forces the write bit
line WBL to logic ” 0 ” level, whereas WBLB stays at the
precharged level. The node voltage of QB continues to be less
than the threshold voltages of M1 transistor while the access
transistors are switched on by asserting the write control signal
WR. Yet the WBL side, in which the voltage is, is where all
the writing is done.
6T
(ns)
0.535
0.522
0.518
0.514
0.527
0.527
7T
(ns)
0.528
0.526
0.518
0.517
0.522
0.530
8T
(ns)
0.603
0.592
0.557
0.542
0.532
0.539
9T
(ns)
0.553
0.542
0.537
0.532
0.530
0.535
10T
(ns)
0.529
0.514
0.479
0.461
0.432
0.421
Proposed
9T
0.473
0.394
0.304
0.254
0.203
0.184
In Table 1, the read delay of the PROP9T, CONV8T, and
CONV6T are displayed for various supply voltages. To make
it simple for us to compare the tabulated findings, a graph
representing it is provided above in Fig 6. As you can see, the
PROP9T’s read delay is lower than the CONV8T’s and the
CONV6T’s at all supply voltages.
C. Hold Operation
The hold state turns off all control lines. (Also known
as the idle state). The access transistors MN3 and MN4
are consequently turned off. No more data can be read
from or put into the bit cell after this since the data flow
has ended.The term ”Hold or Standby Power” refers to the
amount of power used by the SRAM cell when it is not in
use. Majority of cells in any SRAM are inactive. Bit line
charging and discharging when the SRAM bit cell is in its
active state is the main cause of this power loss.The suggested
9T SRAM cell’s hold power analysis at different supply
voltages is displayed in Table 3 and contrasted with the
results of conventional 6T, conventional 7T, conventional 8T,
conventional 9T, and conventional 10T SRAM cell designs.
Fig. 6. Supply voltage (VDD) vs Read Delay.
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Proceedings of the 8th International Conference on Communication and Electronics Systems (ICCES 2023)
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B. Comparison of Write Delay
As said earlier regarding the write operation (Section 3.2).
WWL is set to HIGH during a write operation, and BL is
loaded with the value that will be written into the cell. Write
delay is the time interval between the start of WWL and the
moment at which the values of the storage nodes have entirely
flipped from their starting values.
TABLE II
W RITE D ELAY C OMPARISON AT D IFFERENT S UPPLY VOLTAGES
Vdd
0.2
0.5
0.8
1.0
1.5
1.8
6T
(ns)
0.532
0.383
0.365
0.318
0.151
0.126
7T
(ns)
0.489
0.410
0.314
0.285
0.164
0.126
8T
(ns)
0.495
0.378
0.332
0.302
0.206
0.194
9T
(ns)
0.465
0.398
0.269
0.222
0.121
0.104
10T
(ns)
0.495
0.514
0.320
0.293
0.161
0.127
Proposed
9T
0.473
0.394
0.304
0.254
0.173
0.134
of power consumption was progressively resolved, and as a
consequence, the power issue has been diminished. The graph
shows that CONV6T, 7T, 8T, 9T, and 10T, as well as the
planned 9T, are virtually identical.
C. Hold Power
The Hold Power of the different SRAM cells are listed down
in the table for various Supply Voltages (VDD) and graph has
been plotted. When a memory cell uses hold power, it means
that it uses energy to store data even when it is not being
accessed. In other words, it is the energy needed to keep a
memory cell in its current state throughout the hold period. It
has been demonstrated that the proposed 9T SRAM cell has
less hold power than the standard 6T and 9T SRAM cells.
In some electronic devices, this decrease in hold power may
lead to more energy-efficient operation and longer battery life.
Because power consumption is a major concern in low-power
applications, the suggested circuit design may be a potential
solution.
TABLE III
H OLD P OWER C OMPARISON AT D IFFERENT S UPPLY VOLTAGES
Vdd
0.2
0.5
0.8
1.0
1.5
1.8
6T
(ns)
0.299
5.32
18.12
34.82
113.2
192.6
7T
(ns)
0.087
1.25
14.64
18.46
24.25
38.39
8T
(ns)
0.21
4.67
10.95
18.28
36.05
52.45
9T
(ns)
0.31
6.74
18.90
26.29
48.07
76.47
10T
(ns)
0.41
9.74
18.91
36.30
118.0
200.4
Proposed
9T
0.38
5.70
15.42
30.54
96.37
108.5
The graph plotted between the hold power and supply
voltage is as follows:
Fig. 7. Supply voltage (VDD) vs Write Delay.
In Table 2, the write delay of PROP9T, CONV9T and
CONV6T at various supply voltages are shown in the Table-2.
The tabulated results are plotted as a graph which is shown in
above Fig 7 so that we can compare them easily. As you can
see that write delay of PROP9T is less than the CONV6T.
In comparison to the standard 6T and 9T SRAM cells, our suggested 9T SRAM cell showed a considerable decrease in write
delay. This encouraging outcome might have a big impact on
how well different electronic gadgets that use SRAM memory
work. Our results demonstrate the potential advantages of
investigating different SRAM cell circuit designs and suggest
additional development in this field. Below is the graphical
representation of Write Delay at different supply voltages.
The level of noise that the cell can endure is described in the
previous section. The quantity of noise present in a situation
without changing it is known as the static noise margin
(SNM). It was calculated the SNM. The read operation’s
read static noise margin measures the noise level (RSNM).
Through the use of MN8 and MN7 Transistors, the problem
Fig. 8. Hold Power Vs Supply Voltage.
From the graph we can say that the proposed 10T has less
hold power than the conventional.
D. Write Power
A Static Random Access Memory (SRAM) cell’s write
power is the amount of energy needed to input fresh data into
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Proceedings of the 8th International Conference on Communication and Electronics Systems (ICCES 2023)
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the memory cell. A group of transistors are used by SRAM, a
type of volatile memory, to store and retrieve data. In order to
reduce the total amount of power used by the memory system,
it is crucial to reduce the write power of an SRAM cell.
Longer battery life for mobile devices and less heat production
from high-performance computing systems are both benefits of
lower write power requirements. The write power of different
SRAM cells at different voltages are listed down in the below
table.
9 transistor SRAM configuration with low power dissipation
is suggested. The outcomes supported the fundamental idea
that power dissipation in an entire array may be factored
in by optimising the power consumption of individual cells.
Since this 6T and 9T SRAM designs employed a symmetrical approach, they were less susceptible to component
mismatches. The 9T SRAM also contained an additional three
transistors for read assistance, write assistance, and word line
enhancing techniques, which served to lessen the impact of
manufacturing variation.
TABLE IV
W RITE P OWER C OMPARISON AT D IFFERENT S UPPLY VOLTAGES
Vdd
0.2
0.5
0.8
1.0
1.5
1.8
6T
(ns)
0.095
1.29
5.75
12.15
33.29
51.2
7T
(ns)
0.10
1.47
6.36
11.26
30.69
48.2
8T
(ns)
0.11
1.54
5.94
14.26
41.91
67.82
9T
(ns)
0.16
2.41
9.31
17.2
53.59
88.0
10T
(ns)
0.26
3.46
11.1
27.94
65.0
109.3
Proposed
9T
0.18
2.96
10.42
24.74
59.37
97.34
The graphical representation of Write power of PROPO 10T
and CONV 10T are shown in below figure.
Fig. 9. Write Power Vs Supply Voltage.
From the graph we can see that the PROP 10T has less
write power than CONV 10T SRAM cell. As we discussed the
circuit having less write power can reduce the total amount of
power used by the memory system.
VI. C ONCLUSION
At 180nm CMOS technology nodes, this study proposes 6T
and 9T SRAM memory architectures. Both layouts received a
quality assessment. The suggested 9T SRAM cell has demonstrated superior performance when equated to traditional 6T
and traditional 9T SRAM cells in a number of areas, including
write delay, hold power, write power, and read power.
According to our research, the suggested circuit design may
be able to improve the overall effectiveness and performance
of electronic devices that use SRAM memory. Moreover, a
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