Unit 1: Switched-Capacitor Circuits AdvAIC P.1 S.J.Chang/EE/NCKU Outline Basic building blocks Speed and precision considerations of sampling switches Charge injection cancellation Switched-capacitor gain circuits Switched-capacitor integrator S3 S1 CH S2 X Seq Vin S’1 CH Y S’3 Vout S’2 P.2 Resistive Feedback Circuit (1/2) AdvAIC S.J.Chang/EE/NCKU An inverting amplifier R2 R2 R1 R1 Vin −𝐴𝑣 Vin Vout Vx –AvVx 𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛 𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛 𝑅1 + 𝑉𝑖𝑛 − 𝑅𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡 𝑅1 + 𝑅2 𝑅1 + 𝑅2 Rout Vout 𝑉𝑜𝑢𝑡 − 𝑉𝑖𝑛 𝐼= 𝑅1 + 𝑅2 𝑅𝑜𝑢𝑡 𝐴𝑣 − 𝑅 𝑉𝑜𝑢𝑡 𝑅2 2 =− ∙ 𝑉𝑖𝑛 𝑅1 1 + 𝐴 + 𝑅𝑜𝑢𝑡 + 𝑅2 𝑣 𝑅1 Typically, Rout is quite large in CMOS opamp to increase the open-loop gain AV. (AV –gmRout) P.3 Resistive Feedback Circuit (2/2) AdvAIC S.J.Chang/EE/NCKU 𝑅 𝐴𝑣 − 𝑅𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 𝑅2 2 =− ∙ 𝑉𝑖𝑛 𝑅1 1 + 𝐴 + 𝑅𝑜𝑢𝑡 + 𝑅2 𝑣 𝑅1 Problem A finite value of R2 could heavily drops the open-loop gain, degrading the precision of the circuit Input resistance, R1, continuously loads the proceeding stage while introduces thermal noise to the amplifier stage P.4 Capacitive Feedback Circuit (1/2) AdvAIC S.J.Chang/EE/NCKU Replace the resistors by capacitors to avoid reducing the C2 AV of the opamp 1 1 𝑍 = ; 𝑍2 = 1 𝑠𝐶1 𝑠𝐶2 C1 Vin X After settling down, impedance of C2 (i.e. Z2) 𝑅𝑜𝑢𝑡 𝐴𝑣 − 𝑍 0 𝑉𝑜𝑢𝑡 𝑍2 2 =− ∙ 𝑉𝑖𝑛 𝑍1 1 + 𝐴 + 𝑅𝑜𝑢𝑡 + 𝑍2 𝑣 𝑍1 RF C2 How to set the bias voltage at node X? Add a large feedback resistor RF to provide dc feedback Vout C1 Vin X Vout P.5 Capacitive Feedback Circuit (2/2) AdvAIC S.J.Chang/EE/NCKU (cont.) Add a large feedback resistor RF to provide dc feedback 𝑉𝑜𝑢𝑡 𝑠𝐶1 𝑅𝐹 It exhibits a high-pass transfer function =− 𝑉𝑖𝑛 1 + 𝑠𝐶2 𝑅𝐹 may not be suited to amplify wideband (especially, low-frequency) signals Increase RFC2 to suit low frequency applications too expensive To bias this circuit properly, a switch control configuration is proposed S2 RF C2 C2 C1 Vin X S1 Vout C1 Vin Vout S3 P.6 Switch Capacitor Operation AdvAIC S.J.Chang/EE/NCKU Vin Phase 2: Amplifying S1, S2 open C1 holds Qin0 C2 VA Vin 0 Vout C1 C2 Phase 1: Sampling S1, S2 close, S3 open C1 is charged to Qin0 = C1Vin0 at t = t0 C1 Vin A B Qin0 Vout Qin0 t t0 0 C1 Vout S3 close Qin0 is transferred S from C1 to C2 when t2> t0 Vin C S1 1 0 C2 C1 Qin0 S3 C2 C2Vout C1Vin Vout Vout C1 Vin C2Vout P.7 Switched-Capacitor Circuits AdvAIC S.J.Chang/EE/NCKU Advantage of the SC amplifier over a CT one SC amplifier: after Vout settles, the current through feedback capacitor approaches zero The feedback capacitance does not reduce the gain of the closed-loop amplifier CT amplifier: the feedback resistor continuously loads the amplifier More easier to be implemented in CMOS technology Good switches for sampling and hold High input impedance (ex: opamp’s input) to sense the stored quantities with no corruption A opamp incorporates bipolar transistors as its input will create an error in its output voltage (due to the base currents of bipolar transistors) Basic Building Blocks – Clock Generator AdvAIC P.8 S.J.Chang/EE/NCKU Non-overlapping clocks CK1 Non-overlapping clocks — both clocks are never ON at same time To ensure charge is not inadvertently lost C2 CK1 C1 Vout CK2 CK1 Von Voff CK T n–2 n–1 n n+1 t/T fs CK2 Von Voff 1 T CK1 delay delay CK2 n–(3/2) n–(1/2) n+(1/2) t/T P.9 Basic Building Blocks – Opamps AdvAIC S.J.Chang/EE/NCKU Functional analysis: ideal opamps are usually assumed Performance analysis: consider opamp’s practical nonidealities in SC circuits DC offset: can create dc offset at output Circuit techniques to combat this which also reduce 1/f noise DC gain: sets the accuracy of charge transfer, hence, transferfunction accuracy Unity-gain frequency, phase margin & slew-rate: sets the max clocking frequency. A general rule is that unity-gain frequency should be 5 times (or more) higher than the clock-frequency (assuming little slew-rate behavior occurs), and phase margin is greater than 70 degrees P.10 Phase Margin (1/2) AdvAIC S.J.Chang/EE/NCKU Phase margin (PM) is defined as PM = 180 + H( = 1) where 1 is the gain crossover freq., i.e. |H(=1)| = 1 Example: A two-pole feedback system is designed such that |H( = P2)| = 1 and |P1| << |P2|. What is the phase margin? 20 log H 0 0 –135 H p2 p1 (log scale) (log scale) H p 2 135 PM 45 P.11 Phase Margin (2/2) AdvAIC S.J.Chang/EE/NCKU Close-loop frequency and time response Small margin: H GX 1 0 PX Large margin: H GX 1 0 –180 H PM –180 H PM Y X Y X PX 1 y(t) y(t) t t How Much Phase Margin is Adequate? (1/3) AdvAIC P.12 S.J.Chang/EE/NCKU For PM = 45, at the gain crossover frequency H( = 1) = –135 and |H( = 1)| = 1, yielding 𝑌 𝐻 𝑠 𝑠𝑖𝑛𝑐𝑒 𝑠 = 𝑋 1 + 𝛽𝐻 𝑠 𝑌 𝑋 ⟹ 𝑗𝜔1 = = 1 ⟹ 𝐻 𝑗𝜔1 1 1 𝛽 0.29−0.71𝑗 GX 1 0 –135 H 𝑌 𝐻 𝑗𝜔1 𝐻 𝑗𝜔1 𝑗𝜔1 = = −𝑗135° 𝑋 0.29 − 0.71𝑗 1+1×𝑒 𝑠𝑖𝑛𝑐𝑒 𝛽𝐻 𝑗𝜔1 H ≈ 1 = 𝛽 1.3 𝛽 The freq. resp. of the feedback system suffers from a 30% peak at = 1 Y X 1 1 .3 1 Close-loop frequency response for 45 PM How Much Phase Margin is Adequate? (2/3) AdvAIC P.13 S.J.Chang/EE/NCKU Close-loop time response for 45, 60, and 90 PM: y(t) PM=45 y(t) t PM=60 y(t) PM=90 t t For PM = 60, Av(jt) = 1/, suggesting a negligible frequency peaking It means that the step response of the feedback system exhibits little ringing, providing a fast settling The concept of PM is only suited to “small signals” analysis That is, large-signal step response of feedback amplifiers does not follow the illustration of the above figure How Much Phase Margin is Adequate? (3/3) AdvAIC S.J.Chang/EE/NCKU Ex: unity-gain buffer P.14 VDD M3 M4 PM >> 65 and fu = M5 150 MHz, however, 1.6pF Vin Vout the large-signal step M1 M2 1pF response suffers from 0.5mA 0.3mA significant ringing Vin Vout t The large-signal step resp. of feedback amps. is nonlinear Resulting from large excursions in the bias voltages and currents Such excursions cause the pole and zero frequencies to vary during the transient, leading to a complicated time response For large-signal applications, time-domain simulations of the close-loop system prove more relevant and useful than small-signal ac computations of the open-loop amplifier P.15 Step Response of One- and Two-Stage Opamps AdvAIC S.J.Chang/EE/NCKU Effects of increased load capacitance on step response CC Larger CL t Vin Vout CL Larger CL t Vin Vout CL In one-stage opamps, a higher CL brings the dominant pole closer to the origin, improving the PM (albeit making the feedback system more overdamped) In two-stage opamps, since Miller compensation establishes the p1 at the output of the first stage, a higher CL presented to the second stage moves the p2 toward the origin, degrading the PM The step response approaches an oscillatory behavior if the CL seen by the two-stage opamp is increased Bode Plot of a Well-Compensated Opamp AdvAIC P.16 S.J.Chang/EE/NCKU PM is typically designed > 45 p2 > unit-gain Assumption: p1 << p2 & unit-gain Ex: PM = 60 𝑃𝑀 = 180° − tan−1 𝜔𝑢𝑛𝑖𝑡−𝑔𝑎𝑖𝑛 𝜔𝑢𝑛𝑖𝑡−𝑔𝑎𝑖𝑛 −1 − tan = 60° 𝜔𝑝1 𝜔𝑝2 90 30 𝜔𝑝2 ≅ 1.732𝜔𝑢𝑛𝑖𝑡−𝑔𝑎𝑖𝑛 20log|Av| 0 p2 p1 unit-gain log Single-pole behavior within the unit-gain frequency Step Response of a Single-Pole Circuit AdvAIC S.J.Chang/EE/NCKU A step-function signal of height S R Vin(t) Vin(t) C Vout(t) S t P.17 Step response of a LP STC circuit 𝑉𝑜𝑢𝑡 𝑡 = 𝑆 1 − 𝑒 −𝑡Τ𝜏 Vout(t) Tangent S t t 0.69 2.3 4.6 6.9 Vout(t) 0.5 S 0.9 S 0.99 S 0.999 S Pulse Response of a Single-Pole Circuit AdvAIC P.18 S.J.Chang/EE/NCKU tr : rise time tr Vin(t) T 0.9P tf : fall time tf P << T S t 0.1P 0 t T To P comparable to T P >> T 0 1 e t1 0.1 1 e t2 0.9 T t 0 T 0 1 0.35 tr t f 2.2 f 0 tr t f 2 2 f0 t P.19 Output Behavior of a Switch-Capacitor Circuit AdvAIC S.J.Chang/EE/NCKU It is a pulse response of the SC circuit Vin CK1 0 Vin CK1 CK2 C1 C2 Vout t0 t Analysis Start from the step response of a single-pole circuit Settling error < 10% tsettle > 2.3 Only half clock period for settling clock period > 2tsettle 5 Opamp’s unit-gain should be 5 times higher than the clk To achieve a smaller settling error and take the SR & PM into consideration, unit-gain should be higher than 5clk (say, 20x) Revisit: Basic Building Blocks – Opamps AdvAIC P.20 S.J.Chang/EE/NCKU Ideal opamps are usually assumed Consider opamp’s practical non-idealities in SC circuits DC offset: can create dc offset at output. Circuit techniques to combat this which also reduce 1/f noise. DC gain: sets the accuracy of charge transfer, hence, transferfunction accuracy. Unity-gain frequency, phase margin & slew-rate: sets the max clocking frequency A general rule is that unity-gain frequency should be 5 times (or more) higher than the clock-frequency (assuming little slew-rate behavior occurs), and phase margin is greater than 70 degrees P.21 Basic Building Blocks – Capacitors (1/2) AdvAIC S.J.Chang/EE/NCKU Double-poly (aka PIP) capacitors metal C1 poly1 metal High Linearity but expensive topology thin oxide Cp1 thick oxide C1 Cp2 poly2 (bottom plate) Cp1 Cp2 (substrate – ac ground) cross-section view equivalent circuit A substantial parasitic capacitance, Cp2 (bottom plate capacitance), which may be as large as 20% of C1 A top plate capacitance, Cp1, is typically much smaller than Cp2 (on the order of 1% - 5% of C1) Basic Building Blocks – Capacitors (2/2) AdvAIC S.J.Chang/EE/NCKU Polysilicon-diffusion (heavily doped silicon) capacitors B poly SiO2 A CAB n+ Cp Cp p-substrate P.22 Metal-polysilicon (or metal-metal) capacitors Bottom plate parasitic is on the order of 10 to 20%. C = C1+C2+C3+C4 Metal 4 Metal 3 Metal 2 Metal 1 Poly C1 C2 C3 C4 Cp Substrate P.23 More on Capacitors (1/2) AdvAIC S.J.Chang/EE/NCKU Sandwich capacitor Top view and cross section of sandwich capacitor M4 M5 VIA VIA Minimize the parasitic coupling Composed of odd metal layers [Cao, ISSCC’2008] M4 M3 Top view and cross section of multi-layer sandwich capacitor M5 VIA VIA M4 VIA M3 M1 VIA VIA M2 M3 P.24 More on Capacitors (2/2) AdvAIC S.J.Chang/EE/NCKU Finger-sandwich capacitor ~3x capacitance than 3-layer sandwich capacitor under same area Horizontal Surface Area (AH) Horizontal Distance (d2) Bottom Metal Top Metal 3D Capacitor Horizontal Distance (d2) Top Metal Vertical Distance (d1) Vertical Distance (d1) Via (3~5) Capacitance produced by four metals of different layers Bottom Metal IMD(e) Via (1~5) Connective Metal Shielding Metal Shielding Metal IMD(e) Ceff ≈ (eAH)/d2 Connective Metal P.25 Basic Building Blocks – Switches AdvAIC S.J.Chang/EE/NCKU CK CK Symbol n-channel V1 V1 V1 V2 transmission gate V2 CK CK CK p-channel V2 V2 V1 CK MOSFET switches are good for SC circuits. Roff near G range Ron in 100 to several k range (depends on transistor sizing) Non-ideal effects: non-linear parasitic capacitances, charge-injection, clock feedthrough, … P.26 NMOS Switch (1/3) AdvAIC S.J.Chang/EE/NCKU When the switch is turned on, it behaves as a non-linear resistor The charging or discharging current is nonlinear In the discharging period, how does Vout vary with time? (assume = 0) Before Vout drops below VDD – Vtn, M1 is saturated I D1t 1 W 2 t Vout t VDD VDD nCox VDD Vtn CH 2 L CH CK M1 Vin = 0 ID1 VDD CK Vout CH VDD 0 Vout VDD t0 t1 2VtnCH , M1 enters the triode region, yielding a W nCox VDD Vtn 2 L dV time dependent current I D1 CH out dt After t1 t NMOS Switch (2/3) AdvAIC P.27 S.J.Chang/EE/NCKU 2 dVout Vout W CH nCox VDD Vtn Vout dt L 2 dVout 1 C W n ox dt 2VDD Vtn Vout Vout 2 CH L 1 dVout Cox W 1 dt n CH L Vout 2VDD Vtn Vout VDD Vtn C W ln Vout ln2VDD Vtn Vout VDD Vtn n ox t t1 CH L Vout Cox W t t1 ln VDD Vtn n 2VDD Vtn Vout CH L C W 2VDD Vtn exp VDD Vtn n ox t t1 CH L Vout C W 1 exp VDD Vtn n ox t t1 CH L P.28 NMOS Switch (3/3) AdvAIC S.J.Chang/EE/NCKU In the charging period, how does Vout vary with time? (suppose Vin = VDD) Gate and drain of M1 are at the same potential saturation dVout 1 W 2 I D1 nCox VDD Vout Vtn dt 2 L dVout 1 Cox W n dt 2 VDD Vout Vtn 2 CH L CK CH Vout Vin = VDD ID1 t 1 1 C W n ox VDD Vout Vtn 0 2 CH L 0 1 1 Cox W 1 n t 2 C H L VDD Vtn 0 Vout CH VDD where CLM and body effect is neglected CK 0 and assume Vout (t = 0) is zero. Thus, Vout VDD Vtn M1 VDD–Vtn Vout t0 t If the input signal level is close to VDD, then Vout cannot track Vin Speed Limitation for NMOS/PMOS Switches AdvAIC P.29 S.J.Chang/EE/NCKU On resistance of an NMOS switch increases drastically as Vin VDD – Vtn On resistance of a PMOS switch increases drastically as Vin |Vtp| Settling can be very slow when Vin is high Settling can be very slow when Vin is low Ron,N Ron,P 0 VDD–Vtn Vin 0 |Vtp| Vin P.30 The CMOS Switch AdvAIC S.J.Chang/EE/NCKU Full transmission, NMOS for passing low voltage, PMOS on for passing high voltage R R on,P CK on,N M1 Vin Vout M2 CK CH Ron,eq Ron,eq Ron, N || Ron, P |Vtp| VDD–Vtn 1 || W W nCox VDD Vin Vtn p Cox Vin Vtp L N L P 1 W W W W nCox VDD Vtn nCox p Cox Vin p Cox Vtp L N L N L P L P 1 Ron,eq independent of Vin if nCox W LN pCox W LP Vin P.31 Clock Delay AdvAIC S.J.Chang/EE/NCKU CK NMOS and PMOS switches need to turn off simultaneously to avoid ambiguity in the sampled value t CK Propagation delay t between CK and CK leads to distortion in the sample value Duplicating delay circuit can be employed to minimized t Vin Ideal Value Vout t VDD G2 CK CKin CK I1 P.32 Channel Charge Injection AdvAIC S.J.Chang/EE/NCKU When the switch turns off, Qch exits through the source and drain terminals CK Vin V M1 Vout CH negative shift for NMOS switch Total charge in the inversion layer: Qch WLC ox VDD Vin Vtn If half of Qch is injected onto CH, the results error: V WLCox VDD Vin Vtn 2CH CH , WL V Vin V Charge splitting between source/drain is not certain, worst case estimate could assume all the channel charge is injected onto the sampling capacitor P.33 I/O Characteristics of SC with Charge Injection AdvAIC S.J.Chang/EE/NCKU How does charge injection affect the precision? Assume all the channel charge is injected, no body effect, WLCox VDD Vin Vtn WLCox WLCox VDD Vtn Vin Vout Vin 1 CH CH CH non-unity gain Constant offset Gain error and dc offset exist. Vout Consider body effect: Vout Vin WLCox VDD Vin Vtn0 2B Vin 2B CH With Charge Injection Ideal Vin WLCox WLCox VDD Vtn0 2B WLCox 2B Vin Vin 1 CH CH CH Gain error dc offset Non-linearity Three types of errors exist P.34 Speed-Precision Tradeoff AdvAIC S.J.Chang/EE/NCKU Representing the speed by a simple time constant and the precision by the error V due to charge injection RonC H V 1 nCox W VDD Vin Vtn L CH WLCox VDD Vin Vtn CH Define a figure of merit as F = (V)-1 F 1 2n V L To the first order, the trade-off is independent of W and CH For a give L and n, speed V precision P.35 Clock Feedthrough AdvAIC S.J.Chang/EE/NCKU A MOS switch couples the clock transition to the sampling capacitor through overlap capacitance, Cov This effect introduces error in sampled Vout V VCK WCov C H WCov Cov is the overlap capacitance per unit width V is independent of Vin constant offset in the inputoutput transfer characteristic VCK CK 0 Cov Vin M1 Vout CH P.36 kT/C Noise AdvAIC S.J.Chang/EE/NCKU On-resistance of the switch introduces thermal noise at the output end When the switch is off, the noise is stored on the capacitor with the instantaneous value of the input voltage Vin Ron Vout CH Vin Vin+Vn CH The rms noise voltage of the sampled noise ~ (kT/C)1/2 kT/C noise limits the performance in many high-precision applications To reduce noise, C speed P.37 Charge Injection Cancellation (1/2) AdvAIC S.J.Chang/EE/NCKU Uses dummy transistor CK CK CK CK When M1 turns off and M2 W1Cov 2W2Cov turns on, channel charge of CH M2 Vout M1 is then absorbed by M2 Vin M1 CH Choose W2 = 0.5W1, and W1Cov L2 = L1, then q2 = q1 V VCK W1Cov C H 2W2Cov In reality, equal splitting of charge 2W2Cov is not generally valid, cause VCK W1Cov C H 2W2Cov certain error CK Uses CMOS transmission gate CMOS switch injected opposite charge packet, holes and electrons cancel each other Electrons q1 M1 Vin Vout M2 Holes q2 CK CH P.38 Charge Injection Cancellation (2/2) AdvAIC S.J.Chang/EE/NCKU Uses CMOS transmission gate (cont.) q1 WLCox VCK Vin Vtn q2 WLCox Vin Vtp Assume Vtn = |Vtp|, q1 = q2 only when Vin = VCK/2 Clock feedthrough can also be suppressed, but not precisely, since Cov for NMOS and PMOS are not the same Differential sampling q1 WLC ox VCK Vin1 Vtn1 q2 WLC ox VCK Vin 2 Vtn 2 q1 = q2 only when Vin1 = Vin2 The error cannot be fully cancelled CK q1 q2 WLCox Vin1 Vin 2 2F Vin 2 2F Vin1 Vin1 M1 Differential operation can both removes the constant offset and lowers the nonlinear component M2 Vin2 q1 q2 CH Vout1 Vout2 CH P.39 Unity Gain Sampler/Buffer AdvAIC S.J.Chang/EE/NCKU Topology 1: Input-dependent charge injected by S1 onto CH limits the accuracy S1 Vin Vout Offset, gain and linearity errors Vin Vout CH S3 S2 Topology 2: Sampling: Vin(t = t0) is stored on CH Amplification: Vout = V0 since node X remain at virtual ground Vin Vin Charge injection? S1 CH X Vout V0 V0 CH X Vout X CH Vout P.40 Operation of Unity Gain Buffer AdvAIC S.J.Chang/EE/NCKU Clocking timing control S3 Clock control generator for creating clock edge delay for S1 turn off after CK S2, and S3 turns on after S1 is off S1 Charge injection behavior Vin S2 CH X Vout If S2 turns off slightly before S1 does, since X is at virtual ground q2 is S2 independent of the input level q2 S1 q2 only causes DC offset without Vin nonlinearity which can be easily Vout CH X cancelled After S2 turns off, node X is floating q2 WLC ox VCK VX Vtn no charge can flow to CH Constant error voltage = q2 C H P.41 How About the Charge Injected by S1? AdvAIC S.J.Chang/EE/NCKU Assume a total capacitance equal to CX form X to ground Including the input capacitance of the opamp Charge injection behavior of S1 Each of CH and CX carries a charge equal to q1. The total charge at node X cannot change after S2 turns off. Vin S1 P CH X q1 Vout CX CH The same holds true after S3 turn on. After S3 C X VX Vout VX CH 0, and VX Vout Av1 turns on, V C X C H out Vout C H 0 Vout 0 Vout X CX Av1 The charge injection by S1 introduces no error if S2 turns off first. P.42 Differential Realization of Unity-gain Sampler AdvAIC S.J.Chang/EE/NCKU S3 S1 CH S2 X Seq Vin S’1 CH Y Vout S’2 S’3 Input-independent nature of the charge injected by the S2 allows fully cancellation by differential operation Finite charge injection still exists due to mismatches between S2 and S2’, which can be resolved by adding Seq equalizing the charge of node X and Y Seq turns off slightly after S2 and S2’ (and before S1 and S1’) P.43 Precision Considerations (1/2) AdvAIC S.J.Chang/EE/NCKU Assume opamp with finite input capacitance Cin and finite gain Av1 and Vos,in = 0. How close to unity is the gain? Owing to the finite gain of the opamp, VX 0 in the amplification mode, giving a charge equal to CinVX on Cin. Sample mode: total charge at node X = CHV0 (assume Vos,in = 0) Amplification mode: the conservation of change at node X requires that CinVX comes from CH, reducing the charge on CH to CHV0 + CinVX where VX = –Vout / Av1 Vout V0 1 Cin 1 1 Av1 C H 1 Cin V0 1 1 A C v1 H V0 Vin X CH Cin X Vout Av1 Cin CH Av1 Vout P.44 Precision Considerations (2/2) AdvAIC S.J.Chang/EE/NCKU Vout V0 1 Cin V0 1 1 1 Cin Av1 CH 1 1 Av1 CH As expected, if V0 V Cin / CH << 1 out 1 1 1 Cin 1 This circuit suffers gain error: Av1 CH Av1 It suggests that Cin must be minimized even if speed is not critical W/L Av and Cin , optimum device size is by minimizing gain error rather than increasing Av [Example] Giving Cin = 0.5pF and CH = 2pF. What is the minimum opamp gain that guarantee a gain error of 0.1%? Since Cin / CH = 0.25, we have Av1,min = 1000 1.25 = 1250 Speed Consideration during Sampling AdvAIC P.45 S.J.Chang/EE/NCKU What is the time constant CK when the sampler in S sampling phase? Vin 1 Equivalent resistance of X: Since I X GmVX Ro I X Ron 2 VX CK S2 CH X X Vout sample mode Ron2 IX VX GmVX Equivalent ckt. Ro: the open-loop output impedance of the opamp Hence, the resistance between node X and ground, RX, is given by R Ron 2 1 typically, Ro Ron 2 and Gm Ro 1 RX o 1 Gm Ro Gm The total resistance is series with CH is thus equal to Ron1 + RX The time constant in sampling mode is 1 CH sam Ron1 Gm sam must to sufficiently small to allow settling to the required precision within a short sampling period Ro P.46 Speed Consideration during Amplification (1/2) AdvAIC S.J.Chang/EE/NCKU At the beginning of the amplification mode, since the voltage across CL and CH do not change instantaneously if Vout = 0 and VCH = V0, then VX = –V0. Step response (assume SR ) X Cin Representing the charge on CH by a series voltage source, VS, that goes from 0 to V0 at t = t0 while CH carries no charge itself 1 1 Vout sCL GmVX VS VX Vout sCH and Vout VX VS sCinVX sCH Ro CH 0 Ic_in = IC_H VS CH VX Vout –V0 X V0 Vout Vout VX Cin GmVX Ro CL t CL t0 Time response in amplification mode Equivalent circuit P.47 Speed Consideration during Amplification (2/2) AdvAIC Vout s Ro Gm sCin CH VS s Ro CLCin CinCH CH CL s Gm RoCH CH Cin S.J.Chang/EE/NCKU For s = 0, Vout s VS s 1 , similar to the result in sampling 1 Cin 1 1 Gm Ro CH Gm sCin CH Vout s Typically GmRoCH >> CH, Cin VS s CLCin CinCH CH CL s GmCH Thus, the response can be approximately characterized by a time C C CinCH CH CL constant equal to L in amp amp is independent of the opamp Ro in close-loop operation GmCH A higher Ro leads to a larger gain, eventually yielding a constant speed If Cin << CL, CH then amp CL / Gm = CLRout(close-loop) P.48 Slewing during Amplification AdvAIC S.J.Chang/EE/NCKU When entering the amplification mode, the circuit may experience a large step at the inverting input M7 Using a telescopic opamp as an example Since M2 is off during slewing Vb Cin is negligible node X is floating, CH can be ignored SR ISS / CL VDD M8 M5 M6 ISS M3 M4 M1 Vb1 M2 V0 OFF ISS ISS Vout CL CH X P.49 Bottom Plate Sampling AdvAIC S.J.Chang/EE/NCKU S3 Vin S2 S1 n+ X Vout Cp Input capacitance of the opamp degrades both the speed and precision of the unity gain sampler Bottom plate sampling is usually employed to minimize addition parasitic capacitance seen from node X Top plate of CH is connected to node X Bottom plate is driven by input or opamp Driving the bottom plate by input or output also avoids the injection of substrate noise to node X P.50 Noninverting Amplifier AdvAIC S.J.Chang/EE/NCKU Sampling mode: S1 and S2 are on, and S3 is off Noninverting amplifier Charge stored in C1: Vin0C1 Vin Amplification mode: S1 and S2 are off, and S3 is on VP goes from Vin0 to 0, charge in C1 is transfer to C2 Vout = Vin0(C1/C2) Close loop gain = C1/C2 Capacitance ratio can be precisely determined by geometry ratio S2 C2 C1 S1 S3 Sampling mode V Vout X Vout C1 in Amplification mode C1 V in0 P X X P C2 Vout C1 Vin 0 C2 t Proper Timing for Noninverting Amplifier (1/3) AdvAIC P.51 S.J.Chang/EE/NCKU At the end of sampling, S2 turn off first, injecting a constant charge, q2, onto node X After S2 is off, the total charge at node X remains constant making the circuit insensitive to charge injection of S1 or charge absorption of S3 This input independent offset can be cancelled by differential operation q2 S2 C2 Vin S1 Vin0 PC X 1 Vout Proper Timing for Noninverting Amplifier (2/3) AdvAIC P.52 S.J.Chang/EE/NCKU Subsequently, S1 turn off and S3 turn on VP goes from a fixed voltage, V0, to another, 0, with an intermediate perturbation due to S1 The charge injected by S1, q1, change VP by q1/C1, and hence the output voltage by –q1/C2 Since the output voltage of interest is measured after S3 turn on (VP drops to zero), q1 does not affect the final output Vin0 VP C2 S1 Vin q1 P C1 S3 X S1 turns off VP S3 turns on t Vout Vout C1 C2 Vin0 t Proper Timing for Noninverting Amplifier (3/3) AdvAIC P.53 S.J.Chang/EE/NCKU Two observations The sampling instant is defined by the turn-off of S2 From the time of S2 turns off until the time S1 turns off, the input voltage may change significantly without introducing any error to final output S2 C2 Vin S1 t P C1 X S3 Vout Since the final value of VP is zero, it is not important that it requires some channel charge when S3 turns on P.54 Precision of Noninverting Amplifier AdvAIC S.J.Chang/EE/NCKU sC2 Vout V X sCinV X sC1 V X Vin Vout Av1V X Vout C1 Vin C C2 C1 Cin 2 Av1 C2 Vin C1 X Vout Equivalent circuit Cin during amplification Av1 Vout C1 1 C1 C2 C1 Cin 1 1 For large Av1, Vin C2 1 C2 C1 Cin 1 C2 C2 Av1 C2 Av1 It implies a gain error of C2 C1 Cin C2 Av1 Compare with sampler case C H Cin C H Av1 When nominal gain C1/C2 , gain error For C1 = C2, gain error of this circuit is 2X that of the unity gain sampler Feedback factor of noninverting amplifier = C2 / (C2 + C1 + Cin) 1/2 Feedback factor of unit-gain sampler = CH / (CH + Cin) 1 P.55 Speed of Noninverting Amplifier (1/2) AdvAIC S.J.Chang/EE/NCKU C1 Vin C2 X Cin VX GmVX Ro Vout Thevenin equivalent CL Vin Equivalent circuit in amplification mode VX Vin Vout Ceq Ceq C2 Vout C2 Ceq Vout X VX GmVX Ro C1 ; Ceq C1 Cin where C1 Cin C2 in series with Ceq Ceq C C 1 Gm Vin Vout Vout Vout sCL Vin Vout eq 2 s Ceq C2 Ceq C2 Ro C1 Gm sC2 Ro Ceq V s C1 Cin out Vin s C2Gm Ro Ceq C2 Ro C L Ceq C2 Ceq C2 s CL The negative gain simply means, during amplification mode, if Vin stepped down, then Vout goes up. (not “inverting” amplifier) P.56 Speed of Noninverting Amplifier (2/2) AdvAIC S.J.Chang/EE/NCKU C1 Gm sC2 Ro Vout s C1 Cin Vin s C2Gm Ro sRo C LCeq C LC2 Ceq C2 Ceq For large GmRo, Time constant during amplification amp C LCeq C LC2 Ceq C2 C 2 Gm Compare with sampler case amp CLCin CinCH CH CL GmCH amp nominal gain, C1 / C2. Close-loop gain (feedback factor ) amp (speed ) C1 Cin , independent of C2 Gm Gm Since a larger C2 introduces heavier loading (bad) at the output, it also provides a greater feedback factor (good) If CL = 0, amp Ceq Cin still have significant impact on both its precision and speed P.57 Multiply-by-Two Circuit AdvAIC S.J.Chang/EE/NCKU A high close-loop gain SC amplifier suffers from speed and precision degradation due to low feedback factor One of the compromise results: multiply-by-two circuit S4 In the transition to amplification mode S3 turn off first S1 Charge injected by S3 introduces aVin constant offset Charge injected by S1 and S2, and absorbed by S4 and S5 is unimportant S5 Vout C2 Multiply-by-two circuit C1 X C2 S3 S2 C1 Sampling Vin mode C1 Vout Amplification mode X C2 Vout Error in Conventional SC Circuit AdvAIC P.58 S.J.Chang/EE/NCKU Using multiply-by-two circuit as an example C1 Sampling Vin C2 CL C1 Amplification GND Vref C2 CL Output voltage: t C2 1 Vout 1 Vin 1 e C1 A Static error 1 A High opamp DC gain for low static error P.59 Correlated Double Sampling (CDS) AdvAIC S.J.Chang/EE/NCKU CF Vin CS CF_P Vin CDS CL Sample Vref GND GND Vref Vo` CDS CS_P Estimate Vref Static error C2 CLS 1 A2 CL CDS V` Disadvantages C o 2 L ThreeCLSclockCphase Double loading CF_P CF C1 Vo`` Level Shift CL CS_P CL CS CF_P C1 Eliminate op-amp offset error Alleviate 1/f noise C1 CS_P CF CS Advantages CLS Vref C2 Vo`` CL K. Nagaraj, T. R. Viswanathan, K. Singhal and J. Vlach, “Switched-Capacitor. Circuits with reduced Sensitivity to Amplifier Gain”, IEEE Trans. Circuit Syst., vol. 34, pp. 571-574, May 1987. P.60 Correlated Level Shifting (CLS) AdvAIC Advantages Static error S.J.Chang/EE/NCKU CF 1 A 2Vin C1 CS CF_P Vin CDS CL Sample C2 CS_P No double loading problem CF Rail-to-rail output is possible CLS CL Disadvantage CS CDS C1 Vo` Three clock phase Vref CS_P CF_P Floating output node at last phase CF Vref Possible application: Any circuit with a CS relatively constant capacitive CDS load. Ex: CF_P pipelined ADC, SC-filter, … Vo` GND Vref Estimate CL C2 CLS CL C1 Vo`` Level Shift CL Vref GND CLS C2 CS_P [Ref] B. R. Gregoire, and U. Moon, “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain,” IEEE J. Solid-State Circuits, 2008, pp.2620–2630. Vo`` CL Opamp Considerations without CLS AdvAIC P.61 S.J.Chang/EE/NCKU A 2-stage op-amp 0.18 m process ~18 dB/stage A = ~30dB ACL = 1.95V/V Performance = ~5b Swing = 0.6V 1.95 V/V 150mV Headroom 600mV swing Opamp Considerations with CLS AdvAIC P.62 S.J.Chang/EE/NCKU A 2-stage op-amp 0.18 m process ~18 dB/stage + 36dB A = ~30dB ~65dB ACL = 1.95 2 V/V Performance = ~5b ~10b Swing = 0.6v 0.9V boosting 900mV swing 2 V/V P.63 SC Common-Mode Feedback (CMFB) (1/3) AdvAIC S.J.Chang/EE/NCKU For CMFB, sensing the output CM level (1) by resistors: lowers the differential gain (2) by MOSFETs that operate as source followers: suffer from a limited linear range SC circuits provide an alternative that avoids both of the abovementioned difficulties Outputs are sensed by capacitors rather VDD than resistors If Vout1 and Vout2 experience a positive CM Vout1 change VX ID5 pulling Vout1 and Vout2 down Vin Vout,CM = VGS5 + voltage across C1 and C2 How is the voltage across C1 and C2 defined? M3 M4 C1 V C2 X M1 M5 M2 Vb Vout2 SC Common-Mode Feedback (CMFB) (2/3) AdvAIC S.J.Chang/EE/NCKU How is the voltage across C1 and C2 defined? VDD M3 M4 C1 V C2 X P.64 During CM level definition, amplifier is in sampling (or reset) mode, differential input is zero and S1 is on Vout,CM = VGS6,7 + VGS5 Vin M1 M5 Vb M6 M7 M2 S1 ID At the end of the sampling mode, S1 turns off, leaving a voltage equal to VGS6,7 across C1 and C2 To reduce output loading, M6 and M7 must be small, causing the output CM level hard to be defined accurately SC Common-Mode Feedback (CMFB) (3/3) AdvAIC P.65 S.J.Chang/EE/NCKU For Vout,CM must be defined accurately In the reset mode S1, S4 and S5 on C1,2 sustains a voltage equal to VCM – VGS6 VDD M3 S2 VCM M4 C1 V C2 X Vb S3 S4 S5 M1 M2 VCM Vin M5 IREF S1 M6 In amplification mode S2 and S3 on Vout,CM = VCM – VGS6 + VGS5 Proper definition of ID3 and ID4 w.r.t. IREF can guarantee that VGS5 = VGS6 and hence the Vout,CM = VCM Switched-Capacitor Resistor Equivalent AdvAIC P.66 S.J.Chang/EE/NCKU 1 2 V1 Req V2 V1 V2 C1 C1 charged to V1 and then V2 during each clock period Find equivalent average current I avg 1 1T Q1 C1 V1 V2 C V V2 For equivalent resistor circuit I eq Equating two, we have Req where T is the clock period V1 V2 Req T 1 C1 C1 f s This equivalence is useful when looking at low-frequency portion of a SC-circuit. For higher frequencies, discrete-time analysis is used. P.67 Resistor Equivalence Example AdvAIC S.J.Chang/EE/NCKU What is the equivalent resistance of a 5pF capacitance sampled at a clock frequency of 100kHz? [Solution] Using Req T 1 , we have Req C1 Note that a very large equivalent resistance of 2M can be realized. C1 f s 1 2M 12 3 5 10 100 10 In a typical CMOS process, such a large resistor would normally require a huge amount of silicon area if it is realized as a resistor without any special processing fabrication steps. Requires only 2 transistors, a clock and a relatively small capacitance. P.68 Parasitic-Sensitive Integrator (1/2) AdvAIC S.J.Chang/EE/NCKU Start by looking at an integrator 1 C2 R1 Vin Vc2[nT] Vout 2 Vci(t) Vc1(t) Vout 1 Vin dt R1 C2 1 C2 Vcx(t) Vco(t) C1 Vi[n] = Vci(nT) Vo[n] = Vco(nT) Want to find output voltage at end of 1 in relation to input sampled at end of 1. C2 Vci(nT–T) C1 1 on C2 Vci(nT–T/2) Vco(nT–T) C1 2 on Vco(nT–T/2) P.69 Parasitic-Sensitive Integrator (2/2) AdvAIC S.J.Chang/EE/NCKU At end of 2 C2Vco nT T 2 C2Vco nT T C1Vci nT T But we would like to know the output at end of 1 It leads to C2Vco nT C2Vco nT T C1Vci nT T Modify above to write Vo [n] Vo [n 1] C1 Vi [n 1] C2Vco nT C2Vco nT T 2 C 2 Taking z-transform and re-arranging, we have Vo z C1 z 1 C1 1 H z Vi z C2 1 z 1 C2 z 1 Gain is determined by a ratio of two capacitance values. Ratios of capacitors can be set very accurately on an integrated circuit (within 0.1 percent), leading to very accurate transferfunctions. P.70 Low Frequency Behavior (1/2) AdvAIC S.J.Chang/EE/NCKU We can rewrite the transfer function, H(z), as C1 z 1 C1 z 1 / 2 H z C2 1 z 1 C2 z1 / 2 z 1 / 2 To find freq response, recall that z e jT cosT j sinT , therefore z1/ 2 cos T j sin T 2 2 T T z 1 / 2 cos j sin 2 2 Hence, the transfer function is given by H e Above is exact but when T << 1 (i.e., at low freq.) C1 z 1 2 jT H e C 2 jT x3 x5 Note : sin x x 3! 5! CC1 2 z 1 2 T j 2 sin 2 jT P.71 Low Frequency Behavior (2/2) AdvAIC S.J.Chang/EE/NCKU The z-1/2 in the numerator represents a simple delay and can be ignored Thus, the transfer function is same as a continuous-time integrator having a gain constant of KI C1 1 C2 T which is a function of the integrator capacitor ratio and clock frequency only. For frequencies much less than the sampling frequency, Vo z C1 z 1 C1 1 equation H z Vi z C2 1 z 1 C2 z 1 approximates the transfer function of an ideal continuous-time integrator Parasitic Capacitance Effects (1/2) AdvAIC P.72 S.J.Chang/EE/NCKU Cp3 Cp4 C2 1 2 Vi(n) 1 Vo(n) Cp1 C1 Cp2 Cp1: parasitic capacitance of the top plate of C1 (include capacitance associate with switches) Cp2: parasitic capacitance of the bottom plate of C1 Cp3: parasitic capacitance of the top plate of C2 (include input capacitance of opamp and that of 2 switches) Cp4: parasitic capacitance of the bottom plate of C2 (include any extra capacitance that the opamp must drive) Discard Cp2 and Cp3 since it always connect to ground or virtual ground. Cp4 will affect the speed but not affect the final value of the opamp output. P.73 Parasitic Capacitance Effects (2/2) AdvAIC S.J.Chang/EE/NCKU Accounting for parasitic capacitances, we have C1 C p1 1 H z C2 z 1 C2 2 Vin0 C1 Cp1 Cp1 is a nonlinear capacitor due to the source/drain junctions of switches 1 and 2 The charge stored on Cp1 is not equal to Vin0Cp1, but rather V equal to QCp1 0 C p1dV in 0 QCp1 exhibits a nonlinear dependence on Vin0. Creating a nonlinear component at Vout after the charge is transferred to C2. Vout Thus, gain coefficient is not well controlled and partially non-linear (due to Cp1 being non-linear). P.74 Parasitic-Insensitive Integrators (1/3) AdvAIC S.J.Chang/EE/NCKU 1 C1 2 C2 1 Vci(n) 2 Vco(n) 1 By using 2 extra switches, integrator can be made insensitive to parasitic capacitances More accurate transfer-functions Better linearity (since non-linear capacitances unimportant) C2 C2 Vci(nT–T) Vci(nT–T/2) C1 1 on Vco(nT–T) C1 2 on Vco(nT–T/2) P.75 Parasitic-Insensitive Integrators (2/3) AdvAIC S.J.Chang/EE/NCKU Same analysis as before except that C1 is switched in polarity before discharging into C2 C1 1 Vo z C1 z 1 H z 1 Vi z C2 1 z C2 z 1 A positive integrator (rather than negative as before) Behavior of this non-inverting integrator w.r.t. parasitic capacitances: C C p3 1 2 C1 Vi(n) 2 Cp1 Cp2 1 p4 C2 1 Vo(n) Parasitic-Insensitive Integrators (3/3) AdvAIC P.76 S.J.Chang/EE/NCKU Cp3 has little effect since it is connected to virtual gnd Cp4 has little effect since it is driven by output Cp2 has little effect since it is either connected to virtual gnd or physical gnd Cp1 is continuously being charged to Vi(n) and discharged to ground 1 on – the fact that Cp1 is also charged to Vi(n – 1) does not affect C1 charge 2 on – Cp1 is discharged through the 2 switch attached to its node and does not affect the charge accumulating on C2 While the parasitic capacitances may slow down settling time behavior, they do not affect the discrete-time difference equation Parasitic-Insensitive Inverting Integrator AdvAIC S.J.Chang/EE/NCKU 1 C1 1 C2 Vi(n) Vi(z) 2 2 1 Vo(n) Vo(z) C2Vco nT T 2 C2Vco nT T C2Vco nT C2Vco nT T 2 C1Vci nT Vo [n] Vo [n 1] C1 Vi [n] C2 Present output depends on present input (delay-free) H z P.77 C 1 C1 z Vo z 1 1 Vi z C2 1 z C2 z 1 Delay-free integrator has negative gain while delaying integrator has positive gain. P.78 Summary: A 3-Input SC Summing/Integrator AdvAIC S.J.Chang/EE/NCKU V1(z) V2(z) 1 C1 2 C2 1 V3(z) 2 2 1 Vo(z) 1 1 C3 CA 2 C1 C2 z 1 V z Vo z V1 z 1 2 CA C A 1 z Equivalent signal flow graph V1(z) V2(z) V3(z) C1 1 z C2 z 1 C3 1 1 1 1 C A 1 z C 1 3 V z 1 3 C A 1 z 1 1 C1 1 z 1 C2 z 1 C3 1 C A 1 z Vo(z) P.79 First-Order SC Filter (1/2) AdvAIC S.J.Chang/EE/NCKU Start with a general active-RC structure R3 Replace resistors with delay-free SC equivalents R2 CA Vin(s) Vout(s) Delay-free inputs are used since they create negative integration, as do resistive inputs. 1 1 1 C1 2 SC equivalent Vin(z) –C1(1 – z–1) 2 2 2 CA C1 Vin(z) –C2 C2 C3 1 Vout(z) –C3 1 1 1 C 1 z A Vout(z) Equivalent SFG P.80 First-Order SC Filter (2/2) AdvAIC S.J.Chang/EE/NCKU The equation which describe the previous signal flow graph is Vout z C3Vout z C2Vin z C1 1 z 1 Vin z 1 1 C A 1 z The transfer function is found to be C1 C C C2 C 1 z 1 2 1 z 1 V z C A CA CA CA H z out C Vin z C3 1 z 1 3 1 z 1 CA CA C3 CA 1 z 1 0 z Pole: p C C A C3 A For positive capacitance values, this pole is restricted to the real axis between 0 and 1 circuit is always stable. (note: z=esT; -<s<0 0<z<1) C1 C2 C1 C1 z 0 zz Zero: C C1 C2 CA A H 1 C2 C3 The dc gain is found by setting z = 1 which results in P.81 Switch Sharing AdvAIC 1 Some of the switches are redundant The top plate of both C2 and C3 are always switched to the opamp’s virtual GND and true GND at the same time. One pair of these switches can be eliminated. 1 C2 2 1 2 S.J.Chang/EE/NCKU C3 1 2 2 CA C1 Vin(z) Vout(z) C3 C1 1 Vin(z) 2 C2 1 2 1 2 CA Vout(z) P.82 Charge Injection AdvAIC S.J.Chang/EE/NCKU To reduce charge injection (thereby improving distortion), turn off certain switches first 1 C3 C1 1 Vin(z) 2 C2 2 1a 2a CA Vout(z) Advance 1a and 2a so that only their charge injection affect circuit (result is a dc offset) Note: 2a connected to ground while 1a connected to virtual ground, therefore ... Can use single n-channel transistors Charge injection not signal dependent P.83 Fully-Differential Filters (1/2) AdvAIC S.J.Chang/EE/NCKU Most modern SC filters are fully-differential Difference between two lines represents the signal component Reject common-mode noise 1 Cancel even order distortion terms C3 C1 1 2 C2 2a 2 1a CA Vout(z) Vin(z) 1 2 C2 2a 1a 2 C1 C3 1 CA P.84 Fully-Differential Filters (2/2) AdvAIC S.J.Chang/EE/NCKU In a fully-differential implementation, effective negative capacitances for C1, C2 and C3 can be achieved by simply interchanging the input wires. Example: a negative C1 (equivalent) C3 C1 1 2 C2 2a 1 2 1a CA Vout(z) Vin(z) 1 2 C2 2a 1a 2 C1 C3 1 CA P.85 Summary of Fully-Differential Filters AdvAIC S.J.Chang/EE/NCKU Note that fully-differential version is essentially two copies of single-ended version, however ... area penalty not twice. Only one opamp needed (though common-mode circuit also needed) Input and output signal swings have been doubled so that same dynamic range can be achieved with half capacitor sizes (from kT / C analysis) Switches can be reduced in size since small caps used. However, there is more wiring in fully-differ version but better noise and distortion performance. P.86 Comparator-Based Switched-Capacitor Circuits AdvAIC S.J.Chang/EE/NCKU T. Sepke, J.K. Fiorenza, C.G. Sodini, P. Holloway, and H.S. Lee, “ComparatorBased Switched-Capacitor Circuits for Scaled CMOS Technologies,” ISSCC, pp. 812-813, 2006. L. Brooks and H.S. Lee, “A Zero-Crossing-Based 8b 200MS/s Pipelined ADC,” ISSCC, pp. 460-461, Feb. 2007. L. Brooks and H.S. Lee, “ A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB,” ISSCC, pp. 166-167, 2009. Benjamin P Hershberg, Skyler T Weaver, and Un-Ku Moon, “A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp,” ISSCC, pp. 302-303, 2010. C. Chen, Z. Tan, M.A.P. Pertijs, “A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC” ISSCC, pp. 274-275, Feb. 2013. D.-Y. Chang, C. Munoz, D. Daly, S.-K. Shin, K. Guay, T. Thurston, H.S. Lee, K. Gulati, M. Straayer, “A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR,” ISSCC, pp. 204-205, 2014. P.87 Basic Concept of CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Conventional op-amp-based SC amplifier Vx VCM Vx +Vo- C2 VCM C1 CL Op-amp VCM Vxo VCM The comparator-based SC (CBSC) amplifier Vx VCM C1 Vx Ix C2 VCM Sampling instance t Comparator & Current source +Vo- VCM CL Vxo VCM Vx starts below VCM at Vxo t P.88 Practical CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Additional components Dual-ramp charge-transfer phase (I1 & I2) A comparator-controlled sampling switch (S) S Φ2 Vx VCM C2 VCM C1 P E1 E2 Vo I1 +Vo- I2 CL Vo(n-1) Vo(n) Vx S t VCM Vxo VCM t P.89 Operations of CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Operation at the charge-transfer phase (2) P: brief preset E1: the coarse charge-transfer phase E2: the fine charge-transfer phase S Φ2 Vx VCM C2 VCM C1 P E1 E2 Vo I1 +Vo- I2 CL Vo(n-1) Vo(n) Vx S t VCM Vxo VCM t P.90 Operations of CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Operation at the charge-transfer phase (2) P: brief preset pull Vo to Vss to clear CL ensure Vx starts below VCM S Φ2 Vx VCM C2 VCM C1 P E1 E2 Vo I1 +Vo- I2 CL Vo(n-1) Vo(n) Vx S t VCM Vxo VCM t P.91 Operations of CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Operation at the charge-transfer phase (2) E1: the coarse charge-transfer phase I1 create a fast voltage ramp, Vx VCM Comparator makes decision I1 turns off after Vx crosses VCM Comparator finite delay S Φ2 Vx VCM C2 VCM C1 P E1 E2 Vo I1 +Vo- I2 CL Vo(n-1) Vo(n) Vx S a bc t VCM Vxo VCM t P.92 Operations of CBSC Amplifier AdvAIC S.J.Chang/EE/NCKU Operation at the charge-transfer phase (2) E2: the fine charge-transfer phase Slower ramp & back toward VCM Vx crosses VCM again Sampling switch (S) is opened After the delay of the comp Final overshoot = a constant offset I2 turns off Vx VCM C2 C1 defines the sampling instant S Φ2 P E1 E2 Vo I1 +Vo- I2 CL VCM I1 turns off & I2 turns on (I1 > I2) Vo(n-1) Vo(n) Vx S a bc t VCM Vxo VCM t
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