hbBaltimore
100
SERIES
Metro
CARS
AT0
SYSTEM MANUAL
For additional
information,
contact:
THE BUDD COMPANY
Manager, Customer Relations
Red Lion Plant
1 Red Lion Road
Philadelphia,
PA 19115
Manual
No.
Issued
To:
BALTIMORE AND MIAMI
AT0 SUBSYSTEM MANUAL
(BMPATO)
PREPARED BY WESTINGHOUSEELECTRIC CORPORATION
FOR
BUDD COMPANY
VOLUME IV
FINAL
APRIL 1983
L
COPYRIGHT 1983
WESTINGHOUSEELECTRIC CORPORATION
Transportation
Division
2001 Lebanon Road
West Mifflin,
Pennsylvania
15122
w’
1300M
BALTIMORE AND MIAMI
AT0 SUBSYSTEM MANUAL
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1.0
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Figure 2-3
Figure 2-4A
Figure 2-48
Figure 2-5
Figure 2-10
3 (Contents)
3.2
3.2.3
3.4.1.1
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3.4.1.5
3.5.1
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Table 3-l
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Figure 3-9
Figure 3-13A
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Figure 2-17A
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Figure 3-24
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Figure 3-26A
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3 (pagination
5.3.1
Table 5-3
6.5
(NOVEMBER 1984)
changes)
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AT0 SUBSYSTEM MANUAL
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Table 3-l
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5 (Contents)
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Figure 5-l
Figure 5-2
Figure 5-3
(NOVEMBER1984)
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1300M
LIST OF SECTIONS
SECTION
TITLE
TAB NO.
1
INTRODUCTION
1
2
STATION AND WAYSIDE AUTOMATIC
TRAIN OPERATION (ATO)
2
VEHICLE AUTOMATIC TRAIN OPERATION
(ATO)
3
PREVENTIVE MAINTENANCE
4
TROUBLESHOOTING
5
CORRECTIVE MAINTENANCE
6
3
TABLE OF CONTENTS
L
TITLE
SECTION
1.0
BMPATO
PAGE NO.
INTRODUCTION
l-i
0503M
LIST OF ILLUSTRATIONS
L
FIGURE
TITLE
l-l
AT0 SUBSYSTEM FUNCTIONAL BLOCK DIAGRAM
BMPATO
l-ii
PAGE NO.
0503M
INTRODUCTION
1.0
The Automatic
Train Operation
(ATO) equipment
is a subsystem of Automatic
The AT0 equipment
provides
functions
to automatic
speed
Train Control.
and tractive
effort
generation.
These
regulation,
program station
stopping,
functions
are carried
out nonvitally
subordinate
to the Automatic
Train
Protection
(ATP) subsystem (supplied
by others)
which is responsible
for
The functions
of the AT0 subsystem
comnanded speeds and overspeed
protection.
are implemented
by electronic
hardware located
on the vehicle,
in the
stations,
and at wayside as described
in this book.
Figure l-l
is a block
diagram of the AT0 Subsystem which may be used to follow
the descriptions
in
Figure
3-25 outlines
the software
functions
provided
the following
sections.
by the vehicle
carried
AT0 module.
The hardware components of the AT0 subsystem
on station
and wayside facilities
as follows:
Station
0
0
0
0
Vehicle
vehicle,
and
Tape
Equipment
AT0 Module
0
P & BRK Signal
Generator
AT0 type (1 on each B-car)
Manual type (1 on each car,
0
0
1
Program Stop Transmitter
Assembly
Program Stop Platform
Transmitter
Antenna
Program Stop Marker Transmitter
Antenna
Termination
Boxes
Carried
on the
Equipment
0
0
1
and Wayside
are installed
A or B)
Program Stop Receiver
Antenna
1 assembly on each side of B-car
rear
truck
Termination
Board
Speed Sensors
The decision
making elements
of the system are contained
in the software
(programing)
within
the system's
computer or Central
Processing
Unit (CPU) in
This
module
contains
Printed
Circuit
(PC)
boards
which
the AT0 module.
provide
mounting
surfaces
for the CPU and the associated
electronic
components
which permit signal
interface
between the CPU and external
(other
than AT0
The CPU uses its various
inputs
to determine:
Module) inputs
and outputs.
0
The level
of the P-Signal
Request
the AT0 P & BRK Signal
Generator.
0
The mode of tractive
0
The enabling
BMPATO ( FEBRUARY 1984)
effort,
of start-up
which
propulsion
demands tractive
or brake
effort
from
(P/BRK mode).
circuitry.
l-l
0503l
0
The level
of performance
provided
for
various
commanded speeds.
0
The adherence
to programmed slowdown in preparation
to station
stopping (Program Stop) when that feature
has not been manually
disabled
(Program Stop Cancel) at the operator's
console.
The principle
purpose of the Station
and Wayside AT0 equipment
is the
generation
(Program Stop Transmitter
Assembly)
and transmission
of a 7.07 KHz
signal
in transverse
antennas
(Program Stop Platform
and Marker Antennas)
which the CPU of the AT0 module uses in determining
brake profile
and accurate
stopping
position.
Succeeding
sections
of this manual describe
the AT0 subsystem hardware
physically
and functionally;
first
for the station
and wayside,
then for the
The later
sections
of this manual deal with the software
of
vehicle
hardware.
the AT0 module and system preventive
and corrective
maintenance.
BMPATO
l-2
05034
--
BMPATO
__----
. . .
v---NC-l
. .
*mw?-
-
--
.
.
od 0; d
TABLE OF CONTENTS
TITLE
PAGE NO.
2.0
STATION AND WAYSIDE AUTOMATIC TRAIN OPERATON (ATO)
2-l
2.1
GENERAL DESCRIPTION
2-l
2.2
2.2.1
2.2.2
2.2.3
HARDWARE-- MECHANICAL DESCRIPTION
Program Stop Transmitter
Assembly
Wayside Program Stop Antenna
Program Stop Antenna Termination
Boxes
2-l
2-l
2-3
2-3
2.3
2.3.1
2.3.2
HARDWARE-- FUNCTIONAL DESCRIPTION
Station
Program Stop Transmitter
Assembly
Wayside Program Stop Antennas
2-3
SECTION
I
1
BMPATO (FEBRUARY 1984)
2-i
;I;
05044
LIST OF ILLUSTRATIONS
TITLE
FIGURE
PAGE NO.
2-1A
PS TRANSMITTER ASSEMBLY (SHEET 1)
2-7
2-18
PS TRANSMITTER ASSEMBLY (SHEET 2)
2-8
2-2
PS TRANSMITTER MODULE
2-9
2-3
ANTENNA TAPE INSTALLATION,
BALTIMORE
Z-10
2-4A
ANTENNA TAPE INSTALLATION,
MIAMI (SHEET 1)
2-11
2-48
ANTENNA TAPE INSTALLATION,
MIAMI (SHEET 2)
2-12
2-5
TERMINATION BOX
2-13
2-6
TYPICAL STATION TRANSMITTER ASSEMBLY SCHEMATIC
2-14
2-7
STATION TRANSMITTER ASSEMBLY SCHEMATIC, MIAMI
TEST TRACK
2-15
2-8
TRANSMITTER MODULE BLOCK DIAGRAM
2-16
2-9A
TRANSMITTER MODULE SCHEMATIC (SHEET 1)
2-17
2-98
TRANSMITTER MODULE SCHEMATIC (SHEET 2)
2-18
2-10
PS ANTENNA/RECEIVER CONFIGURATIONS
2-19
BMPATO
2-ii
0504M
2.0
STATION AND WAYSIDE AUTOMATIC TRAIN OPERATION (ATO)
2.1
GENERAL DESCRIPTION
Since the AT0 provides
for station
program stopping
(a joint
effort
between
vehicle
and wayside),
Station
and Wayside AT0 equipment
is necessary
to
provide
the required
control
signal
to the train
for the initiation
and
control
of the program stopping
sequence at the vehicle
level.
The station
and wayside AT0 equipment
is provided
for program stopping
in the normal
direction
of travel
only.
This equipment will
remain energized
at all times
with no control
of the output
signals
except for Miami Okeechobee and Test
Track Stations
(discussed
later).
The station
0
0
0
0
I
and wayside
Program
Program
Program
Terminal
AT0 equipment
provided
is:
Stop Transmitter
Assembly
Stop Platform
Transmitter
Antenna
Stop Marker Transmitter
Antenna
Boxes
Tape
The Program Stop Transmitter
Assembly generates
and transmits
the required
7.07 kHr signals
via interconnect
cables from the Station
to termination
boxes
located
on the wayside near the platform
or marker Program Stop antennas.
The
signal
is coupled
from each termination
box to its respective
antenna.
2.2
HARDWARE--
2.2.1
Program
A.
MECHANICAL DESCRIPTION
Stop Transmitter
Assembly
General
The station
AT0 equipment
consists
of a Program Stop Transmitter
Assembly with one complete assembly provided
for each station.
There
One of the 21 units
are 9 assemblies
for Baltimore
and 21 for Miami.
for Miami will
be used at the Test Track.
For physical
views of the
transmitter
assembly,
refer
to Figure 2-l.
B.
Overall
Frame and Front
Panel
The transmitter
assembly is a 19 inch rack mountable
unit with
all dimensions
15.00" H x 19.00" W x 12.00" D. The unit depth
actually
10.75" into the rack.
Approximate
weight of the unit
lbs.
overis
is 30
The top half of the external
assembly consists
of a fold down front
panel.
Two rows of heavy duty barrier
type terminal
strips
are
mounted on the rear panel of the assembly for external
wiring.
The fold
assembly
contains
down front
panel provides
without
requiring
removal
the following
items:
BMPATO (NOVEMBER 1984)
2-l
access to components inside
the
from the rack.
The front
panel
0504M
1.
2.
3.
C.
24 V power test points
(banana plug type)
ac power breaker
(5 amp, double break)
ac and dc power status
indicating
lamps (yellow
and green
with T-l 3/4 type bulbs:
ac = neon, dc = incandescent)
lens
Power Supply
A 24 Vdc Lambda LNS-W-24 power supply is mounted behind the front
This supply operates
from a nominal 120 VAC, 60 Hz, single
panel.
phase source to produce 24 Vdc power for the transmitter
modules.
The power supply meets MIL-STD-810C and MIL-I-6181
specifications.
Physically
the supply measures 9" x 5" x 2 7/8" and weighs 9.5
The power supply mounts to the side of the transmitter
pounds.
assembly frame (Figure
2-18) through
a hat section
mounting
base
which allows
removal.
The power supply is interfaced
to the other
circuits
of the transmitter
assembly through
a short pigtail
wire
harness and connector.
The mating connector
receptacle
is mounted to
the midsection
shelf
internal
to the assembly.
D.
Control
Relays
For the transmitter
assemblies
of the Miami Okeechobee and Test Track
Stations,
the top section
of the assembly behind the front
panel will
also contain
two relays
style
number 404P443H25.
These relays
are
used to switch the outputs
of transmitter
assemby on or off as
required.
They are plug-in
socket type with hold down spring
The relays
have 12 Vdc encapsulated
coils
and 5 A gold
clamps.
contacts.
E.
Interchangeability
Transmitter
interchangeability
is as follows:
All units
containing
two transmitter
modules (1508F36GOl)
can be interchanged
with each
other but not with the units
(1508F36602)
at Miami Okeechobee or Test
Track stations.
However, the units
at Miami Okeechobee and Test
Track can be used in place of the other units.
F.
Transmitter
Modules
The lower half of the transmitter
assembly houses the plug-in
A module consists
of an aluminum frame which
transmitter
modules.
surrounds
a printed
circuit
board.
This arrangement
can be seen in
Figure 2-18.
The rear of the printed
circuit
board is out fitted
with two connectors
which comprise one-half
of a two piece connector
The mating half connectors
are mounted to the inside
rear of
system.
the transmitter
assembly frame.
The module can be removed from the
transmitter
assembly by simply removing the knurled
nuts (hand
tightened
only)
at either
side of the module and removing it with an
The printed
circuit
board is removed from the
outward pull motion.
frame (if required)
by removing the module frame front
plate.
BMPATO (FEBRUARY 1984)
2-2
0504M
All transmitter
assemblies
will
contain
two transmitter
modules
(Figure
2-lB,
positions
Al, A2) with
exception
of Miami Okeechobee
and Test Track stations
which contain
a third
module (position
A3).
Each module has two transmitter
outputs.
All transmitter
modules are
the same and are interchangeable
except as noted in 2.2.1.E,
above,
from assembly to assembly without
any setup.
2.2.2
Wayside
Program
Stop Antenna
The Program Stop Antenna consists
of encapsulated,
parallel,
insulated
wires
which are transposed
(crossed)
every 12 inches.
The overall
antenna tape
dimensions
are 3.00 inches wide by 0.25 inches thick.
The encapsulating
polyurethane
material
provides
environmental
resistance
and dimensional
stability.
I
The program
coverboard.
stop
antenna
tape
is mounted
directly
on top of the
For Baltimore
and Miami, the antenna tape is mounted
length
in the station
platform
areas.
The center of
the center of the platform
in all cases.
third
rail
in a continuous
450 foot
the tape is aligned
with
A short marker antenna tape is mounted on the normal approach side to the
The length
of the marker tape is indicative
station
(inbound
and outbound).
of the distance
it is located
from the beginning
end of the platform
antenna
tape and varies
based on the maximum speed command or approach velocity
in the
region approaching
the station
platform.
Other factors
determining
this
distance
are the velocity/distance
profile
for a 1.5 mph/set.
deceleration
rate,
the jerk limit,
and the reaction
times of the train.
Charts of the
marker locations
and lengths
are available
on Figures
2-3 (Baltimore)
ana 2-4
(Miami).
2.2.3
Program
Stop Antenna
Termination
Boxes
Located near each wayside program stop antenna tape installation
is a
The box is a standard
NEMA type 4X (14 gauge
termination
box (Figure
2-5).
The overall
dimensions
of the box
stainless
steel)
suitable
for outdoor use.
The box has a hinged cover which is held clamped by
are 10 x 8 x 4 inches.
Inside
the box, a
two screw down clamps on the non-hinged
side of the box.
8.75 x 6.88 inch panel mounts terminal
strips
(for incoming
and outgoing
a current
limit
resistor,
and a lightning
cables),
a matching
transformer,
arrester
(across the cable going to the antenna tape).
This panel can be
detached for maintenance
by removing the four securing
screws.
2.3
HARDWARE--
This section
describes
AT0 equipment.
BMPATO (FEBRUARY 1984)
FUNCTIONAL DESCRIPTION
the
operational
characteristics
2-3
of Station
and Wayside
0504M
Station
2.3.1
Program
Stop Transmitter
Assembly
L
The transmitter
assembly generates
and transmits
a 7.07 KHz signal
to the
The actual
signal
development
is carried
out on
wayside program stop antenna.
the 226P324 transmitter
module (2 per typical
transmitter
assembly).
Figure
2-6 is a schematic
of the overall
transmitter
assembly except for Miami
Okeechobee and Test Track units
the schematic
of which is shown on Figure 2-7.
Power (nominal
120 Vat, 60 Hz, single
phase) is input
through a 5 amp, doublebreak breaker
to the dc power supply,
A4-Al.
The power supply,
in turn,
If the ac
provides
regulated
24 Vdc power for the transmitter
modules Al, A2.
breaker is on, ac power is applied
to the dc power supply and energizes
the
When the dc power supply is energized,
front
panel ac indicator
lamp (DSl).
the front
panel,
dc power, ON lamp (DS2) will
be lit.
From the dc power
supply,
24 Vdc power is fed continuously
to transmitter
modules (Al, A2), each
of which provides
two outputs
of 7.07 KHz program stop signal.
Figure 2-7 details
the transmitter
assembly schematic
for Okeechobee and Test
The assembly is the same as shown for Figure
2-6, except an
Track stations.
additional
transmitter
module and control
relays
(Kl, K2) have been added.
The relays
are connected
to allow double break of the outputs
of transmitter
modules A2 and A3 whenever the relays
are energized
by an external
+12 Vdc
The relays
(Kl, K2) normally
remain de-energized.
signal.
Figure 2-8 is a block diagram of the Program Stop Transmitter
operation
of the transmitter
module is described
below.
module.
The
There are two transmitters
per Program Stop Transmitter
(226P324638)
module.
Each transmitter
is a push pull
design with output
isolation
transformers
for
The module contains
its own oscillator
which produces the 7.07
protection.
The oscillator
is a quartz crystal
KHz signal
needed for Program Stop.
oscillator
that provides
the stability
needed at the receivers
end.
The 7.07
KHz signal
is inverted
to provide
the two equal,
opposite
phase, 7.07 KHz
Both of these signals
are then
signals
needed for the push-pull
driver
stage.
sent through
a circuit
which transforms
the 5D% duty cycle into a 40% duty
This prevents
the driver
transistors
from being on at the same time.
cycle.
From there,
the signals
go to the driver
stage, which provides
current
switching
through
the output
transformer.
Both transmitters
have an LED on the output
to indicate
that a particular
The board is powered by the transmitter
assembly's
24 volt
transmitter
is on.
The
output
driver
state
is
driven
directly
by
the
24
volts.
The
supply.
oscillator
circuit
is powered by +15 volts,
which is regulated
from the 24
A +12 volts
is also derived
from the 24 volt supply.
This +12
volt supply.
volts
powers the circuits
which provide
the 40% duty cycle.
The 226P324G38
module schematic
is provided
on Figure
2-9A and 2-9B.
2.3.2
A.
L
Wayside
Program
Platform
Antenna
Stop Antennae
when energized,
The platform
antenna,
train
lead married
pair truck mounted
BMPATO (FEBRUARY 1984)
2-4
works in conjunction
Program Stop Antenna
with the
to produce
05044
L
7.07 KHz signal
outputs
on the train
carried
PS Antenna.
These out
puts change phase relation
every six inches of train
travel.
Since
all Platform
Program Stop Antennas are the same length
and positioned
in the same manner, the phase reversals
become indicative
of
distance-to-go
to the final
stopping
point.
To understand
the exact manner in which this antenna functions,
wayside antenna tape and vehicle
mounted program stop receiving
antenna must be considered
functioning
together
in the following
manner:
the
Figure 2-10 illustrates
the physical
and electrical
properties
of the
four antenna coils
as a vehicle
borne PS Receive Antenna Assembly
passes a PS Antenna.
Physically,
the car antenna coil centers
are
spaced 6.00 inches apart,
Figure 2-10 (A).
Electrically,
the four
coils
are connected
to form two sets (two channels)
of series
wound
antennas.
An "A" set, which consists
of coils
Al and A2, produces the Channel A
Coils Bl and 82 form the "B" set, which produces the
output
signal.
To understand
how the passing,
vehicle
borne PS
Channel B signal.
antenna arrangement
senses phase reversals
in the adjacent
loops of
the station
PS transmit
antenna,
to be detected,
it is necessary
to
consider
the two conditions
under which current
is induced into the
four receiver
coils
of the vehicle
PS antenna assembly.
L
Figure 2-10 (8) depicts
the Al and Bl coils
positioned
over the same
12 inch loop of the PS transmit
antenna.
Because of antenna spacing,
receiver
coils
A2 and 82 are both positioned
over an adjacent
12.00
inch PS transmit
antenna loop.
Current
flow in the transmit
antenna and induced current
flow in the
four receiver
coils
is indicated
on the diagram.
When the PS antenna
assembly is in this position,
currents
in coils
Al and A2 add to
produce a Channel A output
of indicated
polarity.
Likewise,
the
currents
in Bl and 82 add to produce the indicated
Channel B output.
the Channel A output
is in phase with the Channel 13
In this position,
signal.
In Figure
2-10 (Cl, the PS antenna assembly of the train
has been
displaced
6.00 inches over the stationary
PS transmit
antenna.
Once
again,
the Al and A2 currents
add as do the Bl and B2 currents.
However, now the Channel A output
is 180 degrees out of phase in
respect
to Channel B.
If the vehicle
moves another
6.00 inches,
Channel A and Channel B
Thus, while the train
signals
will
return
to the in-phase
condition.
is passing over the station
PS transmit
antenna,
the functioning
PS
receiver
assembly will
be continually
producing
two output
signals
which are alternately
in-phase
and out-of-phase
every 6.00 inches.
Refer to Section
3.6.3 for further
details
of how the program stop
system uses these phase reversals
to effect
an accurate
stop.
e
BMPATO (FEBRUARY 1984)
2-5
0504M
B.
Marker
Antenna
The Marker Antenna,
when energized,
works in the same manner as the
Platform
Antenna but is much shorter
in length.
This produces only a
burst of phase reversals
that are recognized
by the AT0 which
initiates
the program stop sequence.
The Marker Antenna is located
a
sufficient
distance
from the Platform
Antenna to initiate
Program
Stop from a high train
speed so that speed is smoothly
and
efficiently
reduced prior
to encounter
of the Station
Platform
Antenna which will
direct
the AT0 module to effect
a final,
precise
Specific
marker lengths
are identified
by Figures
2-3, 2-4A,
stop.
and 2-4B.
BMPAT0 (FEBRUARY 1984)
2-6
0504bl
CUT OUTS
CONNECTORS
REAR VIEW
TP
---- -@
- ----------
P
.7---- - ---- - ------
----_ -- --__ -__/---DSl
DS2
-TX2
OUTPUT
LED
ONLY AT
,+- MIAMI TEST
TRACK &
OKEECHOBEE
LOCATIONS
TYPE)
FRONT VIEW
FIGURE Z-1A.
BMPATO
REF: 1508F36
PS TRANSMITTER ASSEMBLY (SHEET 1)
Z-.7
SIDE VIEW
SUPPLY
OR ASSEMBLY
PANEL
(HINGED)
ar
TRANSMITTER
MODULES
(POSITION ~3 LEFT \.Z
BLANK EXCEPT FOR
MIAMI TEST TRACK
& OKEECHOBEE
LOCATIONS)
POSITION
SIDE VIEW
EXPOSED
A2
TRANSMITTER
.ASSEMBLY
TOP VIEW
,--HOLE
FOR IJIRING ACCESS
CONTROLRELAYS,
ONLY AT MIAMI
TEST TRACK &
OKEECHOBEE
POWERSUPPLY
INDICATOR
FIGURE 2-1B.
REF:
1503F3G
PS TRANSMITTER ASSEMBLY (SHEET 2)
BMPATO
2-8
2.50
IN.HANDLES FOR MODULE
INSTALLATION AND
REMOVAL
FASTENERS
GUIDE PIN
HOLES FOR PC CARD
INTERFACE CONNECTORS
(41 PINS EACH)
' ROLLED EDGES
FOR STIFFNESS
MODULECODING
PLATE
/
U
REF:
OUTLINE OF PC BOARD
L
FIGURE 2-2.
PS TRANSMITTER ::ODULE
BlPATO
2-9
l!iP'lF?lG36
hU RKER
UkZAnON
W/f?
STATION
DISTANCE/N
&Ye
STATION
MARKER
W/n
MARKER
LENGTH
LOCXT/ON
TRACK
IN
LENGTff
FCET
-
/z
9.75-f.
rr
I
- -----.--._;:_.
,
COVER
12.00-‘.50
t
I
t
I
11
_.-__
-
-.
+12
A - M.4KE
ITEMS
LEFTOVEU
.2s-.,oj-r
OR MORE AS REQO.
lAISTI1LLAT/OA/
REF
i-27.03!.06
2 AND
3
FUOM
ITEM
ffshVQ
1.
LINTENNA
19 - UAVtZ
EXCESS
AS REQUIRED
ON
TAPBFOR
PRfPARIItfG
EN0 AS ShDWN
WIRE
SPLlCf
PER OWG.
2266040.
DETAIL
D
w?
COVEX SPLICE
NOTCH
/TfM
4
AT
TRACK
I
+----S/5
I
L #WEU UA/L
#wym
I
SPLICC PLATE
7
C-
QUANTITIES
SHOw
ITEMS
EXCEPT
PAINT,
D-
U.V
lNW8lTED, LIGHT CRN
CONFORMlNCi
TO ANSI
255.1
T~K
EKU
END
OF
(SECE-E)
e MAX/NC
ARE FOR
9 (N/NE)
t-f. 7 SUPPLIED
BY
IN
SZ.A~/ONS.
WESTINGHOUSE.
COLOR
NO.
ALL
70,
B/M FOR RE-fERE/VCE ONLY
L.50
XT/ON
E-E
c! EN0 OF Tfil
i
-./BGAP
A
-----
.-
!
'y
TV/?
i- ./2 7-w
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COVER,
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r
- - .-
i_l
I
,$
I
-----I
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W/TH
RIB
AS
YloWN
-7
70
COl/.ER
SUPPOQT ----A
OF
@
SUPPORT
l.‘Js?ZU
AAfTENNA
TAPE (ITEMS
I 2 +4NDd)
wm
SJ~ALOW
DIE MARQRKJ UP. ~444~s
/NDICcITE CONDUC?OR CROS50Y&R5.
SEE DET4lL ‘C:
3PAC.W
/
eI
THIRD
i
SECT/ON
TYP.
COVER
5upmRr
I
OUTiiOUND
MARKER
A4
I~00~orulPA~~
74pE
SUOWN
I
I
I
@
-c-.-ws--
I
e
:
AT /5dO AlO,% APART
2 -A’
-?-RACK
:
AS POSSIELf
RAIL
A:
+
AS UNIFORMLY
:
“I:::::.:::::::.:.::!::::::::.:,.
A
y
DERlL
ARRANGED
A5
2.’
mz4r~
TRANSVERSELY
wm
(iT0.l Q)AND
LONOllUD/MAUY
blMEN5lml5
SHOWA/.
NYN~E
PER
RIVETS
SWOULO SE SBCED
AS WlfOMttY
AS
POSSl8LE
AT MOO NOH.OIMfNSION.
TOOlERANtE
:SOO
IS ONLY FOR CLEARANCE
OF COVERBOARD
SUPPORT
BRACKETS
& CONDUCTOR
CROSSOVCRS.
OF
+
TRRncK
INBOUND _t
REF:
FIGURE 2-3.
BMPATO (FEBRUARY 1984)
AN0
IN
1509FO8 SUB 6
ANTENNA TAPE INSTALLATION
BALTIMORE
2-10
_---
I------.--,
I
/
\
r
_-_
\
_-
-!!t--I
il
_________
-@-
______
1 \
,
--------------
----
--
---_-_
\\
i
( TRACK
I‘
SOlJlH8OCND
4’-
:
WCI
tm;-’
-Q
llWX
NOUTHBOUNQ
-
At
REF.
:
.
(
BMPATO (FEBRUARY 1984)
DM-C-
1fl.I.
tr
I
f
--
I
\
I
I
-[dM%E
f-
!
--a?-
REF: 1509F43 SHEET 1 SUB 5
CHAut-DIM:k450’
TO ENDS
ot
TIPE
FIGURE 2-4P>. ANTENNA TAPE INSTALLATION
MIAMI (SHEET 1)
2-11
.
I
1
i MARKER
LOCATION 1” FEETW/nT1 STATION RA-TFORM WrrUwA TAPE1 NOR1 HBOUNO ’ A” 1 YOUTHS
SThTlOrJ
I
!
IbZV
r3Ccr
I
MARKER
LENGTH
1
I
LlVlL CLl-4I tn
_C&I?\ER..
I
tiE\C+lTS 1
CENTER 1
‘,i’ASHI~l&4
@vZRMCNT
BRICKELL
VIZCAYA
- --.-LI-GROVE
-
RD.
iY STh
MIAMI
CADELAND
NOR%
DADELAND SOUTH
.SOUTH
TRACK
I
6LO
1620
970
620
-72
1620
16.20
17
620
620
17
167.0
970
910
24 10
24 IO
1620
I2
2410
2410
22
22
1620
24 IO
22
22
1
1620
I
24 IO
24
--‘h ICI
I
NOT REQ’D
1
970
I
0
VEHICLE
l-0 NEXl-
IS
tt
VEHICLE
SPEED
IS TRAVELCING
MARKER
AND
AT
AT A SPEED
LOCATION
IS
WI
OF
USED
S SPEED
-
I-I
2410
24 IO
TRAVELLINC
SPEED
COMMAND.
II
12
-
FRowl
PREVIOUSL\/
LOWER
!
7
+ ADD\TIONAL MARKER 13 LOCATED ON W’PWACH
OF OKEECUOBFE STfiT\ON
ONLY ON TRACK 2
I
--#
2410
IO20
-^-
I
1
.-___
22
2410
57A.
I
I;'
2410
-7
LENGTH
iN FEET
1
I
I
I
;;
J7
-I
I
70
53
38
sa
46
59
40
70
I2
I
22
22
REQ.0
12
0
Q
70
58
70
10
YRRO
S\DE
lo
70
58
I
NOT
3
38
5a
-~-_
- 58
38
38
4-a
58
10
70
NOT
I
58
70
7
22
22
I
=0
-3-a
20
-~-XL .___.. I-
If
I
SPEED
IN N.P. Pt.
I-l
17
1
22
I-l
ALREADY
ENTRY
I
I
70
46
REQ’D
0
@RAKING
ENl-RY
46 WW.
NEXT
HIGUER
l-0 AVOID
TRACK
CROSSOVER.
STAllON PLATFORM
I
SOUTHBOUND
STATlOU
PLCITFfXtM
SUPPORT BRACKETS ~0fk THIRD
RAIL COVER t 8Y OTHERS)
REF:
FIGURE 2-4B.
1509F43 SHEET 2 SUB 5
ANTENNA TAPE INSTALLATION,
MIAMI (SHEET 2)
2-12
LIGHlNINCr
TBB
TpA-
. l-4 i
I
I II
-1 I
I
;\ ,!
i
Al
FROM
PS TX
AS%
I
TRRESER
TO PS
ANTENNA
TE,QMh’Al/ON
BOX SCHEMAT/C
DIAGRAM
0+
TI
9
L
a00
6
GND
i
SIDE
VIEW
L/1150
-
L
REF:
FIGURE 2-5.
BMPATO (FEBRUARY1984)
TERMINATION BOX
2-13
2267985
SUB 3
-
5
-
a
I-
:
ti
- -
;.-3
-I
i
t
L\9
-t
t
(
J
:
i! 3
- -
%
;r
-
0’
x
-
BMPATO
2-14
-
c-
DCPMN
I-
PROGRAM
STOP
TX OU-K=JT
CON-T??OL
FROM
TRAIN
COkITROL
LOGIC
I
1
I
I
I
j
I
i
NOTES
.--
:
‘)
T7
2,
--+
LJI
r.
INDICA~TTS
TWISTElI
@ IMDKATES
Tf5T
A
PAli
J
REF:
4683C77 SH 3 SUB 5
A
FONT
V&E
YEF
DWGS
~AKNCS:,
iEl,CR;L
FIGURE 2-7.
BMPATO
A>?jV
STATION TRANSMITTER ASSEMBLY SCHEF;ATIC,
MIAMI TEST TRACK AND OKEECHOBEELOCATION
2-15
B,‘r\
“C712Al70G3Z
2A6,6
W,lL #b-i1
’ 15OYF
36
Ic
I-
BMPATO
2-16
L
BMPATO
2-17
I
I
II
t
f
i
I
BMPATO
1
u
?z
d
0
! -?r
2-18
CHANNEL B
CHANNEL A
B.) A AND 0 l/V PHASE
A
w
+,
C
CHANNEL, B
+
CHANtdEL A
L
FIGURE Z-10.
BMPATO FEBRUARY1984)
PS AWTENNA/RECEIVER CONFIGURATIONS
2-19
TABLE OF CONTENTS
TITLE
SECT1ON
PAGE NO.
3.0
VEHICLE AUTOMATIC TRAIN OPERATION (ATO)
3-l
3.1
GENERAL DESCRIPTION
3-l
3.2
3.2.1
3.2.2
3.2.3
3.2.4
HARDWARE-- MECHANICAL DESCRIPTION
Vehicle
Program Stop Antenna
AT0 Propulsion
& Brake Signal Generator
Vehicle
AT0 Module Assembly
Termination
Board
3-l
3-l
3-2
3-2
3-4
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
AT0 SUBSYSTEM SIGNAL INTERFACE
Secondary
(CKT BRK) Panel
Operator's
Panel
Auxiliary
Relay Panel
Propulsion
& Brake Signal Generator
Vehicle
Mounted Equipment
ATP Subsystem
3-4
3-4
Z.1
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5
3.4.1.6
3.4.2
HARDWARE-- FUNCTIONAL DESCRIPTION
Vehicle
AT0 Module
Motherboard
Digital
Input and Power Supply Board
CPU Board
Program Stop Receiver
Board
Input/Output
Board
Tertzfsetion
Board
Propulsion
and Brake Signal Generator
;I;
3-7
3-8
3-11
3-11
3-12
3.5
3.5.1
3.5.1.1
3.5.2
3.5.2.1
SOFTWARE-- GENERAL STRUCTURE
Initialization
Routine
Check and Clear Memory
Main Loop
Toggle Reset
3-12
3-13
3-14
3-14
3-14
3.6
3.6.1
3.6.2
3.6.3
3.6.3.1
3.6.3.2
3.6.4
SOFTWARE-- FUNCTIONAL DESCRIPTION
AT0 Velocity
Request
Speed Maintaining
(Regulation)
Program Stop
Program Stop Antenna Tape Function
Vehicle
Software
Implementation
of Program
Serial
Link
3-14
3-15
3-17
3-17
3-18
3-18
3-20
BMPATO (FEBRUARY 1984)
3-i
;:;
3-5
3-5
3-6
(ATO)
3-6
3-6
Stop
0505M
LIST OF TABLES
TITLE
TABLE
PAGE NO.
3-l
AT0 MEMORYMAP
3-21
3-2
AT0 MEMORYASSIGNMENT AND DEFINITION
3-23
3-3
I/O BIT ASSIGNMENT SHEET
3-71
3-4
HEXIDECIMAL/DECIMAL CONVERSIONS
3-76
3-5
HEXIDECIMAL/BINARY
3-77
3-6
DEFINITION
BMPATO (FEBRUARY 1984)
CONVERSION
OF TERMS
3-78
3-ii
0505M
LIST OF ILLUSTRATIONS
i
FIGURE
TITLE
PAGE NO.
3-,A
PROGRAMSTOP ANTENNA (SHEET 1)
3-80
3-JB
PROGRAMSTOP ANTENNA (SHEET 2)
3-81
3-2
PROGRAMSTOP ANTENNA CASE ASSEMBLY
3-82
3-3
AT0 MODULE ASSEMBLY OUTLINE
3-83
3-4
MOTHERBOARDASSEMBLY
3-84
3-5
PRINTED CIRCUIT BOARD OUTLINE
3-85
3-6
AT0 SIGNAL INTERFACE
3-86
3-7
AT0 MODULE BLOCK DIAGRAM
3-87
3-8
AT0 INTERCONNECTIONS
3-88
3-9
MOTHERBOARD
3-89
3-10
DIGITAL
INPUT AND POWERSUPPLY BOARD BLOCK DIAGRAM
3-90
3-11
DIGITAL
INPUT BOARD SCHEMATIC
3-91
3-12A
CPU BOARD BLOCK DIAGRAM (SHEET 1)
3-92
3-12B
CPU BOARD BLOCK DIAGRAM (SHEET 2)
3-93
3-12c
CPU BOARD BLOCK DIAGRAM (SHEET 3)
3-94
3-13A
CPU BOARD SCHEMATIC (SHEET 1)
3-95
3-13B
CPU BOARD SCHEMATIC (SHEET 2)
3-96
3-13c
CPU BOARD SCHEMATIC (SHEET 3)
3-97
3-14
PROGRAMSTOP RECEIVER BOARD BLOCK DIAGRAM
3-98
3-15
PROGRAMSTOP RECEIVER BOARD SCHEMATIC
3-99
3-16A
I/O BOARD BLOCK DIAGRAM (SHEET 1)
3-100
3-168
I/O BOARD BLOCK DIAGRAM (SHEET 2)
3-101
3-17A
I/O BOARD SCHEMATIC (SHEET 1)
3-102
3-178
I/O BOARD SCHEMATIC (SHEET 2)
3-103
BMPATO (FEBRUARY 1984)
3-iii
0505M
LIST OF ILLUSTRATIONS (CONT'D)
TITLE
FIGURE
PAGE NO.
3-18
TERMINATION BOARD WIRING
3-104
3-19
SOFTWAREDESIGN FLOW CHART
3-105
3-20
INITIALIZATION
3-706
3-21
CHECK AND CLEAR MEMORYAND BRAM SUBROUTINE
3-107
3-22
MAIN LOOP PROGRAM
3-108
3-23
TOGGLE RESET
3-109
3-24
SOFTWAREFUNCTIONAL BLOCK DIAGRAM
3-110
3-25A
ATO VELOCITY REQUEST ROUTINE (SHEET i)
3-111
3-258
AT0 VELOCITY REQUEST ROUTINE (SHEET 2)
3-112
3-26A
START-UP ROUTINE (SHEET 1)
3-113
3-26B
START-UP ROUTINE (SHEET 2)
3-114
3-26C
START-UP ROUTINE (SHEET 3)
3-115
3-27
BASIC SPEED MAINTAINING SERVO LOOP
3-116
3-28
SPEED MAINTAINING AND OVERSPEEDLIMITS
3-117
3-29A
PROGRAMSTOP INTERRUPT ROUTINE (SHEET 1)
3-118
3-298
PROGRAMSTOP INTERRUPT ROUTINE (SHEET 2)
3-119
3-30A
PROGRAMSTOP SERVICE ROUTINE (SHEET 1)
3-120
3-30B
PROGRAMSTOP SERVICE ROUTINE (SHEET 2)
3-121
3-31
SERIAL LINK LOADER ROUTINE
3-122
3-32
SERIAL LINK RECEIVER ROUTINE
3-123
3-33
SERIAL LINK TRANSMITTER ROUTINE
3-124
BMPATO (FEBRUARY 1984)
ROUTINE
3-iv
0505M
3.0
VEHICLE AUTOMATIC TRAIN OPERATION (ATO)
3.1
GENERAL DESCRIPTION
The vehicle
functions:
0
0
0
0
0
0
AT0 provides
the
following
functions
Start-up
logic
Tractive
effort
request
Automatic
speed regulation
Performance
level
adjustment
Program station
stopping,
full
Diagnostics
A functional
with Station,
subordinate
to the ATP
and low rates
block diagram of the AT0 Subsystem is presented
Wayside, and Vehicle
functions
represented.
by Figure
l-l
The functional
blocks which interact
within
the subsystem are composed of
hardware and software.
The hardware items are identified
(items 1 through
10)
by Figure l-l.
The software
functions
are microprocessor
routines
stored
in
EPROMmemory and executed within
the Central
Processing
Unit (CPU) PC board
The hardware functions
will
be discussed
in Section
3.4.
The
(item 8).
software
functions
carry the intelligence
for subsystem operation,
as will
be
evident
from the operational
description
in Section
3.5.
3.2
The vehicle
termination
Assembly.
3.2.1
HARDWARE--
MECHANICAL DESCRIPTION
AT0 hardware consists
board, an AT0 Module
Vehicle
Program
of Program Stop Antenna Assemblies,
Assembly,
and an AT0 P & BRK Signal
a
Generator
Stop Antenna
One antenna is mounted on the right
and
There are two Program Stop Antennas.
one antenna is mounted on the left
side of the rear B-Car truck assembly.
The
right
and left
vehicle
mounting
arrangement
allows for matching
the Station
Platform
Antenna whether an A or B vehicle
is the leading
end.
The physical
arrangement
truck mounting
scheme is
construction
is detailed
of the Program Stop Antenna,
associated
brackets,
shown by Figure 3-l.
The Program Stop Antenna
by Figure 3-2.
and
The Program Stop Antenna alone consists
of a molded fiberglass
case with overall dimensions
of 28" L x 6" W x 2.19" H. The case contains
four coils
mounted on a printed
circuit
board which provides
for interconnections
between
After
the coils
and PC board are installed
and the interface
cable
the coils.
attached,
the entire
interior
of the case is filled
with potting
compound and
the case lid is installed.
The Program Stop Antenna case and cable/connector
are mounted to an aluminum
casting,
the length
of the antenna case.
A T-bracket
is mounted on this
This
allows
the
entire
assembly
to
be
mounted
on a mating bracket
casting.
BMPATO (FEBRUARY 1984)
3-l
0505Cl
that is welded to the end of the truck bolster.
The T-bracket
is provided
with slots
to allow adjustment
of the assembly (+1.25")
to compensate for
wear, truck tolerance,
etc.,
wheel wear, rail
when the sum of these values has
exceeded a total
of 1.5 inches.
The initial
clearance
of the antenna above
the running
rails
gives 1.5" clearance
of the lowest point on the antenna to
the 13.5" dynamic clearance
envelope.
The highest
point on the wayside
antenna tape is at 11.5" waterline
or 2" below the 13.5" waterline,
as
Thus 1.5" wheel wear, etc.,
required.
is allowed before the antenna assembly
reaches the 13.5" waterline
clearance
with adjustment
required
thereafter.
These clearances
may be better
understood
by referring
to Figure 3-l.
3.2.2
AT0 Propulsion
& Brake
Signal
Generator
The AT0 P & BRK Signal Generator
is described
Section
4-17 of the Heavy Maintenance
Manual
3.2.3
Vehicle
AT0 Module
Assembly
(Figure
mechanically
(BMPABM).
and functionally
in
3-3)
The AT0 module mechanical
construction
is a very rigid,
basic box structure
constructed
of aluminum.
The module has been provided
with handles to
At the lower end of the module (as viewed in the
facilitate
carrying.
electronic
locker)
the mating half of an AMP Series M 160 pin connector
is
provided
for interfacing
to vehicle
wiring.
The module is designed
to house up to seven plug-in
printed
circuit
boards and
Each board position
is provided
with card guide slots
to
a motherboard.
assist
in aligning
the PC board with the edge connectors
which are mounted on
the motherboard
inside
the module.
In addition,
each card position
is
provided
with the mating half of a PC board lever action,
inject-eject
latch
Each board position
is identified
on the module (XAJ, XA2, etc.).
system.
The front
of the module is outfitted
with a readily
removable,
clear,
Lexan
(polycarbonate)
cover for the purpose of sealing
the module and affording
protection
to the PC boards whenever the module is being transported
for
maintenance.
The end caps of the module (carrying
handles are attached
to permit air circulation
through
the module.
here)
are louvered
The module side plates,
end caps, and lower cross stiffners
fasten to each
other and the rear back mounting
plate composed of a one piece 0.62" thick
One end of the rear p late is tapered to mate with the
aluminum sheet.
equipment mounting
rails,
while at the other end are mounted two captive,
stainless
steel mounting
screws.
Located at the lower end of the front
of the module, a 5 amp circuit
breaker
inputs
the 37 Vdc from the battery
to supply the Digital
Input and Power
Supply board.
The mechanical
construction
of the AT0 module is the same for
Logic Module discussed
in Section
4-4 of the Heavy Maintenance
BMPATO
3-2
the Propulsion
Manual (BMPABM).
0505M
The AT0 module
printed
circuit
functions.
a.
contains
boards
a motherboard
each designed
type
ATO
Motherboard
The motherboard
is a printed
circuit
board to which are affixed
seven
pairs of edge type printed
circuit
board connectors
(Figure
3-4).
Also attached
to the motherboard
above the Pl connector
row are 24
two watt carbon resistors
that serve as part of the isolation
to the
optically
coupled digital
input circuits
from car battery
sourced'
Also mounted to the board in front
of the capacitors
is a
signals.
diode that prevents
damage if car battery
source power input polarity
is not observed.
I
The board is constructed
Trace conductors
P13949.
of 0.12" thick
glass epoxy
are per MIL-STD-275C.
per MIL-STD
Attached
also on the Pl row connector
side of the motherboard
is a
wiring
harness that includes
the 160 pin connector
mounted on the end
cap as previously
discussed.
The wires are #20 AWG (19/.008)
conductors,
silver
plated,
with insulation
of Teflon TFE rated at
600 Vdc.
I
b.
id
and four plug-in
edge connector
and selected
to perform specific
Plug-in
Printed
Circuit
Boards
The four plug-in
printed
circuit
boards are shown in position
The boards are 0.063" nominal thickness
of glass
Figure 3-3.
Trace conductors
are per MIL-STD-275C.
per MIL-STD 13949.
on
epoxy
The front
edge of the boards are fitted
with a molded composite
stiffner,
the ends of which contain
the lever portion
of the
Affixed
to the front
face of this
inject-eject
latch
system.
stiffner
are labels
which identify
the board type, name, and position
This arrangement
can be seen pictorially
in Figure
in the module.
3-5.
There is a second stiffner
along the rear of the board which serves
to hold male keying pins (in the center section
of the stiffner)
in
These
pins
must
mate
with
the
an arrangement
unique for each board.
corresponding
hole pattern
in the motherboard
for the board to be
inserted
in a specific
slot position
on the motherboard.
The connector
portion
of the board uses gold plated trace ends for
mating with the edge connector
receptacle
mounted on the
There are forty
such trace ends on either
side of the
motherboard.
board for both the Pl and P2 positions.
BMPATO (FEBRUARY 1984)
3-3
0505M
Termination
3.2.4
Board
The Termination
Board construction
board is 0.12" thick,
glass epoxy
conductors
are per MIL-STD-275C.
is shown by outline
drawing 4684C69.
The
construction
per MIL-STD-P13949.
Trace
Mounted to the board along the longest
sides are barrier
type terminal
strips,
one on each side, with 18 terminal
points
each.
Wiring from vehicle
mounted
equipment
(external
to ATO) connects
to one side of the terminals,
and the
interface
wiring
to the AT0 Module connects
to the other terminal
strip.
Mounted in the section
between the terminal
strips
a re five resistor-capacitor
networks and two Zener diodes,
the function
of which is described
later.
There is one Termination
board per B-car of the marr ied pair,
and it is
located
in the electronic
equipment
locker.
3.3
AT0 SUBSYSTEM SIGNAL INTERFACE
This section
describes
the inputs
and outputs
for the AT0 subsystem.
The
inputs
are primarily
from the operator's
panel, auxiliary
relay panel, ATP
subsystem and secondary
relay panel.
The AT0 provides
output signals
to the
P & BRK Signal
Generator
and the Auxiliary
Relay Panel.
The inputs
and
outputs
are shown on Figure 3-6.
The details
of these interfaces
are shown by
schematic
4682C48 with specific
sheet number references
made herein.
3.3.1
Secondary
The voltage
input from
3.3.2
(CKT BKR) Panel
(4682C48,
Sheet
(+I
required
by the AT0 subsystem,
is
the car battery
via the secondary
relay
Operator's
Panel
(4682C48,
Sheets
11)
28 Vdc to (+) 42 Vdc, as
(CKT BKR) panel.
7, 8)
Many manual inputs
to the AT0 subsystem are provided
by the operator's
panel.
A Mode Selector
Switch is located
on the operator's
panel in the A- and
When one of these switches
is in the AT0 position,
a signal
is
B-cars.
received
by the AT0 identifying
whether an A-car or B-car is the lead car and
An AT0 START pushbutton
will
initiate
that AT0 operation
is selected.
automatic
train
operation,
provided
the required
conditions
exist,
such as
Master Controller
Handle in FULL SERVICE BRAKE, Mode Selector
Switch in AT0
and door interlocks
satisfied.
Mode position,
Depressing
the AT0 STOP pushbutton
results
in an application
of full
service
brakes .by shutting
down the P & BRK Signal Generator.
At the same time an
input
signal
to the AT0 is grounded,
thereby
informing
the AT0 subsystem of
the AT0 STOP activation.
Depressing
the LOW RATE STOP pushbutton
applies
a signal
to the AT0 subsystem,
which results
in program stops which are at a lower rate than is normally
Selection
of low rate must occur before encountering
the marker
executed.
antenna.
BMPATO
3-4
0505M
i
Depressing
the PROGRAMSTOP CANCEL pushbutton
applies
a signal
to the AT0
subsystem,
which results
in cancelling
a program stop, allowing
the train
to
The cancel can be initiated
during program stop.
pass through a station.
Train length
and performance
(4682C48 Sheet 11).
3.3.3
Auxiliary
Relay
level
Panel
inputs
(4682C48,
are provided
Sheets
by thumbwheel
switches
7, 8)
The auxiliary
relay panel contains
relays
and contacts
which receive
and
transfer
signals
from and to the AT0 subsystem.
ZEROSPEEDcontact
closure
is
interpreted
by the AT0 subsystem as the train's
velocity
being at its
minimum.
A DOORS CLOSED contact
closure
indicates
all doors in the train
consist
are closed.
An AIR BRAKE RELEASE contact
closure
indicates
to the AT0
subsystem that the air brakes are fully
released
and full
power can be
When an EMERGENCYSTOP occurs,
a relay contact
is closed to inform
applied.
the AT0 subsystem.
Output signals
from the AT0 subsystem to the auxiliary
relay panel (via a termination
board) are an AT0 START INDICATION, which drives
a relay to indicate that the train
is ready to move; and a PROGRAMSTOP CANCEL INDICATION,
which when lit
indicates
a program stop is in progress.
This lamp is
extinguished
when a cancel is initiated.
3.3.4
Propulsion
& Brake
Signal
Generator
(ATO)
(4682C48,
Sheets
7, 8, 11)
The Propulsion
(P) & Brake (BRK) Signal Generator,
which is interfaced
with
the AT0 module, is a part of the AT0 subsystem.
The interface
signals
between
the AT0 module and the P & BRK Signal Generator
are the power/brake
mode
which commands propulsion
or braking
mode, and the P-signal
request,
signal,
which demands the amount of propulsion
or braking
effort
necessary
in the AT0
mode of operation.
The Propulsion
loop trainlines
& Brake Signal
via auxiliary
Generator
outputs
are transferred
relay panel interlocking.
to the P & BRK
vital
to the operation
of the P & BRK
In addition,
a 24 Vdc enable signal,
is interlocked
with the AT0 STOP pushbutton
on the
Signal Generator,
operator's
console to initiate
direct
shutdown of the P & BRK signal
generator
during AT0 STOP action.
This 24 Vdc signal
is generated
by the P & BRK Signal
Generator.
Battery
voltage
power for the P & BRK Signal Generator
is provided
through
Keyswitch,
Master Controller,
Mode Select Switch,
and Door Interlock
relay
contacts
located
at either
the operator's
console or auxiliary
relay panel.
3.3.5
Vehicle
Mounted
Equipment
(4682C48,
Sheets
the
8, 11)
Vehicle
mounted equipment
is connected
to the AT0 module by a termination
This equipment
is the Program Stop Antennas (2) and a speed sensor
board.
The Program Stop Antennas provide
the AT0 module with signals
from
(axle #3).
the program stop markers and station
program stop tape.
The speed sensor
measures the actual
speed of the train
and feeds it back to the ATD subsystem.
BMPATO
3-5
0505M
ATP Subsystem
3.3.6
(4682C48,
Sheets
11, 14)
Battery
voltage
is supplied
to the ATP subsystem from the AT0 subsystem as a
source voltage
for a set of nonvital
relay contacts.
These contacts
in turn
provide
the AT0 subsystem with the proper speed commands (seven signals
from
In addition,
a VITAL UNDERseven separate
relays)
for automatic
operation.
which is an indication
of the train
operating
within
the allowed
SPEED signal,
tolerance
of the commanded speeds, is also provided
to the AT0 subsystem.
HARDWARE--
3.4
FUNCTIONAL DESCRIPTION
This section
presents
a functional
description
of the AT0 equipment
(AT0
module, printed
circuit
boards,
and the Propulsion
& Brake Signal Generator).
This equipment
interacts
together
as well as with the station
equipment,
to
achieve the desired
performance
of the AT0 subsystem.
Vehicle
3.4.1
AT0 Module
The vehicle
AT0 module provides
the intelligence
for the AT0 subsystem.
In
other words, input signals
from external
sources are examined by the AT0
The AT0 module
module and decisions
are made based on real time calculations.
contains
four printed
circuit
boards (Figure
3-7):
the Digital
Input and
Power Supply,
CPU, Input/Output,
and Program Stop Receiver.
Figure 3-8 shows
the interconnections
within
the AT0 module and connections
to external
The printed
circuit
boards are connected
together
by a common bus
circuitry.
structure
and are also miscelJaneousJy
hard-wired
together
to form a
These boards,
and the programmed
microprocessor
based control
system.
software,
coherently
operate to provide
the following
functions:
Start-Up
Logic
Tractive
Effort
Request
Automatic
Speed Regulation
(Jerk Limited
and AcceJ eration
Performance
Modification
Program Station
Stopping
(Full
and Low Rates)
The vehicle
AT0 module includes
diagnostics,
and maintainability
of the AT0 subsystem.
in detail
in Section
5.3.
which improves
These diagnostics
individually,
the functions
The foJ lowing paragraphs
describe,
printed
circuit
boards and the motherboard
of the AT0 module.
explanation
of the purpose of the termination
printed
circuit
3.4.1.1
Motherboard
(226P402602)
(Figure
Controlled)
the availability
will
be discussed
of the four
Also, an
board is given.
3-9)
The motherboard
contains
two parallel
rows of seven edge-type,
printed
circuit
board connectors
as previously
shown on Figure 3-4.
One row of connectors,
to form a standard
bus consisting
which is designated
"PZ", is interconnected
to be used solely
by the AT0 equipment.
The
of data addresses,
power, etc.,
other row of connectors,
designated
"Pl",
is used for miscel J aneous
input/output
signals
to and from the AT0 equipment
(such as speed commands,
BMPATO
3-6
0505M
analog P-signal
request,
etc.).
dropping
resistors
for digital
3.4.1.2
Digital
Input
and 3-111
In addition,
input signals.
and Power Supply
Board
the motherboard
(226P406602)
contains
(Figures
3-10
The primary
function
of the Digital
Input and Power Supply board (XAJ) is to
supply all other printed
circuit
boards internal
to the AT0 module with JOW
level
dc operating
voltages,
so that these boards meet the specified
performance
at an input voltage
of (+I28 to (+I42 volts
dc.
A switching,
stepdown converter/inverter
circuit,
which operates
from 24 to 42 volts
dc,
produces +5 V (regulated),
+J8 V, -18 V, +12 V, -9 V (unregulated),
and 0 Vdc.
This board also provides
the system's
CPU with 24 digital
inputs,
from a high
voltage
source (such as AT0 Mode A/B Car Lead, AT0 Start,
etc.).
The inputs
are optically
isolated
from internal
circuitry,
and are divided
into three
groups of eight,
which include
three separate
commons.
In addition,
this
for manual inputs
Section
5.3.2.
board contains
three pairs
to the CPU. These switches
of hexadecimal
rotary
switches
are treated
in greater
detail
3.4.1.3
(22605JOGOZ)
and 3-13)
CPU Board
(Figures
3-12
in
The microprocessor
(XA9) of the CPU board obtains
instructions
which are
permanently
stored in the EPROM (XAJ-XA8) in order to operate.
Communication
occurs between the microprocessor
(CPU) and the EPROM via the address,
data,
When power is first
applied
to the board, the CPU (8080A)
and control
buses.
A reset causes the internal
program counter
of the
.is automaticaJ Jy reset.
instructed,
the CPU
CPU to point to address "OOOOH". Unless specifically
orders information
from consecutive
addresses.
The address output by the CPU
is decoded by decoders
(N6, N7) to enable operation
of only the-memory device
which has been preassigned
that specific
address to respond . The EPROM has
address by
been assigned
the addresses
OOOOH-3FFFH. It responds to a valid
unlatching
the data at that location
and placing
it on the data bus.
Temporary variable
data
written
to or read from
addressed
(7400H-77FFH).
is stored in the RAM (XAJO, XAJJ 1. This data is
on, when the RAM is
the RAM, depending on the instructi
52 for external
The address bus (upper 8 bits)
is brought
out to connector
The
upper
8
bits
(A8-A151
of
the
address
bus
provide
an abbreviated
access.
address, to establish
the path for off-board
data transfer
during an IORD or
Therefore,
A8-A15 are used as AO-A7 by devices external
to
IOWR operation.
the CPU board which are I/O mapped.
The data and control
buses are also
brought
out to the 32 connector
for access by external
devices.
The control
bus is generated
by a System Control Jer and Bus Driver
(N4).
The control
bus
consists
of the following
signals:
MEMRD, MEMWR, IORD, and IOWR. These
signals
control
the direction
of data flow between the CPU and other devices.
BMPATO (FEBRUARY 1984)
3-7
0505M
The instructions
(software
programs)
for the CPU are basically
executed
two
The first
method is by executing
a set of instructions
different
ways.
The other method is executing
a set of instructions
continuously
in a loop.
The signals
of the latter
approach are referred
to as
when signaled
to do so.
interrupts
because they may interrupt
at any time the programs executed
in the
Interrupts
are received
by the detection
circuit
components
continuous
cycle.
The inputs
of the detection
circuitry
are normally
at a logical
(NlO-NJ5).
They are preset by addressing
the decoder (NJ61 which selects
the
high level.
proper input to be preset.
When a pulse is input to the circuitry,
the
falling
edge of the pulse is detected
and an output
bit is set high
corresponding
to the interrupt
detected
(INTJ-INT7).
The Priority
Interrupt
Controller
(NJ91 prioritizes
the interrupts
if more than one occurs
simultaneously.
It then outputs
a signal
to a Flip-Flop
(NJ51, which latches
the signal
and interrupts
the CPU.
There are three Programmable Communication
Interfaces
(PCIJ) which transmit
and receive
data in serial
format.
Data which is opto-isolated
(OCJ-OC3), is
received
by the PCI, which interrupts
(RxRDY) the CPU indicating
that data
(transformed
to paral Jel format)
is ready to be read.
The transmitter
operates
in a similar
manner.
The CPU sends data to be transmitted
to the
PCI, which transmits
the data serially
via output
drivers
(QZ-Q4) and
interrupts
(TxRDY) the CPU when it's
ready to transmit
more data.
The PC1 is
reset in software
via output
port N22.
The CPU Board Programmable
Interval
Timer
These clocks are used in counting
clocks.
(PIT11 is used to generate
real -time
and event keying operations.
The power supply for the CPU board consists
of 7 separate
voltages.
Four
from the 52 bus.
The other
voltages
(+J2 V, +5 V, 0 V, -9 V) are received
three voltages
(+18 V, +5 V, 0 V) are received
from the Jl bus.
The latter
three voltages
are on the 31 bus mainly to isolate
the related
circuitry
(PIT,
PCIs, etc.)
from the remaining
circuitry
on the board.
3.4.1.4
Program
Stop Receiver
Board
(226P448)
(Figures
3-14,151
This board (location
XA5) functions
to supply the system's
CPU with
information
that indicates
how far the train
has traveled
in a Program Stop
The board receives
7.07 KHz frequency
signals
from the
mode of operation.
Program Stop antennas on either
side of the lead B-car rear truck.
These
signals
are received
on two channels
(A and B) and are phase related
(in-phase
or out-of-phase)
based on position
relative
to the wayside antenna loops.
The
filtered,
amplified
and compared on the Program Stop
signals
are isolated,
Receiver, board to develop three signals:
0
A pulse that indicates
inch increment
of train
0
A signal
present
(ACTIVE) that goes low to indicate
on at least one channel.
that
the frequency
is
0
A signal
present
(VALID) that goes high
on both channels.
that
the
is
BMPATO (FEBRUARY 1984)
each phase reversal
of channel A and B (six
travel
on a Program Stop tape).
3-8
to indicate
frequency
0505M
Signals
from both channels
of the vehicle
Program Stop antennas are applied
to
transformers
T2,T4 or T3,T5 on the Program Stop Receiver board.
Transformers
T2 and T3 are associated
with one channel
inputs
from either
side of the
train,
and transformers
T4 and T5 are associated
with the other channel inputs
from either
side of the train.
Circuitry
for both channels
operates
in the
same manner.
In a typical
channel,
the signal
from the transformers
(e.g.,
T2 or T3) is
fed into an operational
amplifier
(e.g.,
OA3-C) through either
R68 or R67,
depending
on which side of the train
is receivino
the wayside generated
7.07
KHz signal.
s a low-bass
filter
with a gain of'
The operational
amplifier
JO:1 at 7.07 KHz. The cutoff
frequency
for this circuit
is determined
by R125
and C24.
a gain enhancement for the low pass
Resistors
R65 and R66 provide
filter
that is equal to the value ((R65 R66)/R65).
s passed to a commutating
filter
From the input
transformer,
the signal
consisting
of N4,N5,NJO,NCl,FF5
and R70. These components,
except for R70,
are common to both channels.
Crystal
Y3 and components R71,R72,C32,C33
and N5
are combined in a crystal
oscillator
circuit
resonant
at 311.04 KHz. Device
NJ0 is a divider
that reduces the frequency
by a factor
of 11.
The resultant
frequency
on pin 2 of NJ0 is 28.28 KHz. This frequency
is further
divided
(in
two steps)
via flip-flop
FF5.
The output
of NlO, pin 2 is applied
to FF5,
which is set up as divide-by-2
circuits.
In the first
division,
the frequency
applied
to FF5, is reduced to 14.14 KHz, available
on pin 2.
In the second
division,
a frequency
of 7.069 KHz is provided
from pin 12 of FF5.
Both
frequencies
developed
by FF5 are applied
to multiplexers
of device N4. N4
contains
two muJ tiplexers,
one for each Program Stop channel.
Pin 13 of N4 is
connected
to pins J2,14,15
and 11 when switched
by the clock signals
at pins 9
Pins
12,14,15
and
11
are
sampled
at
the
7.069
KHz
rate.
When
the
and 10.
specific
pin is sampled, R70 is placed in series with one of the four
developed
is also available
at pin 13 of N4.
capacitors
in NCJ. The signal
The function
of the overall
circuit
is to provide
a bandpass filter
centered
around the switching
frequency
of 7.069 KHz. The signal
at pin 13 of N4 will
be a sample (squared)
signal
of the actual
phase changing
Program Stop signal
received
by the vehicle
antennas.
The input/output
for the other Program Stop
channel is pin 3 of N4.
The signal
is then sent through a high and low pass filter
to smooth the
The high pass filter
consists
of capacitor
results
of the commutating
filter.
consists
of OA3-D which has a gain of 9.3.
The
C25. THe low pass filter
The signal
is then applied
to OA3-A,
smoothed output
of OA3-D is a sinewave.
a Schmidt Trigger
with little
hysteresis
in voltage.
This device sauares-up
the sinewave so that N6-C can accurately
compare the phases of the two Program
N6-C extracts
the phase changing event (frequency)
from the
Stop channels.
The output of N6-C is then filtered
by R81 and
carrier
frequency
(7.07 KHz).
C30 to eliminate
the carrier
frequency
(7.07 KHz) before being applied
to
another
trigger
circuit.
BMPATO (FEBRUARY
1984)
3-9
0505M
The signal
from N6-C is present
at test point B as a fairly
well formed square
wave that is half of the crossover
(phase reversal)
freauency.
This signal
is
applied
to Schmitt
Trigger
OA3-B which sauares up the crossover
waveform.
The
square wave passes through a pulse-producing
circuit
consisting
of R84,C31 and
Although
the square wave is connected
directly
to pin 1 of N&A, it is
N6-A.
also connected
to pin 2 through
a de1 ay circuit
composed of R84 and C31.
N&A
will
provide
a low (inactive)
output when both input pins (1 and 2) are high
However, when inputs
signals
are different
(one input hiqh
(active)
or low.
and the other low) the output of N6-A becomes active
(high).
Because of the
delay circuit,
a pulse will
be produced for each change of state occurrina
at
the input of N6-A.
The resulting
siqnal
from N6-A is a train
of 15 volt
pulses'with
each pulse indicating
a change between the two input signa IS.
Resistor
R85 level
shifts
this pulse into a 5 volt pulse for the circu itry
of
circuits
of N3 are used to buffer
N6-A from f lip-flop
N3. Two inverter/buffer
FFJ provides
a square wave that is half of the
FFJ and external
application.
This souare wave is used to drive LED 5 in order to
crossover
frequency.
indicate
that crossovers
are occurring.
Note that al J voltges
from the input transformers
to OA3-A and OA4-A are
referenced
to +7.5 volts
provided
by voJ tage divider
components RJ15 and
OA4-B provides
the current
drive
for this reference.
RlJ6.
The ACTIVE output
signal
is developed
from sinewave signals
from OA3-D and
These signals
are summed through
diodes CR13 and CR14 and applied
to
OA4-D.
When the 7.07 KHz is sensed on either
or both channels,
a
charge pump OA5-A.
developed
voltage
is developed
across capacitor
C42. As long as the voltage
across C42 is greater
than the 1.05 volt threshold
voltage
of OA5-A (set by
resistors
RJ08,109),
the output of OA5-A (pin 1) will
go to +JFi volts.
The
signal
levels
at test points
A and C must therefore
be at least 2.1 volts
peak
to peak in order to charge C42 sufficiently.
Resistor
Rlll
provides
level
shifting
to 5 volts
for protection
of N3, which is the output buffer/inverter
Note that the univerted
ACTIVE signal
is the data
for the ACTIVE signal.
input for flip-flop
FFJ of the VALID signal.
The VALID output
signal
is also developed
from the outputs
of OA3-D and
However, in this case, the output
of OA3-D is used via diode CR12 to
OA4-D.
The output of OA4-D is used via diode CR15 to charge C43. When
charge C41.
C4J gets charged above 1.05 volts,
the output
of OA5-C pin 8 is driven
to +15
THe same thresh01 d is required
of C43 before OA5-B is driven
high.
In
volts.
level
of channel A (as
order to toggle
the clock input of FFJ, the signal
represented
by OA5-C conducting
+15 volts)
and the signal
level
of channel B
(as represented
by OA5-B conducting
+15 voJ ts) must sum together
to provide
enough drive
through
resistors
RllO and R112 to provide
+5 volts at pin 6 of
When this occurs,
a VALID (both channels
active)
signal
is provided
on
FFJ.
the output
(pin 1) of FFJ, if the ACTIVE input to FFJ was present
prior
to the
The output of FFJ is applied
to LED 4, which lights
to
clocking
of FFJ.
indicate
that no VALID signal
is present
and extinguishes
to indicate
that the
The output
of FFJ is also buffered
by N3 (E and F)
VALID signal
is present.
before being supplied
as an external
signal
for the CPU Board.
BMPATO (FEBRUARY 1984)
3-10
0505M
3.4.1.5
Input/Output
Board
(226P438603)
(Figures
3-16 and 3-17)
The Input/Output
(I/O) board of the AT0 Module buffers
and gates analog and
digital
signal
information
being applied
to the AT0 Module.
In addition,
the
I/O board generates
analog and digital
signal
voltages
for indication
and
propulsion
control.
Digital
inputs
are applied
to semiconductor
devices called
Programmable
Peripheral
Interfaces
(PPIs).
Digital
inputs
to the I/O board (PPI-3)
comprise the following
Program Stop signals:
PS ACTIVE
PS VALID
PS RT (A) ANT FAILED
PS RT (B) ANT FAILED
PS LT (A) ANT FAILED
PS LT (B) ANT FAILED
Digital
outputs
are generated
These outputs
include:
by the same PPI then
amplified
for
VMOS output.
AT0 START INDICATION
PS CANCEL INDICATION
ZBRAKE
Analog inputs
to the I/O board include
the regulated
voltages
of the Digital
These analog inputs
are multiplexed
by N8 and
Input and Power Supply board.
converted
to a digital
value by AD1 before being input on PPI-3.
Analog input
polarities
are determined
by OA5 and applied
to PPI-2
A CPU reset signal
TOGGLE RESET is controlled
by a digital
output of PPI-1
This signal
is applied
to a Toggle Reset circuit
so that if the reoccurring
digital
output is lost,
the CPU will
automatically
be reset.
PPI-1 also
provides
digital
outputs
which drive diagnostic
LEDs mounted on the I/O board.
I
The sole analog output of the I/O board is the P-SIG REQ. It
PPI-2 as a digital
tractive
effort
request which is converted
value by a converter
device
(NlO), then amplified
and buffered
amplifiers
(OAZ-B&A).
is generated
by
to an analog
by operational
The Speed Sensor signal
is applied
directly
signal
is developed
and applied
to PIT-l.
information
on the data bus.
where a gating
tachometer
3.4.1.6
Termination
Board
to the I/O board
PIT-l
then places
(226P454608)
The Termination
board connects
the AT0 equipment with external
equipment
such
tachometer,
and the operator's
console.
This
as the Program Stop Antennas,
board (Figure
3-18) contains
filtering
networks which provide
current
and voltage
regulation
for the AT0 equipment.
limitation,
noise suppression,
BMPATO(FEBRUARY 1984)
3-11
0505M
Two terminal
strips
(18 terminals)
connection
and disconnection.
3.4.2
Propulsion
& Brake
The AT0 P & BRK Signal
Generator,
is described
Manual.
Signal
Generator,
in detail
are mounted
Generator
on this
board
to simplify
board
(ATO)
as well as the manual P & BRK Signal
in Section 4-17 of the Heavy Maintenance
The AT0 P & BRK Signal
Generator
receives
a -2 to -10 Vdc analog propulsion
request
from the AT0 module.
In addition,
the AT0 module supplies
a propulsion/braking
mode signal
to the AT0 P & BRK Signal Generator.
The AT0
P & BRK Signal Generator
provides
a trainlined
P-Signal
between 0 and 100 mA,
and a trainlined
BRK Signal
of either
0 or 100 mA to collectively
determine
the tractive
effort
or brake rate imposed throughout
the train.
3.5
SOFTWARE--
GENERAL STRUCTURE
The software
of the AT0 subsystem is executed
in the microprocessor
of the AT0
It consists
of independent,
sequential
programs which are interrupt
Module.
These programs (computer
instructions)
use volatile
memory space for
driven.
as detailed
on the Memory Map, Table 3-l.
The memory map is
variable
storage,
divided
into 256 hexadecimal
address locations
(OOH-FFH).
Each location
which
contains
usable information
is identified
with a mnemonic derived
from its use
or an indication
of its function.
Information
in each location
is described
in Table 3-2 and can be accessed either
by mnemonic name or temporary
memory
location.
The programs of the CPU provide
output or require
are processed.
The input and output .ports which
identified
in Table 3-3, along with the specific
The address assigned
to each port is
of a port.
number at the top of each column in Table 3-2.
input information
as they
transfer
this information
are
use of each of the eight bits
included
as a hexadecimal
As an additional
aid, Tables 3-4 and 3-5 have been added to simplify
converting
hexadecimal
(base 16) numbers (e.g. A9) to decimal (base 10) or
Hexadecimal
numbers are identified
by an "H"
binary
(base 2) values.
designation
succeeding
each number (e.g.,
A9H).
Both Table 3-4 and Table 3-5 provide
sufficient
information
(decimal
and binary)
numbers to hexadecimal
values,
should
Various terms used throughout
this
The reader should familiarize
3-6.
manual are identified
himself
with these
To accomplish
efficient
utilization
of the microprocessor,
divided
among several
tasks.
These tasks are independent,
which occur asynchronously.
Hence, an interrupt
structure
and execution
time is developed
(Figure
3-19).
to convert
that be necessary.
and defined
in Table
terms and definitions.
its activity
is
sequential
programs
based on priority
Interrupt
#0 is a fixed
interrupt
which causes execution
of RST 8 routines.
Upon power-up,
all programmable
integrated
chips are reset.
The initialization routine
is entered
after
a power-up reset (see Section
3.5.1).
I
BMPATO (FEBRUARY 1984)
3-12
0505M
L
Interrupt
#l, which causes execution
of RSTl routines,
priority
of all remaining
interrupts.
It is a Program
is serviced
when valid
Program Stop Antenna crossovers
Section
3.6.3).
has the highest
Stop interrupt,
which
are detected
(see
Interrupts
#2 and #3, which cause the executions
of RST2 and RST3 routines,
respectively,
are reserved
for the serial
link receiver
and serial
link
transmitter
interrupts.
Interrupt
RST2 is activated
only when the Portable
Test Unit (PTU) is applied.
Interrupt
#4 is a Speed Control
interrupt
which causes the execution
of RST4'
routines.
It is serviced,
every 27.27 ms. The Speed Control
service
routine
is divided
into several
subroutines
in order to accelerate,
speed maintain,
and decelerate
the vehicle
in the most effective
manner.
(See Section
3.6.2.)
Interrupts
#5 and #6 are spares.
Interrupt
#7, which causes the execution
of routine
RST7, instructs
the CPU to
jump to location
Ok?H. This provides
the computer with a software
reset
whenever the instruction
FFH (stored
in EPROM) is encountered.
All unused
portions
of EPROM are programmed with FFH.
L
Memory map and I/O assignment
sheets are maintained
for ease in
troubleshooting
software.
See Tables 3-l and 3-3.
Memory maps enable the
user to see where particular
data is stored,
for monitoring
(see Section
5.3.2)
and troubleshooting.
I/O assignments
sheets list
the hexadecimal
assignments
of all input and output
signals.
3.5.1
Initialization
Routine
The initialization
routine
(Figure
3-20) starts
at memory location
@@OH in
immediately
after
power is turned on or when a CPU reset
EPROM. It is entered
After disabling
all interrupts,
it initializes
the stack pointer
occurs.
Several memory locations
have been reserved
(blocks
1 and 2 on Figure 3-20).
(block 3 on Figure 3-20) for directing
control
to other memory locations,
This area is only entered upon
which contain
routines
to service
interrupts.
A PROM page test is performed
(block 4) to verify
all
receiving
an interrupt.
EPROMSare inserted
in the proper sockets and are all of the same job (i.e.,
If the job test is failed,
the Mini-Monitor
of the I/O
Miami or Baltimore).
If the PROM position
test is failed,
the MiniBoard will
flash on and off.
Monitor will
flash at a high frequency,
causing a dim-lit
appearance.
Also, in the initialization
routine
a check is performed on RAM (block 5), and
if the results
are satisfactory,
it is cleared
(see Section
3.5.1.1).
All
programmable
integrated
circuit
chips (PPIs, PITS and PCIs) are initialized
after
the RAM has been checked (blocks
6 and 7), then output
data is preset
Serial
links
are then initialized
(block 9),
and stored in memory (block 8).
and interrupts
are cleared
and initialized
(block 10).
The last step in the
initialization
routine
is to clear
the serial
link buffers
of data (block 11).
BMPATO (NOVEMBER1984)
3-13
0505M
3.5.1.1
Check and Clear
Memory (CACM)
CACM is a subroutine
(Figure
3-21) which is executed
in the initialization
The RAM is exercised
by writing
a prior
known pattern
(55H) (blocks
routine.
702 and 704) into a location,
then writing
another known pattern
(FFH) into
all location
above the present
one being tested.
Then the present
location
is
tested to see if the information
written
to it is still
there (55H).
If it is
ok, then another
pattern
(AAH) is written
to this location,
and the next
location
is checked as stated
above.
When all memory locations
have been
checked with pattern
55H, they should contain
pattern
AAH and memory is then
checked for this pattern.
If the memory is okay, then it is cleared
to OOH (block 706) and the process
is continued
through
the entire
memory, at which time the program jumps to
INITP (which initializes
all I/O ports).
If memory is not okay, the program
jumps to a subroutine
called
BRAM (bad ram).
When this subroutine
is entered,
the CPU board failure
flag is set, and the reset of the memory is checked.
The software
will
continue
normal operation.
3.5.2
Main Loop
The main loop (Figure
3-22) is composed of a number of call
statements
to do
housekeeping
programs such as CPU toggle
reset (TOGRS), checksum (CKSUM),
functional
diagnostics
(DIAG), monitor
diagnostics
(MONIT), and serial
link
Execution
of the main loop programs may be interrupted
at any
loader
(SLLDR).
time in order to perform a more important
task.
3.5.2.1
Toggle
Reset
When the CPU is running
through
its
changes state every time the toggle
normal programs,
one bit of an I/O port
reset function
is performed
(Figure
3-24).
A square wave is generated
from the I/O port and goes to a charge pump circuit
where the output
in turn is tied to the reset input on the CPU board.
The
toggle
reset function
is executed
at a rate such that the difference
between
If for some reason
two successive
executions
is no more than 40 microseconds.
the CPU doesn't
activate
this output
port,
the charge pump circuit
will
forcing
the CPU to jump to location
0000H.
generate
a reset pulse,
3.6
SOFTWARE--
FUNCTIONAL DESCRIPTION
This section
describes
what functions
of the AT0 subsystem are implemented
in
The key inputs
and outputs
of each routine
are presented
here so it
software.
is understood
where these inputs
are derived,
as they are mentioned
in the
individual
routines
discussion
(reference
Figure 3-24).
The SPEED COMMANDroutine
one present,
and outputs
routine,
Figure 3-24.
accepts a speed command, verifies
that there is only
the commanded speed to the AT0 VELOCITY REQUEST
The AT0 VELOCITY REQUEST routine
performs
the start-up
conditions
are satisfied,
as determined
from the inputs
BMPATO(NOVEMBER 1984)
3-14
logic
when the proper
-- AT0 Mode A- or
0505G
B-Car Lead, Doors Closed,
Emergency Stop, Air Brakes Released,
AT0 Stop, Non-O
mph Speed Command, and AT0 Start.
When the conditions
are satisfied,
an
indication
that it is okay to start
is output.
The ATP provided
commanded
speed is then sampled as part of the process of generating
a tractive
effort
The actual
tractive
effort
signal
may be modified
prior
to output by
signal.
performance
level
modifications
(PLl, PLZ) input at the operator's
panel.
The PROGRAMSTOP ROUTINE outputs
the PS velocity
limit
essential
to accurately
stop the vehicle,
as determined
by the PS Crossovers
and the PS Low Rate
Other inputs
important
to this routine
are PS Active
and Valid,
A- or
inputs.
B-Car Lead. and Train Lengths.
The PS Cancel eliminates
all PS velocity
requests
for a particular
station.
As a PS Cancel indication,
the Program
on the operator's
panel is extinguished
when th s condition
Stop indicator
is
true.
power or brake applicat
The SPEED MAIMTAINING ROUTINE requests
on and the
to maintain
speed, based upon the inputs
-- AT0 requested
amount desired
velocity,
actual
velocity
(plus wheel wear compensation),
performance
modified
acceleration,
and vital
underspeed.
3.6.1
AT0 Velocity
Request
The AT0 VELOCITY REQUEST routine
functions
were described
in the
these functions
are performed.
(Figure
previous
3-25) is entered
from RST 4.
Its
section.
This section
explains
how
The reference
velocity
is set equal to the speed command (block
performance
modification
number (PMNO) is input and checked for
The levels
of performance
adjustment
are as follows:
2 and 3).
Performance
Level
1
2
3
Speed Adjustment
Baltimore
100
75
50
Level
Mi ami
100
100
70
(%)
1).
The
a 0 (blocks
Acceleration
Adjustment
Level
Baltimore
Miami
100
100
50
100
50
50
(%)
Therefore,
if a B is encountered,
the PMNO is set equal to 1 (block 4).
If
the number is not 0, then the performance
modified
velocity
(VELPM) and
acceleration
(PMACC) corresponding
to that level
is calculated
(blocks
5-7).
The reference
velocity
(VELRF) is then compared to VELPM (block 8); and if it
is greater
than VELPM, it is set equal to VELPM (block 9).
Next, a check is
made to determine
if the mode of operation
is Program Stop (block lo), and if
not, the Program Stop velocity
(VELPS) is set equal to 255 (block 11) so that
when VELRF is compared to VELPS, VELRF is less and therefore
acted upon.
If
the PS marker flag is set, VELPS is compared to VELRF (block 12).
When VELPS
is less than VELRF, VELRF and VELAC are set equal to it.
Therefore
VELRF is
always equal to the lesser
of VELPM and VELPS (block 13).
Start-up
logic
(Figure
3-26) is entered
after
the reference
velocity
has been
determined.
It first
checks for zero speed (block 14).
AT0 can only be
initialized
when the train
is at zero speed.
Therefore
if the zero speed flag
is not set, this
indicates
the vehicle
is in motion and it will
not be
BMPATO (NOVEMBER 1984)
3-15
0505Cl
necessary
lead car
to determine
which
can only be changed
car is leading
(blocks
19, 20, and 23), since
at the end of a run, (i.e.,
zero speed).
the
If the Zero Speed input is high,
the Zero Speed (ZS) flag is set (block 14A).
For nonvital
vehicle
roll-back
prevention,
a check (block 148) is made to see
if the vehicle
is in motion (INMO).
If the vehicle
is not in motion,
the
program goes to Start-Up
Check 1 (STCKl).
If INMO equals 255 (vehicle
is in
motion),
a check is made to see if the vehicle's
speed is greater
than the
action
velocity
(block 14C).
If so, a very high probabgility
exists
that the
third
rail
power is lost and that the vehicle
will
eventually
roll
backwards.
If the speed is less than the action
velocity,
the program goes to Start-Up
Check 1 (STCKl).
If the zero speed is not high, then a check is made to
determine
if the CLTS (Clear-To-Start)
flag is set (block 15) to 255 and if
not, control
goes to Mode Check 4 (MCK4).
If CLTS equals 255, a timer (ZSTIM)
is initialized
(block 16) so that the Zerospeed signal
(from the ATP
Subsystem) reflects
a true zero speed condition.
This signal
(Zerospeed)
corresponds
to a value between 0 and 2.99 mph.
If the timer is not greater
than 3 seconds (block 17), program execution
continues
in a loop until
either
the timer expires
or the train
accelerates
above the ZEROSPEED threshold.
If the timer exceeds 3 seconds, the vehicle
commanded to brake mode with full
service
brakes applied
(block 18).
All
startup
conditions
must be reestablished
in order to return
to AT0 operation.
I
L'
I
is
Next, the lead car status
has to be determined.
If neither
the A- or B-car is
selected
(blocks
19 and ZO), the vehicle
will
not move, and program control
returns
to the main loop.
If the A- or B-car is selected
as the lead car,
then the proper bits are set and the doors checked (blocks
19, 23, 24, and 25
If both (which does not occur under normal circumstances)
or 20, 21, and 22).
A- and B-car lead are selected
(blocks
19 and 23), then the train
will
not
move until
only one is selected.
If the doors should open (block 26) any
time, or an EMERGENCYSTOP (block 27) or ~~
(block 28) occurs,
the brake
mode will
be set and the P-signal
set to 20 mA. If it is not CLTS (block 28A),
the Speed Command (SCMAN) is checked for being equal to 0 mph.
If SCMANM
If the doors are closed
equals 0 mph (block 38B), the brake mode will
be set.
and no emergency stop or mm
signal
is present,
no CLTS exists,
and the
Speed Command is not equal to 0 mph, then the AT0 start
indicator
(block 30)
is lit
(okay to push START button)
and the AT0 START INDICATOR (ASTRI) byte is
When the operator
sees the AT0 START INDICATION and presses
set (block 31).
the AT0 start
pushbutton
(block 29), then the ASTRI byte (which verifies
the
AT0 START pushbutton
is not held down constantly)
is checked (block 32).
If
the byte is not equal to 255, start-up
is prohibited.
If ASTRI does equal
255, the,byte
is reset to 9 (block 33), and the AT0 START INDICATOR
The vehicle
is then commanded to go to minimum power
extinquished
(block 34).
(blocks
35 and 36) to get the air brakes fully
released
(block 37).
When the
air brakes are fully
released,
the program jumps to the SPEED MAINTAINING
A delay is implemented
to allow the air brakes to be fully
released
routine.
If 3.5 seconds elapse after
the AT0 START pushbutton
is
(blocks
38 and 39).
depressed and the air brakes are still
not released,
then the vehicle
is
returned
to full
service
brakes (blocks
44 and 45), and all the initial
conditions
have to be satisfied
to start
the vehicle.
If at any time CLTS
equals 255 (block 28A), control
goes to the SPEED MAINTAINING routine.
BMPATo (N0v~MB~~i984)
3-16
0505M
Speed Maintaining
3.6.2
This
section
(Regulation)
describes
how speed maintaining
is performed.
The SPEED
is a software
implemented
velocity
servo-loop
which
best as an analog system (Figure
3-27).
It, uses the reference
from the AT0 VELOCITY REQUEST routine
and the actual
velocity
from the tachometer
to determine
a speed error.
MAINTAINING routine
described
velocity
feedback
can be
When the train
is accelerating
or decelerating
(3.0 mph/set.
maximum acceleration)
toward the commanded speed, the P-signal
is adjusted
between a maximum,
of 100 mA and minimum of 20 mA, depending
upon the magnitude of the speed
error.
The proportional
and integral
(PI) controller
decreases the P-signal
to compensate for speed variations.
After being
as the speed error
reduces,
jerk-limited,
this signal
is sent to the P & BRK Signal Generator,
whose
current
output
(20 to 100 mA in linear
response to the controller
request)
to
the trainlines
causes acceleration
or braking
effort
from the propulsion
or
braking
subsystems
respectively.
In speed maintaining,
the reference
velocity
in the power mode is set .67 mph
below the commanded speed (Figure
3-28) and in the brake mode 1.33 mph below
the commanded speed to establish
a nominal speed maintaining
band.
Due to
system inaccuracies
(hardware and software
limitations),
the speed maintaining
accuracy about the nominal value,
will
at best be + 0.33 mph. This speed
maintaining
accuracy
band will
nominally
fall
withTn a 3.0 mph band, and is
directly
dependent upon wheel wear compensation
which must be maintained.
This allows the vehicle
to speed maintain
with minimum power/brake
changeovers.
3.6.3
Program
Stop
Program Stop enables
the station
platform
in a smooth fashion.
the vehicle
(2 8.0 ft.
to come to a stop aligned
at the center of
99% of the time and + 5.0 ft. 95% of the time)
a train
traveling
at high speed detects
a wayside
In normal operation,
The marker is an indication
to the train
of the distance
to go to the
marker.
The
vehicle
now
operates
in
the
Program
Stop
mode
by
decelerating
platform.
in a preprogrammed
velocity-distance
profile
to reach the station
platform
tape at a predefined
velocity
and continue
smoothly and precisely
decellerating
to the final
stopping
point.
Program Stop markers provide
enhanced performance
over the discreet
slow down derived
from speed codes.
When 10 counts of a Program Stop marker tape are detected,
the computer
program (Section
3.6.3.2)
in the CPU of the AT0 Module will
generate
a di ital
output
(Input/Output
Board of AT0 Module) that will
light
the PROGRAMST0Iindicator/switch
on the Back Panel console
in the Operator's
Cab.
Once the PROGRAMSTOP indicator/switch
is lit,
contacts
of the switch are
If the PROGRAMSTOP
monitored
by the Digital
Input board of the AT0 Module.
switch is pressed while lit,
the AT0 Module will
receive
a positive
dc voltage
signal
(PROGRAMSTOP CANCEL), which it will
interpret
as an operator
request
BM~ATO (NOVEMBER1984)
3-17
0505M
to cancel Program Stop for the approaching
station.
The AT0 Module would then
ignore the platform
Program Stop tape and refer
to track speed codes for
passing thru the station.
Normal Program Stop functions
would be initiated
at.
the next station
marker tape unless the operator
presses the PROGRAMSTOP
switch again as described
above.
3.6.3.1
Program
Stop Antenna
Tape Function
The Program Stop platform
tape consists
of a transposed
pair of wires which is
mounted on top of the third
rail
coverboard
along the platform.
A 7070 Hz
signal
is transmitted
through
this tape.
The crossovers
(transpositions)
are
An antenna located
on the vehicle
(comprised
of four coils
one foot apart.
spaced six inches apart)
then receives
the carrier
frequency
as it passes over
the antenna tape and generates
phase changes in the carrier
frequency
for
every six inches traveled
by the train.
The Program Stop Receiver
board
detects
the phase changes and outputs
an interrupt
pulse to the computer for
every phase change.
These crossovers
are used as a measure of distance
to go
before being completely
stopped and are the basis for the selection
of a
reference
velocity
from the velocity
versus distance
profile
for the speed
maintaining
routine
to follow.
The marker is composed of the
in the marker indicate
to the
tape is encountered.
3.6.3.2
Vehicle
Software
same tape.
The number of crossovers
contained
train
how far it must go before the platform
Implementation
of Program
Stop
The Program Stop software
is composed of two routines.
One (Figure
3-29) is
called
the Program Stop Interrupt
Routine
(Restart
1).
It is acted u on when
The other routine
(Figure
3-30) is t t: e Marker
a 6 inch phase reversal
occurs.
This
routine
is
acted
upon
every
27.27
millisecond,
Program Stop Routine.
once crossovers
have been detected.
The Program Stop Interrupt
Routine uses phase reversals
(crossover
signal)
to
decode the marker lengths,
if over a marker,
or to determine
the location
of
Reference velocities
can then be selected
the train
along the platform
tape.
There are four Program Stop
and applied
to the speed maintaining
routine.
reference
velocity
profiles
(velocity
versus distance)
stored in the computer
These four profiles
are divided
into two sets.
One set is for a
memory.
deceleration
rate of 2.0 mph/set.,
and the other set is for a deceleration
Each set consists
of two indepented
profiles.
One is
rate of 1.5 mph/set.
calculated
from the marker to a stop in the center of the platform,
which is
The other profile
is for the distance
along
in distance
increments
of 10 ft.
the platform
tape, and it is scaled at increments
of 1.5 ft. until
the train
is within
21 ft. of a stop; then the distance
increments
are 0.5 ft. for each
All profiles
are generated
with a jerk rate of
PS reference
velocity
update.
2.0 miles per hour per second squared.
When the first
the Interrupt
10 counts (minimum marker length)
are detected
by the computer,
routine
will
light
the PROGRAMSTOP indicator
and energize
the
BMPATO (NOVEMBER1984)
3-18
0505M
associated
switch,
decode the number of cars in a train,
decide whether A- or
B-car leads the train,
and decode the brake rate requested
to stop the car.
After decoding these conditions,
the program will
ignore any changes in them
until
the Program Stop action
is complete.
The program continues
to count
successive
crossovers
to determine
overall
marker length.
If a number less
than the shortest
marker is encountered,
the Program Stop Service
Routine
assumes that noise and not an actual
wayside tape was encountered.
The
service
routine
then resets a13 Program Stop functions.
If a number greater
than the longest
marker is encountered,
the PS Interrupt
Routine assumes there
was no marker and the train
is now in the platform.
At this time the
appropriate
reference
velocities
will
be applied
to the Speed Maintaining
Routine.
Once the train
no longer senses the marker tape, the updated count
of crossover
is set as the marker length.
From this a distance
from the
marker to the platform
and the distance
the train
will
travel
to stop in the
platform
is determined.
During the time the train
is between the marker and
routine
will
not be executed;
however, the
the platform
tape, the PS interrupt
already
initiated
marker PS routine
will
continue
executing.
The Interrupt
Routine resumes execution
with the first
valid
crossover
as the train
reaches
Since the Interrupt
Routine has already
encountered
and
the platform
tape.
left
a marker,
it knows that this new crossover
is the platform
tape and
therefore,
begins determining
Program Stop reference
velocities
from the
At
any
time
after
the
first
crossover
from
the
marker,
or the
profiles.
platform
tape, the program monitors
the Program Stop Cancel button.
Based on
this pushbutton
must be energized
any time between the
operator
decision,
first
crossover
and the final
stop in the platform.
The program will
extinguish
the Program Stop Cancel Indicator
and will
also reset all Program
Stop functions
causing the train
to follow
track speed codes through
the
instead
of the PS reference
profiles.
In such a case,
approaching
station?
the train
will
initiate
the normal program stop functions
at the next marker.
The Program Stop Service
Routine is used to determine
the distance
the train
has traveled
between the marker and the platform
tape.
Using the actual
velocity,
the routine
calculates
the distance
covered.
The routine
updates
the speed, using the PS reference
profiles,
every 10 ft.
This slows the train
down to a velocity
that will
blend smoothly with the platform
PS reference
This routine
also monitors
the Program Stop Cancel Pushbutton
and
profiles.
The Program Stop
will
resist
the Program Stop function
as described
above.
Service
Routine is also used to reset the Program Stop function
after
the
First
it makes sure the train
is in the
train
has stopped in the station.
Next it checks the zero speed indication,
and then it looks for a
platform.
Not until
all three of these
restart
indication
provided
by the operator.
If the operator
stops the
indications
are met will
the program stop reset.
train
before the center of the platform
and then restarts
the train,
the train
will
not Program Stop in the center of the platform.
The train
will
proceed
to the next station
where it will
Program Stop, given there is no Program Stop
If
the
operator
stops
the
train
before he enters the platform
area,
cancel.
the train
will
perform its normal program stop functions.
The train
will
accelerate
towards the speed code within
that section
of track,
it will
then
blend into the PS reference
velocity
profiles,
and then start
to decelerate
Once a train
is at full
stop in a station
and has
and come to a full
stop.
the
Program
Stop
Cancel
Indication
will
be
been given a restart
indication,
BMPATO (NOVEMBER 1984)
3-19
0505M
turned off
crossovers
and the train
will
until1
the antenna
proceed out of the station
ignoring
is no longer over the tape.
all
other
Based on operator
decision,
if a low rate program stop is desired,
the low
rate stop pushbutton
(on the console)
must be energized
before the marker tape
is encountered.
The train
will
then stop in the platform
utilizing
the stored
velocity
versus distance
profile
for the equivalent
1.5 mph/set.
deceleration.
3.6.4
Serial
Link
The Serial
Link routines
are used to transmit
data between the AT0 Module and
test equipment
for the purpose of verifying
AT0 Module operation.
Certain
data is obtained
from CPU board RAM memory and is loaded into reserved
buffer
to the test equipment
for use by
space in RAM. This data is transmitted
computer programs located
in the test equipment.
Data is received
back from
test equipment,
but is not used by the AT0 Module.
Error checks are performed
by the test equipment
to ensure that these serial
links
are working properly.
Flags and counters
are set and in some conditions
the serial
links
are reset
and transmission
starts
over again.
The Serial
Link loader routine
(Figure
3-31) obtains
data from various
sections
of AT0 Module RAM and stores
this data in the buffer
for the Serial
The Serial
Link transmitter
routine
(Figure
3-32) outputs
Link transmitter.
the data to the Serial
Link by applying
correct
control
data to the hardware.
The transmitter
routine
also performs some error
detection
checks and will
reset the serial
link
if specific
conditions
develop.
The Serial
Link
receiver
routine
(Figure
3-31) receives
the data from the Serial
Link, strips
the control
data from the data string,
and stores
the data in the Serial
Link
error
detection
checks
receiver
buffer
in RAM. There are some additional
within
this routine,
but no Serial
Link reset is performed
in this routine.
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TABLE 3-5.
HEXIDECIMAL
VALUE
0
HEXADECIMAL/BINARY CONVERSION
BINARY
VALUE
EXAMPLES
0000
X
2
0001
0020
\1
e---
----
Binary
3
0011
4
0100
5
0101
F
7
Hexadecimal
\1
1111
J
7
0110
0111
0111
Binary
a
1000
9
1001
A
1010
0
2
Hexadecimal
C
1011
1100
\1
0000
i
0000
D
1101
E
1110
F
1111
Y
Hexadecimal
Display
1
6
B
Formula
Value
3
Display
Sample 1
Value
Value
Sample 2
Binary
Value
A typical
hexadecimal
entry would consist
of two hexadecimal
digits
(e.g. AA).
This same value is converted
to binary
form as two sets of four binary
digits
(1010 and 1010) with each set of four digits
representing
the corresponding
hexadecimal
value (x,y).
The sir;rples shown above demonstrate
the conversion
process from hexadecimal
values to binary
numbers.
The first
step in converting
an eight bit binary
value into a hexadecimal
number is to separate
the eight digits
(bits)
of the binary
value (e.g.
00011111) into two groups of four bits
(i.e.
0001 and 1111).
Each set of four
bits can then be converted
to a hexadecimal
value using the above table.
Substitution
of the respective
hexadecimal
value for each of the two groups of
bits
(i.e.
1F for 0001 1111) results
in the equivalent
hexadecimal
number.
I
BMPATO (FEBRUARY 1984)
3-77
0835M
TABLE 3-6.
OF TERMS
DEFINITION
TERM
I
DEFINITION
BIT
Abbreviation
of “Binary
Digit".
Each bit is a binary
unit of information
defining
either
of two states
(1
Eight bits form a byte or word.
or 01.
BUFFER
1.
An isolating
driven
circuit
circuit.
2.
A storage
device used to compensate for a difference in rate of flow of information,
or time of
occurrence
of events,
when transmitting
information from one device to another.
circuit
used to avoid reaction
in a
caused by a corresponding
driving
BYTE
A sequence of eight adjacent
binary
digits
(bits)
operated
The bits of a byte have increasing
signiupon as a unit.
ficance
and can mathematically
be represented
as powers
of the base 2 from 0 through
7. The total
number of bits
in a byte is the sum of all the powers of 2 in the byte.
CENTRAL
PROCESSING
UNIT
The unit of a computing
system that controls
interpretation
and execution
of instruction;
arithmetic
logic
unit.
COMPLEMENT
Reverse all binary
bit
zeros become ones).
DEBUG
Detect,
locate,
hardware.
HARDWARE
Physical
electronic
INTERRUPT
A request
for
to the CPU.
MICROCOMPUTER
A computer system with a microprocessor
plus the
memory and interface
capabilities
necessary
for its
operation
to perform calculations
and specified
information
transformations.
The system is small since
the processor
function
is one or a small number of
chips,
hence, the term microcomputer.
MICROPROCESSOR
A data processor
using large scale
on one or a small number of chips.
BMPATO(FEBRUARY1984)
values
and correct
equipment,
devices.
service
3-78
the
includes
(ones
become zeros,
problems
in a program
mechanical,
generated
electrical,
or
by a device
external
integration
or
(LSI)
0835M
TABLE 3-6.
TERM
DEFINITION
OF TERMS (CONT'O)
DEFINITION
MNEMONIC
A short symbolic
representation
tions designed to allow easy
function
represented.
MONITOR
Software
operation.
NIBBLE
A sequence
a nibble.
a nibble.
PORT
An access to a device or network through which energy
or data may be supplied
or withdrawn,
or where device
or network variables
may be observed or measured.
REGISTER
A hardware
information.
element
capable
ROUTINE
A set of instructions
specific
task.
that
SCRATCH PAD
The term applies
tc memory that is used temporarily
by the CPU to store partially
processed information.
SOFTWARE
routines,
programing
Computer programs,
systems procedures,
and documents which
define
the operation
of the computer.
WORD
A unit of data that can be stored in a single
In this case, a word is
addressable
memory location.
eight bits.
or hardware
that
of machine
identification
observes
instrucof the
or verifies
system
of four adjacent
bits,
or half a byte,
A hexadecimal
digit
can be represented
3-79
of temporarily
causes
is
in
storing
the CPU to execute
a
languages,
direct
or
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LEVE
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FIGURE 3-5.
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BMPATO (FEBRUARY 1984)
PRiNTED CIRCUIT BOARD OUTLINE
3-85
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BMPATO (FEBRUARY 1984)
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AT0 SIGNAL
3-86
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2
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AT0 STOP
EXERG. STOP
ZEROSPEED
DOORSns.
AIR BRAKE REL.
PC BOARDS
4
'I
SPEED CO?lXMDS
VITAL UKDERSPD.
B+
B-
- DATA BUS
) 226P406
+
+
FIGURE 3-7.
BMpATO (FEBRUARY 1984)
- ADDRESS BUS
AT0 MODULE BLOCK DIAGRAM
+
>
+
-_ - _ _ _ _ - - _, -_I
$3
1
SP
.-
P I
U-J
Ii
3
z
x
s
,---*
T.k
--
-
FROM OPFU.
CONTROL
PNL.
REF:
I
FIGURE 3-8.
BMPATO (FEBRUARY 1984)
2271D97 SUB 2
AT0 INTERCONNECTIONS
3-88
f-/o xc4
P/O
XM
TPS
r. \-- c
I,
r.
I
fr
\--
._ \;
-
_ \
.,
\-’
^
.
_
v,
\I
_
-
-1
7
,
-Y
v
I
\_
\-
.
2
-\
7_ \I
_
\
_ \
._ \I
_ \
7 I
\
-7
“L
_ \
v ,
-1
,.
-1
_ \
“”
_ -
_
-\
_
-7
7
I-/”
.r
.
-1
I,
_
\r’l
. .
-\
7,
-.
”
,\
7,
\
I
_
v
Tl_
\
I
I
_
7
\
I
_ \
. ,
e,
\
___
I
_ \
h
l-d
.-\
_ \
T ,
,‘-i
L<
-++--
,..
-4
Y
w”
REF:
BMPATO (FEBRUARY 1984)
Q,b XAb
\-
1x1
\
,
I
\,..A
. ..__I
‘,
\‘I
-‘.,‘_:
. ,.
,
‘:-
3
-
2
226P402 SH 2 SU6 12
FIGURE 3-9.
MOTHERBOARD
3-89
I
I
BMPATO (FEBI?UARY m4)
N
I
3-90
I
‘k
i
JZ
. ;
I
I
I I
111
I-
I.
AMI IX
---- ----!lYlxTd
REF:
FIGURE 3-11.
8
BMPATo (FEBRUARY 1984)
226P406 SHEET 2 SUB 14
DIGITAL
INPUT BOARD
3-91
I”
L
-
111I
!
-
-
BMPATO (FEBRUARY 1984)
3-92
-
!
.
4_I
L
-
-r
-I
E
r
C
I
I-
A.
BMPAT0 (FEBRUARY 1984)
I
an
Y
L
d
+
x
i
.
r
(FEBRUARY
1984)
I BMPAT0
-l-
3-94
05
>
Ln
4
+
XAI
wo
I
----
T
I I
CPU
bus1
BMPATO (FEBRUARY 1984)
. 1.
I 1-1
r
I
L-----AI----he..5Y.2.L
1
i;icGGl
I
I
-
G. 8
&NOTES
7. PIN
I’DOES
E;mB
NOT
EXlS
REF: 226P510,
SH 2 SUB 7
FIGURE 3-13A.
CPU BOARD SCHEMATIC
(SHEET 1)
3-95
tdUM/?tZU
r
_
I”“’
df7R4
dPRs
JPA6
!
!
GO3
!
GO4
-
-MRu 1 /
1 /
1 -
1 -
r/p/?91
,
dPR/OI
- m
I,I
II-I
1
JPR.- WI ,_
Ma;3
r/r../4
JPA/s
/
J/R/c
R
GO.2
E
/
/
u/I--I-l/i
t
TA0L
-
/
/
-
/
I
I
/
GO5
1
/
I
-
_
:/
/
/
II
!
I,
/
/
-
II
1
-lGl
-
;=-I
II/
.I
I
1I
L-
I
;
/
-
1
.
II
f
k
?‘
af
S
EZ
FIGURE 3-13B.
BMPATO (FEBRUARY 1984)
CPU BOARD SCHEMATIC
(SHEET 2)
3-96
I
+M7,827(27)
-------
’
-ymki
1 C&
T.OOKW
F
----------
l-x
--
1.omuF
--_--___-__
1 CJ3
-..
SL/
6ol~
ON
,?iF$gJ
38)AJb,RJU
39).&t,
83)
P
REF:
226P510 SH 4 SUB 7
FIGURE 3-13C.
BMPATO (FEBRUARY 1984)
CPU BOARD SCHEMATIC
(SHEET 3)
3-97
BMPATO (FEBRUARY
1984)
3-98
r
r
ClRCUlT
------
2
SAME
A5
C\RCLJ\T
WC.-30BDo,
q--J-Y---------------
r---------------
I
I
I--
---------
----------------A
----_------
---_
CIRCUIT
-------
3
(6.Q./42
SAME
AS
OUT)
-----
----
CIRCUIT
----._---
T
I
-----
---------__
-__-__-
--------~
I
L---------E-l--------
w
CIRCUIT
6
-1
=
clRcu\f
s
-__--__---------___
-SAME
A5
CIRCLIIT
5
---
--
1
tt-
I-------------------r-J
- - ---
r---------I
C\RCU\T
I
I-- ----
7
(GQ.
SAME
/ 4 2
-------------_
A5
CIRCU\T
- __.- __
1
5
W&Y)
- -‘Zj--
REF
BMPATO (FEBRUARY 1984)
I
226P448 SH 1
FIGURE 3-l 5. PROGRAMSTOP RECEIVER
BDARD SCHEMATIC
3-99
L
I-
I
-4
-
i
1
r
LI
BMPATO (FEBRUARY 1984)
3-100
r-l cd
I
L-
-r
-
r
r
c..
-
-
-
-
-
-
-
-
P
c
BMPATO (FEBRUARY 1984)
3-101
I
I tsvI
N-b- 3
8304
=
..r
Is
N2
8205
..
REF:
226P438 SH 2 SUB 16
FIGURE 3-17A.
BMPATO(FEBRUARY 1984)
I/O BOARD SCHEMATIC
(SHEET 1)
3-102
h ‘ A----
’
’
zz
Tjj
-_..
.
:
-_
._. . .
-
REF:
BMPATO (FEBRUARY 1984)
226P438 SH 3 SUB 16
I/O BOARD SCHEMATIC
FIGURE 3-17B.
(SHEET 3)
3-103
HSZS
FROM
RIGHT
f?S. ANT
CH. A
670,
(516)
-rB’
HS26
JPR 3
L’W
@.-.--<
I
T6i
I
1
.015UF
620.2vJ
(RTN)
-----+RZ
J PR4
US15
)
2
2
H25G
(SHLD)
9
Hl4G
n
3
3
(SIG)
HSZ7
4
620,
JPR13
ZW
0
----m
s
-r
Ii516
4
;Y c4
MS28
FROM
RIGHT
F?S. ANT.
cn.
.015UF
620,2U’
I
“,-------lR6f
JPR 14
H517
1
B
Ul6G
(SHLD)
H27G
”
u6
6
629
2W
JPR23
HSIO
j-m-)
7
I
-l
.015’JF
620,ZW
j-lx-)
FROM
LEFT
c7
JPR24
P, 5. ANT.
Cl-l.
A
HJOG
HZIG
b
”
9
9
JPR33
c_
;
620,2W
H523
-------f
IO
RIG
f
IO
--
620,2W
H524
FR0b-l
CJO
.015tJF
LEFT
JPP34
c-
$RiT-f
3
t/513
/T
II
II
p. 5. AN%
/i5/2
I-\
”
CH. B
H23G
\
TO AT0
S-TART RELAY
u/24
3
”
12
JPR43
JPR‘+/
HI29
12
JPR42
TO
es
CANCEL REw
a CR9
H/38
OV
A
I5
15
JPR5-3
HS07
(SK;)
”
C&------m11
16
c
ATO
JPR%
(R7-d
US08
MO6
0
17
17
SPEEO
SEN5OR
u07G
ASSEMBLY
d
(WLD)
f
”
IS
226
16
-- C/6
22OOhF
FROM
US05
P.454
GO8
FIGURE 3-18.
BMPATO (FEBRUARY 1984)
TERMINATION BOARD WIRING
3-104
HO5&
I8
RST
v
0
P
-0
e
v
RST 1
RST 3
POWER
ON
RESET
AN0
lNlTlALlZATlON
SERIAL
LINK
RX
SPEED
COMMAND
ROUTINE
RET
MLOOP
v
I
RST4
PROGRAM
fi
t
ENABLE
INTERRUPTS
t
MAINTAINING
CALL
TOGRS
t
CALL
MONIT
+
CALL
DIAG
t
CALL
TOGRS
t
CALL
CHKSM
t
CALL
SLLDR
I
INCREMENT
ERROR
COUNTER
CPU
L
SET
FAILURE
FLAGS
FIGURE
I
BMPATO (JEBRUARY)
3-19.
SOFTWARE
3-105
DESIGN
FLOW
CHART
STOP
I
Pr
P
1
L
!
BMPATO (NOVEMBER1984)
3-106
SET RAM
TOGGLE
POINTER
“TOGGLE
= 7400H
RESET”
I
TOGGLE
FAILURE
RAM
“TOGGLE
RESET”
FLAGS
POINTER
J
FIGURE
I
3-21.
BFIPAT~ (FEBRUARY 1984)
CHECK
AND
CLEAR
MEMORY
3-107
AND
BRAM
SUBROUTINE
t
ENABLE
INTERRUPTS
I
CALL
TOGRS
t
CALL
MONIT
t
FIGURE
I
BMPATO (FEBRUARY 1984)
3-22.
MAIN
3-108
CALL
TOGRS
CALL
CHKSM
CALL
SLLDR
LOOP PROGRAM
I
RESET
---CPU
CHARGE
PUMP
- --
DATA
I/O
ADDRESS
a I
FIGURE 3-23.
BMPATO (FEBRUARY 1984)
/
TOGGLE RESET
3-109
-
.
P.S. ACTIVE
b
P.S. VALID
b
P.S. CROSSOVER b
"A" CAR LEAD
b
"B" CAR LEAD
b
TLl
b
TL2
+
P.S. CANCEL
b
)
P.S. LOW RATE
PROGRAM
STOP
ROUTINE
P.S. CANCEL INDICATION
b
RESET
-1
7
P.S. VELOCITY
I
I
AT0 START INDICATION
I
AT0
VELOCITY
REQUEST
ROUTINE
I
SPEED
MAINTAINING
ROUTINE
P-SIG.
REQUEST
I
*
FEE/
BRR MODE
I
J VALID SPEED
COMMAND
L
I
a
ACTUAL VELOCITY
I
**70/70* MPH
fa! 58
_ 50/46
40/38
X1/28
12115
o/o
+
b
+
b
+
j
b
SPEED
SENSOR
SPEED
COMMAND
ROUTINE
NOTE: ** - SPEED COMMANDFOR BALTIMORE
* - SPEED COMMANDFOR MI.4MI
FIGURE 3-24.
BMPATO (FEBRUARY 1984)
SOFTWAREFUNCTIONAL BLOCK DIAGRAM
3-110
b
0
ATOVR
:
&$&+,
I
i=PMNO
4
t
VELPM=
PMVEL(i)
c
pMAcc=
PMACC (i)
I
I
YES
8
VELAC & VELRF
=VELPM
L
9
a
FIGURE 3-25A.
BMPATO (NOVEMBER 1984)
AT0 VELOCITY REQUEST ROUTINE (SHEET 1)
3-111
YES
10
11
YES
1
VELRF=VELAC=
MLPS
13
NO
FtGURE 3-258.
BMPATO (NOVEMBER 1984)
ATU VELOCITY REQUEST ROUTINE [SHEET 21
3-112
N
az
o-cn
.
I
FIGURE 3-26A.
START-UP
ROUTINE [SHEET 11
BMPATO (NOVEMBER1984)
3-113
DORCK
Q
t
NO
LIGHT
AT0 STARTaSET
INDICATOR 30
ASTR’
I
tA
FIGURE 3-268.
BMPATO (NOVEMBER 1984)
START UP ROUTINE (SHEET 2)
3-114
t A
TURN OFF AT0
STR. INDICATOR
I
+
PSIGl==GOMA
34
1 35
1’
t
41,
REST AS-l-RI
1
NO
Y CNT.
38
TURN OFF AT0
STR INDICATOR
I
42
BRKM2
I
DETERMINE
SPEED ERROR
-hi-
1 DISABLE
INTS ( 43
1
I
1
PSIG=PSlGl
=20MA
,
I
I
EXIT
ii
EXIT
0
FIGURE 3-26C.START-UP
BMPATO (NOVEMBER1984)
3-115
44
ROUTlNE (SHEET 31
1
L
I
BMPATO (FEBRUARY 1984)
I--
7
3-116
aNW8 'INIWW 'CldS *3'3dS
h
aNW9 'INIWW 'ads
lW3113ti03Hl
r
atw8 aem
II
I
I I
I I
I I
I I
I
I I
I I
I I
I I
I I
I I
I
II I
0
5
I
I
I
I
I
I I
0
0
4
h
.
I
3I
c3
6
r
I BMPATO ( FEBRUARY 1984)
3-117
3
I
I
I
I
1
I
FIGURE 3-29A.
PROGRAM
STOP
INTERRUPT
ROUTINE
(SHEET 1)
SI+~PATO (FEBRUARY 1984)
3-118
0
PSMRK
SET
PLATFORM
FLAG=1
MARKER
COUNTER
t
ADD DIST
OR 60 MPH
CALCULATE
DISTANCE
GO ON PLATFORM
FOR 58
MARKER
’
TO
wI
MARK
1
Q-
LIGHT
P.S.
CANCEL
INDICATION
MARK
GET P.S. REFERENCE
VELOCITY
FOR PROFILE
TABLE
USING DIST. TO GO
ADD DIST.
OR 40 MPH
4
FOR 36
MARKER
6
EXIT
SET
QI
TAPE
P.S. REFERENCE
VELOCITY
= 0
END
ADD DIST.
OR 50 MPH
SET TAPE FLAG = 1
OF MARKER
FLAG = 1 I
6
FOR 46
MARKER
PSTAP
EXIT
i;
FIGURE
I
3-29B.
BMPATO ( FEBRUARY 1984)
PROGRAM
STOP INTERRUPT
3-119
1
ROUTINE
(SHEET
2)
I
FIGURE 3-30A. PROGRAM STOP SERVICE
ROUTINE (SHEET 1)
BMPATO (FEBRUARY 1984)
3-120
Ui
2
E
BMPATO (FEBRUARY 1984)
I
3-121
SLLDR
0
GET DATA FROM
MEMORY
LOCATIONS
CONTAINING
DESIRED
AT0 DATA AND
LOAD INTO SERIAL
LINK BUFFER
I
I
77
RET
FIGURE
i
I
BMPATO (FEBRUARY 1984)
3-31.
SERIAL.
LINK
3-122
LOADER
ROUTINE
RECEIVED
?
YES
RESET
INTERRUPT
CHECK FOR
RECEIVING
A
POSSIBLE HEADER
STORE DATA IN
RECEIVER
BUFFER
GET DATA
FROM SERIAL
LINK RECEIVER
I
CHECK FOR
TRANSMISSION
ERRORS
CHECK FOR BEING
PAST END
OF BUFFER
I
_ YES
SET ERROR
DISREGARD
DATA
RECEIVED
AND
SET ERROR
CONDITION
NO
CHECK FOR
RECEIVING
TRANSMISSION
HEADER
BYTES
FIGURE
B3'iPAT0 (FEBRUARY 1984)
3-32.
SERIAL
LINK
3-123
RECEIVER
ROUTINE
V
RST3
GET TRANSMITTER
BUFFER POINTER
I
TRANSMIT
HEADER BYTES
OVER TRANSMITTER
LINK
I
SET ERROR
CONDITIONS
-
‘GET DATA FROM
TRANSMITTER
SERIAL
LINK
BUFFER
RESET
SERIAL
LINKS
TRANSMIT
DATA
OVER SERIAL
LINK
RET
e-
POINT
TO
BUFFER
r NO
FIGURE
I
BMPATO (FEBRUARY 1984)
3-33.
SERIAL
LINK’TRANSMITTER
3-124
ROUTINE
TABLE OF CONTENTS
TITLE
SECTION
PAGE IJO.
4.0
PREVENTIVE M4INTENANCE
4-1
4.1
AT0 MODULE CLEARING
4-1
4.2
WHEEL WEARADJUSTMENT
4-1
4.3
TERMINATION BOX INSPECTION
4-l
BMPATO
4-i
0506M
LIST OF TABLES
/
TABLE
4-1
TITLE
WHEEL WEAR COMPENSATION
PAGENO.
4-2
BMPATO
4-ii
0506M
4.0
L
PREVENTIVE MAINTENANCE
Preventive
maintenance
for the vehicle
borne AT0 equipment consists
of
periodic
cleaning
of the module and the adjustment
on an "as required"
basis
for vehicle
wheel wear.
Preventive
maintenance
for station
and wayside
equipment
consists
of periodic
inspection
of Program Stop termination
boxes.
4.1
AT0 MODULE CLEANING
Cleaning
of the AT0 module should not require
the disconnection
of any
equipment,
but rather
a light
cleaning
of the module exterior
and a vacuuming
of the module interior
performed on a yearly
basis.
Access to the module is
gained by opening the Lexan cover latches
and removing the Lexan cover.
4.2
WHEEL WEARADJUSTMENT
Wheel wear adjustment
should be performed
on an "as required"
basis.
Initial
wheel size should be determined
upon initial
vehicle
installation
and wheel
Periodic
wheel measurement,
taken in comparison with a
replacement.
Westinghouse
supplied
change in size standard,
will
determine
when wheel wear
adjustment
is necessary.
Wheel wear adjustment
is accomplished
manually
in
the AT0 module by adjustment
per the Westinghouse
standard
of the hexidecimal
rotary
switches,
as outlined
in the wheel wear compensation
chart
(Table 4-l).
4.3
TERMINATION BOX INSPECTION
Termination
boxes which connect Platform
PS Antenna or Marker PS Antennas to
cabling
from PS Transmitter
Assemblies
should be examined periodically
for
The examination
should also verify
seal integrity,
tightness
of
corrosion.
connections,
and the physical
integrity
of components and insulation.
Signal
levels
should be checked upon initial
installation,
verified
after
the first
year of use, and checked every three years thereafter.
BMPATO
4-l
0506M
TABLE 4-l.
WHEEL WEAR COMPENSATION
* As measured on axle 3 of the B-car.
3, 2, 1, 0 provide
** Switch positions
same response
BMPATO
4-2
as position
4.
0506M
TABLE OF CONTENTS
TITLE
SECTION
PAGE NO.
5.0
TROUBLESHOOTING
5-1
5.1
5.1.1
STATION AND WAYSIDE ATC
Termination
Box/Antenna
Checks
5-l
5-2
5.2
VEHICLE AT0
5-16
5.3
5.3.1
5.3.2
5.3.2.1
55'33*:*3
5:3:2:4
5.3.2.5
5.3.2.6
5.3.2.7
5.3.2.8
5.3.2.9
5.3.2.10
5.3.2.11
DIAGNOSTICS
Functional
Diagnostics
Monitor
Diagnostics
Failed
Board Indication
Memory Mapping
Input Port Data
Display
Tachometer
Display
Speed Command
Lamp Test
Train Simulation
Data
D/A Special
Scaling
BCD Display
Chart Recorder Calibration
Display
Wheel Wear
5-16
5-16
5-20
5-21
5-21
5-21
5-21
5-22
5-22
E;
5-23
5-23
5-23
5.4
CUSTOMERPROGRAMMING
5-23
BMPATO (NOVEMBER 1984)
5-i
050714
LIST OF ILLUSTRATIONS
FIGURE
TITLE
PAGE NC.
5-l
TRANSMITTER OUTPUT SIGNALS
5-24
5-2
CHECKSUMROUTINE
5-25
5-3
PC BOARD MOUNTEDMONITOR AND I/O DEVICE LOCATION
5-26
LIST OF TABLES
TABLE
L
I
1
TITLE
PAGE NO.
5-l
TYPICAL TRANSMITTER SIGNAL AND CABLE CONNECTIONS
5-4
5-2
SPEED REGULATION TROUBLESHOOTINGGUIDE
5-5
5-3
PROGRAMSTOP.TROUBLESHOOTING GUIDE
5-13
5-4
FAILURE FLAGS
5-19
BMPATO (NOVEMBER 1984)
5-ii
D507M
5.0
I
TROUBLESHOOTING
Procedures
for identifying
and correcting
faulty
equipment
in the Station,
Wayside and Vehicle
AT0 are outlined
in the following
sections.
AT0 subsystem
faults
should be corrected
using a remove/replace
approach.
Detailed
instructions on the use of the Portable
and Bench AT0 testers
for corrective
maintenance of the AT0 flodule are presented
in the applicable
manuals (BMPPAT and
BMPBAT). Refer to Tables 5-2 and 5-3 for speed regulation
and program stop
troubleshooting
guidance.
5.1
STATION AND WAYSIDE AT0
As a prerequisite
for wayside AT0 troubleshooting,
maintenance
technicians
should have basic electronics
experience
and be familiar
(Westinghouse
training)
with Program Stop equipment
operation.
They should also be
familiar
with basic test gear use (oscilloscope,
DVM, etc.).
The following
checks are made when equipment operation
is suspected
These checks are performed
in two basic procedures
which
improper.
The first
procedure
checks the source side of the system.
follow.
second procedure
checks the load (antenna)
side of the system.
as
The
a.
Program Stop Transmitter
Module and Transmitter
Assembly panel
LED indicators
are observed.
If the Transmitter
rlodule LEDs are
not energized,
it can be assumed that the Module has failed
or
other inputs
such as dc power or ac power are not present.
The
presence of these inputs
can be established
by observing
the
LEDs on the Transmitter
Assembly Panel.
If the dc and ac
indicators
on the Assembly are correct,
but the transmitter
indicators
are not, it can be assumed that the corresponding
Transmitter
Module has failed.
b.
Gain access to lower terminal
strip
TBA located
at the
the transmitter
assembly in the train
control
equipment
the affected
station.
rear of
room of
Power (120 Vat, 60 Hz) should already
be applied
to the
transmitter
assembly.
(Terminals
1, 2 and 3 of upper terminal
strip
TBA are the ground (GND), 120 VAC (BX 120) and 120 VAC
RETURN (NX 120) connections.)
The ac circuit
breaker
switch,
Sl
should be in the on (up) position
and the amber AC POWERandgreen DC POWERindicators
should both be lit.
The TX OUT 1 and
TX OUT 2 indicators
mounted on the Transmitter
Modules should
also be 1 it.
Using a Fluke 8060A DVM, measure 24 + 0.1 Vdc at
on the front
panel of the Transmitrer
assembly.
the test points
d.
Set up a portable
oscilloscope
for 20 volts
per division
sensitivity
and 50 microseconds
per division
sweep.
The scope
must be connected
to the signal
output and signal
return
lines,
but must remain floating
with respect
to earth ground.
Measure
the signal
output
to each antenna (TX OUT 1 through
TX OUT 4) by
connecting
the scope leads between the appropriate
terminals.
BMPATo (NOVEMBER 1984)
5-l
050711
(Refer to typical
wiring
Table 5-l and installation
drawirlss.)
The output
signal
waveform should be approximately
the same as
lrsiny the Fluke 8DbOA DV!l (or equivalentj,
shown in Figure 5-l.
set at 200 Vat input sensitivity
in the frequency
counter
mode,
and verify
that the frequency
of each signal
is 7.07 ktlz -+ 2 Hz.
e.
5.1 .l
If any of the waveforms are significantly
different
in shape or
magnitude
than Figure 5-1, a transmitter,
cable,
termination
box
transformer
or antenna load may have degraded.
An out-oftolerance
frequency
reading
indicates
that the respective
transmitter
is not operating
properly.
Remember that a corredt
signal
does not eliminate
the possibility
of an open circuit
in
cabling,
connections,
or the antenna itself.
Turn off the
transmitter
assembly by setting
the ac power switch Sl to the
off (down) position
and replace
the respective
module with a
known good one.
Repeat the checks of steps 2 and 3 above.
If
the signal(s)
are now OK, place the assembly in service
and
return
the faulty
module to WELCO for repair.
Termination
Box/Antenna
Checks
If the fault
persists
or cannot be remedied at the Transmitter
troubleshooting
should be continued
on the load end (antenna
circuit,
with the following
checks.
With the Transmitter
Assembly corresponding
and displaying
proper indication,
take the
a.
Clear
access
WARNING:
to the
track
to the
following
and wayside
Assembly,
end) of the
suspect antennas
actions:
powered-up
areas.
CONTACT WITH A ENERGIZED THIRD RAIL COULD RESULT IN DEATH
OR SEVERE ELECTRICAL SHOCk.
IF IT IS NOT POSSIBLE TO hAVt THIRD RAIL POWEROFF AT ThIS
TIME, THEN CO NOT TOUCH ANY TERMINATION BOX BEFORE
VERIFYING THAT NO VOLTAGE IS PRESENT ON THE bDX ChASSIS
WITH RESPECT TO THE RUNNING RAIL (GROUND RETURfuj. FAILURL
TO CHECK FOR THIRD RAIL VOLTAGE Oh THE BOX ClrULD ktSCILT IN
DEATH OR SEVERE ELECTRICAL SHOCK.
b.
Connect the Fluke 8060A DVM across Rl in the wayside Program Stop
termination
box that corresponds
to the transmitter
output
found to
be improper
in step e. (above).
Compare the RMS voltage
reaains
on
the DVM with the value recorded
on the System Test Data Sheet.
c.
If no voltage
is measured,
remove power from the transmitter
assembly.
Check the continuity
of the wiring
between the transmitter
assembly and the primary
winding
of the termination
box transformer,
Remove the wire connected
to terminal
1 of
using an ohmmeter.
terminal
strip
TBA and connect the ohmmeter between terminal
1 and
BlIPAT
(NOVEMBER1984)
5-2
05071~1
The resistance
value measured consists
mainly
the removed wire.
of the cable interconnecting
the transmitter
and termination
box
and will
be in the range of 2 to 28 ohms.
If an open circuit
is
found, check and correct
wiring
connections.
L
d.
If the RMS voltage
as measured does not match the Data Sheet within
20%, remove power from the transmitter
assembly.
Remove the wire
connected
to TBB-1 and connect an ohmmeter between TBB-1 and the
removed wire.
The ohmmeter should indicate
7 to 14 ohms for a platform
Program Stop
This value includes
4 ohms for the antenna resistance
and
antenna.
0.5 ohms for the transformer
impedance,
with the remainder
consisting
of the resistance
of the current
limiting
resistor
Rl.
For a marker
antenna,
the ohmmeter should read out approximately
the value of
resistor
plus 0.5 ohms for the transformer
impedance.
1.
L
If an open circuit
is found, check
connections
between the termination
antenna itself.
and correct
cabling
box and the antenna,
and the
2.
If a resistance
higher
than 14 ohms or the Rl resistor
value as
recorded
on the System Test Data Sheet is measured, connect the
ohmmeter across Rl with the TBB-1 wire off.
Check the
resistance
of Rl against
the value on the System Test Data
Sheet.
Adjust Rl as necessary
to the value given on the System
Test Data Sheet and connect the wire removed from TBB-1.
3.
Reenergize
the transmitter
and confirm
that the RKS voltage
across Rl as measured on the DVM is the same as recorded
on the
System Test Data Sheet.
L
BNPATO (NOVEMBER1984)
5-3
0507f.i
BMPATO (NOVEMBER1984)
5-4
0507M
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BMPATO (NOVEMBER 1984)
5-5
0507M
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5-6
0507M
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5-7
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0507M
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5-8
0507M
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5-10
0507M
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BMPATO(NOVEMBER1984)
5-11
0507M
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BMPATO(NOVEMBER1984)
5-12
0507M
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BMPATO(NOVEMBER1984)
5-13
0507M
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BMPATO (NOVEMBER1984)
5-14
0507M
BMPATO(NOVEMBER 1984)
5-15
0507M
5.2
VEHICLE AT0
The troubleshooting
concepts
for the Vehicle
AT0 are presented
below.
The
as used in the following
discussion
applies
to the assembly in
term 'logic"
The discussion
centers
around the theme of providing
optimum return
general.
to service
of a disabled
vehicle
while requiring
minimum specialized
knowledge
in areas such as microprocessor
operation,
digital
electronic
troubleshooting
or computer programming.
As a prerequisite
for vehicle
AT0 troubleshooting,
should have a good working
knowledge of the vehicle
interactions
(Westinghouse
training).
maintenance
operation
technicians
and subsystem
a.
If the vehicle
does not perform properly
in the automatic
mode, the
AT0 and/or Propulsion
Logic may be suspect.
If proper performance
is
not realized
in the manual or yard modes, the Propulsion
Logic only
may be suspect.
Propulsion
Logic can be eliminated
as suspect in
automatic
running
by verifying
its operation
in Manual.
b.
The fault
isolation
procedure
for the AT0 Logic is based on use of
the AT0 Portable
Test Unit.
This test unit will
allow monitoring
on
built-in
displays
while the train
is running
and also will
allow for
exercising
and monitoring
AT0 Logic without
the need for running
the
This is advantageous
because certain
inputs
to the ATO, such
train.
as various
speed commands and Program Stop signals,
are available
only on the main line and at stations.
In addition
to checking
the AT0 Logic Module, the Portable
Test Unit
will
also allow for monitoring
the AT0 P & Brake Signal
Generator
output signals
while simulating
Automatic
Speed Regulation
and
Program Stop.
5.3
DIAGNOSTIC
Diagnostic
programs can be implemented
in such a way as to aid in determining
The set of diagnostic
routines
hardware problems or software
malfunctions.
herein employed are aimed at both kinds of errors,
in order to diagnose the
operating
state of the AT0 module within
limitations.
5.3.1
I
Functional
Diagnostics
Functional
diagnostics
perform individual
checks on the printed
circuit
(PC)
boards located
in the AT0 module, except for monitor
board in XA7. The
positions
of the PC boards in the AT0 module are labeled
XAl through
XA7. The
8 LEDs (LED 4) located
on the I/O board are used to display
a PC board
If a board has been determined
as faulty,
the corresponding
LED on
failure.
a failed
board in position
XAl
the I/O board will
be turned on and off (i.e.,
results
in LED 1 being flashed).
Also, a failure
flag in temporary
memory may
be set, indicating
which device on a board is faulty.
Failure
flags are
LED 8 is used to display
the status
of the CPU. If
identified
in Table 5-4.
LED 8 is flashing,
then the CPU is executing.
The following
paragraphs
describe
how the boards will
be checked,
and in what sequence.
BMPATO(NOVEMBER1984)
5-16
G507M
These are a few diagnostic
type routines
that are not in the diagnostic
The static
ram test and EPROM position
test of the CPU board
routine
section.
are made first,
since in the initialization
routine
(Section
3.5.11,
its
memory is used to run all other routines.
A checksum routine
(below) tests
the EPROMand is called
from the main loop (see Figure 3-23).
Also, if a
false interruption
#5 or #6 occur,
the CPU board failure
flags are set.
If
any of these test fail,
LED 4 is flashed.
‘b
The digital
input and power supply
(01 & PS) board is checked first
in the
diagnostic
routine.
The spare inputs
on this board are grounded.
The ports
with the spare inputs
are read, and if a logical
"0" is not present,
a fault
is determined
to exist.
Another method involves
monitoring
the inputs
for
illegal
conditions.
These are conditions
that can't
exist
under normal
operation
of the vehicle;
for example,
a "0 mph" and "70 mph" speed command
present
simultaneously.
If input data indicate
both are present,
then there
is a problem,
and the 01 & PS board is diagnosed as bad.
A- or B-car lead end
performance
mode is also checked in this manner.
The power supply circuit
is
tested by readin
the +5 V, +18 V supplies
through the A/D converters
on the
I/O board.
If t 8 e voltages
are not within
tolerance,
the board is faulty,
the
digital
input failure
flag will
be set, and LED 1 will
be flashed.
using the concept of a feedback loop.
A
The I/O board is then checked,
digital
number is output
to a'D/A converter
which produces an output voltage.
This voltage
is fed back to the I/O board, which is digitized
by an A/D
converter.
The original
number which was output can now be compared to the
final
number received.
If the numbers don't match (within
tolerance),
a bad
board is indicated.
A final
check on the I/O board is to test the spare
ports.
Spare inputs
to these ports are
rounded.
The ports are read, and if
a logical
"0" is not present,
then a fau Bt is detected.
The dynamic ram is checked after
the Digital
Input and I/O boards,
in the
The dynamic ram test is performed by saving the contents
diagnotic
routine.
Then a value of 55H is
of a ram location
in the 8080A's temporary
register.
written
to the location
and read back to see if the value is still
55H. Then
a value of AAH is written
to the ram location,
and read back to see if the
value comes back incorrect,
the CPU failure
value is still
AAH. If either
After
the two checks mentioned
above are
flag is set and LED 4 is flashed.
complete,
the original
data is restored
to the location
from the temporary
The pointer
identifying
the location
to be tested
is then
register.
incremented
and program execution
is returned
to the main loop.
One ram
location
is checked for each call
of the CPU diagnostic
routine.
The Program Stop receiver
is only functional
in the program stop mode of
A check is made to verify
that a physical
connection
exists
operation.
between the vehicle
mounted Program Stop antenna and the Program Stop receiver
board.
This is done by monitoring
the antenna fail
diagnostic
outputs
of this
LED 5 is flashed
and PS failure
flag is set if an open circuit
exists
board.
between the antennas and board.
The PS valid
output
is a signal
which
indicates
that both channels
are being received
by the PS board from the
antenna.
The PS active
output
is a signal
which indicates
that at least one
L
I
BMPATO(NOVEMBER1984)
5-17
0507M
channel
is being received
by the PS board
present
and active
is not, then the board
flag is set and LED 5 is flashed.
I
I
I
I
If valid
is
from the antenna.
is faulty,
and again the PS failure
The checksum routine
(Figure
5-2) is used to check if the EPROM has changed
It subdivides
the memory into 256 byte blocks,
called
"pages".
with time.
The checksum is updated (block 2) each time the page is entered,
until
the
If the counter
is not at the end of a page, then
page is completed
(block 3).
the next memory location
is pointed
to, for the next time through
the loop.
ldhen the end of a page is encountered,
the result
is then compared to a stored
value,
which represents
the correct
sum for the page (blocks
3-7).
If the sum
for the current
page is correct,
then the checksum counter
is cleared
(block
8), and the program recycles
(block 4) until
all pages have been checked
(blocks
9 and lo),
at which time the page counter
is cleared.
If the sum is
incorrect
for a page, the program jumps to an error
subroutine.
The error
then continue
checking
the other
routine
will
log an error
in a counter,
If the error
persists
after
a second check, the error
routine
will
set
pages.
the CPU failure
flag (Table 5-2) and flash LED 4, then continue
checking
the
other pages, next call.
The purpose of failure
flags
is to aid in locating
a particular
area which has
In order to access this information
turn switch 2 (UI
caused a board to fail.
'1' and switches
3, 4, 5, and 6 to the positions
and PS board) to position
Monitor
the LEDs on the I/O board to find the
indicated
in Table 5-4.
failure(s).
BNPATO (NOVEMBER1984)
5-18
05C71J
TABLE 5-4.
A.
Input
Digital
& Power Supply
LED 8
LED 7
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
B.
I/O
Board
0.
Program
LED 8
LED 7
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
(Set
switches
to 7-4-2-7)
(Set
switches
to 7-4-2-8)
E
Spare on port 60H is high
A/D/ D/A Converter
failed
CPU Board
LED 8
LED 7
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
Board
+15 V Test Failed
-15 V Test Failed
+ 5 V Test Failed
A-car,
B-car lead simultaneously
Multiple
Speed Commands
PL2 and PLl bits both are low
Spare on port 3AH is high
Spare on port 38H is high
EL! ;
LED 6
LED 5
LED 4
LED 3
LED 2
LED 1
c.
FAILURE FLAGS
(Set
switches
to 7-4-2-9)
xx
Dynamic ram test failed
xx
Static
ram test failed
xx .
Interrupt
occured on RST5 and RST6
xx
Checksum failed
Stop Receiver
Board
(Set
switch
to 7-4-2-A)
xx
XX
xx
PS active
and valid
failed
PS RT-A antenna failed
PS RT-B antenna failed
PS LT-A antenna failed
PS LT-B antenna failed
CL
1
BMPATO(NOVEMBER1984)
5-19
050711
5.3.2
Monitor
Diaanostics
Monitor
diagnostics
aid in troubleshooting
the AT0 Module, by supplying
the
user with information
about how well the software
is working and which PC
in use.
board, if any, is malfunctioning
rlonitor
diagnostics
are available
as
part of the AT0 Module equipment
(I/O board binary
LED display
and 01 board
switches)
and software.
However, diagnostic
access and interpretation
is
enhanced by use of the Monitor
Module (Logic Monitor
Module).
This PC card
assembly (Monitor
Module) is inserted
in the XA7 slot of the AT0 Module with
power OFF.
CAUTION:
INSERTING OR REMOVING PC CARDS TO/FROM THE AT0 MODULE WITHOUT
REMOVING POWERAT THE ON/OFF SWITCH MAY RESULT IN BOARD OR MODULE
FAILURE.
The Monitor
Module provides
six pairs of hexadecimal
switches
and displays
to
act as a 6-channel
monitor.
The Monitor
Module also includes
an ancillary,
8-LED display
and a connector
for external
channel monitoring.
Display
pairs
to the left
of each switch pair indicate
the contents
of memory locations
dialed
up on the switches.
Additional
information
on this device is available
in the Logic Monitor
Module Manual (BMPBPB). More extensive
diagnostic
testing
of the AT0 Module can be accomplished
with the AT0 Portable
Test Unit
(PTU) or AT0 Bench Test Unit (BTU), as described
in their
respective
manuals,
BMPPAT and BMPBAT.
Monitor
diagnostics
are provided
through
the use of the hexadecimal
(hex)
rotary
switches
located
on the 01 and PS board, the eight LEDs (LED 4) on the
I/O board, and the six hex display
pairs and six hex switch pairs on the
Monitor
board when plugged in (Figure
5-3).
The to hex switch
SW 1 (01 and
PS), is used to make wheel wear adjustments.
SW 2 E I and PS allows the user
to select
the diagnostic
mode desired.
SW 2, 4, 5 and 6 (01 and PS) are used
for examining
the data stored at specific
memory locations.
Switch pairs 1
thru 6 on the Monitor
board (MB) are also for examining
the data stored at
The diagnostic
modes are listed
below and
specific
memory locations.
individually
discussed.
DIAGNOSTIC MODES
SW 2 POSITION
FUNCTION
Failedmndication
Memory Mapping
Input Port Data Display
Display
Tach
Display
Speed Command
Lamp Test
Train Simulation
Data
D/A Special
Scaling
Display
Wheel Wear
BCD Display
Chart Recorder Calibration
IO1 AND PS BOARD)
BMPATO (NOVEMBER1984)
5-20
0507fl
5.3.2.1
Failed
Board
Indication
When "0" is dialed
on SW 2 (01 and PS), the LED(s) on the I/O board
corresponding
to the failed
board(s),
if any, will
flash on and off.
For instance,
if the board in position
XA3 failed,
LED 3 will
flash.
This switch
(2) should always be positioned
at "O", so the failed
board mode is activated
during
normal operation.
Note that LED 8
should be flashing
to indicate
that the CPU is running.
L
5.3.2.2
Memory Mapping
This function
is performed
when a "1" is dialed
on SW 2 of the 01 and
PS board.
Using this function,
memory locations
are displayed
on the
I/O board and Monitor
board.
The value of the middle pair of hex
switches
(SW 3 and 4) on the 01 and PS board will
point to a page of
memory (e.g.,
50XXH) for the LED display
on the I/O board and the
first,
second, and third
hex displays
on the Monitor
board.
The
bottom pair of hex switches
(SW 5 and 6) on the 01 and PS board
points
to a location
(e.g.,
50FOH) on the page for the LED display
on
the I/O board and the first
hex display
on the Monitor
board.
Hex
switch
1 on the Monitor
board will
be the location
of the page for
the second hex display
the Monitor
board.
Hex switch 2 on the
Monitor
board will
be on the location
of the page for the third
hex
display
on the Monitor
board.
Hex switch 6 on the Monitor
board will
pont to a page of memory for the fourth,
fifth,
and sixth
hex
displays
on the Monitor
board.
Hex switch 3, on the Monitor
board
will
be the location
for hex display
4.
Hex switch 4, on the Monitor
board, will
be the location
for hex display
5. Hex switch 5, on the
Monitor
board, will
be the location
for hex display
6.
5.3.2.3
Input
Port
Data
on SW 2 of the 01 and
This function
is performed when a "2" in dialed
Hex switches
5 and 6 of the 01 and PS board point to an
PS board.
input port,
which is displayed
on the LED display
of the I/O board
Hex switch 1 on the Monitor
and hex display
1 on the Monitor
board.
board points
to an input port,
which is displayed
on hex display
2 of
Hex switch 2 on the Monitor
board points
to an
the Monitor
board.
input port,
which is displayed
on hex display
3 of the Monitor
Hex displays
4, 5, and 6 of the Monitor
board display
memory
board.
mapped data as discussed
in 5.3.2.2
above.
5.3.2.4
Display
Tachometer
on SW 2 of the 01 and
This function
is performed when a "3" is dialed
The train's
speed from memory location
SPEED (3H=l mph) is
PS board.
displayed
on the LEDs of the I/O board and hex display
1 of the
The trains
speed from memory location
TACH (lh = 1
Monitor
board.
mph) is converted
to its decimal equivalent
and is displayed
on hex
display
2 of the Monitor
board.
L
I
BMPATO (NOVEMBER1984)
5-21
050 714
5.3.2.5
Display
Speed Command
on SW 2 of the 01 and
This function
is performed
when a "4" is dialed
The speed command from memory location
SCt,iAN (3H = 1 mph)
PS board.
is displayed
on the LEDs of the I/O board and hex display
1 of the
The memory location
SCCIAN is divided
by 3 (1H = 1
Monitor
board.
mph), is converted
to its decimal equivalent,
and is displayed
on hex
display
2 of the Monitor
board.
5.3.2.6
Lamp Test
This function
is performed
when a "5" is dialed
on SW 2 of the DI and
PS board.
A value of 55H is displayed
on the LEDs of the I/O board
and all hex displays
of the Monitor
board for about 0.44 second.
Then a value of AAH is displayed
on all displays
for about 0.44
The displays
alternate
between these two values,
lighting
up
second.
all the LEDs of the displays.
5.3.2.7
Train
Simulation
Data
on SW 2 of the 01 and
This function
is performed
when a "6" is dialed
PS board.
This function
outputs
data to displays
and D/A convertor
outputs
for diagnostic
help of speed maintaining.
Memory location
PBRK (Power Brake Mode) is displayed
on LEDs of I/O board and hex
display
1 of the Monitor
board.
Memory location
PSIG (analog
P-signal)
is displayed
on hex display
2 of the Monitor
board.
Plemory
location
VELRF (Reference
Velocity)
is scaled so 10 mph (1E hex) = 1
fiemory
volt,
and is displayed
on hex display
3 of the flonitor
board.
!;;a;:;;
VELPS (Program Stop Reference Velocity)
is scaled,
so 10 mph
= 1 volt,
and is displayed
as hex display
4 of the Flonitor
Memory location
ASE (Analog Speed Error)
is displayed
on hex
board.
display
5 of the Monitor
board.
Memory location
SPEED (Actual
Train
and is displayed
on
Speed) is scaled,
so 10 mph (1E hex) = 1 volt,
hex display
6 of the Monitor
board.
A/D converter
outputs
are
obtained
from the 25 pin connector
at the bottom of the Monitor
The following
are the display-to-pin
number match-ups of the
board.
Monitor
board.
Hex Display
25 Pin Connector
Number
6
5
4
3
1
2
3
4
5
6
5.3.2.8
D/A Special
Pin Number
:
Scaling
on SW 2 of the 01 and
This function
is performed
when a "7" is dialed
PS board.
This function
is the same as the memory mapping function
L
I
BMPATO(NOVEMBER1984)
5-22
0507ri
(Section
5.3.2.2,
above),
except the first
four displays
are scaled.
This allows
the first
four displays
to be monitored
at the A/C
outputs
of the monitor
board with a scaling
of 1C mph (1E hex) = 1
volt.
5.3.2.9
BCD Display
This function
is performed
when a "9" is dialed
on SW 2 of the 01 and
PS board.
This function
is the same as the memory mapping function
(Section
5.3.2.2),
except the last three displays
are shown as their
decimal equivalents.
5.3.2.1C
Chart
Recorder
Calibration
This function
is performed
when an "A" is dialed
on SW 2 of the 01
and PS board.
This function
applies
a square wave to all the
displays,
which are also obtained
at the A/D converter
outputs
on the
25 pin connector
of the Monitor
board.
The square wave has a
frequency
of 0.57 Hz and amplitude
of 0 to 10 volts.
5.3.2.11
Display
Wheel Wear
This function
is a useful
one, in that it allows
the user to verify
data which has been input to the system for wheel wear compensation.
By dialing
SW 2 to position
"8", this function
is selected.
Data
which was input by using SW 1, for wheel wear, is displayed
on the
I/O board for verification,
This eliminates
user errors.
5.4,
CUSTOMERPROGRAMMING
From a normal maintenance
standpoint,
knowledge of how a CPU works is not
Reprogramming
requires
access to a minicomputer
that can perform
needed.
and can program PROMS.
assembly lan uage to machine language conversion,
is not that difficult,
it takes training
While assemb 4y language programmlng
effectively
and safely
use it for driving
the propulsion
logic
hardware.
Reprogramming
requires
detailed
knowledge of the propulsion
system and should
be left
to Westinghouse.
It should be understood
that any customer
initiated
change to the system
hardware or software
which has not been approved by Westinghouse
could
invalidate
any system performance
or safety
guarantees
otherwise
in effect.
L /
I
A program listing
in assembly language
provided
as a separate
document.
and corresponding
BWATO (NOVEMBER1984)
5-23
flow
charts
is
0507M
TYPICAL OUTPUT APPLIED TO STATION PLATFORMANTENNA
140 MICROSECONDS(APPROX.)
b-4
I
60430 V
PP
LJ-
TYPICAL OUTPUTAPPLIED TO MARKERANTENNA
140 MICROSECONDS(APPROX.)
NOTE:
6
OUTPUT SIGNAL AS MEASUREDAT TRANSMITTER ASSEMBLY: 20 VOLTS/DIV
AND 50 MICROSECONDS/DIV.
FIGURE 5-l.
BMPATO (NOVEMBER 1984)
TRANSMITTER OUTPUT SIGNALS
5-24
0
CHKSM
GET CHECKSUM
CALCULATE
POINTER
CHECKSUM
NO
GET
INCREMENT
ERROR
I
1 CLEAR
ERR;,
PAGE CHECKSUM
FROM TABLE
COUNTER
POINT
TO NEXT
]
SET CHECKSUM
POINTER
TO FIRST
0
NEXT
RET
*
FIGURE 5-2.
BMPATO (NOVE'lBER 1984)
PAGE
5-25
CHECKSUMROUTINE
PAGE
I
HEX LED
DISPLAY
PAIR 1 & 2
>HEX
#8 (M.S. >
ROTARY
SWITCH PAIR
l&2
LEDs
DIGITAL INPUT
& PS BOARD
(XAl>
MONITOR
BOARD
(XA7)
I/O
BOARD
(XA3)
0
7
HEX DISPLAY
PDIR 11 & 12
i.,
SW. #l
(WHEEL WEAR)
El
HEX ROTARY
El SWITCHES
-RESET P.B.
a
M.S.
El
LED ARRAY3 & 4
L.S.
25 PIN ANALOG
OUTPUT CONNECTOR
zl
SW. #6
P
POSITION OF LEDs AND HEX SWITCHES AS VIEWED
ON THE PC BOARDS WITH THE AT0 MODULE MOUNTED
IN THE TRAIN.
MONITOR BOARD TEST UNIT IS SHOWNAS IT WOULD
APPEAR IF PLUGGED IN FOR TEST PURPOSES
FIGURE 5-3.
Li
PC BOARD AND LOGIC MONITOR MODULE DIAGNOSTIC DISPLAYS
BMPATO (NOVEMBER1984)
5-26
TABLE OF CONTENTS
L
TITLE
SECTION
PAGE NO.
6.0
CORRECTIVE MAINTENANCE
6-l
6.1
GENERAL
6-1
6.2
6-l
6-l
6.2.2
6.2.3
6.2.4
STATION PROGRAMSTOP TRANSMITTER ASSEMLBY
Transmitter
Module
Power Switch
Relays
Power Supply
6-3
6.3
WAYS1DE JUNCTION BOX
6-4
6.4
6.4.1
6-5
6-5
6.4.2
6.4.3
6.4.4
VEHICLE AT0 EQUIPMENT
AT0 Module
PC Boards
Switch
Hexadecimal
AT0 P & BRK Signal Generator
Board
Termination
Program Stop Antenna
;:s"
6-7
6-7
6-8
6.5
SPECIAL TOOLS AND TEST EQUIPMENT
6-8
6.2.1
6.4.1.1
6.4.1.2
BMPATO
6-i
;I;
0508M
6.0
CORRECTIVE MAINTENANCE
6.1
GENERAL
This section
contains
corrective
maintenance
instructions
procedures
for the
various
components of the AT0 Subsystem.
In-service
equipment which fails
or
is suspect should be replaced
by a known functional
unit.
This approach
'minimizes
train/system
downtime and permits
accurate
localization
of faults
with extensive
troubleshooting.
Corrective
maintenance,
therefore,
comprises
procedures
for removal and replacement
of the various
components of the AT0
These procedures
are discussed
below.
Subsystem.
6.2
STATION PROGRAMSTOP TRANSMITTER ASSEMBLY
Program Stop Transmitter
Assembly removal should
performed
correctly
in the following
steps:
require
0.2
manhours,
a.
Remove power to the Assembly,
and disconnect
two terminal
strips
of the rear panel.
and label
b.
Protect
from damage in shipment.
front
panel
Program Stop Transmitter
be performed
correctly
a.
b.
switches
Assembly installation
in the following
steps:
should
require
on the
0.3 manhours,
With the power removed, position
the assembly near its intended
location
and connect labeled
wiring
to rear panel terminal
strips
Figure 2-7.
to
per
Verify
wiring
accuracy before applying
power to the unit via the
Verify
ac and dc indicators
lit
and Transmit
front
panel switch.
Module LEDs lit.
6.2.1
Transmitter
Transmitter
correctly
Module removal
in the following
Module
should
steps:
require
a.
Remove power to the Transmitter
front
panel switch to OFF.
b.
Remove the two thumb nuts
out by its handles.
c.
Install
a blank plate
assembly from dust.
d.
Reapply
BMPATO
and indicators
wiring
to be
0.1 manhours,
Module
to be performed
by positioning
the Assembly
retaining
the module
and pull
in the module's
position
to protect
power to the Transmitter
6-l
Assembly,
if
that
is
the module
the
desirable.
0508M
Transmitter
correctly
Module installation
should
in the following
steps:
a.
Remove power to the Transmitter
front
panel switch to OFF.
Module
5.
Remove any blank
plate
the
c.
Insert
the module
Assembly until
it
as flat
and evenly
is firmly
seated.
d.
Install
e.
6.2.2
covering
two thumbscrews
them by hand.
tighten
require
at either
0.1
manhours,
to be performed
by positioning
the Assembly
intended
module
as possible
and slide
end of the module
Apply power to the module by positioning
Module transmitter
switch
to ON. Verify
module.
location.
front
into
the
panel
and
the Assembly front
panel
LEDs lit
on the installed
Power Switch
Power Switch
the following
removal
steps:
should
require
0.1
a.
Remove power to the Transmitter
b.
Lower the
c.
With
d.
Disconnect
and tape wiring.
e.
With
four
screwdriver
retaining
f.
Remove the
Power Switch
correctly
in
front
panel
a multimeter,
a slot
screws
manhours,
that
the
two top captive
no power exists
Mark wiring
for
and open end (or
the ON/OFF breaker
in
on switch
screws.
terminals.
reuse.
socket)
switch.
wrench,
remove the
switch.
installation
the following
should
steps:
require
0.1
manhours,
a.
Remove power to the Transmitter
b.
Lower the
c.
With a multimeter,
necessary,
perform
d.
Mount switch in front
panel with appropriate
head screwdriver
and open end wrench.
e.
Connect
Bl4'ATO
correctly
Assembly.
by loosening
verify
to be performed
front
wiring
panel
to be performed
Assembly.
by loosening
the
two top captive
verify
that no power exists
the switch removal procedure
per Figure
on switch
above.
hardware,
screws.
wiring.
using
If
a slot
2-6.
6-2
0508M
f.
Raise
90
Return power to the Transmitter
for proper indication.
L
the
front
panel
and tighten
6.2.3
Relays
Transmitter
performed
Assembly relay removal
correctly
in the following
b.
Lower
the
c.
Select
of the
the correct
socket.
Transmitter
performed
L
after
relay
Assembly relay
correctly
in the
b.
Lower the
screws.
c.
Position
contact
base.
d.
Check visually
enclosure.
to ensure
e.
Raise
the
panel
f.
Return
power to the Assembly
if
the
it
should
steps:
Remove power from the Transmitter
it
manhours,
front
panel
to be
two top captive
screws.
by pulling
it
require
manhours,
0.1
up, by loosening
the known good relay over its socket,
pin alignment,
and insert
it horizontally
front
the
horizontally
out
to be
Assembly.
is
that
screws.
Assembly.
and remove
installation
following
panel,
0.1
loosening
a.
front
and observe
should require
steps:
Remove power from the Transmitter
panel
two top captive
Assembly
a.
front
the
no hand tools
and tighten
its
the
two top captive
oriented
for
and firmly
have been left
correct
in its
in the
two top captive
screws.
all
indications
as proper.
to be performed
correctly
and check
Power Supply
6.2.4
Power Supply
the following
removal
steps:
should
require
0.1
manhours,
a.
Remove power to the Transmitter
Assembly.
b.
Remove power at the Transmitter
Assembly
c.
Loosen the two top captive
front
panel.
screws
d.
With a multimeter,
leads.
that
e.
Disconnect
BMPATO
verify
the power supply
on the
no voltage
in
front
panel
ON/OFF switch.
front
panel
and lower
exists
on the
the
power supply
connector.
6-3
0508M
f.
Remove the
remove the
Power Supply
correctly
in
slot
installation
the following
head screws
should
steps:
retaining
require
0.1
Remove power to the Transmitter
Assembly.
b.
Remove power at the Transmitter
Assembly
c.
Loosen the two top captive
front
panel.
screws
d.
With a multimeter,
supply leads.
that
no voltage
in the
left
Install
with
verify
the power supply
screws.
the Power Supply
manhours,
a.
e.
‘L
four
unit.
on the
and
to be performed
front
panel
ON/OFF switch.
front
panel
and lower
exists
on the
hand portion
the
switch
power
of the assembly
f.
Attach
middle
the power supply connector
of the top support
plate.
to the receptacle
mounted
in the
90
Raise
the
the captive
which
retain
h.
Return
power to the Transmitter
i.
Place
verify
the Transmitter
Assembly power switch in the
that power indicators
and module LEDs light.
L
With multimeter,
front
panel test
front
panel
and tighten
screws
it.
Assembly.
verify
the 24 Vdc output
connections.
of the
ON position
and
power supply
at the
WAYSIDE JUNCTION BOX
6.3
Junction
Box removal
the following
steps:
should
require
0.3
manhours,
to be performed
correctly
a.
Remove transmission
power to the Junction
Box by removing the
corresponding
Transmitter
Module or power to the associated
Transmitter
Assembly.
b.
Open the
top cover
c.
Disconnect
reuse.
wiring
d.
Removerconduit
locknuts
and remove conduit
and leads
e.
Remove l/4-20
hex bolts
in base of Junction
Box.
BWATO
of the Junction
leads
on both
6-4
in
Box.
terminal
strips.
Mark wiring
for
from box.
0508M
Junction
correctly
1.
Box installation
in the following
should require
steps:
0.4 manhours,
to be performed
a.
Remove transmission
power to the intended
site of Junction
Box
installation
by removing the corresponding
Transmitter
Module or
power to the associated
Transmitter
Assembly.
b.
Position
Junction
Junction
Box.
Box in place
C.
Open the
top cover
of the Junction
d.
Insert
wiring
e.
Tighten
conduit
f.
Connect
marked wiring
9*
Close
cover
h.
Return
Transmitter
i.
Observe
system
and conduit
and install
into
l/4-20
bolts
in base of
Box.
box and through
conduit
locknut.
locknut.
and secure
to terminal
operation
VEHICLE AT0 EQUIPMENT
6.4.1
AT0 Module
AT0 Module removal should
the following
steps:
as shown in Figure
2-5.
in place.
Assembly
6.4
strips
or module
to service.
as proper.
require
0.1
manhours,
to be performed
correctly
a.
Remove the 160-pin
handle and pulling
b.
Loosen the two captive
screws securing
the AT0 Module to the
Propulsion
Locker,
rotate
the installation
assist
latch,
and lift
box out of the bottom rail
mounting.
AT0 Module installation
in the following
steps:
connector
from the unit by unscrewing
the cabling
and connector
clear.
should
require
0.1
manhours,
to be performed
a.
Insert
the AT0 Module in the mounting
rails,
engage the
screws (torque
assist
latch,
and tighten
the two captive
inch-pounds).
b.
Install
the proper 160-pin
and receptacle
keying pins
BMPATO
the
in
the
correctly
installation
46
connector
by aligning
the connector
and tightening
the 'T' handle.
6-5
'T'
plug
0508M
6.4.1.1
L
PC Boards
PC boards are only removed from the AT0 Module while power is off.
Removing
PC boards with power applied
to the AT0 Module may result
in damage to
components on the PC board being removed and/or PC boards remaining
in the
PC board removal should require
0.03 manhours.
module.
a.
Remove the Lexan cover
from
the AT0 Module.
b.
Identify
rotating
c.
Grasping
the release
latch
and outside
edge of the PC board
Teflon
guides of the modules,
pull
the board straight
out.
d.
Replace
the PC board to be removed and lift
both release
them away from the center of the PC board.
the Lexan cover
or installation
by:
near
of PC boards
should
disengaged
Excessive
that the
require
0.03
and the undue
force is not
latches
are not
manhours
and is
a.
Remove the Lexan cover
b.
Determine
the correct
slot
board you wish to install.
C.
Orient
d.
Push the PC board
e.
When the board latches
engage
engagement and simultaneously
board.
the AT0 Module, check for proper
rotate
both latches
down to secure
Replace
AT0 Module.
1
f.
6.4.1.2
the PC board
the
Hexadecimal
from the AT0 Module.
(location)
so the component
into
place
Lexan cover
in the AT0 Module
side
is
towards
slot
excessive
force
is
for
the PC
XAl.
not
required.
the
Switch
a.
Remove the Digital
per Section 6.4.1.1.
b.
Grasp
c.
Position
a known good switch
Input board.
Check that the
the board.
BM'ATO
evenly;
on the
Hexadecimal
switch replacement
should
correctly
in the following
steps:
the
both
on the AT0 Module.
Care should be exercised
that both latches
are fully
force is not applied
to components on the PC boards.
required.to
remove PC boards and may be an indication
fully
disengaged.
Replacement
accomplished
latches,
switch
Input
and pull
require
0.1
and Power Supply
it
vertically
above
rotary
6-6
manhours,
board
to be performed
from the AT0 Module
away from the
board.
the DIP socket on the Digital
dial is to the outside
edge of
0508M
d.
Neatly tuck the tip of each pin into its corresponding
and evenly press on the top of the switch.
e.
Push down on the
6.4.2
switch
AT0 P & BRK Signal
AT0 P & BRK Signal
performed
correctly
until
it
is
seated
level,
require
0.3
socket
touching
should
steps:
socket.
manhours,
to be
wires
are marked.
a.
Disconnect
b.
Remove the AT0 P & BRK Signal Generator
from the Propulsion
loosening
the two mounting
screws,
rotating
the installation
latch,
and withdrawing
the unit.
AT0 P & BRK Signal
performed
correctly
the
Generator
Generator
removal
in the following
all
hole
external
wiring.
Ensure
Generator
installation
should
in the following
steps:
that
all
require
0.3
Locker
assist
manhours,
by
to be
a.
Insert the AT0 P & BRK Signal Generator
in its proper location
in the
B-Car Propulsion
Locker,
engage the installation
assist
latch,
and
Torque mounting
screws as noted
tighten
the two mounting
screws.
below.
b.
Connect all external
wiring
Torque associated
terminal
per 4682C48, sheet 85, and wire
hardware as noted below.
TORQUE
HARDWARE
.250"
.164"
.138"
spring ejected
terminal
block
terminal
block
Termination
6.4.3
46 inch-pounds
10 inch-pounds
5 inch-pounds
screws
screws
screws
Board
AT0 Termination
board removal should
correctly
in the following
steps:
a.
Label
b.
Remove the Termination
board to the Propulsion
and disconnect
all
require
wiring
0.2
manhours,
to be performed
to the board.
board by removing the screws retaining
Locker.
Store screws and lockwashers.
AT0 Termination
board installation
performed
correctly
in the following
should require
steps:
0.3
manhours,
Position
the new board in the Propulsion
Locker and insert
(with lockwashers)
through
the board and into the mounting
Start
tightening
the screws by hand.
b.
Evenly
tighten
C.
Using
wires
a schematic
reference
to the board.
all
screws
to secure
and wiring
6-7
the board
in position.
labels,
connect
the
to be
a.
BIQATO
marking.
all
the screws
holes.
external
0508M
6.4.4
Program
Program
correctly
Stop Antenna removal should
in the following
steps:
require
0.1 manhours,
to be performed
a.
Detach
clamp.
the Program Stop Antenna connector
by hand and remove cable
Cover the connector
to prevent
dirt
from entering.
b.
Loosen
bolster.
the
c.
Support the antenna while completely
Tape removed nuts
from the bolster.
for reuse.
Program
correctly
‘L
Stop Antenna
four
nuts
supporting
Stop Antenna installation
in the folowing
steps:
the
should
antenna
from
the
botton
of the
removing nuts and lowering
studs
and lockwashers
to the bolster
require
0.2 manhours,
to be performed
by wire brushing
compound.
and application
of an
a.
Prepare antenna studs
acceptable
anti-seize
b.
Position
antenna under B-truck
bolster
and finger
tighten
nuts.
Ensure antenna is flat
against
bolster
bottom.
Make certain
lockwashers
are in position
for all studs.
c.
Make up the connector
d.
Refer
adjust
to 22681309 for runnina
on bolster
accordingly.
e.
Using
standard
torque
plug
by hand,
then
clearance
procedures,
install
cable
on Program
tighten
nuts
clamp.
Stop Antenna
and
to 75 foot-pounds.
SPECIAL TOOLS AND TEST EQUIPMENT
6.5
The following
and Preventive
Westinghouse.
0
0
0
0
Equipment
as necessary _ to perform Corrective
test equipment
is identified
Maintenance
for the AT0 Subsystem,
but is not provided
by
Could-Brush
#260 Recorder (6 channel)
Digital
Voltmeter
(DVM) -- portable,
battery
operated
battery
Oscilloscope
-- portable,
Frequency
Counter
supplied
by Westinghouse
includes
EQUIPMENT
Portable
AT0 Test Unit (PTU)
Bench AT0 Test Unit (BTU)
BMPATO (FEBRUARY 1984)
the
operated
following.
PURPOSE
Test/Monitor
vehicle
AT0 performance
Test/Monitor
AT0 Module PC Board and/or
P & BRK Signal
Generator
performance.
6-8
0508M