Assignment 3
Problem 1:
Design a circuit that converts an 8-bit signed input to 8-bit sign-magnitude output (where
the MSB is the sign bit and the remaining 7 bits are magnitude). Use a minimal number
of relational and arithmetic operators in your design. Draw the top-level diagram and
derive the VHDL code.
Problem 2:
Design a priority encoder that returns the codes of the highest and second-highest priority
request. The input is an 8-bit req signal and the outputs are code1, code2, valid1 and
valid2, which are the 3-bit codes and 1-bit valid signals of the highest and second-highest
priority requests respectively.
Problem 3:
Many instrument panels use binary-coded-decimal (BCD) format, in which 10 decimal
digits are coded by using 4 bits. During an addition operation, if the sum of a digit exceeds
9, 10 will be subtracted from the current digit and a carry is generated for the next digit.
Design a 3-digit BCD adder which has two 12-bit inputs, representing two 3-digit BCD
numbers, and an output, which is a 4-digit (16-bit) BCD number. Draw the top-level
diagram and derive the VHDL code accordingly.
Problem 4:
Consider a 4-bit counter that counts from 3 ("001 1") to 12 ("1 100") and then wraps
around. If the counter enters an unused state (such as "0000") because of noise, it will
restart from "001 1" at the next rising edge of the clock. Derive the VHDL code for this
circuit and draw the conceptual top-level diagram.
Problem 5:
Design a programmable frequency divider. In addition to clock and reset, it has a control
signal, c, which is a 4-bit signal interpreted as an unsigned number. The circuit has an
output signal, pulse, whose frequency is controlled by c. If the clock frequency is f and the
value of c is m, the frequency of the pulse signal will be f/2m. For example, if c is "0101",
the frequency of the pulse signal be f/25. Derive the VHDL code for this circuit.