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REGULAR PAPER
Japanese Journal of Applied Physics 57, 04FR02 (2018)
https://doi.org/10.7567/JJAP.57.04FR02
Effect of surface roughness of trench sidewalls on electrical properties
in 4H-SiC trench MOSFETs
Katsuhiro Kutsuki1,2*, Yuki Murakami2, Yukihiko Watanabe1, Toru Onishi2,
Kensaku Yamamoto3, Hirokazu Fujiwara2, and Takahiro Ito2
TOYOTA CENTRAL R&D LABS., Inc., Nagakute, Aichi 480-1192, Japan
TOYOTA MOTOR Corporation, Toyota, Aichi 470-0309, Japan
3
Research Division 3, DENSO Corporation, Nisshin, Aichi 470-0111, Japan
1
2
*E-mail: kutsuki-k@mosk.tytlabs.co.jp
Received October 2, 2017; revised November 16, 2017; accepted November 17, 2017; published online February 19, 2018
The effects of the surface roughness of trench sidewalls on electrical properties have been investigated in 4H-SiC trench MOSFETs. The surface
roughness of trench sidewalls was well controlled and evaluated by atomic force microscopy. The effective channel mobility at each measurement
temperature was analyzed on the basis of the mobility model including optical phonon scattering. The results revealed that surface roughness
scattering had a small contribution to channel mobility, and at the arithmetic average roughness in the range of 0.4–1.4 nm, there was no
correlation between the experimental surface roughness and the surface roughness scattering mobility. On the other hand, the characteristics of
the gate leakage current and constant current stress time-dependent dielectric breakdown tests demonstrated that surface morphology had great
impact on the long-term reliability of gate oxides. © 2018 The Japan Society of Applied Physics
1.
Introduction
Silicon carbide (SiC), a compound semiconductor of silicon
and carbon, has superior physical properties to Si in
achieving high blocking voltage, high-temperature operation,
and low loss at high switching speed. SiC devices enable
efficient use of electric power, allowing the reduction in the
size of power supplies and the simplification of cooling
systems.1) In addition, SiC is the only wide-gap semiconductor on which a SiO2 layer can be formed by conventional thermal oxidation as well as silicon. However,
there are severe stopping issues regarding the MOS channel
resistivity and gate oxide reliability toward the practical use
of SiC-based MOS devices.
To reduce the channel resistivity, we focused on the
equation of drain current (ID) in MOSFETs. The drain current
in the linear region can be described by 2)
ID ¼
W
eff COX ðVG Vth ÞVD ;
L
ð1Þ
where W is the channel width, L is the channel length, μeff is
the effective channel mobility, COX is the oxide capacitance,
VG is the gate voltage, Vth is the threshold voltage, and VD is
the drain voltage. A decrease in L causes Vth to decrease
owing to the short-channel effect and punch-through in the
off state depending on the impurity density in the channel
region. Although an increase in COX by dielectric layers with
high permittivity (high-k), e.g., HfAlON, was reported with
appropriate oxide thickness in the application of power
devices,3) the gate leakage current through a high-k layer due
to a narrow band gap4) is a severe problem. Moreover, a
decrease in Vth makes it difficult to design normally-off SiC
MOSFETs in high-voltage power devices. For the above
reasons, increasing W and μeff is concluded to be effective in
increasing ID without disadvantageous effects.
One of the best ways to increase W and μeff simultaneously
is the use of trench MOSFETs (UMOSFETs). Trench
MOSFETs enable us to shrink cell pitch, which results in
the increase in channel width. In addition, when trench
MOSFETs are fabricated on a Si-face, trench sidewalls
face
correspond to non-polar planes, e.g., ð1100Þ
or ð1120Þ
(m-face or a-face), which are reported to reveal high electron
channel mobility compared with a (0001) Si face.5) In fact,
many reports have demonstrated several types of trench
MOSFETs with relatively small specific-on-resistance (RonA)
values.3,6–17) However, the use of trench MOSFETs still
has challenges. One of the challenges is a channel mobility
lower than that expected from lateral MOSFETs. The
reported field effect channel mobility is in the range of only
5–50 cm2 V−1 s−1. The limiting factors of channel mobility
are also unclear. Another challenge is ensuring the reliability
in gate dielectrics.
How to control the shape and morphology of trenches is
believed to be essential for the above-mentioned challenges.
Since SiC is physically hard and chemically stable compared
with Si, its etching rate is low even when using etching
equipment employing high-density plasma, and the etched
shape is difficult to control. Therefore, the transformation
of SiC trenches has been reported at high temperatures.18–23)
For instance, Kawada et al. proposed the two-step process of
annealing at 1700 °C in SiH4=Ar atmosphere followed by
annealing at 1500 °C in H2 atmosphere, which enabled
simultaneous improvements in the shape of trenches and in
the smoothness of substrate surfaces without significant
etching.22) However, they did not pay attention to the surface
morphology of trench sidewalls, which correspond to the
channel region in MOSFETs. Moreover, the impact of the
surface roughness of trench sidewalls on electrical properties
has not been discussed yet.
In this study, we investigated the surface roughness of
trench sidewalls and its effects on electrical properties,
especially channel mobility and the long-term reliability of
gate oxides. To discuss the oxide reliability in detail, the
results of current constant stress time-dependent dielectric
breakdown (CCS-TDDB) tests were added to the original
extended abstract.24)
2.
Experimental methods
The starting material was an n-type 4H-SiC epitaxial layer
grown on a heavily doped n+-SiC (0001) substrate. The
04FR02-1
© 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 04FR02 (2018)
K. Kutsuki et al.
AFM images
Condition A Condition B Condition C
(a)
(b)
(c)
[0001]
[1120]
[
]
[
Fig. 1. (Color online) Schematic image of AFM analysis at trench
sidewalls.
100nm
]
3.5
Height (nm)
Scan area
(400nm x 400nm)
eff ¼
L
@ID =@VD
:
W COX ðVG Vth Þ
ð2Þ
For further investigation, μeff was analyzed on the basis of the
proposed mobility model including optical phonon scattering
mobility (μOP).27) The optical phonon scattering has been
taken into account for the bulk mobility of SiC, and reported
to have great impact on the total mobility.28) Therefore,
instead of acoustic phonon scattering mobility in conventional mobility models,29–33) μOP was applied to the improved
mobility model with Coulomb scattering mobility (μC)32) and
surface roughness scattering mobility (μSR)32) as follows:
1
1
1
1
¼
þ
þ
;
ð3Þ
eff C SR OP
C T
NS C
1þ
;
ð4Þ
C ¼
NT
Nscr
-10.0nm
Line profiles (parallel)
(d)
(e)
(f)
Ra =0.40nm
Ra =0.66nm
Ra =1.4nm
0
-3.5
0
500
500
500
Distance (nm)
Height (nm)
isolated one-cell trenched MOSFETs with n-channel were
fabricated in order to extract the channel resistance
component and determine μeff. The surface roughness of
trench sidewalls was controlled by high-temperature annealing after trench SiC etching (conditions A, B, and C). The
high-temperature annealing was performed above 1000 °C
after activation annealing, which was followed by a gate
fabrication process. The deposition of a 75-nm-thick SiO2
layer as gate oxide was followed by nitridation. The
nitridation process was highly effective, but the Dit values
at SiO2=SiC interfaces were still above 2 × 1012 cm−2 eV−1
at EC − E = 0.2 eV. To evaluate the surface morphology of
trench sidewalls, each sample was cleaved along the trench
direction. Then, the gate electrode and gate oxide were
removed. The scanning area of atomic force microscopy
(AFM) was 400 nm square as shown in Fig. 1. The impurity
concentration in the channel region (NA) was determined by
secondary ion mass spectrometry (SIMS), and the thickness
of the gate oxide and the taper angle of trenches are evaluated
by cross-sectional transmission electron microscopy (TEM)
(data not shown).
The evaluation of electrical properties of isolated one-cell
trench MOSFETs consists of the drain current–gate voltage
(ID–VG) properties, gate leakage current–gate voltage (IG–VG)
properties, and CCS-TDDB test results. The ID–VG characteristics were measured at temperatures in the range of −40 to
250 °C. The interface state density (Dit), Vth and μeff were
calculated directly from the measured ID–VG charactesistics.25,26) Dit was calculated from the subthreshold swing of
the measured ID–VG curves. The calculated Dit locates at the
energy level in the range of 0.1 to 0.2 eV from the conduction
band edge of SiC. According to Eq. (1), μeff was defined by
10.0nm
10
Line profiles (perpendicular)
(h)
(g)
5
(i)
0
-5
Ra =2.6nm
Ra =0.95nm
-10
0
500
Ra =2.4nm
500
500
Distance (nm)
Fig. 2. (Color online) Panels (a)–(c) show AFM images of samples
fabricated under conditions A, B, and C. The scanning area is 400 nm square.
The crystal orientation and current direction are also described. Panels
(d)–(f) are line profiles parallel to the current direction, which correspond to
the AFM images (a)–(c). In addition, panels (g)–(i) are line profiles
perpendicular to the current direction, which correspond to the AFM images
(a)–(c). Ra values of line profiles are described in the figures.
;
E2eff
C
1
C
ħ!OP
¼
OP ¼
exp
1 ;
Eeff Nð!OP Þ Eeff
kT
q
ðNdpl þ NS Þ;
Eeff ¼
"SiC
SR ¼
ð5Þ
ð6Þ
ð7Þ
where NT is the total number of trapped charges, which
include fixed and interface-trapped charges, T is the absolute
temperature, NS is the surface inversion carrier concentration,
Eeff is the effective field,27,30) N(ωOP) is the phonon
occupation factor, ħωOP is the optical phonon energy, k is
Boltzmann’s constant, εSiC is the permittivity of SiC, Ndpl is
the surface concentration of the depletion charge, η is taken to
be 1=2 for the electron mobility, and ΓC, Nscr, ζC, δ, and C are
empirical parameters. The empirical parameters were the
same among the conditions considered. In relation to Eeff, η
was defined on the basis of the Si mobility model.30) μOP is
assumed to be proportional to E1
eff . Under all conditions, an
excellent agreement with experimental data was confirmed,
and the errors between the calculated and experimental
effective mobilities were less than 6% in the range of −40 to
250 °C. In this study, we investigated the impact of surface
morphology on these three mobility factors, i.e., μC, μSR, and
μOP.
3.
Results and discussion
3.1
Surface morphology at trench sidewalls
Figures 2(a)–2(c) show AFM images of samples fabricated
under conditions A, B, and C. A striation can be seen under
conditions B and C. The corresponding line profiles parallel
to the direction of the drain current are shown in Figs. 2(d)–
04FR02-2
© 2018 The Japan Society of Applied Physics
1.5 ¼10-4
1.0 ¼10-4
K. Kutsuki et al.
12
2.0 ¼10-5
Effective Mobility, µeff (cm2V-1s-1)
Drain Current, ID (A)
2.0 ¼10-4
Transconductance, gm(S)
Jpn. J. Appl. Phys. 57, 04FR02 (2018)
1.5 ¼10-5
1.0 ¼10-5
gm
5.0 ¼10-6
0
0
5
Ra: 0.40nm
0.66nm
1.4nm
10 15 20
VG (V)
5.0 ¼10-5
VD=0.1V
measured at 25°C
0
0
5
10
15
20
Gate Bias, VG (V)
Table I. Ra values of line profiles are measured both parallel and
perpendicular to the current direction for each sample. Vth and Dit are also
listed.
Ra values of line profiles (nm)
Ra: 0.40nm
0.66nm
1.4nm
8
6
4
2
VD=0.1V
measured at 25C
0
0.6
0.8
1
1.2
1.4
1.6
Effective Field, Eeff (MV/cm)
Fig. 3. (Color online) ID–VG characteristics of isolated one-cell trench
MOSFETs with different surface morphology. The measurement temperature
was 25 °C and the drain voltage was 0.1 V. The inset shows the
transconductance properties.
Parallel
Perpendicular
Vth
(V)
Dit
(×1012 cm−2 eV−1)
A
0.40
0.95
3.4
2.8
B
0.66
2.6
3.3
2.8
C
1.4
2.4
3.5
2.9
Sample
conditions
10
2(f), and those perpendicular to the drain current are shown
in Figs. 2(g)–2(i). The arithmetic average roughness (Ra)
values of line profiles are also described in the figures. It is
demonstrated that the surface roughness could be controlled
at Ra values parallel to the drain current in the range of 0.4
to 1.4 nm, judging from Figs. 2(d)–2(f). The line profiles
perpendicular to the current flow also revealed that the
average peak-to-valley distance of striations, as shown in
AFM images, [Figs. 2(b) and 2(c)], was about 10 nm. The
trench shape of each sample was confirmed to be almost the
same and the trench angle in the channel region was 87° by
cross-sectional TEM analysis (data not shown).
3.2 Effects on channel mobility
Next, ID–VG characteristics of isolated one-cell trench
MOSFETs were evaluated at temperatures in the range of
−40 to 250 °C. In this section, to discuss the relationship
between channel mobility and surface roughness, we focused
on the surface roughness parallel to the direction of the drain
current. Figure 3 shows ID–VG curves with different surface
morphology measured at 25 °C. The drain voltage (VD) was
0.1 V. The inset shows the transconductance (gm) properties.
The values of Vth and Dit for each sample are summarized in
Table I with Ra values of line profiles both parallel and
perpendicular to the current direction. The correlation
between effective field and channel mobility is also shown
in Fig. 4. The effective mobility in this study was found to be
lower than that expected from lateral MOSFETs. In addition,
the effects of surface roughness on ID–VG characteristics and
extracted parameters appear to be very small at 25 °C.
For further investigation, μeff was broken down into three
factors, namely, μC, μSR, and μOP, on the basis of the
Fig. 4. (Color online) Correlation between effective field and effective
mobility at 25 °C at different surface roughness.
proposed mobility model, and then the limiting factors of
channel mobility for each sample were analyzed. Figure 5
shows the correlation between Ra values from line profiles
and mobility factors measured at each temperature. The
mobility factors are plotted at Eeff = 1 MV=cm. The results
clearly indicate that the limiting factors of the total mobility
(μTOTAL) were μC at low temperatures (≤25 °C) and μOP at
high temperatures (≥150 °C). In addition, μSR had a small
contribution to μTOTAL, and it had no correlation with Ra in
the range of 0.4 to 1.4 nm.
The result about correlation between Ra and surface
roughness scattering is similar to the case in planar
MOSFETs.33) If a much smoother face is achieved at trench
sidewalls with Ra less than 0.4 nm, Ra will correlate with μSR.
In terms of the evaluation method for surface roughness,
however, further investigation is still required. Compared
with the mean free path of electrons in the inversion layers of
4H-SiC MOSFETs (∼15 Å), the interface roughness measured by AFM on the length scale of 100 Å and larger is large
enough not to affect electron scattering.
From the viewpoint of drastic improvement in channel
mobility, the results shown in Fig. 5 suggest that μC and μOP
should be increased. To increase μC, interface states located
at the SiO2=SiC interface, fixed charges near interface, and
charge traps in the SiO2 layer should be reduced. On the other
hand, the origin of μOP is a lattice vibration; thus, the crystal
structure of SiC near SiO2=SiC interface is considered to
affect μOP properties. How to evaluate this phenomenon
physically and=or electrically and how to control μOP are next
key issues that should be resolved. If both μC and μOP
increase, μSR will have strong impact on the total mobility.
3.3 Effects on reliability in gate oxides
Finally, we investigated the effects of surface roughness on
reliability in gate oxides. Figure 6 shows IG–VG characteristics of trench MOSFETs with different surface morphology.
AFM images and Ra values from line profiles perpendicular
to the current direction corresponding to each IG–VG curve
are also described in Fig. 6. There was no correlation
between IG–VG properties and the surface roughness parallel
to the direction of the drain current. On the other hand, the
surface roughness perpendicular to the drain current shows
strong correlation with IG–VG properties. With the increase in
Ra, the gate leakage current started to flow at a lower gate
04FR02-3
© 2018 The Japan Society of Applied Physics
Mobility at Eeff=1MV/cm (cm2V-1s-1)
Jpn. J. Appl. Phys. 57, 04FR02 (2018)
K. Kutsuki et al.
-40ºC
1000
25ºC
(b)
(a)
250ºC
150ºC
(c)
µC
(d)
µOP
100
10
µSR
µSR
µOP
µC
µC
µTOTAL
µC
µSR
µSR
µOP
µTOTAL
µTOTAL
µTOTAL
µOP
1
0.0
0.5
1.0
1.5
2.0
0.5
1.0
1.5
2.0
0.5
1.0
1.5
0.5
2.0
1.0
1.5
2.0
Ra values from line profile (nm)
Gate Leakage, IG (A)
1¼10-1
Charge to breakdown, QBD (C/cm2)
Fig. 5. (Color online) Correlation between Ra values from line profiles and mobility factors measured at each temperature. The mobility factors are plotted
at Eeff = 1 MV=cm.
2.4nm
1¼10-3
200nm
1¼10-5
2.6nm
1¼10-7
1¼10-9
[
]
[
Current
direction
]
1¼10-11
1¼10-13
0
0.95nm
VD=VS=0V
measured at 25C
20
40
60
Fig. 6. (Color online) IG–VG characteristics of trench MOSFETs with
different surface morphology. AFM images and Ra values from line profiles
perpendicular to the current direction for each IG–VG curve are also
described.
bias. This result indicates that the main factor affecting
reliability in gate oxides was the surface roughness perpendicular to the drain current.
Subsequently, the CCS-TDDB tests were performed at
25 °C. Figure 7 shows the results of charge to breakdown
(QBD) as a function of Ra. The constant current was 10 µA
during the CCS-TDDB tests. The surface roughness was
found to affect QBD directly. In the case of the sample with a
Ra value of 0.95 nm, QBD is of the same level as the reported
value.6) With the increase in surface roughness, however,
QBD drastically degraded. It is assumed that the electric field
locally concentrates at the rough SiO2=SiC interface, which
locally increases the amount of charge passing through gate
oxides and shortens the time to reach the dielectric breakdown. For further consideration, we focused on the relationship between electric field concentration and surface roughness based on Gauss’s law. Gauss’s law is a general law
applied to any closed surface and described as
q 1
;
4" r2
15
10
5
IG=10µA
25ºC
0
0.0
80
Gate Bias, VG (V)
E¼
20
ð8Þ
where q is the elementary charge and r is the curvature radius
at the SiC surface. At SiO2=SiC surfaces, a large Ra value
0.5
1.0
1.5
2.0
2.5
3.0
Ra from line profile (nm)
Fig. 7. (Color online) Correlation between QBD and Ra extracted from line
profile perpendicular to the current direction. The applied constant current
was 10 µA and the measurement temperature was 25 °C during CCS-TDDB
tests.
means that the average curvature radius is small as shown in
Figs. 2(g)–2(i). According to Eq. (8), a small curvature
radius results in a large electric field. This is the reason why
the local electric field concentration occurs. In previous
reports, the electric field concentration at the corner of stepbunching on SiC wafers also increased the Fowler–Nordheim
current and shortened the lifetime of gate oxides in planar
MOSFETs.34,35) Judging from these results and previous
reports, in terms of reliability of gate oxides, it is especially
significant to reduce surface roughness in trench sidewalls.
4.
Conclusions
In this study, we focused on the surface morphology of
trench sidewalls and its effects on electrical properties. In
terms of channel mobility, the limiting factors were Coulomb
scattering and optical phonon scattering. Surface roughness
scattering mobility had a small contribution to the total
mobility, and it had no correlation with Ra parallel to the
drain current in the range of 0.4 to 1.4 nm. For further
improvement in channel mobility, it is essential to control
Coulomb scattering and optical phonon scattering. On the
other hand, IG–VG characteristics and CCS-TDDB test results
revealed that the surface roughness directly affected the
reliability of gate oxides.
04FR02-4
© 2018 The Japan Society of Applied Physics
Jpn. J. Appl. Phys. 57, 04FR02 (2018)
K. Kutsuki et al.
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