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65nm Signoff: Signal EM, Power Grid, Timing Closure
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Proprietary & Confidential C 65nm Signoff © 2009 TSMC, Ltd Design and Technology Platform © 2009 TSMC, Ltd. Contents z Signal EM Flow z Power Grid Sign-off z Timing Closure & Sign-off z Dummy filling flow & Timing fixing z Others © 2009 TSMC, Ltd DTP/ P. 2 © 2009 TSMC, Ltd. Proprietary & Confidential C Signal EM Analysis z Peak/Avg./RMS current z AstroRail or TSMC utility (Ref. Flow 4.0/5.0) © 2009 TSMC, Ltd DTP/ P. 3 © 2009 TSMC, Ltd. Proprietary & Confidential C Proprietary & Confidential C Signal EM Analysis Procedure 1. The temperature for the signal EM analysis: 125C. 2. The RC corner for the RC extraction: Cworst in 125C. 3. The power consumption is calculated in the LT corner, or the ML corner. 4. Set the reasonable switching activity in the signal EM analysis. © 2009 TSMC, Ltd DTP/ P. 4 © 2009 TSMC, Ltd. Power Integrity Proprietary & Confidential C z Power grid signed-off in three modes Static IR drop Average power IR drop < 5% VDD+VSS (wire-bond) 3% ( Flip chip) Dynamic IR drop 4-5X Static IR < 15% VDD + VSS Dcap insertion Scan Peak IR around clock-edge < 30% VDD Peak power usually around clock-edge Seen many chips failing even in scan-mode Analyzing IR drop during small timing window when flops are switching z Power reductions Leakage: Multi-Vt by default Dynamic: RTL clock gating is highly recommended Comprehensive power approaches for portable device © 2009 TSMC, Ltd DTP/ P. 5 © 2009 TSMC, Ltd. Proprietary & Confidential C Power Integrity Procedure 1. The temperature for the power EM analysis: 125C. 2. The RC corner for the RC extraction: CWorst in 125C. 3. The power consumption is calculated in the LT corner, -40C/110% VDD/FF, or the ML corner. 4. Set the reasonable toggle rate to calculate the average power consumption. 5. The EM spec is tight in 125C, the current is large in the LT or ML corner, and the power EM criterion in such condition should be most robust. © 2009 TSMC, Ltd DTP/ P. 6 © 2009 TSMC, Ltd. Proprietary & Confidential C Scan Peak Power z The most of flops are switching at almost the same Current time CLK Many flops switching Timing window (t) © 2009 TSMC, Ltd DTP/ P. 7 © 2009 TSMC, Ltd. Clock skew + Average CK-Q delay + Average Transition/2 Scan Power Analysis Proprietary & Confidential C ATPG Test Patterns Peak Switching Cycle Search IR Sensitivity of Each Flop Flop Transition at Peak Switching Cycle Peak Power Calculation SDF & SDC Dynamic IR Analysis Peak IR Report & Hot Spot Colormap © 2009 TSMC, Ltd DTP/ P. 8 © 2009 TSMC, Ltd. Static vs. Dynamic IR-drop Proprietary & Confidential C Current envelope Average current Peak current (n+1)T nT Wire sizing can be used to control static IR-drop • Critical de-cap provides immediate spike filtering • © 2009 TSMC, Ltd DTP/ P. 9 © 2009 TSMC, Ltd. (n+2)T 65nm PI sign off criteria Proprietary & Confidential C Technology node: 65nm PI sign off criteria recommended Package Wirebond Corner Flipchip w/o pkg w/ pkg w/o pkg w/ pkg 5% 5% 3% 3% FF/SS VDD: TT VCD 10% 15-18% 8-10% 13-15% FF/SS VDD: TT Vectorless 10% 15-18% 8-10% 13-15% FF/SS VDD: TT VCD 10% 15-18% 8-10% 13-15% FF, TT VDD: TT Vectorless 10% 15-18% 15-18% 13-15% FF, TT VDD: TT Static Function Dynamic Scan © 2009 TSMC, Ltd DTP/ P. 10 © 2009 TSMC, Ltd. IR limit : VDD+GND Timing Closure Synthesis Synthesis Proprietary & Confidential C (By (Bycustomer customerwith with10% 10% setup setuptime timemargin margin&& CWLM) CWLM) CTS/CTO CTS/CTO (Double (Doublewidth width++spacing spacing ++via) via) Signal SignalEM EM Fixing Fixing TD TDPlacement Placement (Netlist (Netlistw/w/hold holdaware aware buffer insertion +setup buffer insertion +setup time timedriven) driven) Detail Detailrouting routing (Decap pre-insert, Xtalk (Decap pre-insert, Xtalk prevention, prevention,Ant. Ant.fixing) fixing) Decap Decap Insertion Insertion Trial TrialCTS CTS RC RCExtraction Extraction Double DoubleVia Via Setup Setuptime timeOpt. Opt. Setup/Hold Setup/Hold fixing fixing Dummy DummyFill Fill Xtalk XtalkFixing Fixing STA STASign-off Sign-off (Derive (Derivesetup setuptime time requirement for ICG) requirement for ICG) Power PowerOpt. Opt. (Multi-Vt (Multi-Vtswap) swap) © 2009 TSMC, Ltd DTP/ P. 11 © 2009 TSMC, Ltd. (All (Allsign-off sign-offmodes) modes) (Glitch (Glitch&&setup/hold setup/hold fixing) fixing) (setup/hold (setup/holdfixing) fixing) (setup/hold (setup/holdfixing) fixing) Proprietary & Confidential C Timing Sign-off z Timing closure taking all kinds of following effects into account Multi-mode STA Multiple Device & RC Corners WC, WCL, BC or LT (-40C) Cworst, Cbest (RCworst, RCbest, RCtypical) OCV, Hold margin Crosstalk DFM – Dummy metals, Dummy Vias © 2009 TSMC, Ltd DTP/ P. 12 © 2009 TSMC, Ltd. Proprietary & Confidential C OCV z OCV – On Chip Variation © 2009 TSMC, Ltd DTP/ P. 13 © 2009 TSMC, Ltd. Proprietary & Confidential C Timing Sign-off Recommendation z Clock jitter is not included WC + 65nm Cworst WCL + Cworst Setup/ Setup/ hold hold BC or LT + Cbest/Cworst hold Max. transition 0.6ns* OCV WC: 5% BC:10% Setup margin Hold margin 0 50ps *Max transition applied at WC corner. *Over constraint is recommended at APR stage. **Typical number showed here: - OCV and Hold margin design dependant: transition, cell types, IR-drop **Corner shown here: - It is the basis. Customer should add more corners based on product application. © 2009 TSMC, Ltd DTP/ P. 14 © 2009 TSMC, Ltd. Proprietary & Confidential C Dummy filling flow & Timing Fixing APR APR RC RCextraction extraction Add AddExclusive Exclusivelayer layer atatclock nets clock nets STA STA GDS Timing violations Calibre Calibre Dummy GDS ECO ECO © 2009 TSMC, Ltd DTP/ P. 15 © 2009 TSMC, Ltd. (Fi i Proprietary & Confidential C Dummy Fill Guidelines z In a cell-based design area, it’s recommended to use filler cell with DPO/DOD for empty area (please refer TSMC N90 standard cell library). z It’s recommended to use TSMC fill utility for macro block and chip top level for final GDSII to guarantee global uniformity. z If using TSMC fill utility for DM and DOD, low densities violations could be waived by TSMC PE. Otherwise, all densities rules should be met. z Do dummy fill in a bottom-up approach. © 2009 TSMC, Ltd DTP/ P. 16 © 2009 TSMC, Ltd. Macro block meet rules and timing first, then chip level. Macro IP Dummy Fill Timing Flow N90 Dummy Mx utility DMx GDSII GDS Merge N90 Dummy PO,OD utility Dummy GDSII Proprietary & Confidential C Make dummy top cell name the same as IP top cell for StarRC-XT DPO, DOD GDSII Original IP GDSII GDS Merge Final IP GDSII Milkyway Database LVS/LPE by Hercules LPE Netlist (device) RCX by Star-RCXT RCX Netlist (device+RC) Post-layout Simulation * Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT © 2009 TSMC, Ltd DTP/ P. 17 © 2009 TSMC, Ltd. *mky.gds.map OD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 … Top (Digital) Dummy Fill Timing Flow N90 Dummy Mx utility DMx GDSII Chip GDSII GDS Merge N90 Dummy PO,OD utility Dummy GDSII Make dummy top cell name the same as chip top cell for StarRC-XT DPO, DOD GDSII GDS Merge P&R Milkyway Database RCX by Star-RCXT SPEF w/ dummy impact Sign-off STA *mky.gds.map ECO © 2009 TSMC, Ltd DTP/ P. 18 © 2009 TSMC, Ltd. Proprietary & Confidential C * Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT OD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 … Final chip GDSII Others: High-Speed Clocks Top-view M3/M5 M2/M4 M4 End-view VIA34 M3 M3 Clock net Clock Net © 2009 TSMC, Ltd DTP/ P. 19 © 2009 TSMC, Ltd. Shielding Net Proprietary & Confidential C Signoff Task vs. EDA Tool Design tool Signoff © 2009 TSMC, Ltd DTP/ P. 20 © 2009 TSMC, Ltd. Proprietary & Confidential C Task EDA Tool Major Role ATPG Tmax/fastscan Vector generation/simulation Floor plan Astro/SOC encounter Floor plan environment Placement/CTS/Route Astro/SOC encounter Placement/CTS/Route tool SI Celtic Xtalk analysis RC extraction StarRC RC extraction Netlist Handoff Spyglass & Prime Time Sanity Check LEC ( Verplex ) LEC formal validation Static IR Voltage Storm Static IR drop analysis Dynamic IR RedHawk Dynamic IR drop analysis Power EM Voltage Storm Power Ring reliability issue Signal EM Astro/CISD utility Signal wire reliability issue STA w/ Incr. SDF Prime Time Static timing analysis Redundant via insertion Calibre/Laker/Virtuoso Yield improvement Dummy metal insertion Calibre/Laker/Virtuoso Yield improvement Antenna Calibre/Hermcules Antenna effect check DRC/LVS/ERC Calibre/Hercules TSMC design rule checks
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