6/8/2018
ECE4740:
Digital VLSI Design
Lecture 14: Pass transistors and
transmission gates
500
Ratio’ed logic
Other CMOS logic styles
501
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Why do we even care?
• Advantages of static CMOS
– Low static power
– Robust
– Supported by most synthesis & back-end tools
• “Disadvantages” of static CMOS
– For N inputs, requires (at least) 2N transistors
– PUN can be area consuming
– Same function is computed twice
502
Ratio’ed logic
i
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
v
VT
F
In1
In2
In3
PDN
F
In1
In2
In3
PDN
VSS
VSS
VSS
(a) resistive load
(b) depletion load NMOS
(c) pseudo-NMOS
• Goal: Reduce # of transistors over CMOS
• Ratio’ed = functionality depends on ratios!
503
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
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Ratio’ed logic with resistive load
• N transistors + load RL
VDD
remember 2015
practice prelim 1?
• VOH=VDD
• VOL=RPDN/(RPDN+RL)
RL
Out
In1
In2
In3
• Asymmetric VTC
• Reduced noise margin
PDN
• Static power consumption
• tpLH=0.69RLCL
remember 2015
practice prelim 1?
• What is tpHL?
504
Pseudo-NMOS w/ active load
VDD
A
B
C
D
F
CL
• VOH=VDD
V = V (similar to complementary CMOS)
• For VOL assume NMOS lin. & PMOS sat.
to make VOL small
make PMOS small
505
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
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VTC of pseudo-NMOS
3.0
reduce width
of PMOS
2.5
W/L p = 4
Vout [V]
2.0
1.5
W/L = 2
p
1.0
0.5
W/L = 0.5
p
W/L = 1
p
W/L p = 0.25
0.0
0.0
0.5
1.0
1.5
2.0
2.5
V [V]
in
506
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Disadvantage: Static power
• Static power consumption when output is
low (direct current through PMOS)
• Assume PMOS is in saturation:
• One would need better loads!
507
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Ratio’ed logic
Other CMOS logic styles
508
Improving loads is critical
VDD
VDD
M1
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
• Differential cascode voltage switch logic (DCVSL)
509
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
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DCVSL details
VDD
VDD
M1
M2
• PDN1 and PDN2 are
mutually exclusive
on
high
Out
A
A
B
B
low
Out
PDN1
PDN2
VSS
VSS
off
– If PDN1 conducts
PDN2 is off
– And vice versa
• DCVSL has full rail-to-rail swing
• No static power consumption
• Provides complementary signal
• Gate is still ratio’ed!
510
DCVSL example: XOR/XNOR
gate still ratio’ed:
PMOS size critical
for functionality
Out
Out
B
B
A
B
B
A
possible to share
transistors between
PDN1 and PDN2
requires only 8
transistors for XOR
and XNOR
511
Image taken from: CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Harris
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Why aren’t we always using DCVSL?
• Advantages of differential cascode voltage
switch logic (DCVSL) over static CMOS
– Complementary outputs immediately available
– May reduce # of transistors up to 2x
– Keeps values (similar to latches)
• Disadvantages
– Doubles number of wires (affects density)
– Often higher dynamic power dissipation
– Design tools mostly handle only static CMOS
512
Useful for certain logic gates
Pass-transistor logic
513
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Full adder in static CMOS
Cin A B Σ Cout
0
0 0 0
0
0
0 1 1
0
0
1 0 1
0
0
1 1 0
1
1
0 0 1
0
1
0 1 0
1
1
1 0 0
1
1
1 1 1
1
B
A
B
B
A
A
!Cout
Cin
B
Cin
A
Cin
A
A
B
!Sum
Cin
B
A
B
A
Cin
B
• Requires 24+4 (for C and Sum inv.) transistors
514
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Is there a better way?
• XOR/XNOR gates usually require a large
number of transistors in static CMOS logic
• Remember: pass transistors
– NMOS switch closes if gate input is high
A
A
X
B
Y = X if A and B
X
note that this is
true in both
directions
B
Y = X if A or B
• But, NMOS pass strong 0 but weak 1
515
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Pass transistor (PT) logic
• What is this circuit doing?
B
A
B
F
0
• Find truth table
• Is it static (is there
always a low impedance
path to both rails)?
• How many transistors
would you need with
static CMOS?
516
AND gate with pass transistors
B
A
B
0
F=A*B
A
B
F=A*
B
0
0
0
0
1
0
1
0
0
1
1
1
• Requires 4 logic gates (needs an inverter)
• CMOS logic would require 6 logic gates
• The gate can be static
• No rail-to-rail swing
517
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Properties of PT logic
• Gate can be static (if designed properly)
• N transistors instead of 2N
• Usually no static power consumption
• Ratioless
• Gate has no signal directivity, i.e., is
bidirectional (versus unidirectional)
• Non-inverting logic
518
Complementary PT logic (CPL)
• Also called differential PT logic (DPL)
A
A
B
B
PT network
A
A
B
B
inverse PT
network
F
F
F
F
• Similar to DCVSL
– Input complementary inputs
– Output complementary outputs
519
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CPL/DPL efficient for XOR etc.
B
B
B
B
B
A
A
F=AB
B
A
F=A+B
B
A
A
F=AB
B
F=AB
A
A
F=A+B
B
F=AB
A
OR/NOR
AND/NAND
B
XOR/XNOR
• Pros
– No need for extra inverters (theoretically)
– Static and modular (same topology)
– Simple XOR (good for adders)
520
Disadvantages of CPL/DPL
B
B
B
B
B
A
A
F=AB
B
A
F=A+B
B
A
A
F=AB
B
AND/NAND
B
F=AB
A
A
F=A+B
B
F=AB
A
OR/NOR
XOR/XNOR
• Cons
– Additional routing overhead (2x)
– Static power dissipation problems
– Bidirectional
521
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6/8/2018
CPL/DPL-based full adder
B
Cin
B
Cin
A
!Sum
A
Sum
B
B
Cin
Cin
A
!Cout
B
A
Cin
B
Cin
Cout
• 20+4*2 = 28 transistors (=static CMOS)
• Why are we using inverters at the output?
522
Cascading pass transistors
VDD
VDD
VDD
Vout=VDD-VTn
VDD
VDD
output should not drive gate
of another pass transistor
VDD
VDD
VDD
Vout=VDD-3VTn
523
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VTC of PT AND gate
NMOS is a
bad pull up
B
1.5/0.25
2
Vout, V
0.5/0.25
A 0.5/0.25
B
0
B=VDD, A=0VDD
1
F = A*B
0.5/0.25
A=VDD, B=0VDD
A=B=0VDD
0
0
1
2
• Pure PT logic is not regenerative
– Signal gradually degenerates after passing
through a number of PTs (use inverters to fix)
524
Buffered pass transistor logic
• Buffer needed to recover weak 1
3.0
In
x
0.5  m/0.25 m
In
Out
Out
0.5 m/0.25 m
node x can only
charge up to
Vdd-VTn
Voltage [V]
VD D
1.5 m/0.25 m
2.0
x
1.0
0.00
0.5
1
1.5
Time [ns]
2
• Body effect makes it even worse
525
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
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6/8/2018
Body effect revisited
In
VDD
S
D
x
Out
B
• Large VSB when pulling high (B is tied to
GND and S charged close to VDD)
• Voltage drop at node x is even worse
526
VT drop causes static power
In = VDD
A = VDD
Vx = VDD-VTn
M2
M1
• Pass transistor suffers from body effect
• M2 may be weakly conducting forming a
path from VDD to GND
527
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6/8/2018
Solution 1: level restorer
level restorer
on
Mr
off
B
A=1
A=0
x= 0
1
Mn
M2
Out=0
Out=1
M1
• Full swing on node x  no static power
• No static backwards current (restorer only high
when A is high)
• For correct operation Mr must be sized
properly  results in ratio’ed logic!
528
Solution 1: level restorer (cont’d)
on
Mr
B
A=1
Mn
x =1
M2
Out
M1
• Ratio’ed logic:
– When node x going from 1 to 0, Mn must be
stronger than pull up Mr
– Otherwise x never goes below VM of inverter
• Need to size Mn and Mr
529
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Sizing the level restorer
3.0
Voltage [V]
2.0
W/L =1.75/0.25
r
W/L =1.50/0.25
r
1.0
W/L =1.0/0.25
r
0.0
0
100
200
W/L =1.25/0.25
r
300
400
Time [ps]
node x never
goes below VM
make restorer weaker:
 increase Reqr
500
• Restorer also affects speed and power
– Increases capacitance at node x
530
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Proper way of using pass transistors
Transmission gates
531
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Transmission gate
C
C
A
A
B
A=B if C=1
B
C
C
• Full swing bidirectional switch controlled by
the gate signal C
• NMOS good pull-down; PMOS good pull-up
• Enables rail-to-rail swing
532
Resistance of transmission gate
30
25
20
Resistance, k
0V
Rn
Rp
Rp
2.5V
15
Vout
Rn
10
Req=Rp||Rn
2.5V
5
0
0
1
2
• TG has only mild non-linearity
533
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TG 2-to-1 multiplexer (MUX)
S
In2
F
In1
S
S
S
S
F
VDD
S
In2
S
F
In1
GND
S
F = !(In1  S + In2  S)
In1
In2
534
XOR gate using transmission gates
1
A
B
OFF
1
0
AB
B*!A
inverter
• Requires only 6 transistors
• CMOS requires 12 transistors
535
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6/8/2018
XOR gate using transmission gates
0
weak 0 if !A
AB
ON
A
A*!B
weak 1 if A
B
0
1
• Requires only 6 transistors
• Transmission gate ensures no voltage drop!
536
TG-based full adder
P
VDD
VDD
Ci
A
P
A
A
P
B
A
S Sum Generation
Ci
P
B
VDD
P
P
Ci
VDD
A
Ci
Co Carry Generation
Ci
A
Setup
P
• Similar delays for sum and carry
537
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
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TG-based full adder (cont’d)
Cin
B
A
Sum
Cout
• 16 transistors (opposed to 28 for CMOS)
• Full rail-to-rail swing
538
(Differential TG logic)
B
A
B
B
A
A
B
A
A
A
F=AB
GND
B
F=AB
A
B
B
GND
A
VDD
A
F=AB
B
F=AB
A
VDD
B
B
AND/NAND
XOR/XNOR
539
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Caveat: delay in TG networks
• Elmore delay of RC chain:
quadratic delay increase
in number of TGs
540
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
Delay optimization
• Insert buffers into TG network
• Optimum number of buffers:
rule of thumb: no more
than 2-3 TGs in series
541
Image taken from: Digital Integrated Circuits (2nd Edition) by Rabaey, Chandrakasan, Nikolic
21